* configure.in (sim_fpu_cflags): Add -I../common.
[deliverable/binutils-gdb.git] / gdb / ppc-linux-nat.c
CommitLineData
9abe5450 1/* PPC GNU/Linux native support.
2555fe1a
AC
2
3 Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002,
4 2003 Free Software Foundation, Inc.
c877c8e6
KB
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
05f13b9c
EZ
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
c877c8e6
KB
22
23#include "defs.h"
e162d11b 24#include "gdb_string.h"
c877c8e6
KB
25#include "frame.h"
26#include "inferior.h"
27#include "gdbcore.h"
4e052eda 28#include "regcache.h"
c877c8e6
KB
29
30#include <sys/types.h>
31#include <sys/param.h>
32#include <signal.h>
33#include <sys/user.h>
34#include <sys/ioctl.h>
2555fe1a 35#include "gdb_wait.h"
c877c8e6
KB
36#include <fcntl.h>
37#include <sys/procfs.h>
45229ea4 38#include <sys/ptrace.h>
c877c8e6 39
c60c0f5f
MS
40/* Prototypes for supply_gregset etc. */
41#include "gregset.h"
16333c4f 42#include "ppc-tdep.h"
c60c0f5f 43
45229ea4
EZ
44#ifndef PT_READ_U
45#define PT_READ_U PTRACE_PEEKUSR
46#endif
47#ifndef PT_WRITE_U
48#define PT_WRITE_U PTRACE_POKEUSR
49#endif
50
51/* Default the type of the ptrace transfer to int. */
52#ifndef PTRACE_XFER_TYPE
53#define PTRACE_XFER_TYPE int
54#endif
55
9abe5450
EZ
56/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
57 configure time check. Some older glibc's (for instance 2.2.1)
58 don't have a specific powerpc version of ptrace.h, and fall back on
59 a generic one. In such cases, sys/ptrace.h defines
60 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
61 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
62 PTRACE_SETVRREGS to be. This also makes a configury check pretty
63 much useless. */
64
65/* These definitions should really come from the glibc header files,
66 but Glibc doesn't know about the vrregs yet. */
67#ifndef PTRACE_GETVRREGS
68#define PTRACE_GETVRREGS 18
69#define PTRACE_SETVRREGS 19
70#endif
71
72/* This oddity is because the Linux kernel defines elf_vrregset_t as
73 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
74 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
75 the vrsave as an extra 4 bytes at the end. I opted for creating a
76 flat array of chars, so that it is easier to manipulate for gdb.
77
78 There are 32 vector registers 16 bytes longs, plus a VSCR register
79 which is only 4 bytes long, but is fetched as a 16 bytes
80 quantity. Up to here we have the elf_vrregset_t structure.
81 Appended to this there is space for the VRSAVE register: 4 bytes.
82 Even though this vrsave register is not included in the regset
83 typedef, it is handled by the ptrace requests.
84
85 Note that GNU/Linux doesn't support little endian PPC hardware,
86 therefore the offset at which the real value of the VSCR register
87 is located will be always 12 bytes.
88
89 The layout is like this (where x is the actual value of the vscr reg): */
90
91/* *INDENT-OFF* */
92/*
93 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
94 <-------> <-------><-------><->
95 VR0 VR31 VSCR VRSAVE
96*/
97/* *INDENT-ON* */
98
99#define SIZEOF_VRREGS 33*16+4
100
101typedef char gdb_vrregset_t[SIZEOF_VRREGS];
102
103/* For runtime check of ptrace support for VRREGS. */
104int have_ptrace_getvrregs = 1;
105
c877c8e6 106int
fba45db2 107kernel_u_size (void)
c877c8e6
KB
108{
109 return (sizeof (struct user));
110}
111
16333c4f
EZ
112/* *INDENT-OFF* */
113/* registers layout, as presented by the ptrace interface:
114PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
115PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
116PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
117PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
118PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
119PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
120PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
121PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
122PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
123/* *INDENT_ON * */
c877c8e6 124
45229ea4
EZ
125static int
126ppc_register_u_addr (int regno)
c877c8e6 127{
16333c4f 128 int u_addr = -1;
dc5cfeb6 129 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
56d0d96a
AC
130 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
131 interface, and not the wordsize of the program's ABI. */
132 int wordsize = sizeof (PTRACE_XFER_TYPE);
16333c4f
EZ
133
134 /* General purpose registers occupy 1 slot each in the buffer */
8bf659e8
JB
135 if (regno >= tdep->ppc_gp0_regnum
136 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
26e75e5c 137 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
16333c4f 138
49ff75ad
JB
139 /* Floating point regs: eight bytes each in both 32- and 64-bit
140 ptrace interfaces. Thus, two slots each in 32-bit interface, one
141 slot each in 64-bit interface. */
7bcda025 142 if (regno >= tdep->ppc_fp0_regnum
366f009f
JB
143 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
144 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
16333c4f
EZ
145
146 /* UISA special purpose registers: 1 slot each */
147 if (regno == PC_REGNUM)
49ff75ad 148 u_addr = PT_NIP * wordsize;
dc5cfeb6 149 if (regno == tdep->ppc_lr_regnum)
49ff75ad 150 u_addr = PT_LNK * wordsize;
dc5cfeb6 151 if (regno == tdep->ppc_cr_regnum)
49ff75ad 152 u_addr = PT_CCR * wordsize;
dc5cfeb6 153 if (regno == tdep->ppc_xer_regnum)
49ff75ad 154 u_addr = PT_XER * wordsize;
dc5cfeb6 155 if (regno == tdep->ppc_ctr_regnum)
49ff75ad 156 u_addr = PT_CTR * wordsize;
f8c59253 157#ifdef PT_MQ
dc5cfeb6 158 if (regno == tdep->ppc_mq_regnum)
49ff75ad 159 u_addr = PT_MQ * wordsize;
f8c59253 160#endif
dc5cfeb6 161 if (regno == tdep->ppc_ps_regnum)
49ff75ad 162 u_addr = PT_MSR * wordsize;
7bcda025 163 if (regno == tdep->ppc_fpscr_regnum)
49ff75ad 164 u_addr = PT_FPSCR * wordsize;
16333c4f
EZ
165
166 return u_addr;
c877c8e6
KB
167}
168
9abe5450
EZ
169/* The Linux kernel ptrace interface for AltiVec registers uses the
170 registers set mechanism, as opposed to the interface for all the
171 other registers, that stores/fetches each register individually. */
172static void
173fetch_altivec_register (int tid, int regno)
174{
175 int ret;
176 int offset = 0;
177 gdb_vrregset_t regs;
178 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
12c266ea 179 int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
9abe5450
EZ
180
181 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
182 if (ret < 0)
183 {
184 if (errno == EIO)
185 {
186 have_ptrace_getvrregs = 0;
187 return;
188 }
189 perror_with_name ("Unable to fetch AltiVec register");
190 }
191
192 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
193 long on the hardware. We deal only with the lower 4 bytes of the
194 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
195 there is no need to define an offset for it. */
196 if (regno == (tdep->ppc_vrsave_regnum - 1))
12c266ea 197 offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
9abe5450
EZ
198
199 supply_register (regno,
200 regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
201}
202
45229ea4 203static void
05f13b9c 204fetch_register (int tid, int regno)
45229ea4 205{
366f009f 206 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
45229ea4
EZ
207 /* This isn't really an address. But ptrace thinks of it as one. */
208 char mess[128]; /* For messages */
52f0bd74 209 int i;
45229ea4 210 unsigned int offset; /* Offset of registers within the u area. */
d9d9c31f 211 char buf[MAX_REGISTER_SIZE];
45229ea4
EZ
212 CORE_ADDR regaddr = ppc_register_u_addr (regno);
213
9abe5450
EZ
214 if (altivec_register_p (regno))
215 {
216 /* If this is the first time through, or if it is not the first
217 time through, and we have comfirmed that there is kernel
218 support for such a ptrace request, then go and fetch the
219 register. */
220 if (have_ptrace_getvrregs)
221 {
222 fetch_altivec_register (tid, regno);
223 return;
224 }
225 /* If we have discovered that there is no ptrace support for
226 AltiVec registers, fall through and return zeroes, because
227 regaddr will be -1 in this case. */
228 }
229
45229ea4
EZ
230 if (regaddr == -1)
231 {
12c266ea 232 memset (buf, '\0', DEPRECATED_REGISTER_RAW_SIZE (regno)); /* Supply zeroes */
45229ea4
EZ
233 supply_register (regno, buf);
234 return;
235 }
236
56d0d96a
AC
237 /* Read the raw register using PTRACE_XFER_TYPE sized chunks. On a
238 32-bit platform, 64-bit floating-point registers will require two
239 transfers. */
12c266ea 240 for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE))
45229ea4
EZ
241 {
242 errno = 0;
243 *(PTRACE_XFER_TYPE *) & buf[i] = ptrace (PT_READ_U, tid,
244 (PTRACE_ARG3_TYPE) regaddr, 0);
245 regaddr += sizeof (PTRACE_XFER_TYPE);
246 if (errno != 0)
247 {
248 sprintf (mess, "reading register %s (#%d)",
249 REGISTER_NAME (regno), regno);
250 perror_with_name (mess);
251 }
252 }
56d0d96a
AC
253
254 /* Now supply the register. Be careful to map between ptrace's and
255 the current_regcache's idea of the current wordsize. */
366f009f
JB
256 if ((regno >= tdep->ppc_fp0_regnum
257 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
56d0d96a
AC
258 || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
259 /* FPs are always 64 bits. Little endian values are always found
260 at the left-hand end of the register. */
261 regcache_raw_supply (current_regcache, regno, buf);
262 else
263 /* Big endian register, need to fetch the right-hand end. */
264 regcache_raw_supply (current_regcache, regno,
265 (buf + sizeof (PTRACE_XFER_TYPE)
266 - register_size (current_gdbarch, regno)));
45229ea4
EZ
267}
268
9abe5450
EZ
269static void
270supply_vrregset (gdb_vrregset_t *vrregsetp)
271{
272 int i;
273 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
274 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
12c266ea
AC
275 int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
276 int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
9abe5450
EZ
277
278 for (i = 0; i < num_of_vrregs; i++)
279 {
280 /* The last 2 registers of this set are only 32 bit long, not
281 128. However an offset is necessary only for VSCR because it
282 occupies a whole vector, while VRSAVE occupies a full 4 bytes
283 slot. */
284 if (i == (num_of_vrregs - 2))
285 supply_register (tdep->ppc_vr0_regnum + i,
286 *vrregsetp + i * vrregsize + offset);
287 else
288 supply_register (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize);
289 }
290}
291
292static void
293fetch_altivec_registers (int tid)
294{
295 int ret;
296 gdb_vrregset_t regs;
297
298 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
299 if (ret < 0)
300 {
301 if (errno == EIO)
302 {
303 have_ptrace_getvrregs = 0;
304 return;
305 }
306 perror_with_name ("Unable to fetch AltiVec registers");
307 }
308 supply_vrregset (&regs);
309}
310
45229ea4 311static void
05f13b9c 312fetch_ppc_registers (int tid)
45229ea4
EZ
313{
314 int i;
9abe5450
EZ
315 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
316
32b99774
JB
317 for (i = 0; i < ppc_num_gprs; i++)
318 fetch_register (tid, tdep->ppc_gp0_regnum + i);
319 if (tdep->ppc_fp0_regnum >= 0)
320 for (i = 0; i < ppc_num_fprs; i++)
321 fetch_register (tid, tdep->ppc_fp0_regnum + i);
322 fetch_register (tid, PC_REGNUM);
323 if (tdep->ppc_ps_regnum != -1)
324 fetch_register (tid, tdep->ppc_ps_regnum);
325 if (tdep->ppc_cr_regnum != -1)
326 fetch_register (tid, tdep->ppc_cr_regnum);
327 if (tdep->ppc_lr_regnum != -1)
328 fetch_register (tid, tdep->ppc_lr_regnum);
329 if (tdep->ppc_ctr_regnum != -1)
330 fetch_register (tid, tdep->ppc_ctr_regnum);
331 if (tdep->ppc_xer_regnum != -1)
332 fetch_register (tid, tdep->ppc_xer_regnum);
e3f36dbd
KB
333 if (tdep->ppc_mq_regnum != -1)
334 fetch_register (tid, tdep->ppc_mq_regnum);
32b99774
JB
335 if (tdep->ppc_fpscr_regnum != -1)
336 fetch_register (tid, tdep->ppc_fpscr_regnum);
9abe5450
EZ
337 if (have_ptrace_getvrregs)
338 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
339 fetch_altivec_registers (tid);
45229ea4
EZ
340}
341
342/* Fetch registers from the child process. Fetch all registers if
343 regno == -1, otherwise fetch all general registers or all floating
344 point registers depending upon the value of regno. */
345void
346fetch_inferior_registers (int regno)
347{
9abe5450 348 /* Overload thread id onto process id */
05f13b9c
EZ
349 int tid = TIDGET (inferior_ptid);
350
351 /* No thread id, just use process id */
352 if (tid == 0)
353 tid = PIDGET (inferior_ptid);
354
9abe5450 355 if (regno == -1)
05f13b9c 356 fetch_ppc_registers (tid);
45229ea4 357 else
05f13b9c 358 fetch_register (tid, regno);
45229ea4
EZ
359}
360
361/* Store one register. */
9abe5450
EZ
362static void
363store_altivec_register (int tid, int regno)
364{
365 int ret;
366 int offset = 0;
367 gdb_vrregset_t regs;
368 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
12c266ea 369 int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
9abe5450
EZ
370
371 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
372 if (ret < 0)
373 {
374 if (errno == EIO)
375 {
376 have_ptrace_getvrregs = 0;
377 return;
378 }
379 perror_with_name ("Unable to fetch AltiVec register");
380 }
381
382 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
383 long on the hardware. */
384 if (regno == (tdep->ppc_vrsave_regnum - 1))
12c266ea 385 offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
9abe5450
EZ
386
387 regcache_collect (regno,
388 regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
389
390 ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
391 if (ret < 0)
392 perror_with_name ("Unable to store AltiVec register");
393}
394
45229ea4 395static void
05f13b9c 396store_register (int tid, int regno)
45229ea4 397{
366f009f 398 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
45229ea4
EZ
399 /* This isn't really an address. But ptrace thinks of it as one. */
400 CORE_ADDR regaddr = ppc_register_u_addr (regno);
401 char mess[128]; /* For messages */
52f0bd74 402 int i;
45229ea4 403 unsigned int offset; /* Offset of registers within the u area. */
d9d9c31f 404 char buf[MAX_REGISTER_SIZE];
45229ea4 405
9abe5450 406 if (altivec_register_p (regno))
45229ea4 407 {
9abe5450 408 store_altivec_register (tid, regno);
45229ea4
EZ
409 return;
410 }
411
9abe5450
EZ
412 if (regaddr == -1)
413 return;
414
56d0d96a
AC
415 /* First collect the register value from the regcache. Be careful
416 to to convert the regcache's wordsize into ptrace's wordsize. */
417 memset (buf, 0, sizeof buf);
366f009f
JB
418 if ((regno >= tdep->ppc_fp0_regnum
419 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
56d0d96a
AC
420 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
421 /* Floats are always 64-bit. Little endian registers are always
422 at the left-hand end of the register cache. */
423 regcache_raw_collect (current_regcache, regno, buf);
424 else
425 /* Big-endian registers belong at the right-hand end of the
426 buffer. */
427 regcache_raw_collect (current_regcache, regno,
428 (buf + sizeof (PTRACE_XFER_TYPE)
429 - register_size (current_gdbarch, regno)));
430
12c266ea 431 for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE))
45229ea4
EZ
432 {
433 errno = 0;
434 ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr,
435 *(PTRACE_XFER_TYPE *) & buf[i]);
436 regaddr += sizeof (PTRACE_XFER_TYPE);
e3f36dbd
KB
437
438 if (errno == EIO
7bcda025 439 && regno == gdbarch_tdep (current_gdbarch)->ppc_fpscr_regnum)
e3f36dbd
KB
440 {
441 /* Some older kernel versions don't allow fpscr to be written. */
442 continue;
443 }
444
45229ea4
EZ
445 if (errno != 0)
446 {
447 sprintf (mess, "writing register %s (#%d)",
448 REGISTER_NAME (regno), regno);
449 perror_with_name (mess);
450 }
451 }
452}
453
9abe5450
EZ
454static void
455fill_vrregset (gdb_vrregset_t *vrregsetp)
456{
457 int i;
458 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
459 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
12c266ea
AC
460 int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
461 int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum);
9abe5450
EZ
462
463 for (i = 0; i < num_of_vrregs; i++)
464 {
465 /* The last 2 registers of this set are only 32 bit long, not
466 128, but only VSCR is fetched as a 16 bytes quantity. */
467 if (i == (num_of_vrregs - 2))
468 regcache_collect (tdep->ppc_vr0_regnum + i,
469 *vrregsetp + i * vrregsize + offset);
470 else
471 regcache_collect (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize);
472 }
473}
474
475static void
476store_altivec_registers (int tid)
477{
478 int ret;
479 gdb_vrregset_t regs;
480
0897f59b 481 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
9abe5450
EZ
482 if (ret < 0)
483 {
484 if (errno == EIO)
485 {
486 have_ptrace_getvrregs = 0;
487 return;
488 }
489 perror_with_name ("Couldn't get AltiVec registers");
490 }
491
492 fill_vrregset (&regs);
493
0897f59b 494 if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
9abe5450
EZ
495 perror_with_name ("Couldn't write AltiVec registers");
496}
497
45229ea4 498static void
05f13b9c 499store_ppc_registers (int tid)
45229ea4
EZ
500{
501 int i;
9abe5450 502 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
45229ea4 503
32b99774
JB
504 for (i = 0; i < ppc_num_gprs; i++)
505 store_register (tid, tdep->ppc_gp0_regnum + i);
506 if (tdep->ppc_fp0_regnum >= 0)
507 for (i = 0; i < ppc_num_fprs; i++)
508 store_register (tid, tdep->ppc_fp0_regnum + i);
509 store_register (tid, PC_REGNUM);
510 if (tdep->ppc_ps_regnum != -1)
511 store_register (tid, tdep->ppc_ps_regnum);
512 if (tdep->ppc_cr_regnum != -1)
513 store_register (tid, tdep->ppc_cr_regnum);
514 if (tdep->ppc_lr_regnum != -1)
515 store_register (tid, tdep->ppc_lr_regnum);
516 if (tdep->ppc_ctr_regnum != -1)
517 store_register (tid, tdep->ppc_ctr_regnum);
518 if (tdep->ppc_xer_regnum != -1)
519 store_register (tid, tdep->ppc_xer_regnum);
e3f36dbd
KB
520 if (tdep->ppc_mq_regnum != -1)
521 store_register (tid, tdep->ppc_mq_regnum);
32b99774
JB
522 if (tdep->ppc_fpscr_regnum != -1)
523 store_register (tid, tdep->ppc_fpscr_regnum);
9abe5450
EZ
524 if (have_ptrace_getvrregs)
525 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
526 store_altivec_registers (tid);
45229ea4
EZ
527}
528
529void
530store_inferior_registers (int regno)
531{
05f13b9c
EZ
532 /* Overload thread id onto process id */
533 int tid = TIDGET (inferior_ptid);
534
535 /* No thread id, just use process id */
536 if (tid == 0)
537 tid = PIDGET (inferior_ptid);
538
45229ea4 539 if (regno >= 0)
05f13b9c 540 store_register (tid, regno);
45229ea4 541 else
05f13b9c 542 store_ppc_registers (tid);
45229ea4
EZ
543}
544
50c9bd31 545void
8ae45c11 546supply_gregset (gdb_gregset_t *gregsetp)
c877c8e6 547{
f9be684a
AC
548 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
549 interface, and not the wordsize of the program's ABI. */
550 int wordsize = sizeof (PTRACE_XFER_TYPE);
551 ppc_linux_supply_gregset (current_regcache, -1, gregsetp,
552 sizeof (gdb_gregset_t), wordsize);
553}
554
555static void
556right_fill_reg (int regnum, void *reg)
557{
558 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
559 interface, and not the wordsize of the program's ABI. */
560 int wordsize = sizeof (PTRACE_XFER_TYPE);
561 /* Right fill the register. */
562 regcache_raw_collect (current_regcache, regnum,
563 ((bfd_byte *) reg
564 + wordsize
565 - register_size (current_gdbarch, regnum)));
c877c8e6
KB
566}
567
fdb28ac4 568void
8ae45c11 569fill_gregset (gdb_gregset_t *gregsetp, int regno)
fdb28ac4
KB
570{
571 int regi;
2ac44c70 572 elf_greg_t *regp = (elf_greg_t *) gregsetp;
dc5cfeb6 573 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
f9be684a
AC
574 const int elf_ngreg = 48;
575
576
577 /* Start with zeros. */
578 memset (regp, 0, elf_ngreg * sizeof (*regp));
fdb28ac4 579
fdb28ac4
KB
580 for (regi = 0; regi < 32; regi++)
581 {
16333c4f 582 if ((regno == -1) || regno == regi)
f9be684a 583 right_fill_reg (regi, (regp + PT_R0 + regi));
fdb28ac4
KB
584 }
585
16333c4f 586 if ((regno == -1) || regno == PC_REGNUM)
f9be684a 587 right_fill_reg (PC_REGNUM, regp + PT_NIP);
05f13b9c 588 if ((regno == -1) || regno == tdep->ppc_lr_regnum)
f9be684a 589 right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK);
05f13b9c 590 if ((regno == -1) || regno == tdep->ppc_cr_regnum)
dc5cfeb6 591 regcache_collect (tdep->ppc_cr_regnum, regp + PT_CCR);
05f13b9c 592 if ((regno == -1) || regno == tdep->ppc_xer_regnum)
dc5cfeb6 593 regcache_collect (tdep->ppc_xer_regnum, regp + PT_XER);
05f13b9c 594 if ((regno == -1) || regno == tdep->ppc_ctr_regnum)
f9be684a 595 right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR);
f8c59253 596#ifdef PT_MQ
e3f36dbd
KB
597 if (((regno == -1) || regno == tdep->ppc_mq_regnum)
598 && (tdep->ppc_mq_regnum != -1))
f9be684a 599 right_fill_reg (tdep->ppc_mq_regnum, regp + PT_MQ);
f8c59253 600#endif
05f13b9c 601 if ((regno == -1) || regno == tdep->ppc_ps_regnum)
f9be684a 602 right_fill_reg (tdep->ppc_ps_regnum, regp + PT_MSR);
fdb28ac4
KB
603}
604
50c9bd31 605void
8ae45c11 606supply_fpregset (gdb_fpregset_t * fpregsetp)
c877c8e6 607{
f9be684a
AC
608 ppc_linux_supply_fpregset (NULL, current_regcache, -1, fpregsetp,
609 sizeof (gdb_fpregset_t));
c877c8e6 610}
fdb28ac4 611
9abe5450
EZ
612/* Given a pointer to a floating point register set in /proc format
613 (fpregset_t *), update the register specified by REGNO from gdb's
614 idea of the current floating point register set. If REGNO is -1,
615 update them all. */
fdb28ac4 616void
8ae45c11 617fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
fdb28ac4
KB
618{
619 int regi;
e3f36dbd 620 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
f9be684a 621 bfd_byte *fpp = (void *) fpregsetp;
fdb28ac4 622
7bcda025 623 for (regi = 0; regi < 32; regi++)
fdb28ac4 624 {
7bcda025
JB
625 if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
626 regcache_collect (tdep->ppc_fp0_regnum + regi, fpp + 8 * regi);
fdb28ac4 627 }
7bcda025
JB
628 if ((regno == -1) || regno == tdep->ppc_fpscr_regnum)
629 right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
fdb28ac4 630}
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