Commit | Line | Data |
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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, |
9b254dd1 | 4 | 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
20 | |
21 | #include "defs.h" | |
e162d11b | 22 | #include "gdb_string.h" |
c877c8e6 KB |
23 | #include "frame.h" |
24 | #include "inferior.h" | |
25 | #include "gdbcore.h" | |
4e052eda | 26 | #include "regcache.h" |
383f0f5b | 27 | #include "gdb_assert.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | |
411cb3f9 | 31 | #include <stdint.h> |
c877c8e6 KB |
32 | #include <sys/types.h> |
33 | #include <sys/param.h> | |
34 | #include <signal.h> | |
35 | #include <sys/user.h> | |
36 | #include <sys/ioctl.h> | |
2555fe1a | 37 | #include "gdb_wait.h" |
c877c8e6 KB |
38 | #include <fcntl.h> |
39 | #include <sys/procfs.h> | |
45229ea4 | 40 | #include <sys/ptrace.h> |
c877c8e6 | 41 | |
c60c0f5f MS |
42 | /* Prototypes for supply_gregset etc. */ |
43 | #include "gregset.h" | |
16333c4f | 44 | #include "ppc-tdep.h" |
7284e1be UW |
45 | #include "ppc-linux-tdep.h" |
46 | ||
b7622095 LM |
47 | /* Required when using the AUXV. */ |
48 | #include "elf/common.h" | |
49 | #include "auxv.h" | |
50 | ||
7284e1be UW |
51 | /* This sometimes isn't defined. */ |
52 | #ifndef PT_ORIG_R3 | |
53 | #define PT_ORIG_R3 34 | |
54 | #endif | |
55 | #ifndef PT_TRAP | |
56 | #define PT_TRAP 40 | |
57 | #endif | |
c60c0f5f | 58 | |
b7622095 LM |
59 | #ifndef PPC_FEATURE_BOOKE |
60 | #define PPC_FEATURE_BOOKE 0x00008000 | |
61 | #endif | |
62 | ||
9abe5450 EZ |
63 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
64 | configure time check. Some older glibc's (for instance 2.2.1) | |
65 | don't have a specific powerpc version of ptrace.h, and fall back on | |
66 | a generic one. In such cases, sys/ptrace.h defines | |
67 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
68 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
69 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
70 | much useless. */ | |
71 | ||
72 | /* These definitions should really come from the glibc header files, | |
73 | but Glibc doesn't know about the vrregs yet. */ | |
74 | #ifndef PTRACE_GETVRREGS | |
75 | #define PTRACE_GETVRREGS 18 | |
76 | #define PTRACE_SETVRREGS 19 | |
77 | #endif | |
78 | ||
01904826 JB |
79 | |
80 | /* Similarly for the ptrace requests for getting / setting the SPE | |
81 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
82 | gdb_evrregset_t for details. */ | |
83 | #ifndef PTRACE_GETEVRREGS | |
84 | #define PTRACE_GETEVRREGS 20 | |
85 | #define PTRACE_SETEVRREGS 21 | |
86 | #endif | |
87 | ||
e0d24f8d WZ |
88 | /* Similarly for the hardware watchpoint support. */ |
89 | #ifndef PTRACE_GET_DEBUGREG | |
90 | #define PTRACE_GET_DEBUGREG 25 | |
91 | #endif | |
92 | #ifndef PTRACE_SET_DEBUGREG | |
93 | #define PTRACE_SET_DEBUGREG 26 | |
94 | #endif | |
95 | #ifndef PTRACE_GETSIGINFO | |
96 | #define PTRACE_GETSIGINFO 0x4202 | |
97 | #endif | |
01904826 | 98 | |
9abe5450 EZ |
99 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
100 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
101 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
102 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
103 | flat array of chars, so that it is easier to manipulate for gdb. | |
104 | ||
105 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
106 | which is only 4 bytes long, but is fetched as a 16 bytes | |
107 | quantity. Up to here we have the elf_vrregset_t structure. | |
108 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
109 | Even though this vrsave register is not included in the regset | |
110 | typedef, it is handled by the ptrace requests. | |
111 | ||
112 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
113 | therefore the offset at which the real value of the VSCR register | |
114 | is located will be always 12 bytes. | |
115 | ||
116 | The layout is like this (where x is the actual value of the vscr reg): */ | |
117 | ||
118 | /* *INDENT-OFF* */ | |
119 | /* | |
120 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
121 | <-------> <-------><-------><-> | |
122 | VR0 VR31 VSCR VRSAVE | |
123 | */ | |
124 | /* *INDENT-ON* */ | |
125 | ||
126 | #define SIZEOF_VRREGS 33*16+4 | |
127 | ||
128 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
129 | ||
01904826 JB |
130 | |
131 | /* On PPC processors that support the the Signal Processing Extension | |
132 | (SPE) APU, the general-purpose registers are 64 bits long. | |
411cb3f9 PG |
133 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
134 | ptrace calls only access the lower half of each register, to allow | |
135 | them to behave the same way they do on non-SPE systems. There's a | |
136 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
137 | read and write the top halves of all the general-purpose registers | |
138 | at once, along with some SPE-specific registers. | |
01904826 JB |
139 | |
140 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd JB |
141 | bits long. It has unnamed raw registers that hold the upper halves |
142 | of the gprs, and the the full 64-bit SIMD views of the registers, | |
143 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and | |
144 | bottom halves together. | |
01904826 JB |
145 | |
146 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
147 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
148 | struct gdb_evrregset_t | |
149 | { | |
150 | unsigned long evr[32]; | |
151 | unsigned long long acc; | |
152 | unsigned long spefscr; | |
153 | }; | |
154 | ||
155 | ||
156 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
157 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
158 | registers. Zero if we've tried one of them and gotten an | |
159 | error. */ | |
9abe5450 EZ |
160 | int have_ptrace_getvrregs = 1; |
161 | ||
01904826 JB |
162 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
163 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
164 | registers. Zero if we've tried one of them and gotten an | |
165 | error. */ | |
166 | int have_ptrace_getsetevrregs = 1; | |
167 | ||
16333c4f EZ |
168 | /* *INDENT-OFF* */ |
169 | /* registers layout, as presented by the ptrace interface: | |
170 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
171 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
172 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
173 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
174 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
175 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
176 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
177 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
178 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
179 | /* *INDENT_ON * */ | |
c877c8e6 | 180 | |
45229ea4 | 181 | static int |
e101270f | 182 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 183 | { |
16333c4f | 184 | int u_addr = -1; |
e101270f | 185 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
186 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
187 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 188 | int wordsize = sizeof (long); |
16333c4f EZ |
189 | |
190 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
191 | if (regno >= tdep->ppc_gp0_regnum |
192 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 193 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 194 | |
49ff75ad JB |
195 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
196 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
197 | slot each in 64-bit interface. */ | |
383f0f5b JB |
198 | if (tdep->ppc_fp0_regnum >= 0 |
199 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
200 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
201 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
202 | |
203 | /* UISA special purpose registers: 1 slot each */ | |
e101270f | 204 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 205 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 206 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 207 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 208 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 209 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 210 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 211 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 212 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 213 | u_addr = PT_CTR * wordsize; |
f8c59253 | 214 | #ifdef PT_MQ |
dc5cfeb6 | 215 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 216 | u_addr = PT_MQ * wordsize; |
f8c59253 | 217 | #endif |
dc5cfeb6 | 218 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 219 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
220 | if (regno == PPC_ORIG_R3_REGNUM) |
221 | u_addr = PT_ORIG_R3 * wordsize; | |
222 | if (regno == PPC_TRAP_REGNUM) | |
223 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
224 | if (tdep->ppc_fpscr_regnum >= 0 |
225 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
226 | { |
227 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
228 | kernel headers incorrectly contained the 32-bit definition of | |
229 | PT_FPSCR. For the 32-bit definition, floating-point | |
230 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
231 | the secondhalf of such a slot-pair (hence +1). For 64-bit, | |
232 | the FPSCR instead occupies the full 64-bit 2-word-slot and | |
233 | hence no adjustment is necessary. Hack around this. */ | |
234 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
235 | u_addr = (48 + 32) * wordsize; | |
236 | else | |
237 | u_addr = PT_FPSCR * wordsize; | |
238 | } | |
16333c4f | 239 | return u_addr; |
c877c8e6 KB |
240 | } |
241 | ||
9abe5450 EZ |
242 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
243 | registers set mechanism, as opposed to the interface for all the | |
244 | other registers, that stores/fetches each register individually. */ | |
245 | static void | |
56be3814 | 246 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
247 | { |
248 | int ret; | |
249 | int offset = 0; | |
250 | gdb_vrregset_t regs; | |
40a6adc1 MD |
251 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
252 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
253 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
254 | |
255 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
256 | if (ret < 0) | |
257 | { | |
258 | if (errno == EIO) | |
259 | { | |
260 | have_ptrace_getvrregs = 0; | |
261 | return; | |
262 | } | |
e2e0b3e5 | 263 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
264 | } |
265 | ||
266 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
267 | long on the hardware. We deal only with the lower 4 bytes of the | |
268 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
269 | there is no need to define an offset for it. */ | |
270 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 271 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 272 | |
56be3814 | 273 | regcache_raw_supply (regcache, regno, |
23a6d369 | 274 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
275 | } |
276 | ||
01904826 JB |
277 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
278 | SPE-specific registers, and place the results in EVRREGSET. If we | |
279 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
280 | zeros. | |
281 | ||
282 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
283 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
284 | set_spe_registers. */ | |
285 | static void | |
286 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
287 | { | |
288 | if (have_ptrace_getsetevrregs) | |
289 | { | |
290 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
291 | return; | |
292 | else | |
293 | { | |
294 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
295 | we just return zeros. */ | |
296 | if (errno == EIO) | |
297 | have_ptrace_getsetevrregs = 0; | |
298 | else | |
299 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 300 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
301 | } |
302 | } | |
303 | ||
304 | memset (evrregset, 0, sizeof (*evrregset)); | |
305 | } | |
306 | ||
6ced10dd JB |
307 | /* Supply values from TID for SPE-specific raw registers: the upper |
308 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
309 | be the number of an upper half register, acc, spefscr, or -1 to | |
310 | supply the values of all registers. */ | |
01904826 | 311 | static void |
56be3814 | 312 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 313 | { |
40a6adc1 MD |
314 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
316 | struct gdb_evrregset_t evrregs; |
317 | ||
6ced10dd | 318 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 319 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 320 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 321 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 322 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 323 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 324 | |
01904826 JB |
325 | get_spe_registers (tid, &evrregs); |
326 | ||
6ced10dd | 327 | if (regno == -1) |
01904826 | 328 | { |
6ced10dd JB |
329 | int i; |
330 | ||
331 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 332 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 333 | &evrregs.evr[i]); |
01904826 | 334 | } |
6ced10dd JB |
335 | else if (tdep->ppc_ev0_upper_regnum <= regno |
336 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 337 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
338 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
339 | ||
340 | if (regno == -1 | |
341 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 342 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
343 | |
344 | if (regno == -1 | |
345 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 346 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 347 | &evrregs.spefscr); |
01904826 JB |
348 | } |
349 | ||
45229ea4 | 350 | static void |
56be3814 | 351 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 352 | { |
40a6adc1 MD |
353 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
354 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 355 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 356 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 357 | int bytes_transferred; |
45229ea4 | 358 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 359 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 360 | |
be8626e0 | 361 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
362 | { |
363 | /* If this is the first time through, or if it is not the first | |
364 | time through, and we have comfirmed that there is kernel | |
365 | support for such a ptrace request, then go and fetch the | |
366 | register. */ | |
367 | if (have_ptrace_getvrregs) | |
368 | { | |
56be3814 | 369 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
370 | return; |
371 | } | |
372 | /* If we have discovered that there is no ptrace support for | |
373 | AltiVec registers, fall through and return zeroes, because | |
374 | regaddr will be -1 in this case. */ | |
375 | } | |
be8626e0 | 376 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 377 | { |
56be3814 | 378 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
379 | return; |
380 | } | |
9abe5450 | 381 | |
45229ea4 EZ |
382 | if (regaddr == -1) |
383 | { | |
40a6adc1 | 384 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 385 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
386 | return; |
387 | } | |
388 | ||
411cb3f9 | 389 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
390 | 32-bit platform, 64-bit floating-point registers will require two |
391 | transfers. */ | |
4a19ea35 | 392 | for (bytes_transferred = 0; |
40a6adc1 | 393 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 394 | bytes_transferred += sizeof (long)) |
45229ea4 EZ |
395 | { |
396 | errno = 0; | |
411cb3f9 PG |
397 | *(long *) &buf[bytes_transferred] |
398 | = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); | |
399 | regaddr += sizeof (long); | |
45229ea4 EZ |
400 | if (errno != 0) |
401 | { | |
bc97b3ba JB |
402 | char message[128]; |
403 | sprintf (message, "reading register %s (#%d)", | |
40a6adc1 | 404 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 405 | perror_with_name (message); |
45229ea4 EZ |
406 | } |
407 | } | |
56d0d96a | 408 | |
4a19ea35 JB |
409 | /* Now supply the register. Keep in mind that the regcache's idea |
410 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 411 | (long). */ |
40a6adc1 | 412 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
413 | { |
414 | /* Little-endian values are always found at the left end of the | |
415 | bytes transferred. */ | |
56be3814 | 416 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 417 | } |
40a6adc1 | 418 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
419 | { |
420 | /* Big-endian values are found at the right end of the bytes | |
421 | transferred. */ | |
40a6adc1 | 422 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 423 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
424 | } |
425 | else | |
a44bddec | 426 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 427 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 428 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
429 | } |
430 | ||
9abe5450 | 431 | static void |
56be3814 | 432 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
433 | { |
434 | int i; | |
40a6adc1 MD |
435 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
436 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 437 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
438 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
439 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
440 | |
441 | for (i = 0; i < num_of_vrregs; i++) | |
442 | { | |
443 | /* The last 2 registers of this set are only 32 bit long, not | |
444 | 128. However an offset is necessary only for VSCR because it | |
445 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
446 | slot. */ | |
447 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 448 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 449 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 450 | else |
56be3814 | 451 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 452 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
453 | } |
454 | } | |
455 | ||
456 | static void | |
56be3814 | 457 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
458 | { |
459 | int ret; | |
460 | gdb_vrregset_t regs; | |
461 | ||
462 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
463 | if (ret < 0) | |
464 | { | |
465 | if (errno == EIO) | |
466 | { | |
467 | have_ptrace_getvrregs = 0; | |
468 | return; | |
469 | } | |
e2e0b3e5 | 470 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 471 | } |
56be3814 | 472 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
473 | } |
474 | ||
45229ea4 | 475 | static void |
56be3814 | 476 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
477 | { |
478 | int i; | |
40a6adc1 MD |
479 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
480 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 481 | |
6ced10dd | 482 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 483 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
484 | if (tdep->ppc_fp0_regnum >= 0) |
485 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 | 486 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
40a6adc1 | 487 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 488 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 489 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 490 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 491 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 492 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 493 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 494 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 495 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 496 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 497 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 498 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 499 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
500 | if (ppc_linux_trap_reg_p (gdbarch)) |
501 | { | |
502 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
503 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
504 | } | |
32b99774 | 505 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 506 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
507 | if (have_ptrace_getvrregs) |
508 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 509 | fetch_altivec_registers (regcache, tid); |
6ced10dd | 510 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 511 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
512 | } |
513 | ||
514 | /* Fetch registers from the child process. Fetch all registers if | |
515 | regno == -1, otherwise fetch all general registers or all floating | |
516 | point registers depending upon the value of regno. */ | |
10d6c8cd | 517 | static void |
56be3814 | 518 | ppc_linux_fetch_inferior_registers (struct regcache *regcache, int regno) |
45229ea4 | 519 | { |
9abe5450 | 520 | /* Overload thread id onto process id */ |
05f13b9c EZ |
521 | int tid = TIDGET (inferior_ptid); |
522 | ||
523 | /* No thread id, just use process id */ | |
524 | if (tid == 0) | |
525 | tid = PIDGET (inferior_ptid); | |
526 | ||
9abe5450 | 527 | if (regno == -1) |
56be3814 | 528 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 529 | else |
56be3814 | 530 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
531 | } |
532 | ||
533 | /* Store one register. */ | |
9abe5450 | 534 | static void |
56be3814 | 535 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
536 | { |
537 | int ret; | |
538 | int offset = 0; | |
539 | gdb_vrregset_t regs; | |
40a6adc1 MD |
540 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
541 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
542 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
543 | |
544 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
545 | if (ret < 0) | |
546 | { | |
547 | if (errno == EIO) | |
548 | { | |
549 | have_ptrace_getvrregs = 0; | |
550 | return; | |
551 | } | |
e2e0b3e5 | 552 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
553 | } |
554 | ||
555 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
556 | long on the hardware. */ | |
557 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 558 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 559 | |
56be3814 | 560 | regcache_raw_collect (regcache, regno, |
822c9732 | 561 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
562 | |
563 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
564 | if (ret < 0) | |
e2e0b3e5 | 565 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
566 | } |
567 | ||
01904826 JB |
568 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
569 | general-purpose registers and its SPE-specific registers to the | |
570 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
571 | nothing. | |
572 | ||
573 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
574 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
575 | get_spe_registers. */ | |
576 | static void | |
577 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
578 | { | |
579 | if (have_ptrace_getsetevrregs) | |
580 | { | |
581 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
582 | return; | |
583 | else | |
584 | { | |
585 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
586 | supported; we fail silently, and don't try the call | |
587 | again. */ | |
588 | if (errno == EIO) | |
589 | have_ptrace_getsetevrregs = 0; | |
590 | else | |
591 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 592 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
593 | } |
594 | } | |
595 | } | |
596 | ||
6ced10dd JB |
597 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
598 | If REGNO is -1, write the values of all the SPE-specific | |
599 | registers. */ | |
01904826 | 600 | static void |
56be3814 | 601 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 602 | { |
40a6adc1 MD |
603 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
604 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
605 | struct gdb_evrregset_t evrregs; |
606 | ||
6ced10dd | 607 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 608 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 609 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 610 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 611 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 612 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 613 | |
6ced10dd JB |
614 | if (regno == -1) |
615 | /* Since we're going to write out every register, the code below | |
616 | should store to every field of evrregs; if that doesn't happen, | |
617 | make it obvious by initializing it with suspicious values. */ | |
618 | memset (&evrregs, 42, sizeof (evrregs)); | |
619 | else | |
620 | /* We can only read and write the entire EVR register set at a | |
621 | time, so to write just a single register, we do a | |
622 | read-modify-write maneuver. */ | |
623 | get_spe_registers (tid, &evrregs); | |
624 | ||
625 | if (regno == -1) | |
01904826 | 626 | { |
6ced10dd JB |
627 | int i; |
628 | ||
629 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 630 | regcache_raw_collect (regcache, |
6ced10dd JB |
631 | tdep->ppc_ev0_upper_regnum + i, |
632 | &evrregs.evr[i]); | |
01904826 | 633 | } |
6ced10dd JB |
634 | else if (tdep->ppc_ev0_upper_regnum <= regno |
635 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 636 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
637 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
638 | ||
639 | if (regno == -1 | |
640 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 641 | regcache_raw_collect (regcache, |
6ced10dd JB |
642 | tdep->ppc_acc_regnum, |
643 | &evrregs.acc); | |
644 | ||
645 | if (regno == -1 | |
646 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 647 | regcache_raw_collect (regcache, |
6ced10dd JB |
648 | tdep->ppc_spefscr_regnum, |
649 | &evrregs.spefscr); | |
01904826 JB |
650 | |
651 | /* Write back the modified register set. */ | |
652 | set_spe_registers (tid, &evrregs); | |
653 | } | |
654 | ||
45229ea4 | 655 | static void |
56be3814 | 656 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 657 | { |
40a6adc1 MD |
658 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
659 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 660 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 661 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 662 | int i; |
4a19ea35 | 663 | size_t bytes_to_transfer; |
d9d9c31f | 664 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 665 | |
be8626e0 | 666 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 667 | { |
56be3814 | 668 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
669 | return; |
670 | } | |
be8626e0 | 671 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 672 | { |
56be3814 | 673 | store_spe_register (regcache, tid, regno); |
01904826 JB |
674 | return; |
675 | } | |
45229ea4 | 676 | |
9abe5450 EZ |
677 | if (regaddr == -1) |
678 | return; | |
679 | ||
4a19ea35 JB |
680 | /* First collect the register. Keep in mind that the regcache's |
681 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 682 | (long). */ |
56d0d96a | 683 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
684 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
685 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
686 | { |
687 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 688 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 689 | } |
40a6adc1 | 690 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
691 | { |
692 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 693 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 694 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
695 | } |
696 | ||
411cb3f9 | 697 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 EZ |
698 | { |
699 | errno = 0; | |
411cb3f9 PG |
700 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, |
701 | *(long *) &buf[i]); | |
702 | regaddr += sizeof (long); | |
e3f36dbd KB |
703 | |
704 | if (errno == EIO | |
7284e1be UW |
705 | && (regno == tdep->ppc_fpscr_regnum |
706 | || regno == PPC_ORIG_R3_REGNUM | |
707 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 708 | { |
7284e1be UW |
709 | /* Some older kernel versions don't allow fpscr, orig_r3 |
710 | or trap to be written. */ | |
e3f36dbd KB |
711 | continue; |
712 | } | |
713 | ||
45229ea4 EZ |
714 | if (errno != 0) |
715 | { | |
bc97b3ba JB |
716 | char message[128]; |
717 | sprintf (message, "writing register %s (#%d)", | |
40a6adc1 | 718 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 719 | perror_with_name (message); |
45229ea4 EZ |
720 | } |
721 | } | |
722 | } | |
723 | ||
9abe5450 | 724 | static void |
56be3814 | 725 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
726 | { |
727 | int i; | |
40a6adc1 MD |
728 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
729 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 730 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
731 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
732 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
733 | |
734 | for (i = 0; i < num_of_vrregs; i++) | |
735 | { | |
736 | /* The last 2 registers of this set are only 32 bit long, not | |
737 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
738 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 739 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 740 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 741 | else |
56be3814 | 742 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 743 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
744 | } |
745 | } | |
746 | ||
747 | static void | |
56be3814 | 748 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
749 | { |
750 | int ret; | |
751 | gdb_vrregset_t regs; | |
752 | ||
0897f59b | 753 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
754 | if (ret < 0) |
755 | { | |
756 | if (errno == EIO) | |
757 | { | |
758 | have_ptrace_getvrregs = 0; | |
759 | return; | |
760 | } | |
e2e0b3e5 | 761 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
762 | } |
763 | ||
56be3814 | 764 | fill_vrregset (regcache, ®s); |
9abe5450 | 765 | |
0897f59b | 766 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 767 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
768 | } |
769 | ||
45229ea4 | 770 | static void |
56be3814 | 771 | store_ppc_registers (const struct regcache *regcache, int tid) |
45229ea4 EZ |
772 | { |
773 | int i; | |
40a6adc1 MD |
774 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
775 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 776 | |
6ced10dd | 777 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 778 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
779 | if (tdep->ppc_fp0_regnum >= 0) |
780 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 | 781 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
40a6adc1 | 782 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 783 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 784 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 785 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 786 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 787 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 788 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 789 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 790 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 791 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 792 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 793 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 794 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 795 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 796 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
797 | if (ppc_linux_trap_reg_p (gdbarch)) |
798 | { | |
799 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
800 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
801 | } | |
9abe5450 EZ |
802 | if (have_ptrace_getvrregs) |
803 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 804 | store_altivec_registers (regcache, tid); |
6ced10dd | 805 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 806 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
807 | } |
808 | ||
e0d24f8d WZ |
809 | static int |
810 | ppc_linux_check_watch_resources (int type, int cnt, int ot) | |
811 | { | |
812 | int tid; | |
813 | ptid_t ptid = inferior_ptid; | |
814 | ||
815 | /* DABR (data address breakpoint register) is optional for PPC variants. | |
816 | Some variants have one DABR, others have none. So CNT can't be larger | |
817 | than 1. */ | |
818 | if (cnt > 1) | |
819 | return 0; | |
820 | ||
821 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether | |
822 | the target has DABR. If either answer is no, the ptrace call will | |
823 | return -1. Fail in that case. */ | |
824 | tid = TIDGET (ptid); | |
825 | if (tid == 0) | |
826 | tid = PIDGET (ptid); | |
827 | ||
828 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
829 | return 0; | |
830 | return 1; | |
831 | } | |
832 | ||
b7622095 LM |
833 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
834 | unsigned long ppc_linux_get_hwcap (void) | |
835 | { | |
836 | CORE_ADDR field; | |
837 | ||
fcb09a75 | 838 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) |
b7622095 LM |
839 | return (unsigned long) field; |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
e0d24f8d WZ |
844 | static int |
845 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
846 | { | |
847 | /* Handle sub-8-byte quantities. */ | |
848 | if (len <= 0) | |
849 | return 0; | |
850 | ||
b7622095 LM |
851 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
852 | processors. DAC-based processors, like the PowerPC 440, will use | |
853 | addresses aligned to 4-bytes due to the way the read/write flags are | |
854 | passed at the moment. */ | |
855 | if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
856 | && (addr + len) > (addr & ~3) + 4) | |
857 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
858 | return 0; |
859 | ||
860 | return 1; | |
861 | } | |
862 | ||
9f0bdab8 DJ |
863 | /* The cached DABR value, to install in new threads. */ |
864 | static long saved_dabr_value; | |
865 | ||
e0d24f8d | 866 | /* Set a watchpoint of type TYPE at address ADDR. */ |
2c387241 | 867 | static int |
e0d24f8d WZ |
868 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) |
869 | { | |
9f0bdab8 DJ |
870 | struct lwp_info *lp; |
871 | ptid_t ptid; | |
e0d24f8d | 872 | long dabr_value; |
b7622095 LM |
873 | long read_mode, write_mode; |
874 | ||
875 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
876 | { | |
877 | /* PowerPC 440 requires only the read/write flags to be passed | |
878 | to the kernel. */ | |
879 | read_mode = 1; | |
880 | write_mode = 2; | |
881 | } | |
882 | else | |
883 | { | |
884 | /* PowerPC 970 and other DABR-based processors are required to pass | |
885 | the Breakpoint Translation bit together with the flags. */ | |
886 | read_mode = 5; | |
887 | write_mode = 6; | |
888 | } | |
889 | ||
890 | dabr_value = addr & ~(read_mode | write_mode); | |
e0d24f8d WZ |
891 | switch (rw) |
892 | { | |
893 | case hw_read: | |
894 | /* Set read and translate bits. */ | |
b7622095 | 895 | dabr_value |= read_mode; |
e0d24f8d WZ |
896 | break; |
897 | case hw_write: | |
898 | /* Set write and translate bits. */ | |
b7622095 | 899 | dabr_value |= write_mode; |
e0d24f8d WZ |
900 | break; |
901 | case hw_access: | |
902 | /* Set read, write and translate bits. */ | |
b7622095 | 903 | dabr_value |= read_mode | write_mode; |
e0d24f8d WZ |
904 | break; |
905 | } | |
906 | ||
1c86e440 LM |
907 | saved_dabr_value = dabr_value; |
908 | ||
9f0bdab8 DJ |
909 | ALL_LWPS (lp, ptid) |
910 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) | |
911 | return -1; | |
1c86e440 | 912 | |
9f0bdab8 | 913 | return 0; |
e0d24f8d WZ |
914 | } |
915 | ||
2c387241 AM |
916 | static int |
917 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) | |
e0d24f8d | 918 | { |
9f0bdab8 DJ |
919 | struct lwp_info *lp; |
920 | ptid_t ptid; | |
921 | long dabr_value = 0; | |
922 | ||
923 | saved_dabr_value = 0; | |
924 | ALL_LWPS (lp, ptid) | |
925 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) | |
926 | return -1; | |
927 | return 0; | |
e0d24f8d WZ |
928 | } |
929 | ||
9f0bdab8 DJ |
930 | static void |
931 | ppc_linux_new_thread (ptid_t ptid) | |
e0d24f8d | 932 | { |
9f0bdab8 | 933 | ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value); |
e0d24f8d WZ |
934 | } |
935 | ||
936 | static int | |
9f0bdab8 | 937 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 938 | { |
9f0bdab8 | 939 | struct siginfo *siginfo_p; |
e0d24f8d | 940 | |
9f0bdab8 | 941 | siginfo_p = linux_nat_get_siginfo (inferior_ptid); |
e0d24f8d | 942 | |
9f0bdab8 DJ |
943 | if (siginfo_p->si_signo != SIGTRAP |
944 | || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
945 | return 0; |
946 | ||
407f1a2e | 947 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr; |
e0d24f8d WZ |
948 | return 1; |
949 | } | |
950 | ||
9f0bdab8 DJ |
951 | static int |
952 | ppc_linux_stopped_by_watchpoint (void) | |
953 | { | |
954 | CORE_ADDR addr; | |
955 | return ppc_linux_stopped_data_address (¤t_target, &addr); | |
956 | } | |
957 | ||
5009afc5 AS |
958 | static int |
959 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
960 | CORE_ADDR addr, | |
961 | CORE_ADDR start, int length) | |
962 | { | |
b7622095 LM |
963 | int mask; |
964 | ||
965 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
966 | mask = 3; | |
967 | else | |
968 | mask = 7; | |
969 | ||
970 | addr &= ~mask; | |
971 | ||
972 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ | |
973 | return start <= addr + mask && start + length - 1 >= addr; | |
5009afc5 AS |
974 | } |
975 | ||
10d6c8cd | 976 | static void |
56be3814 | 977 | ppc_linux_store_inferior_registers (struct regcache *regcache, int regno) |
45229ea4 | 978 | { |
05f13b9c EZ |
979 | /* Overload thread id onto process id */ |
980 | int tid = TIDGET (inferior_ptid); | |
981 | ||
982 | /* No thread id, just use process id */ | |
983 | if (tid == 0) | |
984 | tid = PIDGET (inferior_ptid); | |
985 | ||
45229ea4 | 986 | if (regno >= 0) |
56be3814 | 987 | store_register (regcache, tid, regno); |
45229ea4 | 988 | else |
56be3814 | 989 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
990 | } |
991 | ||
f2db237a AM |
992 | /* Functions for transferring registers between a gregset_t or fpregset_t |
993 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
994 | by the ptrace interface, not the current program's ABI. eg. If a | |
995 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we | |
996 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
997 | ||
50c9bd31 | 998 | void |
7f7fe91e | 999 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 1000 | { |
f2db237a | 1001 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 1002 | |
f2db237a | 1003 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
1004 | } |
1005 | ||
fdb28ac4 | 1006 | void |
7f7fe91e UW |
1007 | fill_gregset (const struct regcache *regcache, |
1008 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 1009 | { |
f2db237a | 1010 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 1011 | |
f2db237a AM |
1012 | if (regno == -1) |
1013 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
1014 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
1015 | } |
1016 | ||
50c9bd31 | 1017 | void |
7f7fe91e | 1018 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 1019 | { |
f2db237a AM |
1020 | const struct regset *regset = ppc_linux_fpregset (); |
1021 | ||
1022 | ppc_supply_fpregset (regset, regcache, -1, | |
1023 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 1024 | } |
fdb28ac4 | 1025 | |
fdb28ac4 | 1026 | void |
7f7fe91e UW |
1027 | fill_fpregset (const struct regcache *regcache, |
1028 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 1029 | { |
f2db237a AM |
1030 | const struct regset *regset = ppc_linux_fpregset (); |
1031 | ||
1032 | ppc_collect_fpregset (regset, regcache, regno, | |
1033 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 1034 | } |
10d6c8cd | 1035 | |
310a98e1 DJ |
1036 | static const struct target_desc * |
1037 | ppc_linux_read_description (struct target_ops *ops) | |
1038 | { | |
7284e1be UW |
1039 | int altivec = 0; |
1040 | ||
1041 | int tid = TIDGET (inferior_ptid); | |
1042 | if (tid == 0) | |
1043 | tid = PIDGET (inferior_ptid); | |
1044 | ||
310a98e1 DJ |
1045 | if (have_ptrace_getsetevrregs) |
1046 | { | |
1047 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
1048 | |
1049 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
1050 | return tdesc_powerpc_e500l; |
1051 | ||
1052 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
1053 | Anything else needs to be reported. */ | |
1054 | else if (errno != EIO) | |
1055 | perror_with_name (_("Unable to fetch SPE registers")); | |
1056 | } | |
1057 | ||
1058 | if (have_ptrace_getvrregs) | |
1059 | { | |
1060 | gdb_vrregset_t vrregset; | |
1061 | ||
1062 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
1063 | altivec = 1; | |
1064 | ||
1065 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
1066 | Anything else needs to be reported. */ | |
1067 | else if (errno != EIO) | |
1068 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
1069 | } |
1070 | ||
7284e1be UW |
1071 | /* Check for 64-bit inferior process. This is the case when the host is |
1072 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
1073 | #ifdef __powerpc64__ | |
1074 | { | |
1075 | long msr; | |
1076 | errno = 0; | |
1077 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
1078 | if (errno == 0 && msr < 0) | |
1079 | return altivec? tdesc_powerpc_altivec64l : tdesc_powerpc_64l; | |
1080 | } | |
1081 | #endif | |
1082 | ||
1083 | return altivec? tdesc_powerpc_altivec32l : tdesc_powerpc_32l; | |
310a98e1 DJ |
1084 | } |
1085 | ||
10d6c8cd DJ |
1086 | void _initialize_ppc_linux_nat (void); |
1087 | ||
1088 | void | |
1089 | _initialize_ppc_linux_nat (void) | |
1090 | { | |
1091 | struct target_ops *t; | |
1092 | ||
1093 | /* Fill in the generic GNU/Linux methods. */ | |
1094 | t = linux_target (); | |
1095 | ||
1096 | /* Add our register access methods. */ | |
1097 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
1098 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
1099 | ||
e0d24f8d WZ |
1100 | /* Add our watchpoint methods. */ |
1101 | t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; | |
1102 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; | |
1103 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
1104 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
1105 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; | |
1106 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 1107 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
e0d24f8d | 1108 | |
310a98e1 DJ |
1109 | t->to_read_description = ppc_linux_read_description; |
1110 | ||
10d6c8cd | 1111 | /* Register the target. */ |
f973ed9c | 1112 | linux_nat_add_target (t); |
9f0bdab8 | 1113 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 1114 | } |