[deliverable/binutils-gdb.git] / gdb / ppc-ravenscar-thread.c

/* Ravenscar PowerPC target support.

   Copyright (C) 2011-2015 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"
#include "gdbcore.h"
#include "regcache.h"
#include "ppc-tdep.h"
#include "inferior.h"
#include "ravenscar-thread.h"
#include "ppc-ravenscar-thread.h"

#define NO_OFFSET -1

/* See ppc-tdep.h for register numbers.  */

static const int powerpc_context_offsets[] =
{
  /* R0 - R32 */
  NO_OFFSET, 0,         4,         NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, 8,         12,        16,
  20,        24,        28,        32,
  36,        40,        44,        48,
  52,        56,        60,        64,
  68,        72,        76,        80,

  /* F0 - F31 */
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, 96,        104,
  112,       120,       128,       136,
  144,       152,       160,       168,
  176,       184,       192,       200,
  208,       216,       224,       232,

  /* PC, MSR, CR, LR */
  88,        NO_OFFSET, 84,        NO_OFFSET,

  /* CTR, XER, FPSCR  */
  NO_OFFSET, NO_OFFSET, 240
};

static const int e500_context_offsets[] =
{
  /* R0 - R32 */
  NO_OFFSET, 4,         12,        NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, 20,        28,        36,
  44,        52,        60,        68,
  76,        84,        92,        100,
  108,       116,       124,       132,
  140,       148,       156,       164,

  /* F0 - F31 */
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,

  /* PC, MSR, CR, LR */
  172,       NO_OFFSET, 168,       NO_OFFSET,

  /* CTR, XER, FPSCR, MQ  */
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,

  /* Upper R0-R32.  */
  NO_OFFSET, 0,         8,        NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  NO_OFFSET, 16,        24,        32,
  40,        48,        56,        64,
  72,        80,        88,        96,
  104,       112,       120,       128,
  136,       144,       152,       160,

  /* ACC, FSCR */
  NO_OFFSET, 176
};

/* The register layout info.  */

struct ravenscar_reg_info
{
  /* A table providing the offset relative to the context structure
     where each register is saved.  */
  const int *context_offsets;

  /* The number of elements in the context_offsets table above.  */
  int context_offsets_size;
};

/* supply register REGNUM, which has been saved on REGISTER_ADDR, to the
   regcache.  */

static void
supply_register_at_address (struct regcache *regcache, int regnum,
                            CORE_ADDR register_addr)
{
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
  int buf_size = register_size (gdbarch, regnum);
  gdb_byte *buf;

  buf = alloca (buf_size);
  read_memory (register_addr, buf, buf_size);
  regcache_raw_supply (regcache, regnum, buf);
}

/* Return true if, for a non-running thread, REGNUM has been saved on the
   Thread_Descriptor.  */

static int
register_in_thread_descriptor_p (const struct ravenscar_reg_info *reg_info,
				 int regnum)
{
  return (regnum < reg_info->context_offsets_size
	  && reg_info->context_offsets[regnum] != NO_OFFSET);
}

/* to_fetch_registers when inferior_ptid is different from the running
   thread.  */

static void
ppc_ravenscar_generic_fetch_registers
  (const struct ravenscar_reg_info *reg_info,
   struct regcache *regcache, int regnum)
{
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
  const int sp_regnum = gdbarch_sp_regnum (gdbarch);
  const int num_regs = gdbarch_num_regs (gdbarch);
  int current_regnum;
  CORE_ADDR current_address;
  CORE_ADDR thread_descriptor_address;

  /* The tid is the thread_id field, which is a pointer to the thread.  */
  thread_descriptor_address = (CORE_ADDR) ptid_get_tid (inferior_ptid);

  /* Read registers.  */
  for (current_regnum = 0; current_regnum < num_regs; current_regnum++)
    {
      if (register_in_thread_descriptor_p (reg_info, current_regnum))
        {
          current_address = thread_descriptor_address
            + reg_info->context_offsets[current_regnum];
          supply_register_at_address (regcache, current_regnum,
                                      current_address);
        }
    }
}

/* to_prepare_to_store when inferior_ptid is different from the running
   thread.  */

static void
ppc_ravenscar_generic_prepare_to_store (struct regcache *regcache)
{
  /* Nothing to do.  */
}

/* to_store_registers when inferior_ptid is different from the running
   thread.  */

static void
ppc_ravenscar_generic_store_registers
  (const struct ravenscar_reg_info *reg_info,
   struct regcache *regcache, int regnum)
{
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
  int buf_size = register_size (gdbarch, regnum);
  gdb_byte buf[buf_size];
  ULONGEST register_address;

  if (register_in_thread_descriptor_p (reg_info, regnum))
    register_address
      = ptid_get_tid (inferior_ptid) + reg_info->context_offsets [regnum];
  else
    return;

  regcache_raw_collect (regcache, regnum, buf);
  write_memory (register_address,
                buf,
                buf_size);
}

/* The ravenscar_reg_info for most PowerPC targets.  */

static const struct ravenscar_reg_info ppc_reg_info =
{
  powerpc_context_offsets,
  ARRAY_SIZE (powerpc_context_offsets),
};

/* Implement the to_fetch_registers ravenscar_arch_ops method
   for most PowerPC targets.  */

static void
ppc_ravenscar_powerpc_fetch_registers (struct regcache *regcache, int regnum)
{
  ppc_ravenscar_generic_fetch_registers (&ppc_reg_info, regcache, regnum);
}

/* Implement the to_store_registers ravenscar_arch_ops method
   for most PowerPC targets.  */

static void
ppc_ravenscar_powerpc_store_registers (struct regcache *regcache, int regnum)
{
  ppc_ravenscar_generic_store_registers (&ppc_reg_info, regcache, regnum);
}

/* The ravenscar_arch_ops vector for most PowerPC targets.  */

static struct ravenscar_arch_ops ppc_ravenscar_powerpc_ops =
{
  ppc_ravenscar_powerpc_fetch_registers,
  ppc_ravenscar_powerpc_store_registers,
  ppc_ravenscar_generic_prepare_to_store
};

/* Register ppc_ravenscar_powerpc_ops in GDBARCH.  */

void
register_ppc_ravenscar_ops (struct gdbarch *gdbarch)
{
  set_gdbarch_ravenscar_ops (gdbarch, &ppc_ravenscar_powerpc_ops);
}

/* The ravenscar_reg_info for E500 targets.  */

static const struct ravenscar_reg_info e500_reg_info =
{
  e500_context_offsets,
  ARRAY_SIZE (e500_context_offsets),
};

/* Implement the to_fetch_registers ravenscar_arch_ops method
   for E500 targets.  */

static void
ppc_ravenscar_e500_fetch_registers (struct regcache *regcache, int regnum)
{
  ppc_ravenscar_generic_fetch_registers (&e500_reg_info, regcache, regnum);
}

/* Implement the to_store_registers ravenscar_arch_ops method
   for E500 targets.  */

static void
ppc_ravenscar_e500_store_registers (struct regcache *regcache, int regnum)
{
  ppc_ravenscar_generic_store_registers (&e500_reg_info, regcache, regnum);
}

/* The ravenscar_arch_ops vector for E500 targets.  */

static struct ravenscar_arch_ops ppc_ravenscar_e500_ops =
{
  ppc_ravenscar_e500_fetch_registers,
  ppc_ravenscar_e500_store_registers,
  ppc_ravenscar_generic_prepare_to_store
};

/* Register ppc_ravenscar_e500_ops in GDBARCH.  */

void
register_e500_ravenscar_ops (struct gdbarch *gdbarch)
{
  set_gdbarch_ravenscar_ops (gdbarch, &ppc_ravenscar_e500_ops);
}
Commit	Line	Data
debb1f09 JB	1	/* Ravenscar PowerPC target support.
debb1f09 JB	2
32d0add0	3	Copyright (C) 2011-2015 Free Software Foundation, Inc.
debb1f09 JB	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	19
	20	#include "defs.h"
	21	#include "gdbcore.h"
	22	#include "regcache.h"
	23	#include "ppc-tdep.h"
	24	#include "inferior.h"
	25	#include "ravenscar-thread.h"
	26	#include "ppc-ravenscar-thread.h"
	27
	28	#define NO_OFFSET -1
	29
	30	/* See ppc-tdep.h for register numbers. */
	31
	32	static const int powerpc_context_offsets[] =
	33	{
	34	/* R0 - R32 */
	35	NO_OFFSET, 0, 4, NO_OFFSET,
	36	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	37	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	38	NO_OFFSET, 8, 12, 16,
	39	20, 24, 28, 32,
	40	36, 40, 44, 48,
	41	52, 56, 60, 64,
	42	68, 72, 76, 80,
	43
	44	/* F0 - F31 */
	45	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	46	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	47	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	48	NO_OFFSET, NO_OFFSET, 96, 104,
	49	112, 120, 128, 136,
	50	144, 152, 160, 168,
	51	176, 184, 192, 200,
	52	208, 216, 224, 232,
	53
	54	/* PC, MSR, CR, LR */
	55	88, NO_OFFSET, 84, NO_OFFSET,
	56
	57	/* CTR, XER, FPSCR */
	58	NO_OFFSET, NO_OFFSET, 240
	59	};
	60
	61	static const int e500_context_offsets[] =
	62	{
	63	/* R0 - R32 */
	64	NO_OFFSET, 4, 12, NO_OFFSET,
	65	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	66	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
	67	NO_OFFSET, 20, 28, 36,
68	44, 52, 60, 68,
69	76, 84, 92, 100,
70	108, 116, 124, 132,
71	140, 148, 156, 164,
72
73	/* F0 - F31 */
74	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
75	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
76	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
77	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
78	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
79	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
80	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
81	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
82
83	/* PC, MSR, CR, LR */
84	172, NO_OFFSET, 168, NO_OFFSET,
85
86	/* CTR, XER, FPSCR, MQ */
87	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
88
89	/* Upper R0-R32. */
90	NO_OFFSET, 0, 8, NO_OFFSET,
91	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
92	NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
93	NO_OFFSET, 16, 24, 32,
94	40, 48, 56, 64,
95	72, 80, 88, 96,
96	104, 112, 120, 128,
97	136, 144, 152, 160,
98
99	/* ACC, FSCR */
100	NO_OFFSET, 176
101	};
102
103	/* The register layout info. */
104
105	struct ravenscar_reg_info
106	{
107	/* A table providing the offset relative to the context structure
108	where each register is saved. */
109	const int *context_offsets;
110
111	/* The number of elements in the context_offsets table above. */
112	int context_offsets_size;
113	};
114
115	/* supply register REGNUM, which has been saved on REGISTER_ADDR, to the
116	regcache. */
117
118	static void
119	supply_register_at_address (struct regcache *regcache, int regnum,
120	CORE_ADDR register_addr)
121	{
122	struct gdbarch *gdbarch = get_regcache_arch (regcache);
123	int buf_size = register_size (gdbarch, regnum);
948f8e3d	124	gdb_byte *buf;
debb1f09	125
948f8e3d	126	buf = alloca (buf_size);
debb1f09 JB	127	read_memory (register_addr, buf, buf_size);
	128	regcache_raw_supply (regcache, regnum, buf);
	129	}
	130
	131	/* Return true if, for a non-running thread, REGNUM has been saved on the
	132	Thread_Descriptor. */
	133
	134	static int
	135	register_in_thread_descriptor_p (const struct ravenscar_reg_info *reg_info,
	136	int regnum)
	137	{
	138	return (regnum < reg_info->context_offsets_size
	139	&& reg_info->context_offsets[regnum] != NO_OFFSET);
	140	}
	141
	142	/* to_fetch_registers when inferior_ptid is different from the running
	143	thread. */
	144
	145	static void
	146	ppc_ravenscar_generic_fetch_registers
	147	(const struct ravenscar_reg_info *reg_info,
	148	struct regcache *regcache, int regnum)
	149	{
	150	struct gdbarch *gdbarch = get_regcache_arch (regcache);
	151	const int sp_regnum = gdbarch_sp_regnum (gdbarch);
	152	const int num_regs = gdbarch_num_regs (gdbarch);
	153	int current_regnum;
	154	CORE_ADDR current_address;
	155	CORE_ADDR thread_descriptor_address;
	156
	157	/* The tid is the thread_id field, which is a pointer to the thread. */
	158	thread_descriptor_address = (CORE_ADDR) ptid_get_tid (inferior_ptid);
	159
	160	/* Read registers. */
	161	for (current_regnum = 0; current_regnum < num_regs; current_regnum++)
	162	{
	163	if (register_in_thread_descriptor_p (reg_info, current_regnum))
	164	{
	165	current_address = thread_descriptor_address
	166	+ reg_info->context_offsets[current_regnum];
	167	supply_register_at_address (regcache, current_regnum,
	168	current_address);
	169	}
	170	}
	171	}
	172
	173	/* to_prepare_to_store when inferior_ptid is different from the running
	174	thread. */
	175
	176	static void
	177	ppc_ravenscar_generic_prepare_to_store (struct regcache *regcache)
	178	{
	179	/* Nothing to do. */
	180	}
	181
	182	/* to_store_registers when inferior_ptid is different from the running
	183	thread. */
	184
	185	static void
	186	ppc_ravenscar_generic_store_registers
	187	(const struct ravenscar_reg_info *reg_info,
	188	struct regcache *regcache, int regnum)
	189	{
	190	struct gdbarch *gdbarch = get_regcache_arch (regcache);
191	int buf_size = register_size (gdbarch, regnum);
948f8e3d	192	gdb_byte buf[buf_size];
debb1f09 JB	193	ULONGEST register_address;
	194
	195	if (register_in_thread_descriptor_p (reg_info, regnum))
	196	register_address
	197	= ptid_get_tid (inferior_ptid) + reg_info->context_offsets [regnum];
	198	else
	199	return;
	200
	201	regcache_raw_collect (regcache, regnum, buf);
	202	write_memory (register_address,
	203	buf,
	204	buf_size);
	205	}
	206
	207	/* The ravenscar_reg_info for most PowerPC targets. */
	208
	209	static const struct ravenscar_reg_info ppc_reg_info =
	210	{
	211	powerpc_context_offsets,
	212	ARRAY_SIZE (powerpc_context_offsets),
	213	};
	214
	215	/* Implement the to_fetch_registers ravenscar_arch_ops method
	216	for most PowerPC targets. */
	217
	218	static void
	219	ppc_ravenscar_powerpc_fetch_registers (struct regcache *regcache, int regnum)
	220	{
	221	ppc_ravenscar_generic_fetch_registers (&ppc_reg_info, regcache, regnum);
	222	}
	223
	224	/* Implement the to_store_registers ravenscar_arch_ops method
	225	for most PowerPC targets. */
	226
	227	static void
	228	ppc_ravenscar_powerpc_store_registers (struct regcache *regcache, int regnum)
	229	{
	230	ppc_ravenscar_generic_store_registers (&ppc_reg_info, regcache, regnum);
	231	}
	232
	233	/* The ravenscar_arch_ops vector for most PowerPC targets. */
	234
	235	static struct ravenscar_arch_ops ppc_ravenscar_powerpc_ops =
	236	{
	237	ppc_ravenscar_powerpc_fetch_registers,
	238	ppc_ravenscar_powerpc_store_registers,
	239	ppc_ravenscar_generic_prepare_to_store
	240	};
	241
	242	/* Register ppc_ravenscar_powerpc_ops in GDBARCH. */
	243
	244	void
	245	register_ppc_ravenscar_ops (struct gdbarch *gdbarch)
	246	{
	247	set_gdbarch_ravenscar_ops (gdbarch, &ppc_ravenscar_powerpc_ops);
	248	}
	249
	250	/* The ravenscar_reg_info for E500 targets. */
	251
	252	static const struct ravenscar_reg_info e500_reg_info =
	253	{
	254	e500_context_offsets,
	255	ARRAY_SIZE (e500_context_offsets),
	256	};
257
258	/* Implement the to_fetch_registers ravenscar_arch_ops method
259	for E500 targets. */
260
261	static void
262	ppc_ravenscar_e500_fetch_registers (struct regcache *regcache, int regnum)
263	{
264	ppc_ravenscar_generic_fetch_registers (&e500_reg_info, regcache, regnum);
265	}
266
267	/* Implement the to_store_registers ravenscar_arch_ops method
268	for E500 targets. */
269
270	static void
271	ppc_ravenscar_e500_store_registers (struct regcache *regcache, int regnum)
272	{
273	ppc_ravenscar_generic_store_registers (&e500_reg_info, regcache, regnum);
274	}
275
276	/* The ravenscar_arch_ops vector for E500 targets. */
277
278	static struct ravenscar_arch_ops ppc_ravenscar_e500_ops =
279	{
280	ppc_ravenscar_e500_fetch_registers,
281	ppc_ravenscar_e500_store_registers,
282	ppc_ravenscar_generic_prepare_to_store
283	};
284
285	/* Register ppc_ravenscar_e500_ops in GDBARCH. */
286
287	void
288	register_e500_ravenscar_ops (struct gdbarch *gdbarch)
289	{
290	set_gdbarch_ravenscar_ops (gdbarch, &ppc_ravenscar_e500_ops);
291	}