[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street, Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-linux-tdep.c... */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
						    CORE_ADDR bpaddr);
int ppc_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt);
struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
void ppc_linux_supply_gregset (struct regcache *regcache,
			       int regnum, const void *gregs, size_t size,
			       int wordsize);
void ppc_linux_supply_fpregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t size);

enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c... */
int altivec_register_p (int regno);
int spe_register_p (int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;

  /* AltiVec registers.  */
  int vr0_offset;
  int vscr_offset;
  int vrsave_offset;
};

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET. from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET. from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Private data that this module attaches to struct gdbarch. */

struct gdbarch_tdep
  {
    int wordsize;              /* size in bytes of fixed-point word */
    const struct reg *regs;    /* from current variant */
    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* floating-point register 0 */
    int ppc_fpscr_regnum;	/* fp status and condition register */

    /* Segment registers.  */
    int ppc_sr0_regnum;         /* segment register 0 */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register */
    int ppc_vrsave_regnum;	/* Last AltiVec register */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register */
    int ppc_ev0_regnum;         /* First ev register */
    int ppc_ev31_regnum;        /* Last ev register */
    int ppc_acc_regnum;         /* SPE 'acc' register */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register */

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* Minimum possible text address.  */
    CORE_ADDR text_segment_base;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
    struct type *ppc_builtin_type_vec128;
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,          /* 32 general-purpose registers */
    ppc_num_fprs = 32,          /* 32 floating-point registers */
    ppc_num_srs = 16,           /* 16 segment registers */
    ppc_num_vrs = 32            /* 32 Altivec vector registers */
  };


/* Constants for SPR register numbers.  These are *not* GDB register
   numbers: they are the numbers used in the PowerPC ISA itself to
   refer to these registers.

   This table includes all the SPRs from all the variants I could find
   documentation for.

   There may be registers from different PowerPC variants assigned the
   same number, but that's fine: GDB and the SIM always use the
   numbers in the context of a particular variant, so it's not
   ambiguous.

   We need to deviate from the naming pattern when variants have
   special-purpose registers of the same name, but with different
   numbers.  Fortunately, this is rare: look below to see how we
   handle the 'tcr' registers on the 403/403GX and 602.  */

enum
  {
    ppc_spr_mq        =    0,
    ppc_spr_xer       =    1,
    ppc_spr_rtcu      =    4,
    ppc_spr_rtcl      =    5,
    ppc_spr_lr        =    8,
    ppc_spr_ctr       =    9,
    ppc_spr_cnt       =    9,
    ppc_spr_dsisr     =   18,
    ppc_spr_dar       =   19,
    ppc_spr_dec       =   22,
    ppc_spr_sdr1      =   25,
    ppc_spr_srr0      =   26,
    ppc_spr_srr1      =   27,
    ppc_spr_eie       =   80,
    ppc_spr_eid       =   81,
    ppc_spr_nri       =   82,
    ppc_spr_sp        =  102,
    ppc_spr_cmpa      =  144,
    ppc_spr_cmpb      =  145,
    ppc_spr_cmpc      =  146,
    ppc_spr_cmpd      =  147,
    ppc_spr_icr       =  148,
    ppc_spr_der       =  149,
    ppc_spr_counta    =  150,
    ppc_spr_countb    =  151,
    ppc_spr_cmpe      =  152,
    ppc_spr_cmpf      =  153,
    ppc_spr_cmpg      =  154,
    ppc_spr_cmph      =  155,
    ppc_spr_lctrl1    =  156,
    ppc_spr_lctrl2    =  157,
    ppc_spr_ictrl     =  158,
    ppc_spr_bar       =  159,
    ppc_spr_vrsave    =  256,
    ppc_spr_sprg0     =  272,
    ppc_spr_sprg1     =  273,
    ppc_spr_sprg2     =  274,
    ppc_spr_sprg3     =  275,
    ppc_spr_asr       =  280,
    ppc_spr_ear       =  282,
    ppc_spr_tbl       =  284,
    ppc_spr_tbu       =  285,
    ppc_spr_pvr       =  287,
    ppc_spr_spefscr   =  512,
    ppc_spr_ibat0u    =  528,
    ppc_spr_ibat0l    =  529,
    ppc_spr_ibat1u    =  530,
    ppc_spr_ibat1l    =  531,
    ppc_spr_ibat2u    =  532,
    ppc_spr_ibat2l    =  533,
    ppc_spr_ibat3u    =  534,
    ppc_spr_ibat3l    =  535,
    ppc_spr_dbat0u    =  536,
    ppc_spr_dbat0l    =  537,
    ppc_spr_dbat1u    =  538,
    ppc_spr_dbat1l    =  539,
    ppc_spr_dbat2u    =  540,
    ppc_spr_dbat2l    =  541,
    ppc_spr_dbat3u    =  542,
    ppc_spr_dbat3l    =  543,
    ppc_spr_ic_cst    =  560,
    ppc_spr_ic_adr    =  561,
    ppc_spr_ic_dat    =  562,
    ppc_spr_dc_cst    =  568,
    ppc_spr_dc_adr    =  569,
    ppc_spr_dc_dat    =  570,
    ppc_spr_dpdr      =  630,
    ppc_spr_dpir      =  631,
    ppc_spr_immr      =  638,
    ppc_spr_mi_ctr    =  784,
    ppc_spr_mi_ap     =  786,
    ppc_spr_mi_epn    =  787,
    ppc_spr_mi_twc    =  789,
    ppc_spr_mi_rpn    =  790,
    ppc_spr_mi_cam    =  816,
    ppc_spr_mi_ram0   =  817,
    ppc_spr_mi_ram1   =  818,
    ppc_spr_md_ctr    =  792,
    ppc_spr_m_casid   =  793,
    ppc_spr_md_ap     =  794,
    ppc_spr_md_epn    =  795,
    ppc_spr_m_twb     =  796,
    ppc_spr_md_twc    =  797,
    ppc_spr_md_rpn    =  798,
    ppc_spr_m_tw      =  799,
    ppc_spr_mi_dbcam  =  816,
    ppc_spr_mi_dbram0 =  817,
    ppc_spr_mi_dbram1 =  818,
    ppc_spr_md_dbcam  =  824,
    ppc_spr_md_cam    =  824,
    ppc_spr_md_dbram0 =  825,
    ppc_spr_md_ram0   =  825,
    ppc_spr_md_dbram1 =  826,
    ppc_spr_md_ram1   =  826,
    ppc_spr_ummcr0    =  936,
    ppc_spr_upmc1     =  937,
    ppc_spr_upmc2     =  938,
    ppc_spr_usia      =  939,
    ppc_spr_ummcr1    =  940,
    ppc_spr_upmc3     =  941,
    ppc_spr_upmc4     =  942,
    ppc_spr_zpr       =  944,
    ppc_spr_pid       =  945,
    ppc_spr_mmcr0     =  952,
    ppc_spr_pmc1      =  953,
    ppc_spr_sgr       =  953,
    ppc_spr_pmc2      =  954,
    ppc_spr_dcwr      =  954,
    ppc_spr_sia       =  955,
    ppc_spr_mmcr1     =  956,
    ppc_spr_pmc3      =  957,
    ppc_spr_pmc4      =  958,
    ppc_spr_sda       =  959,
    ppc_spr_tbhu      =  972,
    ppc_spr_tblu      =  973,
    ppc_spr_dmiss     =  976,
    ppc_spr_dcmp      =  977,
    ppc_spr_hash1     =  978,
    ppc_spr_hash2     =  979,
    ppc_spr_icdbdr    =  979,
    ppc_spr_imiss     =  980,
    ppc_spr_esr       =  980,
    ppc_spr_icmp      =  981,
    ppc_spr_dear      =  981,
    ppc_spr_rpa       =  982,
    ppc_spr_evpr      =  982,
    ppc_spr_cdbcr     =  983,
    ppc_spr_tsr       =  984,
    ppc_spr_602_tcr   =  984,
    ppc_spr_403_tcr   =  986,
    ppc_spr_ibr       =  986,
    ppc_spr_pit       =  987,
    ppc_spr_esasrr    =  988,
    ppc_spr_tbhi      =  988,
    ppc_spr_tblo      =  989,
    ppc_spr_srr2      =  990,
    ppc_spr_sebr      =  990,
    ppc_spr_srr3      =  991,
    ppc_spr_ser       =  991,
    ppc_spr_hid0      = 1008,
    ppc_spr_dbsr      = 1008,
    ppc_spr_hid1      = 1009,
    ppc_spr_iabr      = 1010,
    ppc_spr_dbcr      = 1010,
    ppc_spr_iac1      = 1012,
    ppc_spr_dabr      = 1013,
    ppc_spr_iac2      = 1013,
    ppc_spr_dac1      = 1014,
    ppc_spr_dac2      = 1015,
    ppc_spr_l2cr      = 1017,
    ppc_spr_dccr      = 1018,
    ppc_spr_ictc      = 1019,
    ppc_spr_iccr      = 1019,
    ppc_spr_thrm1     = 1020,
    ppc_spr_pbl1      = 1020,
    ppc_spr_thrm2     = 1021,
    ppc_spr_pbu1      = 1021,
    ppc_spr_thrm3     = 1022,
    ppc_spr_pbl2      = 1022,
    ppc_spr_fpecr     = 1022,
    ppc_spr_lt        = 1022,
    ppc_spr_pir       = 1023,
    ppc_spr_pbu2      = 1023
  };

/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
6aba47ca	3	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007
a0c75879	4	Free Software Foundation, Inc.
9aa1e687 KB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
197e01b6 EZ	20	Foundation, Inc., 51 Franklin Street, Fifth Floor,
197e01b6 EZ	21	Boston, MA 02110-1301, USA. */
9aa1e687	22
3a1c5313 AC	23	#ifndef PPC_TDEP_H
	24	#define PPC_TDEP_H
	25
da3331ec	26	struct gdbarch;
3a1c5313 AC	27	struct frame_info;
3a1c5313 AC	28	struct value;
4a4b3fed	29	struct regcache;
221c12ff	30	struct type;
3a1c5313	31
9aa1e687	32	/* From ppc-linux-tdep.c... */
05580c65 AC	33	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
	34	struct type *valtype,
	35	struct regcache *regcache,
50fd1280 AC	36	gdb_byte *readbuf,
50fd1280 AC	37	const gdb_byte *writebuf);
05580c65 AC	38	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
	39	struct type *valtype,
	40	struct regcache *regcache,
50fd1280 AC	41	gdb_byte *readbuf,
50fd1280 AC	42	const gdb_byte *writebuf);
77b2b6d4	43	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	44	struct value *function,
77b2b6d4 AC	45	struct regcache *regcache,
	46	CORE_ADDR bp_addr, int nargs,
	47	struct value **args, CORE_ADDR sp,
	48	int struct_return,
	49	CORE_ADDR struct_addr);
8be9034a	50	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	51	struct value *function,
8be9034a AC	52	struct regcache *regcache,
	53	CORE_ADDR bp_addr, int nargs,
	54	struct value **args, CORE_ADDR sp,
	55	int struct_return,
	56	CORE_ADDR struct_addr);
6066c3de AC	57	CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
6066c3de AC	58	CORE_ADDR bpaddr);
8181d85f	59	int ppc_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt);
6ded7999	60	struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
f9be684a AC	61	void ppc_linux_supply_gregset (struct regcache *regcache,
	62	int regnum, const void *gregs, size_t size,
	63	int wordsize);
	64	void ppc_linux_supply_fpregset (const struct regset *regset,
	65	struct regcache *regcache,
	66	int regnum, const void *gregs, size_t size);
9aa1e687	67
05580c65 AC	68	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
	69	struct type *valtype,
	70	struct regcache *regcache,
50fd1280 AC	71	gdb_byte *readbuf,
50fd1280 AC	72	const gdb_byte *writebuf);
9aa1e687 KB	73
9aa1e687 KB	74	/* From rs6000-tdep.c... */
1fcc0bb8	75	int altivec_register_p (int regno);
867e2dc5	76	int spe_register_p (int regno);
9aa1e687	77
383f0f5b JB	78	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	79	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	80	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	81
d195bc9f MK	82	/* Register set description. */
	83
	84	struct ppc_reg_offsets
	85	{
	86	/* General-purpose registers. */
	87	int r0_offset;
	88	int pc_offset;
	89	int ps_offset;
	90	int cr_offset;
	91	int lr_offset;
	92	int ctr_offset;
	93	int xer_offset;
	94	int mq_offset;
	95
	96	/* Floating-point registers. */
	97	int f0_offset;
	98	int fpscr_offset;
	99
	100	/* AltiVec registers. */
	101	int vr0_offset;
	102	int vscr_offset;
	103	int vrsave_offset;
	104	};
	105
	106	/* Supply register REGNUM in the general-purpose register set REGSET
	107	from the buffer specified by GREGS and LEN to register cache
	108	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	109
	110	extern void ppc_supply_gregset (const struct regset *regset,
	111	struct regcache *regcache,
	112	int regnum, const void *gregs, size_t len);
	113
	114	/* Supply register REGNUM in the floating-point register set REGSET
	115	from the buffer specified by FPREGS and LEN to register cache
	116	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	117
	118	extern void ppc_supply_fpregset (const struct regset *regset,
	119	struct regcache *regcache,
	120	int regnum, const void *fpregs, size_t len);
	121
	122	/* Collect register REGNUM in the general-purpose register set
	123	REGSET. from register cache REGCACHE into the buffer specified by
	124	GREGS and LEN. If REGNUM is -1, do this for all registers in
	125	REGSET. */
	126
	127	extern void ppc_collect_gregset (const struct regset *regset,
	128	const struct regcache *regcache,
	129	int regnum, void *gregs, size_t len);
	130
	131	/* Collect register REGNUM in the floating-point register set
	132	REGSET. from register cache REGCACHE into the buffer specified by
	133	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	134	REGSET. */
	135
	136	extern void ppc_collect_fpregset (const struct regset *regset,
	137	const struct regcache *regcache,
	138	int regnum, void *fpregs, size_t len);
	139
2188cbdd EZ	140	/* Private data that this module attaches to struct gdbarch. */
	141
	142	struct gdbarch_tdep
	143	{
	144	int wordsize; /* size in bytes of fixed-point word */
2188cbdd EZ	145	const struct reg regs; / from current variant */
2188cbdd EZ	146	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	147	int ppc_toc_regnum; /* TOC register */
	148	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	149	int ppc_cr_regnum; /* Condition register */
	150	int ppc_lr_regnum; /* Link register */
	151	int ppc_ctr_regnum; /* Count register */
	152	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	153
826d5376 PG	154	/* Not all PPC and RS6000 variants will have the registers
	155	represented below. A -1 is used to indicate that the register
	156	is not present in this variant. */
	157
	158	/* Floating-point registers. */
366f009f	159	int ppc_fp0_regnum; /* floating-point register 0 */
826d5376 PG	160	int ppc_fpscr_regnum; /* fp status and condition register */
	161
	162	/* Segment registers. */
	163	int ppc_sr0_regnum; /* segment register 0 */
383f0f5b	164
826d5376 PG	165	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	166	int ppc_mq_regnum;
f86a7158	167
826d5376	168	/* Altivec registers. */
1fcc0bb8 EZ	169	int ppc_vr0_regnum; /* First AltiVec register */
1fcc0bb8 EZ	170	int ppc_vrsave_regnum; /* Last AltiVec register */
826d5376 PG	171
826d5376 PG	172	/* SPE registers. */
6ced10dd	173	int ppc_ev0_upper_regnum; /* First GPR upper half register */
c8001721 EZ	174	int ppc_ev0_regnum; /* First ev register */
c8001721 EZ	175	int ppc_ev31_regnum; /* Last ev register */
867e2dc5 JB	176	int ppc_acc_regnum; /* SPE 'acc' register */
867e2dc5 JB	177	int ppc_spefscr_regnum; /* SPE 'spefscr' register */
826d5376 PG	178
	179	/* Offset to ABI specific location where link register is saved. */
	180	int lr_frame_offset;
9f643768 JB	181
	182	/* An array of integers, such that sim_regno[I] is the simulator
	183	register number for GDB register number I, or -1 if the
	184	simulator does not implement that register. */
	185	int *sim_regno;
6f7f3f0d UW	186
	187	/* Minimum possible text address. */
	188	CORE_ADDR text_segment_base;
794ac428 UW	189
	190	/* ISA-specific types. */
	191	struct type *ppc_builtin_type_vec64;
	192	struct type *ppc_builtin_type_vec128;
2188cbdd	193	};
3a1c5313	194
b967e06f JB	195
	196	/* Constants for register set sizes. */
	197	enum
	198	{
8bf659e8	199	ppc_num_gprs = 32, /* 32 general-purpose registers */
cc98b5cc	200	ppc_num_fprs = 32, /* 32 floating-point registers */
8f088af7	201	ppc_num_srs = 16, /* 16 segment registers */
cc98b5cc	202	ppc_num_vrs = 32 /* 32 Altivec vector registers */
b967e06f JB	203	};
b967e06f JB	204
0ea0ec5f JB	205
	206	/* Constants for SPR register numbers. These are not GDB register
	207	numbers: they are the numbers used in the PowerPC ISA itself to
	208	refer to these registers.
	209
	210	This table includes all the SPRs from all the variants I could find
	211	documentation for.
	212
	213	There may be registers from different PowerPC variants assigned the
	214	same number, but that's fine: GDB and the SIM always use the
	215	numbers in the context of a particular variant, so it's not
	216	ambiguous.
	217
	218	We need to deviate from the naming pattern when variants have
	219	special-purpose registers of the same name, but with different
	220	numbers. Fortunately, this is rare: look below to see how we
	221	handle the 'tcr' registers on the 403/403GX and 602. */
	222
	223	enum
	224	{
	225	ppc_spr_mq = 0,
	226	ppc_spr_xer = 1,
	227	ppc_spr_rtcu = 4,
	228	ppc_spr_rtcl = 5,
	229	ppc_spr_lr = 8,
	230	ppc_spr_ctr = 9,
	231	ppc_spr_cnt = 9,
	232	ppc_spr_dsisr = 18,
	233	ppc_spr_dar = 19,
	234	ppc_spr_dec = 22,
	235	ppc_spr_sdr1 = 25,
	236	ppc_spr_srr0 = 26,
	237	ppc_spr_srr1 = 27,
	238	ppc_spr_eie = 80,
	239	ppc_spr_eid = 81,
	240	ppc_spr_nri = 82,
	241	ppc_spr_sp = 102,
	242	ppc_spr_cmpa = 144,
	243	ppc_spr_cmpb = 145,
	244	ppc_spr_cmpc = 146,
	245	ppc_spr_cmpd = 147,
	246	ppc_spr_icr = 148,
	247	ppc_spr_der = 149,
	248	ppc_spr_counta = 150,
	249	ppc_spr_countb = 151,
	250	ppc_spr_cmpe = 152,
	251	ppc_spr_cmpf = 153,
	252	ppc_spr_cmpg = 154,
	253	ppc_spr_cmph = 155,
	254	ppc_spr_lctrl1 = 156,
	255	ppc_spr_lctrl2 = 157,
	256	ppc_spr_ictrl = 158,
	257	ppc_spr_bar = 159,
	258	ppc_spr_vrsave = 256,
	259	ppc_spr_sprg0 = 272,
	260	ppc_spr_sprg1 = 273,
	261	ppc_spr_sprg2 = 274,
	262	ppc_spr_sprg3 = 275,
5109a438	263	ppc_spr_asr = 280,
0ea0ec5f JB	264	ppc_spr_ear = 282,
	265	ppc_spr_tbl = 284,
	266	ppc_spr_tbu = 285,
	267	ppc_spr_pvr = 287,
	268	ppc_spr_spefscr = 512,
	269	ppc_spr_ibat0u = 528,
	270	ppc_spr_ibat0l = 529,
	271	ppc_spr_ibat1u = 530,
	272	ppc_spr_ibat1l = 531,
	273	ppc_spr_ibat2u = 532,
	274	ppc_spr_ibat2l = 533,
	275	ppc_spr_ibat3u = 534,
	276	ppc_spr_ibat3l = 535,
	277	ppc_spr_dbat0u = 536,
	278	ppc_spr_dbat0l = 537,
	279	ppc_spr_dbat1u = 538,
	280	ppc_spr_dbat1l = 539,
	281	ppc_spr_dbat2u = 540,
	282	ppc_spr_dbat2l = 541,
	283	ppc_spr_dbat3u = 542,
	284	ppc_spr_dbat3l = 543,
	285	ppc_spr_ic_cst = 560,
	286	ppc_spr_ic_adr = 561,
	287	ppc_spr_ic_dat = 562,
	288	ppc_spr_dc_cst = 568,
	289	ppc_spr_dc_adr = 569,
	290	ppc_spr_dc_dat = 570,
	291	ppc_spr_dpdr = 630,
	292	ppc_spr_dpir = 631,
	293	ppc_spr_immr = 638,
	294	ppc_spr_mi_ctr = 784,
	295	ppc_spr_mi_ap = 786,
	296	ppc_spr_mi_epn = 787,
	297	ppc_spr_mi_twc = 789,
	298	ppc_spr_mi_rpn = 790,
	299	ppc_spr_mi_cam = 816,
	300	ppc_spr_mi_ram0 = 817,
	301	ppc_spr_mi_ram1 = 818,
	302	ppc_spr_md_ctr = 792,
	303	ppc_spr_m_casid = 793,
	304	ppc_spr_md_ap = 794,
	305	ppc_spr_md_epn = 795,
5109a438	306	ppc_spr_m_twb = 796,
0ea0ec5f JB	307	ppc_spr_md_twc = 797,
	308	ppc_spr_md_rpn = 798,
	309	ppc_spr_m_tw = 799,
5109a438 JB	310	ppc_spr_mi_dbcam = 816,
	311	ppc_spr_mi_dbram0 = 817,
	312	ppc_spr_mi_dbram1 = 818,
0ea0ec5f	313	ppc_spr_md_dbcam = 824,
5109a438	314	ppc_spr_md_cam = 824,
0ea0ec5f	315	ppc_spr_md_dbram0 = 825,
5109a438	316	ppc_spr_md_ram0 = 825,
0ea0ec5f	317	ppc_spr_md_dbram1 = 826,
5109a438	318	ppc_spr_md_ram1 = 826,
0ea0ec5f JB	319	ppc_spr_ummcr0 = 936,
	320	ppc_spr_upmc1 = 937,
	321	ppc_spr_upmc2 = 938,
	322	ppc_spr_usia = 939,
	323	ppc_spr_ummcr1 = 940,
	324	ppc_spr_upmc3 = 941,
	325	ppc_spr_upmc4 = 942,
	326	ppc_spr_zpr = 944,
	327	ppc_spr_pid = 945,
	328	ppc_spr_mmcr0 = 952,
	329	ppc_spr_pmc1 = 953,
	330	ppc_spr_sgr = 953,
	331	ppc_spr_pmc2 = 954,
	332	ppc_spr_dcwr = 954,
	333	ppc_spr_sia = 955,
	334	ppc_spr_mmcr1 = 956,
	335	ppc_spr_pmc3 = 957,
	336	ppc_spr_pmc4 = 958,
	337	ppc_spr_sda = 959,
	338	ppc_spr_tbhu = 972,
	339	ppc_spr_tblu = 973,
	340	ppc_spr_dmiss = 976,
	341	ppc_spr_dcmp = 977,
	342	ppc_spr_hash1 = 978,
	343	ppc_spr_hash2 = 979,
	344	ppc_spr_icdbdr = 979,
	345	ppc_spr_imiss = 980,
	346	ppc_spr_esr = 980,
	347	ppc_spr_icmp = 981,
	348	ppc_spr_dear = 981,
	349	ppc_spr_rpa = 982,
	350	ppc_spr_evpr = 982,
	351	ppc_spr_cdbcr = 983,
	352	ppc_spr_tsr = 984,
	353	ppc_spr_602_tcr = 984,
	354	ppc_spr_403_tcr = 986,
	355	ppc_spr_ibr = 986,
	356	ppc_spr_pit = 987,
	357	ppc_spr_esasrr = 988,
	358	ppc_spr_tbhi = 988,
	359	ppc_spr_tblo = 989,
	360	ppc_spr_srr2 = 990,
	361	ppc_spr_sebr = 990,
	362	ppc_spr_srr3 = 991,
	363	ppc_spr_ser = 991,
	364	ppc_spr_hid0 = 1008,
	365	ppc_spr_dbsr = 1008,
	366	ppc_spr_hid1 = 1009,
	367	ppc_spr_iabr = 1010,
	368	ppc_spr_dbcr = 1010,
	369	ppc_spr_iac1 = 1012,
	370	ppc_spr_dabr = 1013,
	371	ppc_spr_iac2 = 1013,
	372	ppc_spr_dac1 = 1014,
	373	ppc_spr_dac2 = 1015,
	374	ppc_spr_l2cr = 1017,
	375	ppc_spr_dccr = 1018,
	376	ppc_spr_ictc = 1019,
	377	ppc_spr_iccr = 1019,
	378	ppc_spr_thrm1 = 1020,
	379	ppc_spr_pbl1 = 1020,
	380	ppc_spr_thrm2 = 1021,
	381	ppc_spr_pbu1 = 1021,
	382	ppc_spr_thrm3 = 1022,
383	ppc_spr_pbl2 = 1022,
384	ppc_spr_fpecr = 1022,
385	ppc_spr_lt = 1022,
386	ppc_spr_pir = 1023,
387	ppc_spr_pbu2 = 1023
388	};
389
a0c75879 MK	390	/* Instruction size. */
	391	#define PPC_INSN_SIZE 4
	392
0d1243d9 PG	393	/* Estimate for the maximum number of instrctions in a function epilogue. */
	394	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	395
a0c75879	396	#endif /* ppc-tdep.h */