[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000-2018 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-sysv-tdep.c ...  */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct value *function,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct value *function,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct value *function,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c...  */
int altivec_register_p (struct gdbarch *gdbarch, int regno);
int vsx_register_p (struct gdbarch *gdbarch, int regno);
int spe_register_p (struct gdbarch *gdbarch, int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
int ppc_altivec_support_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   VSX registers (vsr0 --- vsr63).  */
int vsx_support_p (struct gdbarch *gdbarch);
std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
  (struct regcache *regcache);


/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  int xr_size;  /* size for cr, xer, mq.  */
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;
  int fpscr_size;
};

extern void ppc_supply_reg (struct regcache *regcache, int regnum,
			    const gdb_byte *regs, size_t offset, int regsize);

extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
			     gdb_byte *regs, size_t offset, int regsize);

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Supply register REGNUM in the Altivec register set REGSET
   from the buffer specified by VRREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vrregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vrregs, size_t len);

/* Supply register REGNUM in the VSX register set REGSET
   from the buffer specified by VSXREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vsxregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vsxregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET, from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET, from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Collect register REGNUM in the Altivec register set
   REGSET from register cache REGCACHE into the buffer specified by
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vrregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vrregs, size_t len);

/* Collect register REGNUM in the VSX register set
   REGSET from register cache REGCACHE into the buffer specified by
   VSXREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vsxregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vsxregs, size_t len);

/* Private data that this module attaches to struct gdbarch.  */

/* ELF ABI version used by the inferior.  */
enum powerpc_elf_abi
{
  POWERPC_ELF_AUTO,
  POWERPC_ELF_V1,
  POWERPC_ELF_V2,
  POWERPC_ELF_LAST
};

/* Vector ABI used by the inferior.  */
enum powerpc_vector_abi
{
  POWERPC_VEC_AUTO,
  POWERPC_VEC_GENERIC,
  POWERPC_VEC_ALTIVEC,
  POWERPC_VEC_SPE,
  POWERPC_VEC_LAST
};

/* long double ABI version used by the inferior.  */
enum powerpc_long_double_abi
{
  POWERPC_LONG_DOUBLE_AUTO,
  POWERPC_LONG_DOUBLE_IBM128,
  POWERPC_LONG_DOUBLE_IEEE128,
  POWERPC_LONG_DOUBLE_LAST
};

struct gdbarch_tdep
  {
    int wordsize;		/* Size in bytes of fixed-point word.  */
    int soft_float;		/* Avoid FP registers for arguments?  */

    enum powerpc_elf_abi elf_abi;	/* ELF ABI version.  */

    /* Format to use for the "long double" data type.  */
    enum powerpc_long_double_abi long_double_abi;

    /* How to pass vector arguments.  Never set to AUTO or LAST.  */
    enum powerpc_vector_abi vector_abi;

    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* Floating-point register 0.  */
    int ppc_fpscr_regnum;	/* fp status and condition register.  */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* POWER7 VSX registers.  */
    int ppc_vsr0_regnum;	/* First VSX register.  */
    int ppc_vsr0_upper_regnum;  /* First right most dword vsx register.  */
    int ppc_efpr0_regnum;	/* First Extended FP register.  */

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register.  */
    int ppc_vrsave_regnum;	/* Last AltiVec register.  */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register.  */
    int ppc_ev0_regnum;         /* First ev register.  */
    int ppc_acc_regnum;         /* SPE 'acc' register.  */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register.  */

    /* Program Priority Register.  */
    int ppc_ppr_regnum;

    /* Data Stream Control Register.  */
    int ppc_dscr_regnum;

    /* Target Address Register.  */
    int ppc_tar_regnum;

    /* Decimal 128 registers.  */
    int ppc_dl0_regnum;		/* First Decimal128 argument register pair.  */

    int have_ebb;

    /* PMU registers.  */
    int ppc_mmcr0_regnum;
    int ppc_mmcr2_regnum;
    int ppc_siar_regnum;
    int ppc_sdar_regnum;
    int ppc_sier_regnum;

    /* Hardware Transactional Memory registers.  */
    int have_htm_spr;
    int have_htm_core;
    int have_htm_fpu;
    int have_htm_altivec;
    int have_htm_vsx;
    int ppc_cppr_regnum;
    int ppc_cdscr_regnum;
    int ppc_ctar_regnum;

    /* HTM pseudo registers.  */
    int ppc_cdl0_regnum;
    int ppc_cvsr0_regnum;
    int ppc_cefpr0_regnum;

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
    struct type *ppc_builtin_type_vec128;

    int (*ppc_syscall_record) (struct regcache *regcache);
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,		/* 32 general-purpose registers.  */
    ppc_num_fprs = 32,		/* 32 floating-point registers.  */
    ppc_num_srs = 16,		/* 16 segment registers.  */
    ppc_num_vrs = 32,		/* 32 Altivec vector registers.  */
    ppc_num_vshrs = 32,		/* 32 doublewords (dword 1 of vs0~vs31).  */
    ppc_num_vsrs = 64,		/* 64 VSX vector registers.  */
    ppc_num_efprs = 32		/* 32 Extended FP registers.  */
  };


/* Register number constants.  These are GDB internal register
   numbers; they are not used for the simulator or remote targets.
   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
   numbers above PPC_NUM_REGS.  So are segment registers and other
   target-defined registers.  */
enum {
  PPC_R0_REGNUM = 0,
  PPC_F0_REGNUM = 32,
  PPC_PC_REGNUM = 64,
  PPC_MSR_REGNUM = 65,
  PPC_CR_REGNUM = 66,
  PPC_LR_REGNUM = 67,
  PPC_CTR_REGNUM = 68,
  PPC_XER_REGNUM = 69,
  PPC_FPSCR_REGNUM = 70,
  PPC_MQ_REGNUM = 71,
  PPC_SPE_UPPER_GP0_REGNUM = 72,
  PPC_SPE_ACC_REGNUM = 104,
  PPC_SPE_FSCR_REGNUM = 105,
  PPC_VR0_REGNUM = 106,
  PPC_VSCR_REGNUM = 138,
  PPC_VRSAVE_REGNUM = 139,
  PPC_VSR0_UPPER_REGNUM = 140,
  PPC_VSR31_UPPER_REGNUM = 171,
  PPC_PPR_REGNUM = 172,
  PPC_DSCR_REGNUM = 173,
  PPC_TAR_REGNUM = 174,

  /* EBB registers.  */
  PPC_BESCR_REGNUM = 175,
  PPC_EBBHR_REGNUM = 176,
  PPC_EBBRR_REGNUM = 177,

  /* PMU registers.  */
  PPC_MMCR0_REGNUM = 178,
  PPC_MMCR2_REGNUM = 179,
  PPC_SIAR_REGNUM = 180,
  PPC_SDAR_REGNUM = 181,
  PPC_SIER_REGNUM = 182,

  /* Hardware transactional memory registers.  */
  PPC_TFHAR_REGNUM = 183,
  PPC_TEXASR_REGNUM = 184,
  PPC_TFIAR_REGNUM = 185,

  PPC_CR0_REGNUM = 186,
  PPC_CCR_REGNUM = 218,
  PPC_CXER_REGNUM = 219,
  PPC_CLR_REGNUM = 220,
  PPC_CCTR_REGNUM = 221,

  PPC_CF0_REGNUM = 222,
  PPC_CFPSCR_REGNUM = 254,

  PPC_CVR0_REGNUM = 255,
  PPC_CVSCR_REGNUM = 287,
  PPC_CVRSAVE_REGNUM = 288,

  PPC_CVSR0_UPPER_REGNUM = 289,

  PPC_CPPR_REGNUM = 321,
  PPC_CDSCR_REGNUM = 322,
  PPC_CTAR_REGNUM = 323,
  PPC_NUM_REGS
};

/* Big enough to hold the size of the largest register in bytes.  */
#define PPC_MAX_REGISTER_SIZE	64

#define PPC_IS_EBB_REGNUM(i) \
	((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)

#define PPC_IS_PMU_REGNUM(i) \
	((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)

#define PPC_IS_TMSPR_REGNUM(i) \
  ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)

#define PPC_IS_CKPTGP_REGNUM(i) \
  ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)

#define PPC_IS_CKPTFP_REGNUM(i) \
  ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)

#define PPC_IS_CKPTVMX_REGNUM(i) \
  ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)

#define PPC_IS_CKPTVSX_REGNUM(i) \
  ((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32))

/* An instruction to match.  */

struct ppc_insn_pattern
{
  unsigned int mask;            /* mask the insn with this...  */
  unsigned int data;            /* ...and see if it matches this.  */
  int optional;                 /* If non-zero, this insn may be absent.  */
};

extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
				    const struct ppc_insn_pattern *pattern,
				    unsigned int *insns);
extern CORE_ADDR ppc_insn_d_field (unsigned int insn);

extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);

extern int ppc_process_record (struct gdbarch *gdbarch,
			       struct regcache *regcache, CORE_ADDR addr);

/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
e2882c85	3	Copyright (C) 2000-2018 Free Software Foundation, Inc.
9aa1e687 KB	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9aa1e687 KB	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9aa1e687	19
3a1c5313 AC	20	#ifndef PPC_TDEP_H
	21	#define PPC_TDEP_H
	22
da3331ec	23	struct gdbarch;
3a1c5313 AC	24	struct frame_info;
3a1c5313 AC	25	struct value;
4a4b3fed	26	struct regcache;
221c12ff	27	struct type;
3a1c5313	28
0df8b418	29	/* From ppc-sysv-tdep.c ... */
05580c65	30	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
6a3a010b	31	struct value *function,
05580c65 AC	32	struct type *valtype,
05580c65 AC	33	struct regcache *regcache,
50fd1280 AC	34	gdb_byte *readbuf,
50fd1280 AC	35	const gdb_byte *writebuf);
05580c65	36	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
6a3a010b	37	struct value *function,
05580c65 AC	38	struct type *valtype,
05580c65 AC	39	struct regcache *regcache,
50fd1280 AC	40	gdb_byte *readbuf,
50fd1280 AC	41	const gdb_byte *writebuf);
77b2b6d4	42	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	43	struct value *function,
77b2b6d4 AC	44	struct regcache *regcache,
	45	CORE_ADDR bp_addr, int nargs,
	46	struct value **args, CORE_ADDR sp,
	47	int struct_return,
	48	CORE_ADDR struct_addr);
8be9034a	49	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	50	struct value *function,
8be9034a AC	51	struct regcache *regcache,
	52	CORE_ADDR bp_addr, int nargs,
	53	struct value **args, CORE_ADDR sp,
	54	int struct_return,
	55	CORE_ADDR struct_addr);
05580c65	56	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
6a3a010b	57	struct value *function,
05580c65 AC	58	struct type *valtype,
05580c65 AC	59	struct regcache *regcache,
50fd1280 AC	60	gdb_byte *readbuf,
50fd1280 AC	61	const gdb_byte *writebuf);
9aa1e687	62
0df8b418	63	/* From rs6000-tdep.c... */
be8626e0	64	int altivec_register_p (struct gdbarch *gdbarch, int regno);
604c2f83	65	int vsx_register_p (struct gdbarch *gdbarch, int regno);
be8626e0	66	int spe_register_p (struct gdbarch *gdbarch, int regno);
9aa1e687	67
383f0f5b JB	68	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	69	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	70	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	71
06caf7d2 CES	72	/* Return non-zero if the architecture described by GDBARCH has
	73	Altivec registers (vr0 --- vr31, vrsave and vscr). */
	74	int ppc_altivec_support_p (struct gdbarch *gdbarch);
	75
604c2f83 LM	76	/* Return non-zero if the architecture described by GDBARCH has
	77	VSX registers (vsr0 --- vsr63). */
	78	int vsx_support_p (struct gdbarch *gdbarch);
a0ff9e1a SM	79	std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
a0ff9e1a SM	80	(struct regcache *regcache);
4a7622d1 UW	81
4a7622d1 UW	82
d195bc9f MK	83	/* Register set description. */
	84
	85	struct ppc_reg_offsets
	86	{
	87	/* General-purpose registers. */
	88	int r0_offset;
f2db237a AM	89	int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
f2db237a AM	90	int xr_size; /* size for cr, xer, mq. */
d195bc9f MK	91	int pc_offset;
	92	int ps_offset;
	93	int cr_offset;
	94	int lr_offset;
	95	int ctr_offset;
	96	int xer_offset;
	97	int mq_offset;
	98
	99	/* Floating-point registers. */
	100	int f0_offset;
	101	int fpscr_offset;
f2db237a	102	int fpscr_size;
d195bc9f MK	103	};
d195bc9f MK	104
7284e1be UW	105	extern void ppc_supply_reg (struct regcache *regcache, int regnum,
	106	const gdb_byte *regs, size_t offset, int regsize);
	107
	108	extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
	109	gdb_byte *regs, size_t offset, int regsize);
	110
d195bc9f MK	111	/* Supply register REGNUM in the general-purpose register set REGSET
	112	from the buffer specified by GREGS and LEN to register cache
	113	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	114
	115	extern void ppc_supply_gregset (const struct regset *regset,
	116	struct regcache *regcache,
	117	int regnum, const void *gregs, size_t len);
	118
	119	/* Supply register REGNUM in the floating-point register set REGSET
	120	from the buffer specified by FPREGS and LEN to register cache
	121	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	122
	123	extern void ppc_supply_fpregset (const struct regset *regset,
	124	struct regcache *regcache,
	125	int regnum, const void *fpregs, size_t len);
	126
06caf7d2 CES	127	/* Supply register REGNUM in the Altivec register set REGSET
	128	from the buffer specified by VRREGS and LEN to register cache
	129	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	130
	131	extern void ppc_supply_vrregset (const struct regset *regset,
	132	struct regcache *regcache,
	133	int regnum, const void *vrregs, size_t len);
	134
604c2f83 LM	135	/* Supply register REGNUM in the VSX register set REGSET
	136	from the buffer specified by VSXREGS and LEN to register cache
	137	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	138
	139	extern void ppc_supply_vsxregset (const struct regset *regset,
	140	struct regcache *regcache,
	141	int regnum, const void *vsxregs, size_t len);
	142
d195bc9f	143	/* Collect register REGNUM in the general-purpose register set
0df8b418	144	REGSET, from register cache REGCACHE into the buffer specified by
d195bc9f MK	145	GREGS and LEN. If REGNUM is -1, do this for all registers in
	146	REGSET. */
	147
	148	extern void ppc_collect_gregset (const struct regset *regset,
	149	const struct regcache *regcache,
	150	int regnum, void *gregs, size_t len);
	151
	152	/* Collect register REGNUM in the floating-point register set
0df8b418	153	REGSET, from register cache REGCACHE into the buffer specified by
d195bc9f MK	154	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	155	REGSET. */
	156
	157	extern void ppc_collect_fpregset (const struct regset *regset,
	158	const struct regcache *regcache,
	159	int regnum, void *fpregs, size_t len);
	160
06caf7d2 CES	161	/* Collect register REGNUM in the Altivec register set
	162	REGSET from register cache REGCACHE into the buffer specified by
	163	VRREGS and LEN. If REGNUM is -1, do this for all registers in
	164	REGSET. */
	165
	166	extern void ppc_collect_vrregset (const struct regset *regset,
	167	const struct regcache *regcache,
	168	int regnum, void *vrregs, size_t len);
	169
604c2f83 LM	170	/* Collect register REGNUM in the VSX register set
	171	REGSET from register cache REGCACHE into the buffer specified by
	172	VSXREGS and LEN. If REGNUM is -1, do this for all registers in
	173	REGSET. */
	174
	175	extern void ppc_collect_vsxregset (const struct regset *regset,
	176	const struct regcache *regcache,
	177	int regnum, void *vsxregs, size_t len);
	178
0df8b418	179	/* Private data that this module attaches to struct gdbarch. */
2188cbdd	180
cd453cd0 UW	181	/* ELF ABI version used by the inferior. */
	182	enum powerpc_elf_abi
	183	{
	184	POWERPC_ELF_AUTO,
	185	POWERPC_ELF_V1,
	186	POWERPC_ELF_V2,
	187	POWERPC_ELF_LAST
	188	};
	189
55eddb0f DJ	190	/* Vector ABI used by the inferior. */
	191	enum powerpc_vector_abi
	192	{
	193	POWERPC_VEC_AUTO,
	194	POWERPC_VEC_GENERIC,
	195	POWERPC_VEC_ALTIVEC,
	196	POWERPC_VEC_SPE,
	197	POWERPC_VEC_LAST
	198	};
	199
ed0f4273 UW	200	/* long double ABI version used by the inferior. */
	201	enum powerpc_long_double_abi
	202	{
	203	POWERPC_LONG_DOUBLE_AUTO,
	204	POWERPC_LONG_DOUBLE_IBM128,
	205	POWERPC_LONG_DOUBLE_IEEE128,
	206	POWERPC_LONG_DOUBLE_LAST
	207	};
	208
2188cbdd EZ	209	struct gdbarch_tdep
2188cbdd EZ	210	{
55eddb0f DJ	211	int wordsize; /* Size in bytes of fixed-point word. */
	212	int soft_float; /* Avoid FP registers for arguments? */
	213
cd453cd0 UW	214	enum powerpc_elf_abi elf_abi; /* ELF ABI version. */
cd453cd0 UW	215
ed0f4273 UW	216	/* Format to use for the "long double" data type. */
	217	enum powerpc_long_double_abi long_double_abi;
	218
55eddb0f DJ	219	/* How to pass vector arguments. Never set to AUTO or LAST. */
	220	enum powerpc_vector_abi vector_abi;
	221
2188cbdd	222	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	223	int ppc_toc_regnum; /* TOC register */
	224	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	225	int ppc_cr_regnum; /* Condition register */
	226	int ppc_lr_regnum; /* Link register */
	227	int ppc_ctr_regnum; /* Count register */
	228	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	229
826d5376 PG	230	/* Not all PPC and RS6000 variants will have the registers
	231	represented below. A -1 is used to indicate that the register
	232	is not present in this variant. */
	233
	234	/* Floating-point registers. */
0df8b418 MS	235	int ppc_fp0_regnum; /* Floating-point register 0. */
0df8b418 MS	236	int ppc_fpscr_regnum; /* fp status and condition register. */
826d5376	237
826d5376 PG	238	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	239	int ppc_mq_regnum;
f86a7158	240
604c2f83 LM	241	/* POWER7 VSX registers. */
	242	int ppc_vsr0_regnum; /* First VSX register. */
	243	int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
	244	int ppc_efpr0_regnum; /* First Extended FP register. */
	245
826d5376	246	/* Altivec registers. */
0df8b418 MS	247	int ppc_vr0_regnum; /* First AltiVec register. */
0df8b418 MS	248	int ppc_vrsave_regnum; /* Last AltiVec register. */
826d5376 PG	249
826d5376 PG	250	/* SPE registers. */
0df8b418 MS	251	int ppc_ev0_upper_regnum; /* First GPR upper half register. */
	252	int ppc_ev0_regnum; /* First ev register. */
	253	int ppc_acc_regnum; /* SPE 'acc' register. */
	254	int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
826d5376	255
7ca18ed6 EBM	256	/* Program Priority Register. */
	257	int ppc_ppr_regnum;
	258
	259	/* Data Stream Control Register. */
	260	int ppc_dscr_regnum;
	261
f2cf6173 EBM	262	/* Target Address Register. */
	263	int ppc_tar_regnum;
	264
f949c649 TJB	265	/* Decimal 128 registers. */
	266	int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
	267
232bfb86 EBM	268	int have_ebb;
	269
	270	/* PMU registers. */
	271	int ppc_mmcr0_regnum;
	272	int ppc_mmcr2_regnum;
	273	int ppc_siar_regnum;
	274	int ppc_sdar_regnum;
	275	int ppc_sier_regnum;
	276
8d619c01 EBM	277	/* Hardware Transactional Memory registers. */
	278	int have_htm_spr;
	279	int have_htm_core;
	280	int have_htm_fpu;
	281	int have_htm_altivec;
	282	int have_htm_vsx;
	283	int ppc_cppr_regnum;
	284	int ppc_cdscr_regnum;
	285	int ppc_ctar_regnum;
	286
	287	/* HTM pseudo registers. */
	288	int ppc_cdl0_regnum;
	289	int ppc_cvsr0_regnum;
	290	int ppc_cefpr0_regnum;
	291
826d5376 PG	292	/* Offset to ABI specific location where link register is saved. */
826d5376 PG	293	int lr_frame_offset;
9f643768 JB	294
	295	/* An array of integers, such that sim_regno[I] is the simulator
	296	register number for GDB register number I, or -1 if the
	297	simulator does not implement that register. */
	298	int *sim_regno;
6f7f3f0d	299
794ac428 UW	300	/* ISA-specific types. */
794ac428 UW	301	struct type *ppc_builtin_type_vec64;
604c2f83	302	struct type *ppc_builtin_type_vec128;
b4cdae6f WW	303
b4cdae6f WW	304	int (ppc_syscall_record) (struct regcache regcache);
2188cbdd	305	};
3a1c5313	306
b967e06f JB	307
	308	/* Constants for register set sizes. */
	309	enum
	310	{
604c2f83 LM	311	ppc_num_gprs = 32, /* 32 general-purpose registers. */
	312	ppc_num_fprs = 32, /* 32 floating-point registers. */
	313	ppc_num_srs = 16, /* 16 segment registers. */
	314	ppc_num_vrs = 32, /* 32 Altivec vector registers. */
	315	ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
	316	ppc_num_vsrs = 64, /* 64 VSX vector registers. */
	317	ppc_num_efprs = 32 /* 32 Extended FP registers. */
b967e06f JB	318	};
b967e06f JB	319
0ea0ec5f	320
7cc46491 DJ	321	/* Register number constants. These are GDB internal register
	322	numbers; they are not used for the simulator or remote targets.
	323	Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
	324	numbers above PPC_NUM_REGS. So are segment registers and other
	325	target-defined registers. */
	326	enum {
	327	PPC_R0_REGNUM = 0,
	328	PPC_F0_REGNUM = 32,
	329	PPC_PC_REGNUM = 64,
	330	PPC_MSR_REGNUM = 65,
	331	PPC_CR_REGNUM = 66,
	332	PPC_LR_REGNUM = 67,
	333	PPC_CTR_REGNUM = 68,
	334	PPC_XER_REGNUM = 69,
	335	PPC_FPSCR_REGNUM = 70,
	336	PPC_MQ_REGNUM = 71,
	337	PPC_SPE_UPPER_GP0_REGNUM = 72,
	338	PPC_SPE_ACC_REGNUM = 104,
	339	PPC_SPE_FSCR_REGNUM = 105,
	340	PPC_VR0_REGNUM = 106,
	341	PPC_VSCR_REGNUM = 138,
	342	PPC_VRSAVE_REGNUM = 139,
604c2f83 LM	343	PPC_VSR0_UPPER_REGNUM = 140,
604c2f83 LM	344	PPC_VSR31_UPPER_REGNUM = 171,
7ca18ed6 EBM	345	PPC_PPR_REGNUM = 172,
7ca18ed6 EBM	346	PPC_DSCR_REGNUM = 173,
f2cf6173	347	PPC_TAR_REGNUM = 174,
232bfb86 EBM	348
	349	/* EBB registers. */
	350	PPC_BESCR_REGNUM = 175,
	351	PPC_EBBHR_REGNUM = 176,
	352	PPC_EBBRR_REGNUM = 177,
	353
	354	/* PMU registers. */
	355	PPC_MMCR0_REGNUM = 178,
	356	PPC_MMCR2_REGNUM = 179,
	357	PPC_SIAR_REGNUM = 180,
	358	PPC_SDAR_REGNUM = 181,
	359	PPC_SIER_REGNUM = 182,
	360
8d619c01 EBM	361	/* Hardware transactional memory registers. */
	362	PPC_TFHAR_REGNUM = 183,
	363	PPC_TEXASR_REGNUM = 184,
	364	PPC_TFIAR_REGNUM = 185,
	365
	366	PPC_CR0_REGNUM = 186,
	367	PPC_CCR_REGNUM = 218,
	368	PPC_CXER_REGNUM = 219,
	369	PPC_CLR_REGNUM = 220,
	370	PPC_CCTR_REGNUM = 221,
	371
	372	PPC_CF0_REGNUM = 222,
	373	PPC_CFPSCR_REGNUM = 254,
	374
	375	PPC_CVR0_REGNUM = 255,
	376	PPC_CVSCR_REGNUM = 287,
	377	PPC_CVRSAVE_REGNUM = 288,
	378
	379	PPC_CVSR0_UPPER_REGNUM = 289,
	380
	381	PPC_CPPR_REGNUM = 321,
	382	PPC_CDSCR_REGNUM = 322,
	383	PPC_CTAR_REGNUM = 323,
7cc46491 DJ	384	PPC_NUM_REGS
7cc46491 DJ	385	};
0ea0ec5f	386
0f068fb5 AH	387	/* Big enough to hold the size of the largest register in bytes. */
	388	#define PPC_MAX_REGISTER_SIZE 64
	389
232bfb86 EBM	390	#define PPC_IS_EBB_REGNUM(i) \
	391	((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)
	392
	393	#define PPC_IS_PMU_REGNUM(i) \
	394	((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)
	395
8d619c01 EBM	396	#define PPC_IS_TMSPR_REGNUM(i) \
	397	((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)
	398
	399	#define PPC_IS_CKPTGP_REGNUM(i) \
	400	((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)
	401
	402	#define PPC_IS_CKPTFP_REGNUM(i) \
	403	((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)
	404
	405	#define PPC_IS_CKPTVMX_REGNUM(i) \
	406	((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)
	407
	408	#define PPC_IS_CKPTVSX_REGNUM(i) \
	409	((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32))
	410
d78489bf AT	411	/* An instruction to match. */
	412
	413	struct ppc_insn_pattern
	414	{
	415	unsigned int mask; /* mask the insn with this... */
	416	unsigned int data; /* ...and see if it matches this. */
	417	int optional; /* If non-zero, this insn may be absent. */
	418	};
	419
845d4708	420	extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
7433498b	421	const struct ppc_insn_pattern *pattern,
845d4708	422	unsigned int *insns);
d78489bf AT	423	extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
	424
	425	extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
0ea0ec5f	426
b4cdae6f WW	427	extern int ppc_process_record (struct gdbarch *gdbarch,
	428	struct regcache *regcache, CORE_ADDR addr);
	429
a0c75879 MK	430	/* Instruction size. */
	431	#define PPC_INSN_SIZE 4
	432
0d1243d9 PG	433	/* Estimate for the maximum number of instrctions in a function epilogue. */
	434	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	435
a0c75879	436	#endif /* ppc-tdep.h */