[deliverable/binutils-gdb.git] / gdb / riscv-fbsd-tdep.c

/* Target-dependent code for FreeBSD on RISC-V processors.
   Copyright (C) 2018-2020 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"
#include "fbsd-tdep.h"
#include "osabi.h"
#include "riscv-tdep.h"
#include "riscv-fbsd-tdep.h"
#include "solib-svr4.h"
#include "target.h"
#include "trad-frame.h"
#include "tramp-frame.h"
#include "gdbarch.h"

/* Register maps.  */

static const struct regcache_map_entry riscv_fbsd_gregmap[] =
  {
    { 1, RISCV_RA_REGNUM, 0 },
    { 1, RISCV_SP_REGNUM, 0 },
    { 1, RISCV_GP_REGNUM, 0 },
    { 1, RISCV_TP_REGNUM, 0 },
    { 3, 5, 0 },		/* t0 - t2 */
    { 4, 28, 0 },		/* t3 - t6 */
    { 2, RISCV_FP_REGNUM, 0 },	/* s0 - s1 */
    { 10, 18, 0 },		/* s2 - s11 */
    { 8, RISCV_A0_REGNUM, 0 },	/* a0 - a7 */
    { 1, RISCV_PC_REGNUM, 0 },
    { 1, RISCV_CSR_SSTATUS_REGNUM, 0 },
    { 0 }
  };

static const struct regcache_map_entry riscv_fbsd_fpregmap[] =
  {
    { 32, RISCV_FIRST_FP_REGNUM, 16 },
    { 1, RISCV_CSR_FCSR_REGNUM, 8 },
    { 0 }
  };

/* Supply the general-purpose registers stored in GREGS to REGCACHE.
   This function only exists to supply the always-zero x0 in addition
   to the registers in GREGS.  */

static void
riscv_fbsd_supply_gregset (const struct regset *regset,
			   struct regcache *regcache, int regnum,
			   const void *gregs, size_t len)
{
  regcache->supply_regset (&riscv_fbsd_gregset, regnum, gregs, len);
  if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
    regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
}

/* Register set definitions.  */

const struct regset riscv_fbsd_gregset =
  {
    riscv_fbsd_gregmap,
    riscv_fbsd_supply_gregset, regcache_collect_regset
  };

const struct regset riscv_fbsd_fpregset =
  {
    riscv_fbsd_fpregmap,
    regcache_supply_regset, regcache_collect_regset
  };

/* Implement the "regset_from_core_section" gdbarch method.  */

static void
riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
					 iterate_over_regset_sections_cb *cb,
					 void *cb_data,
					 const struct regcache *regcache)
{
  cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
      RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
      &riscv_fbsd_gregset, NULL, cb_data);
  cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET,
      &riscv_fbsd_fpregset, NULL, cb_data);
}

/* In a signal frame, sp points to a 'struct sigframe' which is
   defined as:

   struct sigframe {
	   siginfo_t	sf_si;
	   ucontext_t	sf_uc;
   };

   ucontext_t is defined as:

   struct __ucontext {
	   sigset_t	uc_sigmask;
	   mcontext_t	uc_mcontext;
	   ...
   };

   The mcontext_t contains the general purpose register set followed
   by the floating point register set.  The floating point register
   set is only valid if the _MC_FP_VALID flag is set in mc_flags.  */

#define RISCV_SIGFRAME_UCONTEXT_OFFSET 		80
#define RISCV_UCONTEXT_MCONTEXT_OFFSET		16
#define RISCV_MCONTEXT_FLAG_FP_VALID		0x1

/* Implement the "init" method of struct tramp_frame.  */

static void
riscv_fbsd_sigframe_init (const struct tramp_frame *self,
			  struct frame_info *this_frame,
			  struct trad_frame_cache *this_cache,
			  CORE_ADDR func)
{
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
  CORE_ADDR mcontext_addr
    = (sp
       + RISCV_SIGFRAME_UCONTEXT_OFFSET
       + RISCV_UCONTEXT_MCONTEXT_OFFSET);
  gdb_byte buf[4];

  trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr,
			     RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));

  CORE_ADDR fpregs_addr
    = mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
  CORE_ADDR fp_flags_addr
    = fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET;
  if (target_read_memory (fp_flags_addr, buf, 4) == 0
      && (extract_unsigned_integer (buf, 4, byte_order)
	  & RISCV_MCONTEXT_FLAG_FP_VALID))
    trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr,
			       RISCV_FBSD_SIZEOF_FPREGSET);

  trad_frame_set_id (this_cache, frame_id_build (sp, func));
}

/* RISC-V supports 16-bit instructions ("C") as well as 32-bit
   instructions.  The signal trampoline on FreeBSD uses a mix of
   these, but tramp_frame assumes a fixed instruction size.  To cope,
   claim that all instructions are 16 bits and use two "slots" for
   32-bit instructions.  */

static const struct tramp_frame riscv_fbsd_sigframe =
{
  SIGTRAMP_FRAME,
  2,
  {
    {0x850a, ULONGEST_MAX},		/* mov  a0, sp  */
    {0x0513, ULONGEST_MAX},		/* addi a0, a0, #SF_UC  */
    {0x0505, ULONGEST_MAX},
    {0x0293, ULONGEST_MAX},		/* li   t0, #SYS_sigreturn  */
    {0x1a10, ULONGEST_MAX},
    {0x0073, ULONGEST_MAX},		/* ecall  */
    {0x0000, ULONGEST_MAX},
    {TRAMP_SENTINEL_INSN, ULONGEST_MAX}
  },
  riscv_fbsd_sigframe_init
};

/* Implement the "get_thread_local_address" gdbarch method.  */

static CORE_ADDR
riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
				     CORE_ADDR lm_addr, CORE_ADDR offset)
{
  struct regcache *regcache;

  regcache = get_thread_arch_regcache (ptid, gdbarch);

  target_fetch_registers (regcache, RISCV_TP_REGNUM);

  ULONGEST tp;
  if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
    error (_("Unable to fetch %%tp"));

  /* %tp points to the end of the TCB which contains two pointers.
      The first pointer in the TCB points to the DTV array.  */
  CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
  return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
}

/* Implement the 'init_osabi' method of struct gdb_osabi_handler.  */

static void
riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
  /* Generic FreeBSD support.  */
  fbsd_init_abi (info, gdbarch);

  set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);

  set_solib_svr4_fetch_link_map_offsets (gdbarch,
					 (riscv_isa_xlen (gdbarch) == 4
					  ? svr4_ilp32_fetch_link_map_offsets
					  : svr4_lp64_fetch_link_map_offsets));

  tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe);

  set_gdbarch_iterate_over_regset_sections
    (gdbarch, riscv_fbsd_iterate_over_regset_sections);

  set_gdbarch_fetch_tls_load_module_address (gdbarch,
					     svr4_fetch_objfile_link_map);
  set_gdbarch_get_thread_local_address (gdbarch,
					riscv_fbsd_get_thread_local_address);
}

void
_initialize_riscv_fbsd_tdep (void)
{
  gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD,
			  riscv_fbsd_init_abi);
}
Commit	Line	Data
ed65e20b	1	/* Target-dependent code for FreeBSD on RISC-V processors.
b811d2c2	2	Copyright (C) 2018-2020 Free Software Foundation, Inc.
ed65e20b JB	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	18
	19	#include "defs.h"
	20	#include "fbsd-tdep.h"
	21	#include "osabi.h"
	22	#include "riscv-tdep.h"
	23	#include "riscv-fbsd-tdep.h"
	24	#include "solib-svr4.h"
	25	#include "target.h"
	26	#include "trad-frame.h"
	27	#include "tramp-frame.h"
0d12e84c	28	#include "gdbarch.h"
ed65e20b JB	29
	30	/* Register maps. */
	31
	32	static const struct regcache_map_entry riscv_fbsd_gregmap[] =
	33	{
	34	{ 1, RISCV_RA_REGNUM, 0 },
	35	{ 1, RISCV_SP_REGNUM, 0 },
	36	{ 1, RISCV_GP_REGNUM, 0 },
	37	{ 1, RISCV_TP_REGNUM, 0 },
	38	{ 3, 5, 0 }, /* t0 - t2 */
	39	{ 4, 28, 0 }, /* t3 - t6 */
	40	{ 2, RISCV_FP_REGNUM, 0 }, /* s0 - s1 */
	41	{ 10, 18, 0 }, /* s2 - s11 */
	42	{ 8, RISCV_A0_REGNUM, 0 }, /* a0 - a7 */
	43	{ 1, RISCV_PC_REGNUM, 0 },
	44	{ 1, RISCV_CSR_SSTATUS_REGNUM, 0 },
	45	{ 0 }
	46	};
	47
	48	static const struct regcache_map_entry riscv_fbsd_fpregmap[] =
	49	{
	50	{ 32, RISCV_FIRST_FP_REGNUM, 16 },
	51	{ 1, RISCV_CSR_FCSR_REGNUM, 8 },
	52	{ 0 }
	53	};
	54
	55	/* Supply the general-purpose registers stored in GREGS to REGCACHE.
	56	This function only exists to supply the always-zero x0 in addition
	57	to the registers in GREGS. */
	58
	59	static void
	60	riscv_fbsd_supply_gregset (const struct regset *regset,
	61	struct regcache *regcache, int regnum,
	62	const void *gregs, size_t len)
	63	{
	64	regcache->supply_regset (&riscv_fbsd_gregset, regnum, gregs, len);
	65	if (regnum == -1 \|\| regnum == RISCV_ZERO_REGNUM)
	66	regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
	67	}
	68
	69	/* Register set definitions. */
	70
	71	const struct regset riscv_fbsd_gregset =
	72	{
	73	riscv_fbsd_gregmap,
	74	riscv_fbsd_supply_gregset, regcache_collect_regset
	75	};
	76
	77	const struct regset riscv_fbsd_fpregset =
	78	{
	79	riscv_fbsd_fpregmap,
	80	regcache_supply_regset, regcache_collect_regset
	81	};
	82
	83	/* Implement the "regset_from_core_section" gdbarch method. */
	84
	85	static void
	86	riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	87	iterate_over_regset_sections_cb *cb,
	88	void *cb_data,
	89	const struct regcache *regcache)
	90	{
	91	cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
	92	RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
93	&riscv_fbsd_gregset, NULL, cb_data);
94	cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET,
95	&riscv_fbsd_fpregset, NULL, cb_data);
96	}
97
98	/* In a signal frame, sp points to a 'struct sigframe' which is
99	defined as:
100
101	struct sigframe {
102	siginfo_t sf_si;
103	ucontext_t sf_uc;
104	};
105
106	ucontext_t is defined as:
107
108	struct __ucontext {
109	sigset_t uc_sigmask;
110	mcontext_t uc_mcontext;
111	...
112	};
113
114	The mcontext_t contains the general purpose register set followed
115	by the floating point register set. The floating point register
116	set is only valid if the _MC_FP_VALID flag is set in mc_flags. */
117
118	#define RISCV_SIGFRAME_UCONTEXT_OFFSET 80
119	#define RISCV_UCONTEXT_MCONTEXT_OFFSET 16
120	#define RISCV_MCONTEXT_FLAG_FP_VALID 0x1
121
122	/* Implement the "init" method of struct tramp_frame. */
123
124	static void
125	riscv_fbsd_sigframe_init (const struct tramp_frame *self,
126	struct frame_info *this_frame,
127	struct trad_frame_cache *this_cache,
128	CORE_ADDR func)
129	{
130	struct gdbarch *gdbarch = get_frame_arch (this_frame);
131	enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
132	CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
133	CORE_ADDR mcontext_addr
134	= (sp
135	+ RISCV_SIGFRAME_UCONTEXT_OFFSET
136	+ RISCV_UCONTEXT_MCONTEXT_OFFSET);
137	gdb_byte buf[4];
ed65e20b JB	138
	139	trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr,
	140	RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));
	141
	142	CORE_ADDR fpregs_addr
	143	= mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
	144	CORE_ADDR fp_flags_addr
	145	= fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET;
	146	if (target_read_memory (fp_flags_addr, buf, 4) == 0
	147	&& (extract_unsigned_integer (buf, 4, byte_order)
	148	& RISCV_MCONTEXT_FLAG_FP_VALID))
	149	trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr,
	150	RISCV_FBSD_SIZEOF_FPREGSET);
	151
	152	trad_frame_set_id (this_cache, frame_id_build (sp, func));
	153	}
	154
	155	/* RISC-V supports 16-bit instructions ("C") as well as 32-bit
	156	instructions. The signal trampoline on FreeBSD uses a mix of
	157	these, but tramp_frame assumes a fixed instruction size. To cope,
	158	claim that all instructions are 16 bits and use two "slots" for
	159	32-bit instructions. */
	160
	161	static const struct tramp_frame riscv_fbsd_sigframe =
	162	{
	163	SIGTRAMP_FRAME,
	164	2,
	165	{
	166	{0x850a, ULONGEST_MAX}, /* mov a0, sp */
	167	{0x0513, ULONGEST_MAX}, /* addi a0, a0, #SF_UC */
	168	{0x0505, ULONGEST_MAX},
	169	{0x0293, ULONGEST_MAX}, /* li t0, #SYS_sigreturn */
	170	{0x1a10, ULONGEST_MAX},
	171	{0x0073, ULONGEST_MAX}, /* ecall */
	172	{0x0000, ULONGEST_MAX},
	173	{TRAMP_SENTINEL_INSN, ULONGEST_MAX}
	174	},
	175	riscv_fbsd_sigframe_init
	176	};
	177
b0f87ed0 JB	178	/* Implement the "get_thread_local_address" gdbarch method. */
	179
	180	static CORE_ADDR
	181	riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
	182	CORE_ADDR lm_addr, CORE_ADDR offset)
	183	{
	184	struct regcache *regcache;
	185
	186	regcache = get_thread_arch_regcache (ptid, gdbarch);
	187
	188	target_fetch_registers (regcache, RISCV_TP_REGNUM);
	189
	190	ULONGEST tp;
	191	if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
	192	error (_("Unable to fetch %%tp"));
	193
	194	/* %tp points to the end of the TCB which contains two pointers.
	195	The first pointer in the TCB points to the DTV array. */
	196	CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
	197	return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
	198	}
	199
ed65e20b JB	200	/* Implement the 'init_osabi' method of struct gdb_osabi_handler. */
	201
	202	static void
	203	riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
	204	{
ed65e20b JB	205	/* Generic FreeBSD support. */
	206	fbsd_init_abi (info, gdbarch);
	207
	208	set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
	209
	210	set_solib_svr4_fetch_link_map_offsets (gdbarch,
	211	(riscv_isa_xlen (gdbarch) == 4
	212	? svr4_ilp32_fetch_link_map_offsets
	213	: svr4_lp64_fetch_link_map_offsets));
	214
	215	tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe);
	216
	217	set_gdbarch_iterate_over_regset_sections
	218	(gdbarch, riscv_fbsd_iterate_over_regset_sections);
b0f87ed0 JB	219
	220	set_gdbarch_fetch_tls_load_module_address (gdbarch,
	221	svr4_fetch_objfile_link_map);
	222	set_gdbarch_get_thread_local_address (gdbarch,
	223	riscv_fbsd_get_thread_local_address);
ed65e20b JB	224	}
	225
	226	void
	227	_initialize_riscv_fbsd_tdep (void)
	228	{
	229	gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD,
	230	riscv_fbsd_init_abi);
	231	}