projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| dbbb1059 AB |
1 | /* Target-dependent header for the RISC-V architecture, for GDB, the GNU Debugger. |
| 2 | ||
| 3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
| 4 | ||
| 5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU | |
| 6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin | |
| 7 | and by Todd Snyder <todd@bluespec.com> | |
| 8 | and by Mike Frysinger <vapier@gentoo.org>. | |
| 9 | ||
| 10 | This file is part of GDB. | |
| 11 | ||
| 12 | This program is free software; you can redistribute it and/or modify | |
| 13 | it under the terms of the GNU General Public License as published by | |
| 14 | the Free Software Foundation; either version 3 of the License, or | |
| 15 | (at your option) any later version. | |
| 16 | ||
| 17 | This program is distributed in the hope that it will be useful, | |
| 18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 | GNU General Public License for more details. | |
| 21 | ||
| 22 | You should have received a copy of the GNU General Public License | |
| 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
| 24 | ||
| 25 | #ifndef RISCV_TDEP_H | |
| 26 | #define RISCV_TDEP_H | |
| 27 | ||
| 28 | /* RiscV register numbers. */ | |
| 29 | enum | |
| 30 | { | |
| 31 | RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */ | |
| 32 | RISCV_RA_REGNUM = 1, /* Return Address. */ | |
| 33 | RISCV_SP_REGNUM = 2, /* Stack Pointer. */ | |
| 34 | RISCV_GP_REGNUM = 3, /* Global Pointer. */ | |
| 35 | RISCV_TP_REGNUM = 4, /* Thread Pointer. */ | |
| 36 | RISCV_FP_REGNUM = 8, /* Frame Pointer. */ | |
| 37 | RISCV_A0_REGNUM = 10, /* First argument. */ | |
| 38 | RISCV_A1_REGNUM = 11, /* Second argument. */ | |
| 39 | RISCV_PC_REGNUM = 32, /* Program Counter. */ | |
| 40 | ||
| 41 | RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */ | |
| 42 | RISCV_FA0_REGNUM = 43, | |
| 43 | RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1, | |
| 44 | RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ | |
| 45 | ||
| 46 | RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ | |
| 47 | #define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num, | |
| 48 | #include "opcode/riscv-opc.h" | |
| 49 | #undef DECLARE_CSR | |
| 50 | RISCV_LAST_CSR_REGNUM = 4160, | |
| 51 | RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10, | |
| 52 | ||
| 53 | RISCV_PRIV_REGNUM = 4161, | |
| 54 | ||
| 55 | RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM | |
| 56 | }; | |
| 57 | ||
| 58 | /* RISC-V specific per-architecture information. */ | |
| 59 | struct gdbarch_tdep | |
| 60 | { | |
| 61 | union | |
| 62 | { | |
| 63 | /* Provide access to the whole ABI in one value. */ | |
| 64 | unsigned value; | |
| 65 | ||
| 66 | struct | |
| 67 | { | |
| 68 | /* Encode the base machine length following the same rules as in the | |
| 69 | MISA register. */ | |
| 70 | unsigned base_len : 2; | |
| 71 | ||
| 72 | /* Encode which floating point ABI is in use following the same rules | |
| 73 | as the ELF e_flags field. */ | |
| 74 | unsigned float_abi : 2; | |
| 75 | } fields; | |
| 76 | } abi; | |
| 77 | ||
| 78 | /* Only the least significant 26 bits are (possibly) valid, and indicate | |
| 79 | features that are supported on the target. These could be cached from | |
| 80 | the target, or read from the executable when available. */ | |
| 81 | unsigned core_features; | |
| 82 | }; | |
| 83 | ||
| 84 | #endif /* RISCV_TDEP_H */ |