projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Split python docs into separate file.
[deliverable/binutils-gdb.git] / gdb / rl78-tdep.c
CommitLineData
9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
ecd75fc8 3 Copyright (C) 2011-2014 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
ba89f962 97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
c47a44f4
KB		 98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
ba89f962
KB		 108 RL78_PC_REGNUM = RL78_NUM_REGS,
109 RL78_SP_REGNUM,
c47a44f4
KB		 110
111 RL78_X_REGNUM,
112 RL78_A_REGNUM,
113 RL78_C_REGNUM,
114 RL78_B_REGNUM,
115 RL78_E_REGNUM,
116 RL78_D_REGNUM,
117 RL78_L_REGNUM,
118 RL78_H_REGNUM,
119
120 RL78_AX_REGNUM,
121 RL78_BC_REGNUM,
122 RL78_DE_REGNUM,
123 RL78_HL_REGNUM,
124
125 RL78_BANK0_R0_REGNUM,
9058f767
KB		 126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
133
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
142
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
151
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
160
c47a44f4 161 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
165
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
170
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
175
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
180
9058f767
KB		 181 RL78_NUM_TOTAL_REGS,
182 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
183};
184
185/* Architecture specific data. */
186
187struct gdbarch_tdep
188{
189 /* The ELF header flags specify the multilib used. */
190 int elf_flags;
191
192 struct type *rl78_void,
193 *rl78_uint8,
194 *rl78_int8,
195 *rl78_uint16,
196 *rl78_int16,
197 *rl78_uint32,
198 *rl78_int32,
199 *rl78_data_pointer,
200 *rl78_code_pointer;
201};
202
203/* This structure holds the results of a prologue analysis. */
204
205struct rl78_prologue
206{
207 /* The offset from the frame base to the stack pointer --- always
208 zero or negative.
209
210 Calling this a "size" is a bit misleading, but given that the
211 stack grows downwards, using offsets for everything keeps one
212 from going completely sign-crazy: you never change anything's
213 sign for an ADD instruction; always change the second operand's
214 sign for a SUB instruction; and everything takes care of
215 itself. */
216 int frame_size;
217
218 /* Non-zero if this function has initialized the frame pointer from
219 the stack pointer, zero otherwise. */
220 int has_frame_ptr;
221
222 /* If has_frame_ptr is non-zero, this is the offset from the frame
223 base to where the frame pointer points. This is always zero or
224 negative. */
225 int frame_ptr_offset;
226
227 /* The address of the first instruction at which the frame has been
228 set up and the arguments are where the debug info says they are
229 --- as best as we can tell. */
230 CORE_ADDR prologue_end;
231
232 /* reg_offset[R] is the offset from the CFA at which register R is
233 saved, or 1 if register R has not been saved. (Real values are
234 always zero or negative.) */
235 int reg_offset[RL78_NUM_TOTAL_REGS];
236};
237
238/* Implement the "register_type" gdbarch method. */
239
240static struct type *
241rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
242{
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244
245 if (reg_nr == RL78_PC_REGNUM)
246 return tdep->rl78_code_pointer;
ba89f962
KB		 247 else if (reg_nr == RL78_RAW_PC_REGNUM)
248 return tdep->rl78_uint32;
9058f767 249 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 250 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
251 || (RL78_BANK0_R0_REGNUM <= reg_nr
252 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767
KB		 253 return tdep->rl78_int8;
254 else
255 return tdep->rl78_data_pointer;
256}
257
258/* Implement the "register_name" gdbarch method. */
259
260static const char *
261rl78_register_name (struct gdbarch *gdbarch, int regnr)
262{
263 static const char *const reg_names[] =
264 {
c47a44f4
KB		 265 "", /* bank0_r0 */
266 "", /* bank0_r1 */
267 "", /* bank0_r2 */
268 "", /* bank0_r3 */
269 "", /* bank0_r4 */
270 "", /* bank0_r5 */
271 "", /* bank0_r6 */
272 "", /* bank0_r7 */
273
274 "", /* bank1_r0 */
275 "", /* bank1_r1 */
276 "", /* bank1_r2 */
277 "", /* bank1_r3 */
278 "", /* bank1_r4 */
279 "", /* bank1_r5 */
280 "", /* bank1_r6 */
281 "", /* bank1_r7 */
282
283 "", /* bank2_r0 */
284 "", /* bank2_r1 */
285 "", /* bank2_r2 */
286 "", /* bank2_r3 */
287 "", /* bank2_r4 */
288 "", /* bank2_r5 */
289 "", /* bank2_r6 */
290 "", /* bank2_r7 */
291
292 "", /* bank3_r0 */
293 "", /* bank3_r1 */
294 "", /* bank3_r2 */
295 "", /* bank3_r3 */
296 "", /* bank3_r4 */
297 "", /* bank3_r5 */
298 "", /* bank3_r6 */
299 "", /* bank3_r7 */
300
301 "psw",
302 "es",
303 "cs",
ba89f962 304 "",
c47a44f4
KB		 305
306 "", /* spl */
307 "", /* sph */
308 "pmc",
309 "mem",
310
ba89f962 311 "pc",
c47a44f4
KB		 312 "sp",
313
314 "x",
315 "a",
316 "c",
317 "b",
318 "e",
319 "d",
320 "l",
321 "h",
322
323 "ax",
324 "bc",
325 "de",
326 "hl",
327
9058f767
KB		 328 "bank0_r0",
329 "bank0_r1",
330 "bank0_r2",
331 "bank0_r3",
332 "bank0_r4",
333 "bank0_r5",
334 "bank0_r6",
335 "bank0_r7",
336
337 "bank1_r0",
338 "bank1_r1",
339 "bank1_r2",
340 "bank1_r3",
341 "bank1_r4",
342 "bank1_r5",
343 "bank1_r6",
344 "bank1_r7",
345
346 "bank2_r0",
347 "bank2_r1",
348 "bank2_r2",
349 "bank2_r3",
350 "bank2_r4",
351 "bank2_r5",
352 "bank2_r6",
353 "bank2_r7",
354
355 "bank3_r0",
356 "bank3_r1",
357 "bank3_r2",
358 "bank3_r3",
359 "bank3_r4",
360 "bank3_r5",
361 "bank3_r6",
362 "bank3_r7",
363
9058f767
KB		 364 "bank0_rp0",
365 "bank0_rp1",
366 "bank0_rp2",
367 "bank0_rp3",
368
369 "bank1_rp0",
370 "bank1_rp1",
371 "bank1_rp2",
372 "bank1_rp3",
373
374 "bank2_rp0",
375 "bank2_rp1",
376 "bank2_rp2",
377 "bank2_rp3",
378
379 "bank3_rp0",
380 "bank3_rp1",
381 "bank3_rp2",
c47a44f4
KB		 382 "bank3_rp3"
383 };
9058f767 384
c47a44f4
KB		 385 return reg_names[regnr];
386}
9058f767 387
c47a44f4 388/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 389
c47a44f4
KB		 390static int
391rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
392 struct reggroup *group)
393{
394 if (group == all_reggroup)
395 return 1;
9058f767 396
c47a44f4
KB		 397 /* All other registers are saved and restored. */
398 if (group == save_reggroup || group == restore_reggroup)
399 {
b3ce41ea 400 if ((regnum < RL78_NUM_REGS
ba89f962
KB		 401 && regnum != RL78_SPL_REGNUM
402 && regnum != RL78_SPH_REGNUM
403 && regnum != RL78_RAW_PC_REGNUM)
404 || regnum == RL78_SP_REGNUM
405 || regnum == RL78_PC_REGNUM)
c47a44f4
KB		 406 return 1;
407 else
408 return 0;
409 }
410
411 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
412 || regnum == RL78_ES_REGNUM
413 || regnum == RL78_CS_REGNUM
414 || regnum == RL78_SPL_REGNUM
415 || regnum == RL78_SPH_REGNUM
416 || regnum == RL78_PMC_REGNUM
417 || regnum == RL78_MEM_REGNUM
ba89f962 418 || regnum == RL78_RAW_PC_REGNUM
c47a44f4
KB		 419 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
420 return group == system_reggroup;
421
422 return group == general_reggroup;
9058f767
KB		 423}
424
425/* Strip bits to form an instruction address. (When fetching a
426 32-bit address from the stack, the high eight bits are garbage.
427 This function strips off those unused bits.) */
428
429static CORE_ADDR
430rl78_make_instruction_address (CORE_ADDR addr)
431{
432 return addr & 0xffffff;
433}
434
435/* Set / clear bits necessary to make a data address. */
436
437static CORE_ADDR
438rl78_make_data_address (CORE_ADDR addr)
439{
440 return (addr & 0xffff) | 0xf0000;
441}
442
443/* Implement the "pseudo_register_read" gdbarch method. */
444
445static enum register_status
446rl78_pseudo_register_read (struct gdbarch *gdbarch,
447 struct regcache *regcache,
448 int reg, gdb_byte *buffer)
449{
450 enum register_status status;
451
c47a44f4
KB		 452 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
453 {
454 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
455 + (reg - RL78_BANK0_R0_REGNUM);
456
457 status = regcache_raw_read (regcache, raw_regnum, buffer);
458 }
459 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 460 {
461 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 462 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 463
464 status = regcache_raw_read (regcache, raw_regnum, buffer);
465 if (status == REG_VALID)
466 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
467 }
468 else if (reg == RL78_SP_REGNUM)
469 {
470 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
471 if (status == REG_VALID)
472 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
473 }
ba89f962
KB		 474 else if (reg == RL78_PC_REGNUM)
475 {
476 gdb_byte rawbuf[4];
477
478 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
479 memcpy (buffer, rawbuf, 3);
480 }
9058f767
KB		 481 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
482 {
483 ULONGEST psw;
484
485 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
486 if (status == REG_VALID)
487 {
488 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
489 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 490 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 491 + (reg - RL78_X_REGNUM);
492 status = regcache_raw_read (regcache, raw_regnum, buffer);
493 }
494 }
495 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
496 {
497 ULONGEST psw;
498
499 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
500 if (status == REG_VALID)
501 {
502 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
503 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 504 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 505 + 2 * (reg - RL78_AX_REGNUM);
506 status = regcache_raw_read (regcache, raw_regnum, buffer);
507 if (status == REG_VALID)
508 status = regcache_raw_read (regcache, raw_regnum + 1,
509 buffer + 1);
510 }
511 }
512 else
513 gdb_assert_not_reached ("invalid pseudo register number");
514 return status;
515}
516
517/* Implement the "pseudo_register_write" gdbarch method. */
518
519static void
520rl78_pseudo_register_write (struct gdbarch *gdbarch,
521 struct regcache *regcache,
522 int reg, const gdb_byte *buffer)
523{
c47a44f4
KB		 524 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
525 {
526 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
527 + (reg - RL78_BANK0_R0_REGNUM);
528
529 regcache_raw_write (regcache, raw_regnum, buffer);
530 }
531 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 532 {
533 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 534 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 535
536 regcache_raw_write (regcache, raw_regnum, buffer);
537 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
538 }
539 else if (reg == RL78_SP_REGNUM)
540 {
541 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
542 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
543 }
ba89f962
KB		 544 else if (reg == RL78_PC_REGNUM)
545 {
546 gdb_byte rawbuf[4];
547
548 memcpy (rawbuf, buffer, 3);
549 rawbuf[3] = 0;
550 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
551 }
9058f767
KB		 552 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
553 {
554 ULONGEST psw;
555 int bank;
556 int raw_regnum;
557
558 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
559 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
560 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 561 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 562 + (reg - RL78_X_REGNUM);
563 regcache_raw_write (regcache, raw_regnum, buffer);
564 }
565 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
566 {
567 ULONGEST psw;
568 int bank, raw_regnum;
569
570 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
571 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
572 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 573 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 574 + 2 * (reg - RL78_AX_REGNUM);
575 regcache_raw_write (regcache, raw_regnum, buffer);
576 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
577 }
578 else
579 gdb_assert_not_reached ("invalid pseudo register number");
580}
581
582/* Implement the "breakpoint_from_pc" gdbarch method. */
583
693be288 584static const gdb_byte *
9058f767
KB		 585rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
586 int *lenptr)
587{
588 /* The documented BRK instruction is actually a two byte sequence,
589 {0x61, 0xcc}, but instructions may be as short as one byte.
590 Correspondence with Renesas revealed that the one byte sequence
591 0xff is used when a one byte breakpoint instruction is required. */
592 static gdb_byte breakpoint[] = { 0xff };
593
594 *lenptr = sizeof breakpoint;
595 return breakpoint;
596}
597
598/* Define a "handle" struct for fetching the next opcode. */
599
600struct rl78_get_opcode_byte_handle
601{
602 CORE_ADDR pc;
603};
604
605/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
606 the memory address of the next byte to fetch. If successful,
607 the address in the handle is updated and the byte fetched is
608 returned as the value of the function. If not successful, -1
609 is returned. */
610
611static int
612rl78_get_opcode_byte (void *handle)
613{
614 struct rl78_get_opcode_byte_handle *opcdata = handle;
615 int status;
616 gdb_byte byte;
617
618 status = target_read_memory (opcdata->pc, &byte, 1);
619 if (status == 0)
620 {
621 opcdata->pc += 1;
622 return byte;
623 }
624 else
625 return -1;
626}
627
628/* Function for finding saved registers in a 'struct pv_area'; this
629 function is passed to pv_area_scan.
630
631 If VALUE is a saved register, ADDR says it was saved at a constant
632 offset from the frame base, and SIZE indicates that the whole
633 register was saved, record its offset. */
634
635static void
636check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
637 pv_t value)
638{
639 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
640
641 if (value.kind == pvk_register
642 && value.k == 0
643 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 644 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 645 result->reg_offset[value.reg] = addr.k;
646}
647
648/* Analyze a prologue starting at START_PC, going no further than
649 LIMIT_PC. Fill in RESULT as appropriate. */
650
651static void
652rl78_analyze_prologue (CORE_ADDR start_pc,
653 CORE_ADDR limit_pc, struct rl78_prologue *result)
654{
655 CORE_ADDR pc, next_pc;
656 int rn;
657 pv_t reg[RL78_NUM_TOTAL_REGS];
658 struct pv_area *stack;
659 struct cleanup *back_to;
660 CORE_ADDR after_last_frame_setup_insn = start_pc;
661 int bank = 0;
662
663 memset (result, 0, sizeof (*result));
664
665 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
666 {
667 reg[rn] = pv_register (rn, 0);
668 result->reg_offset[rn] = 1;
669 }
670
f5656ead 671 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 672 back_to = make_cleanup_free_pv_area (stack);
673
674 /* The call instruction has saved the return address on the stack. */
675 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
676 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
677
678 pc = start_pc;
679 while (pc < limit_pc)
680 {
681 int bytes_read;
682 struct rl78_get_opcode_byte_handle opcode_handle;
683 RL78_Opcode_Decoded opc;
684
685 opcode_handle.pc = pc;
686 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
687 &opcode_handle);
688 next_pc = pc + bytes_read;
689
690 if (opc.id == RLO_sel)
691 {
692 bank = opc.op[1].addend;
693 }
694 else if (opc.id == RLO_mov
695 && opc.op[0].type == RL78_Operand_PreDec
696 && opc.op[0].reg == RL78_Reg_SP
697 && opc.op[1].type == RL78_Operand_Register)
698 {
699 int rsrc = (bank * RL78_REGS_PER_BANK)
700 + 2 * (opc.op[1].reg - RL78_Reg_AX);
701
702 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
703 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
704 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
705 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
706 after_last_frame_setup_insn = next_pc;
707 }
708 else if (opc.id == RLO_sub
709 && opc.op[0].type == RL78_Operand_Register
710 && opc.op[0].reg == RL78_Reg_SP
711 && opc.op[1].type == RL78_Operand_Immediate)
712 {
713 int addend = opc.op[1].addend;
714
715 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
716 -addend);
717 after_last_frame_setup_insn = next_pc;
718 }
719 else
720 {
721 /* Terminate the prologue scan. */
722 break;
723 }
724
725 pc = next_pc;
726 }
727
728 /* Is the frame size (offset, really) a known constant? */
729 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
730 result->frame_size = reg[RL78_SP_REGNUM].k;
731
732 /* Record where all the registers were saved. */
733 pv_area_scan (stack, check_for_saved, (void *) result);
734
735 result->prologue_end = after_last_frame_setup_insn;
736
737 do_cleanups (back_to);
738}
739
740/* Implement the "addr_bits_remove" gdbarch method. */
741
742static CORE_ADDR
743rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
744{
745 return addr & 0xffffff;
746}
747
748/* Implement the "address_to_pointer" gdbarch method. */
749
750static void
751rl78_address_to_pointer (struct gdbarch *gdbarch,
752 struct type *type, gdb_byte *buf, CORE_ADDR addr)
753{
754 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
755
756 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
757 addr & 0xffffff);
758}
759
760/* Implement the "pointer_to_address" gdbarch method. */
761
762static CORE_ADDR
763rl78_pointer_to_address (struct gdbarch *gdbarch,
764 struct type *type, const gdb_byte *buf)
765{
766 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
767 CORE_ADDR addr
768 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
769
770 /* Is it a code address? */
771 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
772 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
773 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
774 || TYPE_LENGTH (type) == 4)
775 return rl78_make_instruction_address (addr);
776 else
777 return rl78_make_data_address (addr);
778}
779
780/* Implement the "skip_prologue" gdbarch method. */
781
782static CORE_ADDR
783rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
784{
e4569f1e 785 const char *name;
9058f767
KB		 786 CORE_ADDR func_addr, func_end;
787 struct rl78_prologue p;
788
789 /* Try to find the extent of the function that contains PC. */
790 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
791 return pc;
792
793 rl78_analyze_prologue (pc, func_end, &p);
794 return p.prologue_end;
795}
796
797/* Implement the "unwind_pc" gdbarch method. */
798
799static CORE_ADDR
800rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
801{
802 return rl78_addr_bits_remove
803 (arch, frame_unwind_register_unsigned (next_frame,
804 RL78_PC_REGNUM));
805}
806
807/* Implement the "unwind_sp" gdbarch method. */
808
809static CORE_ADDR
810rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
811{
812 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
813}
814
815/* Given a frame described by THIS_FRAME, decode the prologue of its
816 associated function if there is not cache entry as specified by
817 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
818 return that struct as the value of this function. */
819
820static struct rl78_prologue *
821rl78_analyze_frame_prologue (struct frame_info *this_frame,
822 void **this_prologue_cache)
823{
824 if (!*this_prologue_cache)
825 {
826 CORE_ADDR func_start, stop_addr;
827
828 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
829
830 func_start = get_frame_func (this_frame);
831 stop_addr = get_frame_pc (this_frame);
832
833 /* If we couldn't find any function containing the PC, then
834 just initialize the prologue cache, but don't do anything. */
835 if (!func_start)
836 stop_addr = func_start;
837
838 rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
839 }
840
841 return *this_prologue_cache;
842}
843
844/* Given a frame and a prologue cache, return this frame's base. */
845
846static CORE_ADDR
847rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
848{
849 struct rl78_prologue *p
850 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
851 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
852
853 return rl78_make_data_address (sp - p->frame_size);
854}
855
856/* Implement the "frame_this_id" method for unwinding frames. */
857
858static void
859rl78_this_id (struct frame_info *this_frame,
860 void **this_prologue_cache, struct frame_id *this_id)
861{
862 *this_id = frame_id_build (rl78_frame_base (this_frame,
863 this_prologue_cache),
864 get_frame_func (this_frame));
865}
866
867/* Implement the "frame_prev_register" method for unwinding frames. */
868
869static struct value *
870rl78_prev_register (struct frame_info *this_frame,
871 void **this_prologue_cache, int regnum)
872{
873 struct rl78_prologue *p
874 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
875 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
876
877 if (regnum == RL78_SP_REGNUM)
878 return frame_unwind_got_constant (this_frame, regnum, frame_base);
879
880 else if (regnum == RL78_SPL_REGNUM)
881 return frame_unwind_got_constant (this_frame, regnum,
882 (frame_base & 0xff));
883
884 else if (regnum == RL78_SPH_REGNUM)
885 return frame_unwind_got_constant (this_frame, regnum,
886 ((frame_base >> 8) & 0xff));
887
888 /* If prologue analysis says we saved this register somewhere,
889 return a description of the stack slot holding it. */
890 else if (p->reg_offset[regnum] != 1)
891 {
892 struct value *rv =
893 frame_unwind_got_memory (this_frame, regnum,
894 frame_base + p->reg_offset[regnum]);
895
896 if (regnum == RL78_PC_REGNUM)
897 {
898 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
899
900 return frame_unwind_got_constant (this_frame, regnum, pc);
901 }
902 return rv;
903 }
904
905 /* Otherwise, presume we haven't changed the value of this
906 register, and get it from the next frame. */
907 else
908 return frame_unwind_got_register (this_frame, regnum, regnum);
909}
910
911static const struct frame_unwind rl78_unwind =
912{
913 NORMAL_FRAME,
914 default_frame_unwind_stop_reason,
915 rl78_this_id,
916 rl78_prev_register,
917 NULL,
918 default_frame_sniffer
919};
920
921/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
922
923static int
924rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
925{
926 if (0 <= reg && reg <= 31)
927 {
928 if ((reg & 1) == 0)
929 /* Map even registers to their 16-bit counterparts. This
930 is usually what is required from the DWARF info. */
931 return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
932 else
933 return reg;
934 }
935 else if (reg == 32)
936 return RL78_SP_REGNUM;
937 else if (reg == 33)
b3ce41ea
KB		 938 return -1; /* ap */
939 else if (reg == 34)
940 return RL78_PSW_REGNUM;
941 else if (reg == 35)
942 return RL78_ES_REGNUM;
943 else if (reg == 36)
944 return RL78_CS_REGNUM;
945 else if (reg == 37)
9058f767
KB		 946 return RL78_PC_REGNUM;
947 else
948 internal_error (__FILE__, __LINE__,
949 _("Undefined dwarf2 register mapping of reg %d"),
950 reg);
951}
952
c47a44f4
KB		 953/* Implement the `register_sim_regno' gdbarch method. */
954
955static int
956rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
957{
958 gdb_assert (regnum < RL78_NUM_REGS);
959
960 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
961 just want to override the default here which disallows register
962 numbers which have no names. */
963 return regnum;
964}
965
9058f767
KB		 966/* Implement the "return_value" gdbarch method. */
967
968static enum return_value_convention
969rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 970 struct value *function,
9058f767
KB		 971 struct type *valtype,
972 struct regcache *regcache,
973 gdb_byte *readbuf, const gdb_byte *writebuf)
974{
975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
976 ULONGEST valtype_len = TYPE_LENGTH (valtype);
977
978 if (valtype_len > 8)
979 return RETURN_VALUE_STRUCT_CONVENTION;
980
981 if (readbuf)
982 {
983 ULONGEST u;
c47a44f4 984 int argreg = RL78_RAW_BANK1_R0_REGNUM;
9058f767
KB		 985 int offset = 0;
986
987 while (valtype_len > 0)
988 {
989 regcache_cooked_read_unsigned (regcache, argreg, &u);
990 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
991 valtype_len -= 1;
992 offset += 1;
993 argreg++;
994 }
995 }
996
997 if (writebuf)
998 {
999 ULONGEST u;
c47a44f4 1000 int argreg = RL78_RAW_BANK1_R0_REGNUM;
9058f767
KB		 1001 int offset = 0;
1002
1003 while (valtype_len > 0)
1004 {
1005 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
1006 regcache_cooked_write_unsigned (regcache, argreg, u);
1007 valtype_len -= 1;
1008 offset += 1;
1009 argreg++;
1010 }
1011 }
1012
1013 return RETURN_VALUE_REGISTER_CONVENTION;
1014}
1015
1016
1017/* Implement the "frame_align" gdbarch method. */
1018
1019static CORE_ADDR
1020rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1021{
1022 return rl78_make_data_address (align_down (sp, 2));
1023}
1024
1025
1026/* Implement the "dummy_id" gdbarch method. */
1027
1028static struct frame_id
1029rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1030{
1031 return
1032 frame_id_build (rl78_make_data_address
1033 (get_frame_register_unsigned
1034 (this_frame, RL78_SP_REGNUM)),
1035 get_frame_pc (this_frame));
1036}
1037
1038
1039/* Implement the "push_dummy_call" gdbarch method. */
1040
1041static CORE_ADDR
1042rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1043 struct regcache *regcache, CORE_ADDR bp_addr,
1044 int nargs, struct value **args, CORE_ADDR sp,
1045 int struct_return, CORE_ADDR struct_addr)
1046{
1047 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1048 gdb_byte buf[4];
1049 int i;
1050
1051 /* Push arguments in reverse order. */
1052 for (i = nargs - 1; i >= 0; i--)
1053 {
1054 struct type *value_type = value_enclosing_type (args[i]);
1055 int len = TYPE_LENGTH (value_type);
1056 int container_len = (len + 1) & ~1;
9058f767
KB		 1057
1058 sp -= container_len;
1059 write_memory (rl78_make_data_address (sp),
1060 value_contents_all (args[i]), len);
1061 }
1062
1063 /* Store struct value address. */
1064 if (struct_return)
1065 {
1066 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1067 sp -= 2;
1068 write_memory (rl78_make_data_address (sp), buf, 2);
1069 }
1070
1071 /* Store return address. */
1072 sp -= 4;
1073 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1074 write_memory (rl78_make_data_address (sp), buf, 4);
1075
1076 /* Finally, update the stack pointer... */
1077 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1078
1079 /* DWARF2/GCC uses the stack address *before* the function call as a
1080 frame's CFA. */
1081 return rl78_make_data_address (sp + 4);
1082}
1083
1084/* Allocate and initialize a gdbarch object. */
1085
1086static struct gdbarch *
1087rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1088{
1089 struct gdbarch *gdbarch;
1090 struct gdbarch_tdep *tdep;
1091 int elf_flags;
1092
1093 /* Extract the elf_flags if available. */
1094 if (info.abfd != NULL
1095 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1096 elf_flags = elf_elfheader (info.abfd)->e_flags;
1097 else
1098 elf_flags = 0;
1099
1100
1101 /* Try to find the architecture in the list of already defined
1102 architectures. */
1103 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1104 arches != NULL;
1105 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1106 {
1107 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1108 continue;
1109
1110 return arches->gdbarch;
1111 }
1112
1113 /* None found, create a new architecture from the information
1114 provided. */
1115 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
1116 gdbarch = gdbarch_alloc (&info, tdep);
1117 tdep->elf_flags = elf_flags;
1118
1119 /* Initialize types. */
1120 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1121 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1122 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1123 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1124 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1125 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1126 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1127
1128 tdep->rl78_data_pointer
1129 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1130 xstrdup ("rl78_data_addr_t"));
1131 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1132 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1133
1134 tdep->rl78_code_pointer
1135 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1136 xstrdup ("rl78_code_addr_t"));
1137 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1138 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1139
1140 /* Registers. */
1141 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1142 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
1143 set_gdbarch_register_name (gdbarch, rl78_register_name);
1144 set_gdbarch_register_type (gdbarch, rl78_register_type);
1145 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1146 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1147 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1148 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1149 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1150 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1151 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1152
1153 /* Data types. */
1154 set_gdbarch_char_signed (gdbarch, 0);
1155 set_gdbarch_short_bit (gdbarch, 16);
1156 set_gdbarch_int_bit (gdbarch, 16);
1157 set_gdbarch_long_bit (gdbarch, 32);
1158 set_gdbarch_long_long_bit (gdbarch, 64);
1159 set_gdbarch_ptr_bit (gdbarch, 16);
1160 set_gdbarch_addr_bit (gdbarch, 32);
b3ce41ea 1161 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
9058f767
KB		 1162 set_gdbarch_float_bit (gdbarch, 32);
1163 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1164 set_gdbarch_double_bit (gdbarch, 32);
1165 set_gdbarch_long_double_bit (gdbarch, 64);
1166 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1167 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1168 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1169 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1170 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1171
1172 /* Breakpoints. */
1173 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1174 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1175
1176 /* Disassembly. */
1177 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1178
1179 /* Frames, prologues, etc. */
1180 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1181 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1182 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1183 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1184 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
b3ce41ea
KB		 1185
1186 dwarf2_append_unwinders (gdbarch);
9058f767
KB		 1187 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1188
1189 /* Dummy frames, return values. */
1190 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1191 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1192 set_gdbarch_return_value (gdbarch, rl78_return_value);
1193
1194 /* Virtual tables. */
1195 set_gdbarch_vbit_in_delta (gdbarch, 1);
1196
1197 return gdbarch;
1198}
1199
693be288
JK		 1200/* -Wmissing-prototypes */
1201extern initialize_file_ftype _initialize_rl78_tdep;
1202
9058f767
KB		 1203/* Register the above initialization routine. */
1204
1205void
1206_initialize_rl78_tdep (void)
1207{
1208 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1209}
GDB Binutils - Deliverables
This page took 0.313897 seconds and 4 git commands to generate.