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struct breakpoint: Fix indentation
[deliverable/binutils-gdb.git] / gdb / rl78-tdep.c
CommitLineData
9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
61baf725 3 Copyright (C) 2011-2017 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
ba89f962 97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
c47a44f4
KB		 98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
ba89f962
KB		 108 RL78_PC_REGNUM = RL78_NUM_REGS,
109 RL78_SP_REGNUM,
c47a44f4
KB		 110
111 RL78_X_REGNUM,
112 RL78_A_REGNUM,
113 RL78_C_REGNUM,
114 RL78_B_REGNUM,
115 RL78_E_REGNUM,
116 RL78_D_REGNUM,
117 RL78_L_REGNUM,
118 RL78_H_REGNUM,
119
120 RL78_AX_REGNUM,
121 RL78_BC_REGNUM,
122 RL78_DE_REGNUM,
123 RL78_HL_REGNUM,
124
125 RL78_BANK0_R0_REGNUM,
9058f767
KB		 126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
133
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
142
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
151
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
160
c47a44f4 161 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
165
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
170
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
175
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
180
6d451942
KB		 181 /* These are the same as the above 16 registers, but have
182 a pointer type for use as base registers in expression
183 evaluation. These are not user visible registers. */
184 RL78_BANK0_RP0_PTR_REGNUM,
185 RL78_BANK0_RP1_PTR_REGNUM,
186 RL78_BANK0_RP2_PTR_REGNUM,
187 RL78_BANK0_RP3_PTR_REGNUM,
188
189 RL78_BANK1_RP0_PTR_REGNUM,
190 RL78_BANK1_RP1_PTR_REGNUM,
191 RL78_BANK1_RP2_PTR_REGNUM,
192 RL78_BANK1_RP3_PTR_REGNUM,
193
194 RL78_BANK2_RP0_PTR_REGNUM,
195 RL78_BANK2_RP1_PTR_REGNUM,
196 RL78_BANK2_RP2_PTR_REGNUM,
197 RL78_BANK2_RP3_PTR_REGNUM,
198
199 RL78_BANK3_RP0_PTR_REGNUM,
200 RL78_BANK3_RP1_PTR_REGNUM,
201 RL78_BANK3_RP2_PTR_REGNUM,
202 RL78_BANK3_RP3_PTR_REGNUM,
203
9058f767
KB		 204 RL78_NUM_TOTAL_REGS,
205 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
206};
207
0bca7f99
KB		 208#define RL78_SP_ADDR 0xffff8
209
9058f767
KB		 210/* Architecture specific data. */
211
212struct gdbarch_tdep
213{
214 /* The ELF header flags specify the multilib used. */
215 int elf_flags;
216
217 struct type *rl78_void,
218 *rl78_uint8,
219 *rl78_int8,
220 *rl78_uint16,
221 *rl78_int16,
222 *rl78_uint32,
223 *rl78_int32,
224 *rl78_data_pointer,
e6280369
KB		 225 *rl78_code_pointer,
226 *rl78_psw_type;
9058f767
KB		 227};
228
229/* This structure holds the results of a prologue analysis. */
230
231struct rl78_prologue
232{
233 /* The offset from the frame base to the stack pointer --- always
234 zero or negative.
235
236 Calling this a "size" is a bit misleading, but given that the
237 stack grows downwards, using offsets for everything keeps one
238 from going completely sign-crazy: you never change anything's
239 sign for an ADD instruction; always change the second operand's
240 sign for a SUB instruction; and everything takes care of
241 itself. */
242 int frame_size;
243
244 /* Non-zero if this function has initialized the frame pointer from
245 the stack pointer, zero otherwise. */
246 int has_frame_ptr;
247
248 /* If has_frame_ptr is non-zero, this is the offset from the frame
249 base to where the frame pointer points. This is always zero or
250 negative. */
251 int frame_ptr_offset;
252
253 /* The address of the first instruction at which the frame has been
254 set up and the arguments are where the debug info says they are
255 --- as best as we can tell. */
256 CORE_ADDR prologue_end;
257
258 /* reg_offset[R] is the offset from the CFA at which register R is
259 saved, or 1 if register R has not been saved. (Real values are
260 always zero or negative.) */
261 int reg_offset[RL78_NUM_TOTAL_REGS];
262};
263
1a31b34a
YQ		 264/* Construct type for PSW register. */
265
266static struct type *
267rl78_psw_type (struct gdbarch *gdbarch)
268{
269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270
271 if (tdep->rl78_psw_type == NULL)
272 {
273 tdep->rl78_psw_type = arch_flags_type (gdbarch,
274 "builtin_type_rl78_psw", 1);
275 append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
276 append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
277 append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
278 append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
279 append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
280 append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
281 append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
282 append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
283 }
284
285 return tdep->rl78_psw_type;
286}
287
9058f767
KB		 288/* Implement the "register_type" gdbarch method. */
289
290static struct type *
291rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
292{
293 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
294
295 if (reg_nr == RL78_PC_REGNUM)
296 return tdep->rl78_code_pointer;
ba89f962
KB		 297 else if (reg_nr == RL78_RAW_PC_REGNUM)
298 return tdep->rl78_uint32;
e6280369 299 else if (reg_nr == RL78_PSW_REGNUM)
1a31b34a 300 return rl78_psw_type (gdbarch);
9058f767 301 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 302 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
303 || (RL78_BANK0_R0_REGNUM <= reg_nr
304 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767 305 return tdep->rl78_int8;
6d451942
KB		 306 else if (reg_nr == RL78_SP_REGNUM
307 || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
308 && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
9058f767 309 return tdep->rl78_data_pointer;
6d451942
KB		 310 else
311 return tdep->rl78_int16;
9058f767
KB		 312}
313
314/* Implement the "register_name" gdbarch method. */
315
316static const char *
317rl78_register_name (struct gdbarch *gdbarch, int regnr)
318{
319 static const char *const reg_names[] =
320 {
c47a44f4
KB		 321 "", /* bank0_r0 */
322 "", /* bank0_r1 */
323 "", /* bank0_r2 */
324 "", /* bank0_r3 */
325 "", /* bank0_r4 */
326 "", /* bank0_r5 */
327 "", /* bank0_r6 */
328 "", /* bank0_r7 */
329
330 "", /* bank1_r0 */
331 "", /* bank1_r1 */
332 "", /* bank1_r2 */
333 "", /* bank1_r3 */
334 "", /* bank1_r4 */
335 "", /* bank1_r5 */
336 "", /* bank1_r6 */
337 "", /* bank1_r7 */
338
339 "", /* bank2_r0 */
340 "", /* bank2_r1 */
341 "", /* bank2_r2 */
342 "", /* bank2_r3 */
343 "", /* bank2_r4 */
344 "", /* bank2_r5 */
345 "", /* bank2_r6 */
346 "", /* bank2_r7 */
347
348 "", /* bank3_r0 */
349 "", /* bank3_r1 */
350 "", /* bank3_r2 */
351 "", /* bank3_r3 */
352 "", /* bank3_r4 */
353 "", /* bank3_r5 */
354 "", /* bank3_r6 */
355 "", /* bank3_r7 */
356
357 "psw",
358 "es",
359 "cs",
ba89f962 360 "",
c47a44f4
KB		 361
362 "", /* spl */
363 "", /* sph */
364 "pmc",
365 "mem",
366
ba89f962 367 "pc",
c47a44f4
KB		 368 "sp",
369
370 "x",
371 "a",
372 "c",
373 "b",
374 "e",
375 "d",
376 "l",
377 "h",
378
379 "ax",
380 "bc",
381 "de",
382 "hl",
383
9058f767
KB		 384 "bank0_r0",
385 "bank0_r1",
386 "bank0_r2",
387 "bank0_r3",
388 "bank0_r4",
389 "bank0_r5",
390 "bank0_r6",
391 "bank0_r7",
392
393 "bank1_r0",
394 "bank1_r1",
395 "bank1_r2",
396 "bank1_r3",
397 "bank1_r4",
398 "bank1_r5",
399 "bank1_r6",
400 "bank1_r7",
401
402 "bank2_r0",
403 "bank2_r1",
404 "bank2_r2",
405 "bank2_r3",
406 "bank2_r4",
407 "bank2_r5",
408 "bank2_r6",
409 "bank2_r7",
410
411 "bank3_r0",
412 "bank3_r1",
413 "bank3_r2",
414 "bank3_r3",
415 "bank3_r4",
416 "bank3_r5",
417 "bank3_r6",
418 "bank3_r7",
419
9058f767
KB		 420 "bank0_rp0",
421 "bank0_rp1",
422 "bank0_rp2",
423 "bank0_rp3",
424
425 "bank1_rp0",
426 "bank1_rp1",
427 "bank1_rp2",
428 "bank1_rp3",
429
430 "bank2_rp0",
431 "bank2_rp1",
432 "bank2_rp2",
433 "bank2_rp3",
434
435 "bank3_rp0",
436 "bank3_rp1",
437 "bank3_rp2",
6d451942
KB		 438 "bank3_rp3",
439
440 /* The 16 register slots would be named
441 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
442 want these to be user visible registers. */
443 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
c47a44f4 444 };
9058f767 445
c47a44f4
KB		 446 return reg_names[regnr];
447}
9058f767 448
bc3c6b36
KB		 449/* Implement the "register_name" gdbarch method for the g10 variant. */
450
451static const char *
452rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
453{
454 static const char *const reg_names[] =
455 {
456 "", /* bank0_r0 */
457 "", /* bank0_r1 */
458 "", /* bank0_r2 */
459 "", /* bank0_r3 */
460 "", /* bank0_r4 */
461 "", /* bank0_r5 */
462 "", /* bank0_r6 */
463 "", /* bank0_r7 */
464
465 "", /* bank1_r0 */
466 "", /* bank1_r1 */
467 "", /* bank1_r2 */
468 "", /* bank1_r3 */
469 "", /* bank1_r4 */
470 "", /* bank1_r5 */
471 "", /* bank1_r6 */
472 "", /* bank1_r7 */
473
474 "", /* bank2_r0 */
475 "", /* bank2_r1 */
476 "", /* bank2_r2 */
477 "", /* bank2_r3 */
478 "", /* bank2_r4 */
479 "", /* bank2_r5 */
480 "", /* bank2_r6 */
481 "", /* bank2_r7 */
482
483 "", /* bank3_r0 */
484 "", /* bank3_r1 */
485 "", /* bank3_r2 */
486 "", /* bank3_r3 */
487 "", /* bank3_r4 */
488 "", /* bank3_r5 */
489 "", /* bank3_r6 */
490 "", /* bank3_r7 */
491
492 "psw",
493 "es",
494 "cs",
495 "",
496
497 "", /* spl */
498 "", /* sph */
499 "pmc",
500 "mem",
501
502 "pc",
503 "sp",
504
505 "x",
506 "a",
507 "c",
508 "b",
509 "e",
510 "d",
511 "l",
512 "h",
513
514 "ax",
515 "bc",
516 "de",
517 "hl",
518
519 "bank0_r0",
520 "bank0_r1",
521 "bank0_r2",
522 "bank0_r3",
523 "bank0_r4",
524 "bank0_r5",
525 "bank0_r6",
526 "bank0_r7",
527
528 "",
529 "",
530 "",
531 "",
532 "",
533 "",
534 "",
535 "",
536
537 "",
538 "",
539 "",
540 "",
541 "",
542 "",
543 "",
544 "",
545
546 "",
547 "",
548 "",
549 "",
550 "",
551 "",
552 "",
553 "",
554
555 "bank0_rp0",
556 "bank0_rp1",
557 "bank0_rp2",
558 "bank0_rp3",
559
560 "",
561 "",
562 "",
563 "",
564
565 "",
566 "",
567 "",
568 "",
569
570 "",
571 "",
572 "",
6d451942
KB		 573 "",
574
575 /* The 16 register slots would be named
576 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
577 want these to be user visible registers. */
578 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
bc3c6b36
KB		 579 };
580
581 return reg_names[regnr];
582}
583
c47a44f4 584/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 585
c47a44f4
KB		 586static int
587rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
588 struct reggroup *group)
589{
590 if (group == all_reggroup)
591 return 1;
9058f767 592
c47a44f4
KB		 593 /* All other registers are saved and restored. */
594 if (group == save_reggroup || group == restore_reggroup)
595 {
b3ce41ea 596 if ((regnum < RL78_NUM_REGS
ba89f962
KB		 597 && regnum != RL78_SPL_REGNUM
598 && regnum != RL78_SPH_REGNUM
599 && regnum != RL78_RAW_PC_REGNUM)
600 || regnum == RL78_SP_REGNUM
601 || regnum == RL78_PC_REGNUM)
c47a44f4
KB		 602 return 1;
603 else
604 return 0;
605 }
606
607 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
608 || regnum == RL78_ES_REGNUM
609 || regnum == RL78_CS_REGNUM
610 || regnum == RL78_SPL_REGNUM
611 || regnum == RL78_SPH_REGNUM
612 || regnum == RL78_PMC_REGNUM
613 || regnum == RL78_MEM_REGNUM
ba89f962 614 || regnum == RL78_RAW_PC_REGNUM
c47a44f4
KB		 615 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
616 return group == system_reggroup;
617
618 return group == general_reggroup;
9058f767
KB		 619}
620
621/* Strip bits to form an instruction address. (When fetching a
622 32-bit address from the stack, the high eight bits are garbage.
623 This function strips off those unused bits.) */
624
625static CORE_ADDR
626rl78_make_instruction_address (CORE_ADDR addr)
627{
628 return addr & 0xffffff;
629}
630
631/* Set / clear bits necessary to make a data address. */
632
633static CORE_ADDR
634rl78_make_data_address (CORE_ADDR addr)
635{
636 return (addr & 0xffff) | 0xf0000;
637}
638
639/* Implement the "pseudo_register_read" gdbarch method. */
640
641static enum register_status
642rl78_pseudo_register_read (struct gdbarch *gdbarch,
643 struct regcache *regcache,
644 int reg, gdb_byte *buffer)
645{
646 enum register_status status;
647
c47a44f4
KB		 648 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
649 {
650 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
651 + (reg - RL78_BANK0_R0_REGNUM);
652
653 status = regcache_raw_read (regcache, raw_regnum, buffer);
654 }
655 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 656 {
657 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 658 + RL78_RAW_BANK0_R0_REGNUM;
9058f767 659
6d451942
KB		 660 status = regcache_raw_read (regcache, raw_regnum, buffer);
661 if (status == REG_VALID)
662 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
663 }
664 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
665 {
666 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
667 + RL78_RAW_BANK0_R0_REGNUM;
668
9058f767
KB		 669 status = regcache_raw_read (regcache, raw_regnum, buffer);
670 if (status == REG_VALID)
671 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
672 }
673 else if (reg == RL78_SP_REGNUM)
674 {
675 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
676 if (status == REG_VALID)
677 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
678 }
ba89f962
KB		 679 else if (reg == RL78_PC_REGNUM)
680 {
681 gdb_byte rawbuf[4];
682
683 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
684 memcpy (buffer, rawbuf, 3);
685 }
9058f767
KB		 686 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
687 {
688 ULONGEST psw;
689
690 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
691 if (status == REG_VALID)
692 {
693 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
694 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 695 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 696 + (reg - RL78_X_REGNUM);
697 status = regcache_raw_read (regcache, raw_regnum, buffer);
698 }
699 }
700 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
701 {
702 ULONGEST psw;
703
704 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
705 if (status == REG_VALID)
706 {
707 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
708 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 709 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 710 + 2 * (reg - RL78_AX_REGNUM);
711 status = regcache_raw_read (regcache, raw_regnum, buffer);
712 if (status == REG_VALID)
713 status = regcache_raw_read (regcache, raw_regnum + 1,
714 buffer + 1);
715 }
716 }
717 else
718 gdb_assert_not_reached ("invalid pseudo register number");
719 return status;
720}
721
722/* Implement the "pseudo_register_write" gdbarch method. */
723
724static void
725rl78_pseudo_register_write (struct gdbarch *gdbarch,
726 struct regcache *regcache,
727 int reg, const gdb_byte *buffer)
728{
c47a44f4
KB		 729 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
730 {
731 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
732 + (reg - RL78_BANK0_R0_REGNUM);
733
734 regcache_raw_write (regcache, raw_regnum, buffer);
735 }
736 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 737 {
738 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 739 + RL78_RAW_BANK0_R0_REGNUM;
9058f767 740
6d451942
KB		 741 regcache_raw_write (regcache, raw_regnum, buffer);
742 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
743 }
744 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
745 {
746 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
747 + RL78_RAW_BANK0_R0_REGNUM;
748
9058f767
KB		 749 regcache_raw_write (regcache, raw_regnum, buffer);
750 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
751 }
752 else if (reg == RL78_SP_REGNUM)
753 {
754 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
755 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
756 }
ba89f962
KB		 757 else if (reg == RL78_PC_REGNUM)
758 {
759 gdb_byte rawbuf[4];
760
761 memcpy (rawbuf, buffer, 3);
762 rawbuf[3] = 0;
763 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
764 }
9058f767
KB		 765 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
766 {
767 ULONGEST psw;
768 int bank;
769 int raw_regnum;
770
771 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
772 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
773 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 774 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 775 + (reg - RL78_X_REGNUM);
776 regcache_raw_write (regcache, raw_regnum, buffer);
777 }
778 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
779 {
780 ULONGEST psw;
781 int bank, raw_regnum;
782
783 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
784 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
785 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 786 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 787 + 2 * (reg - RL78_AX_REGNUM);
788 regcache_raw_write (regcache, raw_regnum, buffer);
789 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
790 }
791 else
792 gdb_assert_not_reached ("invalid pseudo register number");
793}
794
598cc9dc
YQ		 795/* The documented BRK instruction is actually a two byte sequence,
796 {0x61, 0xcc}, but instructions may be as short as one byte.
797 Correspondence with Renesas revealed that the one byte sequence
798 0xff is used when a one byte breakpoint instruction is required. */
04180708 799constexpr gdb_byte rl78_break_insn[] = { 0xff };
9058f767 800
04180708 801typedef BP_MANIPULATION (rl78_break_insn) rl78_breakpoint;
9058f767
KB		 802
803/* Define a "handle" struct for fetching the next opcode. */
804
805struct rl78_get_opcode_byte_handle
806{
807 CORE_ADDR pc;
808};
809
0bca7f99
KB		 810static int
811opc_reg_to_gdb_regnum (int opcreg)
812{
813 switch (opcreg)
814 {
815 case RL78_Reg_X:
816 return RL78_X_REGNUM;
817 case RL78_Reg_A:
818 return RL78_A_REGNUM;
819 case RL78_Reg_C:
820 return RL78_C_REGNUM;
821 case RL78_Reg_B:
822 return RL78_B_REGNUM;
823 case RL78_Reg_E:
824 return RL78_E_REGNUM;
825 case RL78_Reg_D:
826 return RL78_D_REGNUM;
827 case RL78_Reg_L:
828 return RL78_L_REGNUM;
829 case RL78_Reg_H:
830 return RL78_H_REGNUM;
831 case RL78_Reg_AX:
832 return RL78_AX_REGNUM;
833 case RL78_Reg_BC:
834 return RL78_BC_REGNUM;
835 case RL78_Reg_DE:
836 return RL78_DE_REGNUM;
837 case RL78_Reg_HL:
838 return RL78_HL_REGNUM;
839 case RL78_Reg_SP:
840 return RL78_SP_REGNUM;
841 case RL78_Reg_PSW:
842 return RL78_PSW_REGNUM;
843 case RL78_Reg_CS:
844 return RL78_CS_REGNUM;
845 case RL78_Reg_ES:
846 return RL78_ES_REGNUM;
847 case RL78_Reg_PMC:
848 return RL78_PMC_REGNUM;
849 case RL78_Reg_MEM:
850 return RL78_MEM_REGNUM;
851 default:
852 internal_error (__FILE__, __LINE__,
853 _("Undefined mapping for opc reg %d"),
854 opcreg);
855 }
856
857 /* Not reached. */
858 return 0;
859}
860
9058f767
KB		 861/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
862 the memory address of the next byte to fetch. If successful,
863 the address in the handle is updated and the byte fetched is
864 returned as the value of the function. If not successful, -1
865 is returned. */
866
867static int
868rl78_get_opcode_byte (void *handle)
869{
19ba03f4
SM		 870 struct rl78_get_opcode_byte_handle *opcdata
871 = (struct rl78_get_opcode_byte_handle *) handle;
9058f767
KB		 872 int status;
873 gdb_byte byte;
874
875 status = target_read_memory (opcdata->pc, &byte, 1);
876 if (status == 0)
877 {
878 opcdata->pc += 1;
879 return byte;
880 }
881 else
882 return -1;
883}
884
885/* Function for finding saved registers in a 'struct pv_area'; this
886 function is passed to pv_area_scan.
887
888 If VALUE is a saved register, ADDR says it was saved at a constant
889 offset from the frame base, and SIZE indicates that the whole
890 register was saved, record its offset. */
891
892static void
893check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
894 pv_t value)
895{
896 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
897
898 if (value.kind == pvk_register
899 && value.k == 0
900 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 901 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 902 result->reg_offset[value.reg] = addr.k;
903}
904
905/* Analyze a prologue starting at START_PC, going no further than
906 LIMIT_PC. Fill in RESULT as appropriate. */
907
908static void
909rl78_analyze_prologue (CORE_ADDR start_pc,
910 CORE_ADDR limit_pc, struct rl78_prologue *result)
911{
912 CORE_ADDR pc, next_pc;
913 int rn;
914 pv_t reg[RL78_NUM_TOTAL_REGS];
915 struct pv_area *stack;
916 struct cleanup *back_to;
917 CORE_ADDR after_last_frame_setup_insn = start_pc;
918 int bank = 0;
919
920 memset (result, 0, sizeof (*result));
921
922 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
923 {
924 reg[rn] = pv_register (rn, 0);
925 result->reg_offset[rn] = 1;
926 }
927
f5656ead 928 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 929 back_to = make_cleanup_free_pv_area (stack);
930
931 /* The call instruction has saved the return address on the stack. */
932 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
933 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
934
935 pc = start_pc;
936 while (pc < limit_pc)
937 {
938 int bytes_read;
939 struct rl78_get_opcode_byte_handle opcode_handle;
940 RL78_Opcode_Decoded opc;
941
942 opcode_handle.pc = pc;
943 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
0952813b 944 &opcode_handle, RL78_ISA_DEFAULT);
9058f767
KB		 945 next_pc = pc + bytes_read;
946
947 if (opc.id == RLO_sel)
948 {
949 bank = opc.op[1].addend;
950 }
951 else if (opc.id == RLO_mov
952 && opc.op[0].type == RL78_Operand_PreDec
953 && opc.op[0].reg == RL78_Reg_SP
954 && opc.op[1].type == RL78_Operand_Register)
955 {
956 int rsrc = (bank * RL78_REGS_PER_BANK)
957 + 2 * (opc.op[1].reg - RL78_Reg_AX);
958
959 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
960 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
961 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
962 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
963 after_last_frame_setup_insn = next_pc;
964 }
965 else if (opc.id == RLO_sub
966 && opc.op[0].type == RL78_Operand_Register
967 && opc.op[0].reg == RL78_Reg_SP
968 && opc.op[1].type == RL78_Operand_Immediate)
969 {
970 int addend = opc.op[1].addend;
971
972 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
973 -addend);
974 after_last_frame_setup_insn = next_pc;
975 }
0bca7f99
KB		 976 else if (opc.id == RLO_mov
977 && opc.size == RL78_Word
978 && opc.op[0].type == RL78_Operand_Register
979 && opc.op[1].type == RL78_Operand_Indirect
980 && opc.op[1].addend == RL78_SP_ADDR)
981 {
982 reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
983 = reg[RL78_SP_REGNUM];
984 }
985 else if (opc.id == RLO_sub
986 && opc.size == RL78_Word
987 && opc.op[0].type == RL78_Operand_Register
988 && opc.op[1].type == RL78_Operand_Immediate)
989 {
990 int addend = opc.op[1].addend;
991 int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
992
993 reg[regnum] = pv_add_constant (reg[regnum], -addend);
994 }
995 else if (opc.id == RLO_mov
996 && opc.size == RL78_Word
997 && opc.op[0].type == RL78_Operand_Indirect
998 && opc.op[0].addend == RL78_SP_ADDR
999 && opc.op[1].type == RL78_Operand_Register)
1000 {
1001 reg[RL78_SP_REGNUM]
1002 = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
1003 after_last_frame_setup_insn = next_pc;
1004 }
9058f767
KB		 1005 else
1006 {
1007 /* Terminate the prologue scan. */
1008 break;
1009 }
1010
1011 pc = next_pc;
1012 }
1013
1014 /* Is the frame size (offset, really) a known constant? */
1015 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
1016 result->frame_size = reg[RL78_SP_REGNUM].k;
1017
1018 /* Record where all the registers were saved. */
1019 pv_area_scan (stack, check_for_saved, (void *) result);
1020
1021 result->prologue_end = after_last_frame_setup_insn;
1022
1023 do_cleanups (back_to);
1024}
1025
1026/* Implement the "addr_bits_remove" gdbarch method. */
1027
1028static CORE_ADDR
1029rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
1030{
1031 return addr & 0xffffff;
1032}
1033
1034/* Implement the "address_to_pointer" gdbarch method. */
1035
1036static void
1037rl78_address_to_pointer (struct gdbarch *gdbarch,
1038 struct type *type, gdb_byte *buf, CORE_ADDR addr)
1039{
1040 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1041
1042 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
1043 addr & 0xffffff);
1044}
1045
1046/* Implement the "pointer_to_address" gdbarch method. */
1047
1048static CORE_ADDR
1049rl78_pointer_to_address (struct gdbarch *gdbarch,
1050 struct type *type, const gdb_byte *buf)
1051{
1052 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1053 CORE_ADDR addr
1054 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
1055
1056 /* Is it a code address? */
1057 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
1058 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
1059 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
1060 || TYPE_LENGTH (type) == 4)
1061 return rl78_make_instruction_address (addr);
1062 else
1063 return rl78_make_data_address (addr);
1064}
1065
1066/* Implement the "skip_prologue" gdbarch method. */
1067
1068static CORE_ADDR
1069rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1070{
e4569f1e 1071 const char *name;
9058f767
KB		 1072 CORE_ADDR func_addr, func_end;
1073 struct rl78_prologue p;
1074
1075 /* Try to find the extent of the function that contains PC. */
1076 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1077 return pc;
1078
1079 rl78_analyze_prologue (pc, func_end, &p);
1080 return p.prologue_end;
1081}
1082
1083/* Implement the "unwind_pc" gdbarch method. */
1084
1085static CORE_ADDR
1086rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1087{
1088 return rl78_addr_bits_remove
1089 (arch, frame_unwind_register_unsigned (next_frame,
1090 RL78_PC_REGNUM));
1091}
1092
1093/* Implement the "unwind_sp" gdbarch method. */
1094
1095static CORE_ADDR
1096rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1097{
1098 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
1099}
1100
1101/* Given a frame described by THIS_FRAME, decode the prologue of its
1102 associated function if there is not cache entry as specified by
1103 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
1104 return that struct as the value of this function. */
1105
1106static struct rl78_prologue *
1107rl78_analyze_frame_prologue (struct frame_info *this_frame,
1108 void **this_prologue_cache)
1109{
1110 if (!*this_prologue_cache)
1111 {
1112 CORE_ADDR func_start, stop_addr;
1113
1114 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
1115
1116 func_start = get_frame_func (this_frame);
1117 stop_addr = get_frame_pc (this_frame);
1118
1119 /* If we couldn't find any function containing the PC, then
1120 just initialize the prologue cache, but don't do anything. */
1121 if (!func_start)
1122 stop_addr = func_start;
1123
19ba03f4
SM		 1124 rl78_analyze_prologue (func_start, stop_addr,
1125 (struct rl78_prologue *) *this_prologue_cache);
9058f767
KB		 1126 }
1127
19ba03f4 1128 return (struct rl78_prologue *) *this_prologue_cache;
9058f767
KB		 1129}
1130
1131/* Given a frame and a prologue cache, return this frame's base. */
1132
1133static CORE_ADDR
1134rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1135{
1136 struct rl78_prologue *p
1137 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1138 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
1139
1140 return rl78_make_data_address (sp - p->frame_size);
1141}
1142
1143/* Implement the "frame_this_id" method for unwinding frames. */
1144
1145static void
1146rl78_this_id (struct frame_info *this_frame,
1147 void **this_prologue_cache, struct frame_id *this_id)
1148{
1149 *this_id = frame_id_build (rl78_frame_base (this_frame,
1150 this_prologue_cache),
1151 get_frame_func (this_frame));
1152}
1153
1154/* Implement the "frame_prev_register" method for unwinding frames. */
1155
1156static struct value *
1157rl78_prev_register (struct frame_info *this_frame,
1158 void **this_prologue_cache, int regnum)
1159{
1160 struct rl78_prologue *p
1161 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1162 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1163
1164 if (regnum == RL78_SP_REGNUM)
1165 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1166
1167 else if (regnum == RL78_SPL_REGNUM)
1168 return frame_unwind_got_constant (this_frame, regnum,
1169 (frame_base & 0xff));
1170
1171 else if (regnum == RL78_SPH_REGNUM)
1172 return frame_unwind_got_constant (this_frame, regnum,
1173 ((frame_base >> 8) & 0xff));
1174
1175 /* If prologue analysis says we saved this register somewhere,
1176 return a description of the stack slot holding it. */
1177 else if (p->reg_offset[regnum] != 1)
1178 {
1179 struct value *rv =
1180 frame_unwind_got_memory (this_frame, regnum,
1181 frame_base + p->reg_offset[regnum]);
1182
1183 if (regnum == RL78_PC_REGNUM)
1184 {
1185 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1186
1187 return frame_unwind_got_constant (this_frame, regnum, pc);
1188 }
1189 return rv;
1190 }
1191
1192 /* Otherwise, presume we haven't changed the value of this
1193 register, and get it from the next frame. */
1194 else
1195 return frame_unwind_got_register (this_frame, regnum, regnum);
1196}
1197
1198static const struct frame_unwind rl78_unwind =
1199{
1200 NORMAL_FRAME,
1201 default_frame_unwind_stop_reason,
1202 rl78_this_id,
1203 rl78_prev_register,
1204 NULL,
1205 default_frame_sniffer
1206};
1207
1208/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1209
1210static int
1211rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1212{
1213 if (0 <= reg && reg <= 31)
1214 {
1215 if ((reg & 1) == 0)
6d451942
KB		 1216 /* Map even registers to their 16-bit counterparts which have a
1217 pointer type. This is usually what is required from the DWARF
1218 info. */
1219 return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
9058f767
KB		 1220 else
1221 return reg;
1222 }
1223 else if (reg == 32)
1224 return RL78_SP_REGNUM;
1225 else if (reg == 33)
b3ce41ea
KB		 1226 return -1; /* ap */
1227 else if (reg == 34)
1228 return RL78_PSW_REGNUM;
1229 else if (reg == 35)
1230 return RL78_ES_REGNUM;
1231 else if (reg == 36)
1232 return RL78_CS_REGNUM;
1233 else if (reg == 37)
9058f767
KB		 1234 return RL78_PC_REGNUM;
1235 else
0fde2c53 1236 return -1;
9058f767
KB		 1237}
1238
c47a44f4
KB		 1239/* Implement the `register_sim_regno' gdbarch method. */
1240
1241static int
1242rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1243{
1244 gdb_assert (regnum < RL78_NUM_REGS);
1245
1246 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1247 just want to override the default here which disallows register
1248 numbers which have no names. */
1249 return regnum;
1250}
1251
9058f767
KB		 1252/* Implement the "return_value" gdbarch method. */
1253
1254static enum return_value_convention
1255rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 1256 struct value *function,
9058f767
KB		 1257 struct type *valtype,
1258 struct regcache *regcache,
1259 gdb_byte *readbuf, const gdb_byte *writebuf)
1260{
1261 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1262 ULONGEST valtype_len = TYPE_LENGTH (valtype);
bc3c6b36 1263 int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
9058f767
KB		 1264
1265 if (valtype_len > 8)
1266 return RETURN_VALUE_STRUCT_CONVENTION;
1267
1268 if (readbuf)
1269 {
1270 ULONGEST u;
c47a44f4 1271 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1272 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1273 int offset = 0;
1274
1275 while (valtype_len > 0)
1276 {
bc3c6b36
KB		 1277 if (is_g10)
1278 u = read_memory_integer (g10_raddr, 1,
1279 gdbarch_byte_order (gdbarch));
1280 else
1281 regcache_cooked_read_unsigned (regcache, argreg, &u);
9058f767
KB		 1282 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1283 valtype_len -= 1;
1284 offset += 1;
1285 argreg++;
bc3c6b36 1286 g10_raddr++;
9058f767
KB		 1287 }
1288 }
1289
1290 if (writebuf)
1291 {
1292 ULONGEST u;
c47a44f4 1293 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1294 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1295 int offset = 0;
1296
1297 while (valtype_len > 0)
1298 {
1299 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
bc3c6b36
KB		 1300 if (is_g10) {
1301 gdb_byte b = u & 0xff;
1302 write_memory (g10_raddr, &b, 1);
1303 }
1304 else
1305 regcache_cooked_write_unsigned (regcache, argreg, u);
9058f767
KB		 1306 valtype_len -= 1;
1307 offset += 1;
1308 argreg++;
bc3c6b36 1309 g10_raddr++;
9058f767
KB		 1310 }
1311 }
1312
1313 return RETURN_VALUE_REGISTER_CONVENTION;
1314}
1315
1316
1317/* Implement the "frame_align" gdbarch method. */
1318
1319static CORE_ADDR
1320rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1321{
1322 return rl78_make_data_address (align_down (sp, 2));
1323}
1324
1325
1326/* Implement the "dummy_id" gdbarch method. */
1327
1328static struct frame_id
1329rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1330{
1331 return
1332 frame_id_build (rl78_make_data_address
1333 (get_frame_register_unsigned
1334 (this_frame, RL78_SP_REGNUM)),
1335 get_frame_pc (this_frame));
1336}
1337
1338
1339/* Implement the "push_dummy_call" gdbarch method. */
1340
1341static CORE_ADDR
1342rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1343 struct regcache *regcache, CORE_ADDR bp_addr,
1344 int nargs, struct value **args, CORE_ADDR sp,
1345 int struct_return, CORE_ADDR struct_addr)
1346{
1347 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1348 gdb_byte buf[4];
1349 int i;
1350
1351 /* Push arguments in reverse order. */
1352 for (i = nargs - 1; i >= 0; i--)
1353 {
1354 struct type *value_type = value_enclosing_type (args[i]);
1355 int len = TYPE_LENGTH (value_type);
1356 int container_len = (len + 1) & ~1;
9058f767
KB		 1357
1358 sp -= container_len;
1359 write_memory (rl78_make_data_address (sp),
1360 value_contents_all (args[i]), len);
1361 }
1362
1363 /* Store struct value address. */
1364 if (struct_return)
1365 {
1366 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1367 sp -= 2;
1368 write_memory (rl78_make_data_address (sp), buf, 2);
1369 }
1370
1371 /* Store return address. */
1372 sp -= 4;
1373 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1374 write_memory (rl78_make_data_address (sp), buf, 4);
1375
1376 /* Finally, update the stack pointer... */
1377 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1378
1379 /* DWARF2/GCC uses the stack address *before* the function call as a
1380 frame's CFA. */
1381 return rl78_make_data_address (sp + 4);
1382}
1383
1384/* Allocate and initialize a gdbarch object. */
1385
1386static struct gdbarch *
1387rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1388{
1389 struct gdbarch *gdbarch;
1390 struct gdbarch_tdep *tdep;
1391 int elf_flags;
1392
1393 /* Extract the elf_flags if available. */
1394 if (info.abfd != NULL
1395 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1396 elf_flags = elf_elfheader (info.abfd)->e_flags;
1397 else
1398 elf_flags = 0;
1399
1400
1401 /* Try to find the architecture in the list of already defined
1402 architectures. */
1403 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1404 arches != NULL;
1405 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1406 {
1407 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1408 continue;
1409
1410 return arches->gdbarch;
1411 }
1412
1413 /* None found, create a new architecture from the information
1414 provided. */
8d749320 1415 tdep = XNEW (struct gdbarch_tdep);
9058f767
KB		 1416 gdbarch = gdbarch_alloc (&info, tdep);
1417 tdep->elf_flags = elf_flags;
1418
1419 /* Initialize types. */
1420 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1421 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1422 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1423 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1424 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1425 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1426 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1427
1428 tdep->rl78_data_pointer
88dfca6c 1429 = arch_pointer_type (gdbarch, 16, "rl78_data_addr_t", tdep->rl78_void);
9058f767 1430 tdep->rl78_code_pointer
88dfca6c 1431 = arch_pointer_type (gdbarch, 32, "rl78_code_addr_t", tdep->rl78_void);
9058f767
KB		 1432
1433 /* Registers. */
1434 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1435 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
bc3c6b36
KB		 1436 if (tdep->elf_flags & E_FLAG_RL78_G10)
1437 set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1438 else
1439 set_gdbarch_register_name (gdbarch, rl78_register_name);
9058f767
KB		 1440 set_gdbarch_register_type (gdbarch, rl78_register_type);
1441 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1442 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1443 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1444 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1445 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1446 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1447 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1448
1449 /* Data types. */
1450 set_gdbarch_char_signed (gdbarch, 0);
1451 set_gdbarch_short_bit (gdbarch, 16);
1452 set_gdbarch_int_bit (gdbarch, 16);
1453 set_gdbarch_long_bit (gdbarch, 32);
1454 set_gdbarch_long_long_bit (gdbarch, 64);
1455 set_gdbarch_ptr_bit (gdbarch, 16);
1456 set_gdbarch_addr_bit (gdbarch, 32);
b3ce41ea 1457 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
9058f767
KB		 1458 set_gdbarch_float_bit (gdbarch, 32);
1459 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1460 set_gdbarch_double_bit (gdbarch, 32);
1461 set_gdbarch_long_double_bit (gdbarch, 64);
1462 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1463 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1464 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1465 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1466 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1467
1468 /* Breakpoints. */
04180708
YQ		 1469 set_gdbarch_breakpoint_kind_from_pc (gdbarch, rl78_breakpoint::kind_from_pc);
1470 set_gdbarch_sw_breakpoint_from_kind (gdbarch, rl78_breakpoint::bp_from_kind);
9058f767
KB		 1471 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1472
1473 /* Disassembly. */
1474 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1475
1476 /* Frames, prologues, etc. */
1477 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1478 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1479 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1480 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1481 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
b3ce41ea
KB		 1482
1483 dwarf2_append_unwinders (gdbarch);
9058f767
KB		 1484 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1485
1486 /* Dummy frames, return values. */
1487 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1488 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1489 set_gdbarch_return_value (gdbarch, rl78_return_value);
1490
1491 /* Virtual tables. */
1492 set_gdbarch_vbit_in_delta (gdbarch, 1);
1493
1494 return gdbarch;
1495}
1496
693be288
JK		 1497/* -Wmissing-prototypes */
1498extern initialize_file_ftype _initialize_rl78_tdep;
1499
9058f767
KB		 1500/* Register the above initialization routine. */
1501
1502void
1503_initialize_rl78_tdep (void)
1504{
1505 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1506}
GDB Binutils - Deliverables
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