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Update rx sim so that it'll print load statistics.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
0b302171 3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c5aa993b 10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b 17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 19
c378eb4e
MS		 20/* Contributed by Steve Chamberlain
21 sac@cygnus.com. */
c906108c
SS		 22
23#include "defs.h"
24#include "frame.h"
1c0159e0
CV		 25#include "frame-base.h"
26#include "frame-unwind.h"
27#include "dwarf2-frame.h"
c906108c 28#include "symtab.h"
c906108c
SS		 29#include "gdbtypes.h"
30#include "gdbcmd.h"
31#include "gdbcore.h"
32#include "value.h"
33#include "dis-asm.h"
73c1f219 34#include "inferior.h"
c906108c 35#include "gdb_string.h"
1c0159e0 36#include "gdb_assert.h"
b4a20239 37#include "arch-utils.h"
fb409745 38#include "floatformat.h"
4e052eda 39#include "regcache.h"
d16aafd8 40#include "doublest.h"
4be87837 41#include "osabi.h"
dda63807 42#include "reggroups.h"
c9ac0a72 43#include "regset.h"
cb2cf4ce 44#include "objfiles.h"
c906108c 45
ab3b8126 46#include "sh-tdep.h"
04dcf5fa 47#include "sh64-tdep.h"
ab3b8126 48
d658f924 49#include "elf-bfd.h"
1a8629c7
MS		 50#include "solib-svr4.h"
51
55ff77ac 52/* sh flags */
283150cd 53#include "elf/sh.h"
fa8f86ff 54#include "dwarf2.h"
c378eb4e 55/* registers numbers shared with the simulator. */
1c922164 56#include "gdb/sim-sh.h"
283150cd 57
c055b101
CV		 58/* List of "set sh ..." and "show sh ..." commands. */
59static struct cmd_list_element *setshcmdlist = NULL;
60static struct cmd_list_element *showshcmdlist = NULL;
61
62static const char sh_cc_gcc[] = "gcc";
63static const char sh_cc_renesas[] = "renesas";
40478521 64static const char *const sh_cc_enum[] = {
c055b101
CV		 65 sh_cc_gcc,
66 sh_cc_renesas,
67 NULL
68};
69
70static const char *sh_active_calling_convention = sh_cc_gcc;
71
c458d6db 72static void (*sh_show_regs) (struct frame_info *);
cc17453a 73
da962468 74#define SH_NUM_REGS 67
88e04cc1 75
1c0159e0 76struct sh_frame_cache
cc17453a 77{
1c0159e0
CV		 78 /* Base address. */
79 CORE_ADDR base;
80 LONGEST sp_offset;
81 CORE_ADDR pc;
82
c378eb4e 83 /* Flag showing that a frame has been created in the prologue code. */
1c0159e0
CV		 84 int uses_fp;
85
86 /* Saved registers. */
87 CORE_ADDR saved_regs[SH_NUM_REGS];
88 CORE_ADDR saved_sp;
63978407 89};
c906108c 90
c055b101
CV		 91static int
92sh_is_renesas_calling_convention (struct type *func_type)
93{
ca193e27
TS		 94 int val = 0;
95
96 if (func_type)
97 {
98 func_type = check_typedef (func_type);
99
100 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
101 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
102
103 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
104 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
105 val = 1;
106 }
107
108 if (sh_active_calling_convention == sh_cc_renesas)
109 val = 1;
110
111 return val;
c055b101
CV		 112}
113
fa88f677 114static const char *
d93859e2 115sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 116{
617daa0e
CV		 117 static char *register_names[] = {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
121 "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
da962468 127 "", "", "", "", "", "", "", "",
cc17453a
EZ		 128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134}
135
fa88f677 136static const char *
d93859e2 137sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 138{
617daa0e
CV		 139 static char *register_names[] = {
140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
143 "", "",
144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "ssr", "spc",
cc17453a
EZ		 147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 149 "", "", "", "", "", "", "", "",
cc17453a
EZ		 150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156}
157
fa88f677 158static const char *
d93859e2 159sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 160{
617daa0e
CV		 161 static char *register_names[] = {
162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 165 "fpul", "fpscr",
617daa0e
CV		 166 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
167 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
168 "ssr", "spc",
cc17453a
EZ		 169 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
170 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 171 "", "", "", "", "", "", "", "",
cc17453a
EZ		 172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178}
179
2d188dd3 180static const char *
d93859e2 181sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
2d188dd3 182{
617daa0e
CV		 183 static char *register_names[] = {
184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 187 "fpul", "fpscr",
617daa0e
CV		 188 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
189 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
190 "", "",
2d188dd3
NC		 191 "", "", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
da962468
CV		 193 "", "", "", "", "", "", "", "",
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200}
201
202static const char *
d93859e2 203sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 204{
205 static char *register_names[] = {
206 /* general registers 0-15 */
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 /* 16 - 22 */
210 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 /* 23, 24 */
212 "fpul", "fpscr",
213 /* floating point registers 25 - 40 */
214 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
215 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
216 /* 41, 42 */
217 "", "",
218 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 219 the bank register (63). */
da962468
CV		 220 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
221 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
222 "machb", "ivnb", "prb", "gbrb", "maclb",
223 /* 63: register bank number, not a real register but used to
224 communicate the register bank currently get/set. This register
225 is hidden to the user, who manipulates it using the pseudo
226 register called "bank" (67). See below. */
227 "",
228 /* 64 - 66 */
229 "ibcr", "ibnr", "tbr",
230 /* 67: register bank number, the user visible pseudo register. */
231 "bank",
232 /* double precision (pseudo) 68 - 75 */
233 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
234 };
235 if (reg_nr < 0)
236 return NULL;
237 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
238 return NULL;
239 return register_names[reg_nr];
240}
241
242static const char *
d93859e2 243sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 244{
245 static char *register_names[] = {
246 /* general registers 0-15 */
247 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
248 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
249 /* 16 - 22 */
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 /* 23, 24 */
252 "", "",
253 /* floating point registers 25 - 40 */
254 "", "", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
256 /* 41, 42 */
257 "", "",
258 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 259 the bank register (63). */
da962468
CV		 260 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
261 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
262 "machb", "ivnb", "prb", "gbrb", "maclb",
263 /* 63: register bank number, not a real register but used to
264 communicate the register bank currently get/set. This register
265 is hidden to the user, who manipulates it using the pseudo
266 register called "bank" (67). See below. */
267 "",
268 /* 64 - 66 */
269 "ibcr", "ibnr", "tbr",
270 /* 67: register bank number, the user visible pseudo register. */
271 "bank",
272 /* double precision (pseudo) 68 - 75 */
273 "", "", "", "", "", "", "", "",
2d188dd3
NC		 274 };
275 if (reg_nr < 0)
276 return NULL;
277 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
278 return NULL;
279 return register_names[reg_nr];
280}
281
fa88f677 282static const char *
d93859e2 283sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 284{
617daa0e
CV		 285 static char *register_names[] = {
286 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
287 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
288 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
289 "", "dsr",
290 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
291 "y0", "y1", "", "", "", "", "", "mod",
292 "", "",
293 "rs", "re", "", "", "", "", "", "",
294 "", "", "", "", "", "", "", "",
da962468 295 "", "", "", "", "", "", "", "",
cc17453a
EZ		 296 };
297 if (reg_nr < 0)
298 return NULL;
299 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
300 return NULL;
301 return register_names[reg_nr];
302}
303
fa88f677 304static const char *
d93859e2 305sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 306{
617daa0e
CV		 307 static char *register_names[] = {
308 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
309 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
310 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
311 "", "dsr",
312 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
313 "y0", "y1", "", "", "", "", "", "mod",
314 "ssr", "spc",
315 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 316 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
317 "", "", "", "", "", "", "", "",
da962468 318 "", "", "", "", "", "", "", "",
cc17453a
EZ		 319 };
320 if (reg_nr < 0)
321 return NULL;
322 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
323 return NULL;
324 return register_names[reg_nr];
325}
326
fa88f677 327static const char *
d93859e2 328sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
53116e27 329{
617daa0e 330 static char *register_names[] = {
a38d2a54 331 /* general registers 0-15 */
617daa0e
CV		 332 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
333 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 334 /* 16 - 22 */
617daa0e 335 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 336 /* 23, 24 */
53116e27 337 "fpul", "fpscr",
a38d2a54 338 /* floating point registers 25 - 40 */
617daa0e
CV		 339 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
340 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 341 /* 41, 42 */
617daa0e 342 "ssr", "spc",
a38d2a54 343 /* bank 0 43 - 50 */
53116e27 344 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 345 /* bank 1 51 - 58 */
53116e27 346 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 347 "", "", "", "", "", "", "", "",
c378eb4e 348 /* pseudo bank register. */
da962468 349 "",
a38d2a54 350 /* double precision (pseudo) 59 - 66 */
617daa0e 351 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 352 /* vectors (pseudo) 67 - 70 */
617daa0e 353 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 354 /* FIXME: missing XF 71 - 86 */
355 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 356 };
357 if (reg_nr < 0)
358 return NULL;
359 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
360 return NULL;
361 return register_names[reg_nr];
362}
363
474e5826 364static const char *
d93859e2 365sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 366{
367 static char *register_names[] = {
368 /* general registers 0-15 */
369 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
370 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
371 /* 16 - 22 */
372 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* 23, 24 */
374 "", "",
375 /* floating point registers 25 - 40 -- not for nofpu target */
376 "", "", "", "", "", "", "", "",
377 "", "", "", "", "", "", "", "",
378 /* 41, 42 */
379 "ssr", "spc",
380 /* bank 0 43 - 50 */
381 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
382 /* bank 1 51 - 58 */
383 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 384 "", "", "", "", "", "", "", "",
c378eb4e 385 /* pseudo bank register. */
da962468 386 "",
474e5826
CV		 387 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
388 "", "", "", "", "", "", "", "",
389 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
390 "", "", "", "",
391 };
392 if (reg_nr < 0)
393 return NULL;
394 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
395 return NULL;
396 return register_names[reg_nr];
397}
398
399static const char *
d93859e2 400sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 401{
402 static char *register_names[] = {
403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
405 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "", "dsr",
407 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
408 "y0", "y1", "", "", "", "", "", "mod",
409 "ssr", "spc",
410 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 411 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
412 "", "", "", "", "", "", "", "",
da962468 413 "", "", "", "", "", "", "", "",
474e5826
CV		 414 };
415 if (reg_nr < 0)
416 return NULL;
417 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
418 return NULL;
419 return register_names[reg_nr];
420}
421
3117ed25 422static const unsigned char *
67d57894 423sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
cc17453a 424{
c378eb4e 425 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
617daa0e
CV		 426 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
427
bac718a6
UW		 428 /* For remote stub targets, trapa #20 is used. */
429 if (strcmp (target_shortname, "remote") == 0)
430 {
431 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
432 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
433
67d57894 434 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 435 {
436 *lenptr = sizeof (big_remote_breakpoint);
437 return big_remote_breakpoint;
438 }
439 else
440 {
441 *lenptr = sizeof (little_remote_breakpoint);
442 return little_remote_breakpoint;
443 }
444 }
445
cc17453a
EZ		 446 *lenptr = sizeof (breakpoint);
447 return breakpoint;
448}
c906108c
SS		 449
450/* Prologue looks like
1c0159e0
CV		 451 mov.l r14,@-r15
452 sts.l pr,@-r15
453 mov.l <regs>,@-r15
454 sub <room_for_loca_vars>,r15
455 mov r15,r14
8db62801 456
c378eb4e 457 Actually it can be more complicated than this but that's it, basically. */
c906108c 458
1c0159e0
CV		 459#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
460#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
461
5f883edd
FF		 462/* JSR @Rm 0100mmmm00001011 */
463#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
464
8db62801
EZ		 465/* STS.L PR,@-r15 0100111100100010
466 r15-4-->r15, PR-->(r15) */
c906108c 467#define IS_STS(x) ((x) == 0x4f22)
8db62801 468
03131d99
CV		 469/* STS.L MACL,@-r15 0100111100010010
470 r15-4-->r15, MACL-->(r15) */
471#define IS_MACL_STS(x) ((x) == 0x4f12)
472
8db62801
EZ		 473/* MOV.L Rm,@-r15 00101111mmmm0110
474 r15-4-->r15, Rm-->(R15) */
c906108c 475#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 476
8db62801
EZ		 477/* MOV r15,r14 0110111011110011
478 r15-->r14 */
c906108c 479#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 480
481/* ADD #imm,r15 01111111iiiiiiii
482 r15+imm-->r15 */
1c0159e0 483#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 484
c906108c
SS		 485#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
486#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 487
488/* ADD r3,r15 0011111100111100
489 r15+r3-->r15 */
c906108c 490#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 491
492/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 493 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 494 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907 495/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
c378eb4e 496 make this entirely clear. */
1c0159e0
CV		 497/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
498#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
499
500/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
501#define IS_MOV_ARG_TO_REG(x) \
502 (((x) & 0xf00f) == 0x6003 && \
503 ((x) & 0x00f0) >= 0x0040 && \
504 ((x) & 0x00f0) <= 0x0070)
505/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
506#define IS_MOV_ARG_TO_IND_R14(x) \
507 (((x) & 0xff0f) == 0x2e02 && \
508 ((x) & 0x00f0) >= 0x0040 && \
509 ((x) & 0x00f0) <= 0x0070)
510/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
511#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
512 (((x) & 0xff00) == 0x1e00 && \
513 ((x) & 0x00f0) >= 0x0040 && \
514 ((x) & 0x00f0) <= 0x0070)
515
516/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
517#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
518/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
519#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 520/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
521#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 522/* SUB Rn,R15 00111111nnnn1000 */
523#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 524
1c0159e0 525#define FPSCR_SZ (1 << 20)
cc17453a 526
c378eb4e 527/* The following instructions are used for epilogue testing. */
1c0159e0
CV		 528#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
529#define IS_RTS(x) ((x) == 0x000b)
530#define IS_LDS(x) ((x) == 0x4f26)
03131d99 531#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 532#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
533#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
534#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 535
cc17453a 536static CORE_ADDR
e17a4113
UW		 537sh_analyze_prologue (struct gdbarch *gdbarch,
538 CORE_ADDR pc, CORE_ADDR current_pc,
d2ca4222 539 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 540{
e17a4113 541 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 542 ULONGEST inst;
543 CORE_ADDR opc;
544 int offset;
545 int sav_offset = 0;
c906108c 546 int r3_val = 0;
1c0159e0 547 int reg, sav_reg = -1;
cc17453a 548
1c0159e0
CV		 549 if (pc >= current_pc)
550 return current_pc;
cc17453a 551
1c0159e0 552 cache->uses_fp = 0;
cc17453a
EZ		 553 for (opc = pc + (2 * 28); pc < opc; pc += 2)
554 {
e17a4113 555 inst = read_memory_unsigned_integer (pc, 2, byte_order);
c378eb4e 556 /* See where the registers will be saved to. */
f2ea0907 557 if (IS_PUSH (inst))
cc17453a 558 {
1c0159e0
CV		 559 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
560 cache->sp_offset += 4;
cc17453a 561 }
f2ea0907 562 else if (IS_STS (inst))
cc17453a 563 {
1c0159e0
CV		 564 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
565 cache->sp_offset += 4;
cc17453a 566 }
03131d99
CV		 567 else if (IS_MACL_STS (inst))
568 {
569 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
570 cache->sp_offset += 4;
571 }
f2ea0907 572 else if (IS_MOV_R3 (inst))
cc17453a 573 {
f2ea0907 574 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 575 }
f2ea0907 576 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 577 {
578 r3_val <<= 1;
579 }
f2ea0907 580 else if (IS_ADD_R3SP (inst))
cc17453a 581 {
1c0159e0 582 cache->sp_offset += -r3_val;
cc17453a 583 }
f2ea0907 584 else if (IS_ADD_IMM_SP (inst))
cc17453a 585 {
1c0159e0
CV		 586 offset = ((inst & 0xff) ^ 0x80) - 0x80;
587 cache->sp_offset -= offset;
c906108c 588 }
1c0159e0 589 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 590 {
1c0159e0
CV		 591 if (sav_reg < 0)
592 {
593 reg = GET_TARGET_REG (inst);
594 if (reg < 14)
595 {
596 sav_reg = reg;
a2b4a96c 597 offset = (inst & 0xff) << 1;
1c0159e0 598 sav_offset =
e17a4113 599 read_memory_integer ((pc + 4) + offset, 2, byte_order);
1c0159e0
CV		 600 }
601 }
c906108c 602 }
1c0159e0 603 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 604 {
1c0159e0
CV		 605 if (sav_reg < 0)
606 {
a2b4a96c 607 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 608 if (reg < 14)
609 {
610 sav_reg = reg;
a2b4a96c 611 offset = (inst & 0xff) << 2;
1c0159e0 612 sav_offset =
e17a4113
UW		 613 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
614 4, byte_order);
1c0159e0
CV		 615 }
616 }
c906108c 617 }
03131d99
CV		 618 else if (IS_MOVI20 (inst))
619 {
620 if (sav_reg < 0)
621 {
622 reg = GET_TARGET_REG (inst);
623 if (reg < 14)
624 {
625 sav_reg = reg;
626 sav_offset = GET_SOURCE_REG (inst) << 16;
c378eb4e 627 /* MOVI20 is a 32 bit instruction! */
03131d99 628 pc += 2;
e17a4113
UW		 629 sav_offset
630 |= read_memory_unsigned_integer (pc, 2, byte_order);
03131d99
CV		 631 /* Now sav_offset contains an unsigned 20 bit value.
632 It must still get sign extended. */
633 if (sav_offset & 0x00080000)
634 sav_offset |= 0xfff00000;
635 }
636 }
637 }
1c0159e0 638 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 639 {
1c0159e0
CV		 640 reg = GET_SOURCE_REG (inst);
641 if (sav_reg > 0 && reg == sav_reg)
642 {
643 sav_reg = -1;
644 }
645 cache->sp_offset += sav_offset;
c906108c 646 }
f2ea0907 647 else if (IS_FPUSH (inst))
c906108c 648 {
d2ca4222 649 if (fpscr & FPSCR_SZ)
c906108c 650 {
1c0159e0 651 cache->sp_offset += 8;
c906108c
SS		 652 }
653 else
654 {
1c0159e0 655 cache->sp_offset += 4;
c906108c
SS		 656 }
657 }
f2ea0907 658 else if (IS_MOV_SP_FP (inst))
617daa0e 659 {
960ccd7d 660 cache->uses_fp = 1;
1c0159e0
CV		 661 /* At this point, only allow argument register moves to other
662 registers or argument register moves to @(X,fp) which are
663 moving the register arguments onto the stack area allocated
664 by a former add somenumber to SP call. Don't allow moving
c378eb4e 665 to an fp indirect address above fp + cache->sp_offset. */
1c0159e0
CV		 666 pc += 2;
667 for (opc = pc + 12; pc < opc; pc += 2)
668 {
e17a4113 669 inst = read_memory_integer (pc, 2, byte_order);
1c0159e0 670 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 671 {
1c0159e0
CV		 672 reg = GET_SOURCE_REG (inst);
673 if (cache->sp_offset > 0)
617daa0e 674 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 675 }
676 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 677 {
1c0159e0
CV		 678 reg = GET_SOURCE_REG (inst);
679 offset = (inst & 0xf) * 4;
680 if (cache->sp_offset > offset)
681 cache->saved_regs[reg] = cache->sp_offset - offset;
682 }
683 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 684 continue;
1c0159e0
CV		 685 else
686 break;
687 }
688 break;
689 }
5f883edd
FF		 690 else if (IS_JSR (inst))
691 {
692 /* We have found a jsr that has been scheduled into the prologue.
693 If we continue the scan and return a pc someplace after this,
694 then setting a breakpoint on this function will cause it to
695 appear to be called after the function it is calling via the
696 jsr, which will be very confusing. Most likely the next
697 instruction is going to be IS_MOV_SP_FP in the delay slot. If
c378eb4e 698 so, note that before returning the current pc. */
e17a4113 699 inst = read_memory_integer (pc + 2, 2, byte_order);
5f883edd
FF		 700 if (IS_MOV_SP_FP (inst))
701 cache->uses_fp = 1;
702 break;
703 }
c378eb4e
MS		 704#if 0 /* This used to just stop when it found an instruction
705 that was not considered part of the prologue. Now,
706 we just keep going looking for likely
707 instructions. */
c906108c
SS		 708 else
709 break;
2bfa91ee 710#endif
c906108c
SS		 711 }
712
1c0159e0
CV		 713 return pc;
714}
c906108c 715
c378eb4e 716/* Skip any prologue before the guts of a function. */
1c0159e0 717static CORE_ADDR
8a8bc27f 718sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 719{
8a8bc27f 720 CORE_ADDR post_prologue_pc, func_addr;
1c0159e0
CV		 721 struct sh_frame_cache cache;
722
723 /* See if we can determine the end of the prologue via the symbol table.
724 If so, then return either PC, or the PC after the prologue, whichever
725 is greater. */
8a8bc27f
TS		 726 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
727 {
728 post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
729 if (post_prologue_pc != 0)
730 return max (pc, post_prologue_pc);
731 }
cc17453a 732
8a8bc27f
TS		 733 /* Can't determine prologue from the symbol table, need to examine
734 instructions. */
c906108c 735
1c0159e0 736 cache.sp_offset = -4;
8a8bc27f
TS		 737 post_prologue_pc = sh_analyze_prologue (gdbarch, pc, (CORE_ADDR) -1, &cache, 0);
738 if (cache.uses_fp)
739 pc = post_prologue_pc;
c906108c 740
1c0159e0
CV		 741 return pc;
742}
743
2e952408 744/* The ABI says:
9a5cef92
EZ		 745
746 Aggregate types not bigger than 8 bytes that have the same size and
747 alignment as one of the integer scalar types are returned in the
748 same registers as the integer type they match.
749
750 For example, a 2-byte aligned structure with size 2 bytes has the
751 same size and alignment as a short int, and will be returned in R0.
752 A 4-byte aligned structure with size 8 bytes has the same size and
753 alignment as a long long int, and will be returned in R0 and R1.
754
755 When an aggregate type is returned in R0 and R1, R0 contains the
756 first four bytes of the aggregate, and R1 contains the
c378eb4e 757 remainder. If the size of the aggregate type is not a multiple of 4
9a5cef92 758 bytes, the aggregate is tail-padded up to a multiple of 4
c378eb4e 759 bytes. The value of the padding is undefined. For little-endian
9a5cef92
EZ		 760 targets the padding will appear at the most significant end of the
761 last element, for big-endian targets the padding appears at the
762 least significant end of the last element.
763
c378eb4e 764 All other aggregate types are returned by address. The caller
9a5cef92 765 function passes the address of an area large enough to hold the
c378eb4e 766 aggregate value in R2. The called function stores the result in
7fe958be 767 this location.
9a5cef92
EZ		 768
769 To reiterate, structs smaller than 8 bytes could also be returned
770 in memory, if they don't pass the "same size and alignment as an
771 integer type" rule.
772
773 For example, in
774
775 struct s { char c[3]; } wibble;
776 struct s foo(void) { return wibble; }
777
778 the return value from foo() will be in memory, not
779 in R0, because there is no 3-byte integer type.
780
7fe958be
EZ		 781 Similarly, in
782
783 struct s { char c[2]; } wibble;
784 struct s foo(void) { return wibble; }
785
786 because a struct containing two chars has alignment 1, that matches
787 type char, but size 2, that matches type short. There's no integer
788 type that has alignment 1 and size 2, so the struct is returned in
c378eb4e 789 memory. */
9a5cef92 790
1c0159e0 791static int
c055b101 792sh_use_struct_convention (int renesas_abi, struct type *type)
1c0159e0
CV		 793{
794 int len = TYPE_LENGTH (type);
795 int nelem = TYPE_NFIELDS (type);
3f997a97 796
c055b101
CV		 797 /* The Renesas ABI returns aggregate types always on stack. */
798 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
799 || TYPE_CODE (type) == TYPE_CODE_UNION))
800 return 1;
801
3f997a97
CV		 802 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
803 fit in two registers anyway) use struct convention. */
804 if (len != 1 && len != 2 && len != 4 && len != 8)
805 return 1;
806
807 /* Scalar types and aggregate types with exactly one field are aligned
808 by definition. They are returned in registers. */
809 if (nelem <= 1)
810 return 0;
811
812 /* If the first field in the aggregate has the same length as the entire
813 aggregate type, the type is returned in registers. */
814 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
815 return 0;
816
817 /* If the size of the aggregate is 8 bytes and the first field is
818 of size 4 bytes its alignment is equal to long long's alignment,
819 so it's returned in registers. */
820 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
821 return 0;
822
823 /* Otherwise use struct convention. */
824 return 1;
283150cd
EZ		 825}
826
c055b101
CV		 827static int
828sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
829{
830 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
831 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
832 return 1;
833 return sh_use_struct_convention (renesas_abi, type);
834}
835
19f59343
MS		 836static CORE_ADDR
837sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
838{
839 return sp & ~3;
840}
841
55ff77ac 842/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 843 Setup the function arguments for calling a function in the inferior.
844
85a453d5 845 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 846 which are dedicated for passing function arguments. Up to the first
847 four arguments (depending on size) may go into these registers.
848 The rest go on the stack.
849
6df2bf50
MS		 850 MVS: Except on SH variants that have floating point registers.
851 In that case, float and double arguments are passed in the same
852 manner, but using FP registers instead of GP registers.
853
c906108c
SS		 854 Arguments that are smaller than 4 bytes will still take up a whole
855 register or a whole 32-bit word on the stack, and will be
856 right-justified in the register or the stack word. This includes
857 chars, shorts, and small aggregate types.
858
859 Arguments that are larger than 4 bytes may be split between two or
860 more registers. If there are not enough registers free, an argument
861 may be passed partly in a register (or registers), and partly on the
c378eb4e 862 stack. This includes doubles, long longs, and larger aggregates.
c906108c
SS		 863 As far as I know, there is no upper limit to the size of aggregates
864 that will be passed in this way; in other words, the convention of
865 passing a pointer to a large aggregate instead of a copy is not used.
866
6df2bf50 867 MVS: The above appears to be true for the SH variants that do not
55ff77ac 868 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 869 aggregate argument onto the stack (and not place it in registers)
870 if it is larger than 16 bytes (four GP registers).
871
c906108c
SS		 872 An exceptional case exists for struct arguments (and possibly other
873 aggregates such as arrays) if the size is larger than 4 bytes but
874 not a multiple of 4 bytes. In this case the argument is never split
875 between the registers and the stack, but instead is copied in its
876 entirety onto the stack, AND also copied into as many registers as
877 there is room for. In other words, space in registers permitting,
878 two copies of the same argument are passed in. As far as I can tell,
879 only the one on the stack is used, although that may be a function
880 of the level of compiler optimization. I suspect this is a compiler
881 bug. Arguments of these odd sizes are left-justified within the
882 word (as opposed to arguments smaller than 4 bytes, which are
883 right-justified).
c5aa993b 884
c906108c
SS		 885 If the function is to return an aggregate type such as a struct, it
886 is either returned in the normal return value register R0 (if its
887 size is no greater than one byte), or else the caller must allocate
888 space into which the callee will copy the return value (if the size
889 is greater than one byte). In this case, a pointer to the return
890 value location is passed into the callee in register R2, which does
891 not displace any of the other arguments passed in via registers R4
c378eb4e 892 to R7. */
c906108c 893
c378eb4e 894/* Helper function to justify value in register according to endianess. */
e5e33cd9 895static char *
d93859e2 896sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
e5e33cd9
CV		 897{
898 static char valbuf[4];
899
617daa0e 900 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 901 if (len < 4)
902 {
c378eb4e 903 /* value gets right-justified in the register or stack word. */
d93859e2 904 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
0fd88904 905 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 906 else
0fd88904 907 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 908 return valbuf;
909 }
0fd88904 910 return (char *) value_contents (val);
617daa0e 911}
e5e33cd9 912
c378eb4e 913/* Helper function to eval number of bytes to allocate on stack. */
e5e33cd9
CV		 914static CORE_ADDR
915sh_stack_allocsize (int nargs, struct value **args)
916{
917 int stack_alloc = 0;
918 while (nargs-- > 0)
4991999e 919 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 920 return stack_alloc;
921}
922
923/* Helper functions for getting the float arguments right. Registers usage
924 depends on the ABI and the endianess. The comments should enlighten how
c378eb4e 925 it's intended to work. */
e5e33cd9 926
c378eb4e 927/* This array stores which of the float arg registers are already in use. */
e5e33cd9
CV		 928static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
929
c378eb4e 930/* This function just resets the above array to "no reg used so far". */
e5e33cd9
CV		 931static void
932sh_init_flt_argreg (void)
933{
934 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
935}
936
937/* This function returns the next register to use for float arg passing.
938 It returns either a valid value between FLOAT_ARG0_REGNUM and
939 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
940 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
941
942 Note that register number 0 in flt_argreg_array corresponds with the
943 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
944 29) the parity of the register number is preserved, which is important
c378eb4e 945 for the double register passing test (see the "argreg & 1" test below). */
e5e33cd9 946static int
c055b101 947sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
e5e33cd9
CV		 948{
949 int argreg;
950
c378eb4e 951 /* First search for the next free register. */
617daa0e
CV		 952 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
953 ++argreg)
e5e33cd9
CV		 954 if (!flt_argreg_array[argreg])
955 break;
956
c378eb4e 957 /* No register left? */
e5e33cd9
CV		 958 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
959 return FLOAT_ARGLAST_REGNUM + 1;
960
961 if (len == 8)
962 {
c378eb4e 963 /* Doubles are always starting in a even register number. */
e5e33cd9 964 if (argreg & 1)
617daa0e 965 {
c055b101
CV		 966 /* In gcc ABI, the skipped register is lost for further argument
967 passing now. Not so in Renesas ABI. */
968 if (!sh_is_renesas_calling_convention (func_type))
969 flt_argreg_array[argreg] = 1;
e5e33cd9
CV		 970
971 ++argreg;
972
c378eb4e 973 /* No register left? */
e5e33cd9
CV		 974 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
975 return FLOAT_ARGLAST_REGNUM + 1;
976 }
c378eb4e 977 /* Also mark the next register as used. */
e5e33cd9
CV		 978 flt_argreg_array[argreg + 1] = 1;
979 }
c055b101
CV		 980 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
981 && !sh_is_renesas_calling_convention (func_type))
e5e33cd9 982 {
c378eb4e 983 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
e5e33cd9
CV		 984 if (!flt_argreg_array[argreg + 1])
985 ++argreg;
986 }
987 flt_argreg_array[argreg] = 1;
988 return FLOAT_ARG0_REGNUM + argreg;
989}
990
afce3d2a
CV		 991/* Helper function which figures out, if a type is treated like a float type.
992
2e952408 993 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 994 Structures with exactly one member, which is of type float or double, are
995 treated exactly as the base types float or double:
996
997 struct sf {
998 float f;
999 };
1000
1001 struct sd {
1002 double d;
1003 };
1004
1005 are handled the same way as just
1006
1007 float f;
1008
1009 double d;
1010
1011 As a result, arguments of these struct types are pushed into floating point
1012 registers exactly as floats or doubles, using the same decision algorithm.
1013
1014 The same is valid if these types are used as function return types. The
1015 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1016 or even using struct convention as it is for other structs. */
1017
1018static int
1019sh_treat_as_flt_p (struct type *type)
1020{
1021 int len = TYPE_LENGTH (type);
1022
1023 /* Ordinary float types are obviously treated as float. */
1024 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1025 return 1;
1026 /* Otherwise non-struct types are not treated as float. */
1027 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1028 return 0;
1029 /* Otherwise structs with more than one memeber are not treated as float. */
1030 if (TYPE_NFIELDS (type) != 1)
1031 return 0;
1032 /* Otherwise if the type of that member is float, the whole type is
1033 treated as float. */
1034 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1035 return 1;
1036 /* Otherwise it's not treated as float. */
1037 return 0;
1038}
1039
cc17453a 1040static CORE_ADDR
617daa0e 1041sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1042 struct value *function,
617daa0e 1043 struct regcache *regcache,
6df2bf50 1044 CORE_ADDR bp_addr, int nargs,
617daa0e 1045 struct value **args,
6df2bf50
MS		 1046 CORE_ADDR sp, int struct_return,
1047 CORE_ADDR struct_addr)
1048{
e17a4113 1049 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1050 int stack_offset = 0;
1051 int argreg = ARG0_REGNUM;
8748518b 1052 int flt_argreg = 0;
6df2bf50 1053 int argnum;
c055b101 1054 struct type *func_type = value_type (function);
6df2bf50
MS		 1055 struct type *type;
1056 CORE_ADDR regval;
1057 char *val;
8748518b 1058 int len, reg_size = 0;
afce3d2a
CV		 1059 int pass_on_stack = 0;
1060 int treat_as_flt;
c055b101
CV		 1061 int last_reg_arg = INT_MAX;
1062
1063 /* The Renesas ABI expects all varargs arguments, plus the last
1064 non-vararg argument to be on the stack, no matter how many
1065 registers have been used so far. */
1066 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1067 && TYPE_VARARGS (func_type))
c055b101 1068 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
6df2bf50 1069
c378eb4e 1070 /* First force sp to a 4-byte alignment. */
6df2bf50
MS		 1071 sp = sh_frame_align (gdbarch, sp);
1072
c378eb4e 1073 /* Make room on stack for args. */
e5e33cd9
CV		 1074 sp -= sh_stack_allocsize (nargs, args);
1075
c378eb4e 1076 /* Initialize float argument mechanism. */
e5e33cd9 1077 sh_init_flt_argreg ();
6df2bf50
MS		 1078
1079 /* Now load as many as possible of the first arguments into
1080 registers, and push the rest onto the stack. There are 16 bytes
1081 in four registers available. Loop thru args from first to last. */
e5e33cd9 1082 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1083 {
4991999e 1084 type = value_type (args[argnum]);
6df2bf50 1085 len = TYPE_LENGTH (type);
d93859e2 1086 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
e5e33cd9
CV		 1087
1088 /* Some decisions have to be made how various types are handled.
c378eb4e 1089 This also differs in different ABIs. */
e5e33cd9 1090 pass_on_stack = 0;
e5e33cd9 1091
c378eb4e 1092 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1093 treat_as_flt = sh_treat_as_flt_p (type);
1094 if (treat_as_flt)
c055b101
CV		 1095 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1096 /* In Renesas ABI, long longs and aggregate types are always passed
1097 on stack. */
1098 else if (sh_is_renesas_calling_convention (func_type)
1099 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1100 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1101 || TYPE_CODE (type) == TYPE_CODE_UNION))
1102 pass_on_stack = 1;
afce3d2a
CV		 1103 /* In contrast to non-FPU CPUs, arguments are never split between
1104 registers and stack. If an argument doesn't fit in the remaining
1105 registers it's always pushed entirely on the stack. */
1106 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1107 pass_on_stack = 1;
48db5a3c 1108
6df2bf50
MS		 1109 while (len > 0)
1110 {
afce3d2a
CV		 1111 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1112 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
c055b101
CV		 1113 || pass_on_stack))
1114 || argnum > last_reg_arg)
617daa0e 1115 {
c378eb4e 1116 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1117 reg_size = (len + 3) & ~3;
1118 write_memory (sp + stack_offset, val, reg_size);
1119 stack_offset += reg_size;
6df2bf50 1120 }
afce3d2a 1121 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1122 {
e5e33cd9
CV		 1123 /* Argument goes in a float argument register. */
1124 reg_size = register_size (gdbarch, flt_argreg);
e17a4113 1125 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408
CV		 1126 /* In little endian mode, float types taking two registers
1127 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1128 be stored swapped in the argument registers. The below
1129 code first writes the first 32 bits in the next but one
1130 register, increments the val and len values accordingly
1131 and then proceeds as normal by writing the second 32 bits
c378eb4e 1132 into the next register. */
b47193f7 1133 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1134 && TYPE_LENGTH (type) == 2 * reg_size)
1135 {
1136 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1137 regval);
1138 val += reg_size;
1139 len -= reg_size;
c378eb4e
MS		 1140 regval = extract_unsigned_integer (val, reg_size,
1141 byte_order);
2e952408 1142 }
6df2bf50
MS		 1143 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1144 }
afce3d2a 1145 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1146 {
6df2bf50 1147 /* there's room in a register */
e5e33cd9 1148 reg_size = register_size (gdbarch, argreg);
e17a4113 1149 regval = extract_unsigned_integer (val, reg_size, byte_order);
6df2bf50
MS		 1150 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1151 }
c378eb4e
MS		 1152 /* Store the value one register at a time or in one step on
1153 stack. */
e5e33cd9
CV		 1154 len -= reg_size;
1155 val += reg_size;
6df2bf50
MS		 1156 }
1157 }
1158
c055b101
CV		 1159 if (struct_return)
1160 {
1161 if (sh_is_renesas_calling_convention (func_type))
1162 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1163 the stack and store the struct return address there. */
e17a4113 1164 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1165 else
1166 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1167 its own dedicated register. */
1168 regcache_cooked_write_unsigned (regcache,
1169 STRUCT_RETURN_REGNUM, struct_addr);
1170 }
1171
c378eb4e 1172 /* Store return address. */
55ff77ac 1173 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1174
1175 /* Update stack pointer. */
3e8c568d 1176 regcache_cooked_write_unsigned (regcache,
b47193f7 1177 gdbarch_sp_regnum (gdbarch), sp);
6df2bf50
MS		 1178
1179 return sp;
1180}
1181
1182static CORE_ADDR
617daa0e 1183sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1184 struct value *function,
617daa0e
CV		 1185 struct regcache *regcache,
1186 CORE_ADDR bp_addr,
1187 int nargs, struct value **args,
1188 CORE_ADDR sp, int struct_return,
6df2bf50 1189 CORE_ADDR struct_addr)
c906108c 1190{
e17a4113 1191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1192 int stack_offset = 0;
1193 int argreg = ARG0_REGNUM;
c906108c 1194 int argnum;
c055b101 1195 struct type *func_type = value_type (function);
c906108c
SS		 1196 struct type *type;
1197 CORE_ADDR regval;
1198 char *val;
c055b101
CV		 1199 int len, reg_size = 0;
1200 int pass_on_stack = 0;
1201 int last_reg_arg = INT_MAX;
1202
1203 /* The Renesas ABI expects all varargs arguments, plus the last
1204 non-vararg argument to be on the stack, no matter how many
1205 registers have been used so far. */
1206 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1207 && TYPE_VARARGS (func_type))
c055b101 1208 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
c906108c 1209
c378eb4e 1210 /* First force sp to a 4-byte alignment. */
19f59343 1211 sp = sh_frame_align (gdbarch, sp);
c906108c 1212
c378eb4e 1213 /* Make room on stack for args. */
e5e33cd9 1214 sp -= sh_stack_allocsize (nargs, args);
c906108c 1215
c906108c
SS		 1216 /* Now load as many as possible of the first arguments into
1217 registers, and push the rest onto the stack. There are 16 bytes
1218 in four registers available. Loop thru args from first to last. */
e5e33cd9 1219 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1220 {
4991999e 1221 type = value_type (args[argnum]);
c5aa993b 1222 len = TYPE_LENGTH (type);
d93859e2 1223 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
c906108c 1224
c055b101 1225 /* Some decisions have to be made how various types are handled.
c378eb4e 1226 This also differs in different ABIs. */
c055b101
CV		 1227 pass_on_stack = 0;
1228 /* Renesas ABI pushes doubles and long longs entirely on stack.
1229 Same goes for aggregate types. */
1230 if (sh_is_renesas_calling_convention (func_type)
1231 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1232 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1233 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1234 || TYPE_CODE (type) == TYPE_CODE_UNION))
1235 pass_on_stack = 1;
c906108c
SS		 1236 while (len > 0)
1237 {
c055b101
CV		 1238 if (argreg > ARGLAST_REGNUM || pass_on_stack
1239 || argnum > last_reg_arg)
617daa0e 1240 {
e5e33cd9 1241 /* The remainder of the data goes entirely on the stack,
c378eb4e 1242 4-byte aligned. */
e5e33cd9
CV		 1243 reg_size = (len + 3) & ~3;
1244 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1245 stack_offset += reg_size;
c906108c 1246 }
e5e33cd9 1247 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1248 {
c378eb4e 1249 /* There's room in a register. */
e5e33cd9 1250 reg_size = register_size (gdbarch, argreg);
e17a4113 1251 regval = extract_unsigned_integer (val, reg_size, byte_order);
48db5a3c 1252 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1253 }
e5e33cd9
CV		 1254 /* Store the value reg_size bytes at a time. This means that things
1255 larger than reg_size bytes may go partly in registers and partly
c906108c 1256 on the stack. */
e5e33cd9
CV		 1257 len -= reg_size;
1258 val += reg_size;
c906108c
SS		 1259 }
1260 }
48db5a3c 1261
c055b101
CV		 1262 if (struct_return)
1263 {
1264 if (sh_is_renesas_calling_convention (func_type))
1265 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1266 the stack and store the struct return address there. */
e17a4113 1267 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1268 else
1269 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1270 its own dedicated register. */
1271 regcache_cooked_write_unsigned (regcache,
1272 STRUCT_RETURN_REGNUM, struct_addr);
1273 }
1274
c378eb4e 1275 /* Store return address. */
55ff77ac 1276 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1277
1278 /* Update stack pointer. */
3e8c568d 1279 regcache_cooked_write_unsigned (regcache,
b47193f7 1280 gdbarch_sp_regnum (gdbarch), sp);
48db5a3c 1281
c906108c
SS		 1282 return sp;
1283}
1284
cc17453a
EZ		 1285/* Find a function's return value in the appropriate registers (in
1286 regbuf), and copy it into valbuf. Extract from an array REGBUF
1287 containing the (raw) register state a function return value of type
1288 TYPE, and copy that, in virtual format, into VALBUF. */
1289static void
3ffc5b9b
CV		 1290sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1291 void *valbuf)
c906108c 1292{
e17a4113
UW		 1293 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cc17453a 1295 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1296 int return_register = R0_REGNUM;
1297 int offset;
617daa0e 1298
cc17453a 1299 if (len <= 4)
3116c80a 1300 {
48db5a3c
CV		 1301 ULONGEST c;
1302
1303 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
e17a4113 1304 store_unsigned_integer (valbuf, len, byte_order, c);
3116c80a 1305 }
48db5a3c 1306 else if (len == 8)
3116c80a 1307 {
48db5a3c
CV		 1308 int i, regnum = R0_REGNUM;
1309 for (i = 0; i < len; i += 4)
617daa0e 1310 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1311 }
1312 else
8a3fe4f8 1313 error (_("bad size for return value"));
3116c80a
EZ		 1314}
1315
1316static void
3ffc5b9b
CV		 1317sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1318 void *valbuf)
3116c80a 1319{
d93859e2 1320 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1321 if (sh_treat_as_flt_p (type))
3116c80a 1322 {
48db5a3c 1323 int len = TYPE_LENGTH (type);
d93859e2 1324 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1325 for (i = 0; i < len; i += 4)
d93859e2 1326 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c378eb4e
MS		 1327 regcache_raw_read (regcache, regnum++,
1328 (char *) valbuf + len - 4 - i);
2e952408
CV		 1329 else
1330 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1331 }
cc17453a 1332 else
3ffc5b9b 1333 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1334}
c906108c 1335
cc17453a
EZ		 1336/* Write into appropriate registers a function return value
1337 of type TYPE, given in virtual format.
1338 If the architecture is sh4 or sh3e, store a function's return value
1339 in the R0 general register or in the FP0 floating point register,
c378eb4e
MS		 1340 depending on the type of the return value. In all the other cases
1341 the result is stored in r0, left-justified. */
cc17453a 1342static void
3ffc5b9b
CV		 1343sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1344 const void *valbuf)
cc17453a 1345{
e17a4113
UW		 1346 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1347 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
48db5a3c
CV		 1348 ULONGEST val;
1349 int len = TYPE_LENGTH (type);
d19b71be 1350
48db5a3c 1351 if (len <= 4)
d19b71be 1352 {
e17a4113 1353 val = extract_unsigned_integer (valbuf, len, byte_order);
48db5a3c 1354 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1355 }
1356 else
48db5a3c
CV		 1357 {
1358 int i, regnum = R0_REGNUM;
1359 for (i = 0; i < len; i += 4)
617daa0e 1360 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1361 }
cc17453a 1362}
c906108c 1363
cc17453a 1364static void
3ffc5b9b
CV		 1365sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1366 const void *valbuf)
cc17453a 1367{
d93859e2 1368 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1369 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1370 {
1371 int len = TYPE_LENGTH (type);
d93859e2 1372 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1373 for (i = 0; i < len; i += 4)
d93859e2 1374 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1375 regcache_raw_write (regcache, regnum++,
1376 (char *) valbuf + len - 4 - i);
1377 else
1378 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1379 }
cc17453a 1380 else
3ffc5b9b 1381 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1382}
1383
c0409442 1384static enum return_value_convention
c055b101
CV		 1385sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1386 struct type *type, struct regcache *regcache,
18cf8b5b 1387 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1388{
c055b101
CV		 1389 if (sh_use_struct_convention_nofpu (
1390 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1391 return RETURN_VALUE_STRUCT_CONVENTION;
1392 if (writebuf)
3ffc5b9b 1393 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1394 else if (readbuf)
3ffc5b9b 1395 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1396 return RETURN_VALUE_REGISTER_CONVENTION;
1397}
1398
1399static enum return_value_convention
c055b101
CV		 1400sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1401 struct type *type, struct regcache *regcache,
18cf8b5b 1402 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1403{
c055b101
CV		 1404 if (sh_use_struct_convention (
1405 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1406 return RETURN_VALUE_STRUCT_CONVENTION;
1407 if (writebuf)
3ffc5b9b 1408 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1409 else if (readbuf)
3ffc5b9b 1410 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1411 return RETURN_VALUE_REGISTER_CONVENTION;
1412}
1413
c378eb4e 1414/* Print the registers in a form similar to the E7000. */
c906108c
SS		 1415
1416static void
c458d6db 1417sh_generic_show_regs (struct frame_info *frame)
c906108c 1418{
c458d6db
UW		 1419 printf_filtered
1420 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1421 phex (get_frame_register_unsigned (frame,
1422 gdbarch_pc_regnum
1423 (get_frame_arch (frame))), 4),
c458d6db
UW		 1424 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1425 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1426 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1427
c458d6db
UW		 1428 printf_filtered
1429 (" GBR %08lx VBR %08lx MACL %08lx\n",
1430 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1431 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1432 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1433
617daa0e 1434 printf_filtered
a6b0a3f3 1435 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1436 (long) get_frame_register_unsigned (frame, 0),
1437 (long) get_frame_register_unsigned (frame, 1),
1438 (long) get_frame_register_unsigned (frame, 2),
1439 (long) get_frame_register_unsigned (frame, 3),
1440 (long) get_frame_register_unsigned (frame, 4),
1441 (long) get_frame_register_unsigned (frame, 5),
1442 (long) get_frame_register_unsigned (frame, 6),
1443 (long) get_frame_register_unsigned (frame, 7));
1444 printf_filtered
1445 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1446 (long) get_frame_register_unsigned (frame, 8),
1447 (long) get_frame_register_unsigned (frame, 9),
1448 (long) get_frame_register_unsigned (frame, 10),
1449 (long) get_frame_register_unsigned (frame, 11),
1450 (long) get_frame_register_unsigned (frame, 12),
1451 (long) get_frame_register_unsigned (frame, 13),
1452 (long) get_frame_register_unsigned (frame, 14),
1453 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1454}
c906108c 1455
cc17453a 1456static void
c458d6db 1457sh3_show_regs (struct frame_info *frame)
cc17453a 1458{
c458d6db
UW		 1459 printf_filtered
1460 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1461 phex (get_frame_register_unsigned (frame,
1462 gdbarch_pc_regnum
1463 (get_frame_arch (frame))), 4),
c458d6db
UW		 1464 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1465 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1466 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1467
1468 printf_filtered
1469 (" GBR %08lx VBR %08lx MACL %08lx\n",
1470 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1471 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1472 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1473 printf_filtered
1474 (" SSR %08lx SPC %08lx\n",
1475 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1476 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1477
617daa0e 1478 printf_filtered
a6b0a3f3 1479 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1480 (long) get_frame_register_unsigned (frame, 0),
1481 (long) get_frame_register_unsigned (frame, 1),
1482 (long) get_frame_register_unsigned (frame, 2),
1483 (long) get_frame_register_unsigned (frame, 3),
1484 (long) get_frame_register_unsigned (frame, 4),
1485 (long) get_frame_register_unsigned (frame, 5),
1486 (long) get_frame_register_unsigned (frame, 6),
1487 (long) get_frame_register_unsigned (frame, 7));
1488 printf_filtered
1489 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1490 (long) get_frame_register_unsigned (frame, 8),
1491 (long) get_frame_register_unsigned (frame, 9),
1492 (long) get_frame_register_unsigned (frame, 10),
1493 (long) get_frame_register_unsigned (frame, 11),
1494 (long) get_frame_register_unsigned (frame, 12),
1495 (long) get_frame_register_unsigned (frame, 13),
1496 (long) get_frame_register_unsigned (frame, 14),
1497 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1498}
1499
2d188dd3 1500static void
c458d6db 1501sh2e_show_regs (struct frame_info *frame)
2d188dd3 1502{
b47193f7 1503 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1504 printf_filtered
1505 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1506 phex (get_frame_register_unsigned (frame,
1507 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1508 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1509 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1510 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1511
1512 printf_filtered
1513 (" GBR %08lx VBR %08lx MACL %08lx\n",
1514 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1515 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1516 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1517 printf_filtered
1518 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1519 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1520 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1521 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1522 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1523
1524 printf_filtered
a6b0a3f3 1525 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1526 (long) get_frame_register_unsigned (frame, 0),
1527 (long) get_frame_register_unsigned (frame, 1),
1528 (long) get_frame_register_unsigned (frame, 2),
1529 (long) get_frame_register_unsigned (frame, 3),
1530 (long) get_frame_register_unsigned (frame, 4),
1531 (long) get_frame_register_unsigned (frame, 5),
1532 (long) get_frame_register_unsigned (frame, 6),
1533 (long) get_frame_register_unsigned (frame, 7));
1534 printf_filtered
1535 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1536 (long) get_frame_register_unsigned (frame, 8),
1537 (long) get_frame_register_unsigned (frame, 9),
1538 (long) get_frame_register_unsigned (frame, 10),
1539 (long) get_frame_register_unsigned (frame, 11),
1540 (long) get_frame_register_unsigned (frame, 12),
1541 (long) get_frame_register_unsigned (frame, 13),
1542 (long) get_frame_register_unsigned (frame, 14),
1543 (long) get_frame_register_unsigned (frame, 15));
1544
1545 printf_filtered
1546 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1547 (long) get_frame_register_unsigned
b47193f7 1548 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1549 (long) get_frame_register_unsigned
b47193f7 1550 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1551 (long) get_frame_register_unsigned
b47193f7 1552 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1553 (long) get_frame_register_unsigned
b47193f7 1554 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1555 (long) get_frame_register_unsigned
b47193f7 1556 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1557 (long) get_frame_register_unsigned
b47193f7 1558 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1559 (long) get_frame_register_unsigned
b47193f7 1560 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1561 (long) get_frame_register_unsigned
b47193f7 1562 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1563 printf_filtered
1564 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1565 (long) get_frame_register_unsigned
b47193f7 1566 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1567 (long) get_frame_register_unsigned
b47193f7 1568 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1569 (long) get_frame_register_unsigned
b47193f7 1570 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1571 (long) get_frame_register_unsigned
b47193f7 1572 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1573 (long) get_frame_register_unsigned
b47193f7 1574 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1575 (long) get_frame_register_unsigned
b47193f7 1576 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1577 (long) get_frame_register_unsigned
b47193f7 1578 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1579 (long) get_frame_register_unsigned
b47193f7 1580 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2d188dd3
NC		 1581}
1582
da962468 1583static void
c458d6db 1584sh2a_show_regs (struct frame_info *frame)
da962468 1585{
b47193f7 1586 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1587 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1588
1589 printf_filtered
1590 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1591 phex (get_frame_register_unsigned (frame,
1592 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1593 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1594 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1595 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1596
1597 printf_filtered
1598 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1599 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1600 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1601 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1602 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1603 printf_filtered
1604 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1605 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1606 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1607 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1608 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1609
1610 printf_filtered
1611 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1612 (long) get_frame_register_unsigned (frame, 0),
1613 (long) get_frame_register_unsigned (frame, 1),
1614 (long) get_frame_register_unsigned (frame, 2),
1615 (long) get_frame_register_unsigned (frame, 3),
1616 (long) get_frame_register_unsigned (frame, 4),
1617 (long) get_frame_register_unsigned (frame, 5),
1618 (long) get_frame_register_unsigned (frame, 6),
1619 (long) get_frame_register_unsigned (frame, 7));
1620 printf_filtered
1621 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1622 (long) get_frame_register_unsigned (frame, 8),
1623 (long) get_frame_register_unsigned (frame, 9),
1624 (long) get_frame_register_unsigned (frame, 10),
1625 (long) get_frame_register_unsigned (frame, 11),
1626 (long) get_frame_register_unsigned (frame, 12),
1627 (long) get_frame_register_unsigned (frame, 13),
1628 (long) get_frame_register_unsigned (frame, 14),
1629 (long) get_frame_register_unsigned (frame, 15));
1630
1631 printf_filtered
1632 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1633 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1634 (long) get_frame_register_unsigned
b47193f7 1635 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1636 (long) get_frame_register_unsigned
b47193f7 1637 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1638 (long) get_frame_register_unsigned
b47193f7 1639 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1640 (long) get_frame_register_unsigned
b47193f7 1641 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1642 (long) get_frame_register_unsigned
b47193f7 1643 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1644 (long) get_frame_register_unsigned
b47193f7 1645 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1646 (long) get_frame_register_unsigned
b47193f7 1647 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1648 (long) get_frame_register_unsigned
b47193f7 1649 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1650 printf_filtered
1651 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1652 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1653 (long) get_frame_register_unsigned
b47193f7 1654 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1655 (long) get_frame_register_unsigned
b47193f7 1656 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1657 (long) get_frame_register_unsigned
b47193f7 1658 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1659 (long) get_frame_register_unsigned
b47193f7 1660 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1661 (long) get_frame_register_unsigned
b47193f7 1662 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1663 (long) get_frame_register_unsigned
b47193f7 1664 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1665 (long) get_frame_register_unsigned
b47193f7 1666 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1667 (long) get_frame_register_unsigned
b47193f7 1668 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
c458d6db
UW		 1669 printf_filtered
1670 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1671 printf_filtered
1672 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1673 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1674 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1675 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1676 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1677 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1678 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1679 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1680 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1681 printf_filtered
1682 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1683 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1684 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1685 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1686 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1687 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1688 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1689 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1690 printf_filtered
1691 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1692 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1697}
1698
1699static void
c458d6db 1700sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1701{
c458d6db
UW		 1702 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1703
1704 printf_filtered
1705 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1706 phex (get_frame_register_unsigned (frame,
1707 gdbarch_pc_regnum
1708 (get_frame_arch (frame))), 4),
c458d6db
UW		 1709 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1710 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1711 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1712
1713 printf_filtered
1714 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1715 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1716 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1717 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1718 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1719 printf_filtered
1720 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1721 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1722 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1723 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1724 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1725
1726 printf_filtered
1727 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1728 (long) get_frame_register_unsigned (frame, 0),
1729 (long) get_frame_register_unsigned (frame, 1),
1730 (long) get_frame_register_unsigned (frame, 2),
1731 (long) get_frame_register_unsigned (frame, 3),
1732 (long) get_frame_register_unsigned (frame, 4),
1733 (long) get_frame_register_unsigned (frame, 5),
1734 (long) get_frame_register_unsigned (frame, 6),
1735 (long) get_frame_register_unsigned (frame, 7));
1736 printf_filtered
1737 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1738 (long) get_frame_register_unsigned (frame, 8),
1739 (long) get_frame_register_unsigned (frame, 9),
1740 (long) get_frame_register_unsigned (frame, 10),
1741 (long) get_frame_register_unsigned (frame, 11),
1742 (long) get_frame_register_unsigned (frame, 12),
1743 (long) get_frame_register_unsigned (frame, 13),
1744 (long) get_frame_register_unsigned (frame, 14),
1745 (long) get_frame_register_unsigned (frame, 15));
1746
1747 printf_filtered
1748 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1749 printf_filtered
1750 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1751 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1752 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1753 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1754 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1755 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1756 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1757 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1758 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1759 printf_filtered
1760 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1761 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1762 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1763 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1764 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1765 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1766 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1767 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1768 printf_filtered
1769 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1770 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1775}
1776
cc17453a 1777static void
c458d6db 1778sh3e_show_regs (struct frame_info *frame)
cc17453a 1779{
b47193f7 1780 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1781 printf_filtered
1782 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1783 phex (get_frame_register_unsigned (frame,
1784 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1785 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1786 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1787 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1788
1789 printf_filtered
1790 (" GBR %08lx VBR %08lx MACL %08lx\n",
1791 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1792 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1793 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1794 printf_filtered
1795 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1796 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1797 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1798 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1799 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1800
617daa0e 1801 printf_filtered
a6b0a3f3 1802 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1803 (long) get_frame_register_unsigned (frame, 0),
1804 (long) get_frame_register_unsigned (frame, 1),
1805 (long) get_frame_register_unsigned (frame, 2),
1806 (long) get_frame_register_unsigned (frame, 3),
1807 (long) get_frame_register_unsigned (frame, 4),
1808 (long) get_frame_register_unsigned (frame, 5),
1809 (long) get_frame_register_unsigned (frame, 6),
1810 (long) get_frame_register_unsigned (frame, 7));
1811 printf_filtered
1812 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1813 (long) get_frame_register_unsigned (frame, 8),
1814 (long) get_frame_register_unsigned (frame, 9),
1815 (long) get_frame_register_unsigned (frame, 10),
1816 (long) get_frame_register_unsigned (frame, 11),
1817 (long) get_frame_register_unsigned (frame, 12),
1818 (long) get_frame_register_unsigned (frame, 13),
1819 (long) get_frame_register_unsigned (frame, 14),
1820 (long) get_frame_register_unsigned (frame, 15));
1821
1822 printf_filtered
1823 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1824 (long) get_frame_register_unsigned
b47193f7 1825 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1826 (long) get_frame_register_unsigned
b47193f7 1827 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1828 (long) get_frame_register_unsigned
b47193f7 1829 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1830 (long) get_frame_register_unsigned
b47193f7 1831 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1832 (long) get_frame_register_unsigned
b47193f7 1833 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1834 (long) get_frame_register_unsigned
b47193f7 1835 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1836 (long) get_frame_register_unsigned
b47193f7 1837 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1838 (long) get_frame_register_unsigned
b47193f7 1839 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1840 printf_filtered
1841 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1842 (long) get_frame_register_unsigned
b47193f7 1843 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1844 (long) get_frame_register_unsigned
b47193f7 1845 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1846 (long) get_frame_register_unsigned
b47193f7 1847 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1848 (long) get_frame_register_unsigned
b47193f7 1849 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1850 (long) get_frame_register_unsigned
b47193f7 1851 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1852 (long) get_frame_register_unsigned
b47193f7 1853 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1854 (long) get_frame_register_unsigned
b47193f7 1855 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1856 (long) get_frame_register_unsigned
b47193f7 1857 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 1858}
1859
1860static void
c458d6db 1861sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1862{
c458d6db
UW		 1863 printf_filtered
1864 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1865 phex (get_frame_register_unsigned (frame,
1866 gdbarch_pc_regnum
1867 (get_frame_arch (frame))), 4),
c458d6db
UW		 1868 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1869 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1870 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1871
c458d6db
UW		 1872 printf_filtered
1873 (" GBR %08lx VBR %08lx MACL %08lx\n",
1874 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1875 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1876 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1877
c458d6db
UW		 1878 printf_filtered
1879 (" SSR %08lx SPC %08lx DSR %08lx\n",
1880 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1881 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1882 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1883
1884 printf_filtered
a6b0a3f3 1885 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1886 (long) get_frame_register_unsigned (frame, 0),
1887 (long) get_frame_register_unsigned (frame, 1),
1888 (long) get_frame_register_unsigned (frame, 2),
1889 (long) get_frame_register_unsigned (frame, 3),
1890 (long) get_frame_register_unsigned (frame, 4),
1891 (long) get_frame_register_unsigned (frame, 5),
1892 (long) get_frame_register_unsigned (frame, 6),
1893 (long) get_frame_register_unsigned (frame, 7));
1894 printf_filtered
1895 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1896 (long) get_frame_register_unsigned (frame, 8),
1897 (long) get_frame_register_unsigned (frame, 9),
1898 (long) get_frame_register_unsigned (frame, 10),
1899 (long) get_frame_register_unsigned (frame, 11),
1900 (long) get_frame_register_unsigned (frame, 12),
1901 (long) get_frame_register_unsigned (frame, 13),
1902 (long) get_frame_register_unsigned (frame, 14),
1903 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1904
1905 printf_filtered
1906 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1907 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1908 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1909 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1910 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1911 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1912 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1913 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1914 printf_filtered
1915 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1916 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1917 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1918 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1919 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1920 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1921 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1922}
1923
cc17453a 1924static void
c458d6db 1925sh4_show_regs (struct frame_info *frame)
cc17453a 1926{
b47193f7 1927 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1928 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1929
1930 printf_filtered
1931 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1932 phex (get_frame_register_unsigned (frame,
1933 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1934 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1935 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1936 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1937
1938 printf_filtered
1939 (" GBR %08lx VBR %08lx MACL %08lx\n",
1940 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1941 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1942 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1943 printf_filtered
1944 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1945 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1946 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1947 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1948 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1949
1950 printf_filtered
1951 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1952 (long) get_frame_register_unsigned (frame, 0),
1953 (long) get_frame_register_unsigned (frame, 1),
1954 (long) get_frame_register_unsigned (frame, 2),
1955 (long) get_frame_register_unsigned (frame, 3),
1956 (long) get_frame_register_unsigned (frame, 4),
1957 (long) get_frame_register_unsigned (frame, 5),
1958 (long) get_frame_register_unsigned (frame, 6),
1959 (long) get_frame_register_unsigned (frame, 7));
1960 printf_filtered
1961 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1962 (long) get_frame_register_unsigned (frame, 8),
1963 (long) get_frame_register_unsigned (frame, 9),
1964 (long) get_frame_register_unsigned (frame, 10),
1965 (long) get_frame_register_unsigned (frame, 11),
1966 (long) get_frame_register_unsigned (frame, 12),
1967 (long) get_frame_register_unsigned (frame, 13),
1968 (long) get_frame_register_unsigned (frame, 14),
1969 (long) get_frame_register_unsigned (frame, 15));
1970
1971 printf_filtered
1972 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1973 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1974 (long) get_frame_register_unsigned
b47193f7 1975 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1976 (long) get_frame_register_unsigned
b47193f7 1977 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1978 (long) get_frame_register_unsigned
b47193f7 1979 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1980 (long) get_frame_register_unsigned
b47193f7 1981 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1982 (long) get_frame_register_unsigned
b47193f7 1983 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1984 (long) get_frame_register_unsigned
b47193f7 1985 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1986 (long) get_frame_register_unsigned
b47193f7 1987 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1988 (long) get_frame_register_unsigned
b47193f7 1989 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1990 printf_filtered
1991 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1992 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1993 (long) get_frame_register_unsigned
b47193f7 1994 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1995 (long) get_frame_register_unsigned
b47193f7 1996 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1997 (long) get_frame_register_unsigned
b47193f7 1998 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1999 (long) get_frame_register_unsigned
b47193f7 2000 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 2001 (long) get_frame_register_unsigned
b47193f7 2002 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 2003 (long) get_frame_register_unsigned
b47193f7 2004 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 2005 (long) get_frame_register_unsigned
b47193f7 2006 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 2007 (long) get_frame_register_unsigned
b47193f7 2008 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 2009}
2010
474e5826 2011static void
c458d6db 2012sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 2013{
c458d6db
UW		 2014 printf_filtered
2015 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2016 phex (get_frame_register_unsigned (frame,
2017 gdbarch_pc_regnum
2018 (get_frame_arch (frame))), 4),
c458d6db
UW		 2019 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2020 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2021 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2022
2023 printf_filtered
2024 (" GBR %08lx VBR %08lx MACL %08lx\n",
2025 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2026 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2027 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2028 printf_filtered
2029 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2030 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2031 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2032 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2033 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2034
2035 printf_filtered
2036 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2037 (long) get_frame_register_unsigned (frame, 0),
2038 (long) get_frame_register_unsigned (frame, 1),
2039 (long) get_frame_register_unsigned (frame, 2),
2040 (long) get_frame_register_unsigned (frame, 3),
2041 (long) get_frame_register_unsigned (frame, 4),
2042 (long) get_frame_register_unsigned (frame, 5),
2043 (long) get_frame_register_unsigned (frame, 6),
2044 (long) get_frame_register_unsigned (frame, 7));
2045 printf_filtered
2046 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2047 (long) get_frame_register_unsigned (frame, 8),
2048 (long) get_frame_register_unsigned (frame, 9),
2049 (long) get_frame_register_unsigned (frame, 10),
2050 (long) get_frame_register_unsigned (frame, 11),
2051 (long) get_frame_register_unsigned (frame, 12),
2052 (long) get_frame_register_unsigned (frame, 13),
2053 (long) get_frame_register_unsigned (frame, 14),
2054 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 2055}
2056
cc17453a 2057static void
c458d6db 2058sh_dsp_show_regs (struct frame_info *frame)
cc17453a 2059{
c458d6db
UW		 2060 printf_filtered
2061 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2062 phex (get_frame_register_unsigned (frame,
2063 gdbarch_pc_regnum
2064 (get_frame_arch (frame))), 4),
c458d6db
UW		 2065 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2066 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2067 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 2068
c458d6db
UW		 2069 printf_filtered
2070 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2071 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2072 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2073 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2074 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 2075
2076 printf_filtered
a6b0a3f3 2077 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 2078 (long) get_frame_register_unsigned (frame, 0),
2079 (long) get_frame_register_unsigned (frame, 1),
2080 (long) get_frame_register_unsigned (frame, 2),
2081 (long) get_frame_register_unsigned (frame, 3),
2082 (long) get_frame_register_unsigned (frame, 4),
2083 (long) get_frame_register_unsigned (frame, 5),
2084 (long) get_frame_register_unsigned (frame, 6),
2085 (long) get_frame_register_unsigned (frame, 7));
2086 printf_filtered
2087 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2088 (long) get_frame_register_unsigned (frame, 8),
2089 (long) get_frame_register_unsigned (frame, 9),
2090 (long) get_frame_register_unsigned (frame, 10),
2091 (long) get_frame_register_unsigned (frame, 11),
2092 (long) get_frame_register_unsigned (frame, 12),
2093 (long) get_frame_register_unsigned (frame, 13),
2094 (long) get_frame_register_unsigned (frame, 14),
2095 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 2096
2097 printf_filtered
2098 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 2099 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2100 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2101 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2102 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2103 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2104 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2105 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 2106 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 2107 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2108 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2109 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2110 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2111 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2112 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 2113}
2114
a78f21af
AC		 2115static void
2116sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 2117{
2118 if (sh_show_regs)
c458d6db 2119 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 2120}
2121
da962468
CV		 2122static struct type *
2123sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2124{
b47193f7 2125 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
da962468 2126 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2127 return builtin_type (gdbarch)->builtin_float;
da962468 2128 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2129 return builtin_type (gdbarch)->builtin_double;
da962468 2130 else
0dfff4cb 2131 return builtin_type (gdbarch)->builtin_int;
da962468
CV		 2132}
2133
cc17453a
EZ		 2134/* Return the GDB type object for the "standard" data type
2135 of data in register N. */
cc17453a 2136static struct type *
48db5a3c 2137sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2138{
b47193f7 2139 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2140 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2141 return builtin_type (gdbarch)->builtin_float;
8db62801 2142 else
0dfff4cb 2143 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2144}
2145
7f4dbe94 2146static struct type *
0dfff4cb 2147sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
7f4dbe94 2148{
e3506a9f
UW		 2149 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2150 0, high);
7f4dbe94
EZ		 2151}
2152
53116e27 2153static struct type *
48db5a3c 2154sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 2155{
b47193f7 2156 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2157 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2158 return builtin_type (gdbarch)->builtin_float;
617daa0e 2159 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2160 return builtin_type (gdbarch)->builtin_double;
617daa0e 2161 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
0dfff4cb 2162 return sh_sh4_build_float_register_type (gdbarch, 3);
53116e27 2163 else
0dfff4cb 2164 return builtin_type (gdbarch)->builtin_int;
53116e27
EZ		 2165}
2166
cc17453a 2167static struct type *
48db5a3c 2168sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2169{
0dfff4cb 2170 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2171}
2172
dda63807
AS		 2173/* Is a register in a reggroup?
2174 The default code in reggroup.c doesn't identify system registers, some
2175 float registers or any of the vector registers.
2176 TODO: sh2a and dsp registers. */
63807e1d 2177static int
dda63807
AS		 2178sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2179 struct reggroup *reggroup)
2180{
b47193f7
UW		 2181 if (gdbarch_register_name (gdbarch, regnum) == NULL
2182 || *gdbarch_register_name (gdbarch, regnum) == '\0')
dda63807
AS		 2183 return 0;
2184
2185 if (reggroup == float_reggroup
2186 && (regnum == FPUL_REGNUM
2187 || regnum == FPSCR_REGNUM))
2188 return 1;
2189
2190 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2191 {
2192 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2193 return 1;
2194 if (reggroup == general_reggroup)
2195 return 0;
2196 }
2197
2198 if (regnum == VBR_REGNUM
2199 || regnum == SR_REGNUM
2200 || regnum == FPSCR_REGNUM
2201 || regnum == SSR_REGNUM
2202 || regnum == SPC_REGNUM)
2203 {
2204 if (reggroup == system_reggroup)
2205 return 1;
2206 if (reggroup == general_reggroup)
2207 return 0;
2208 }
2209
2210 /* The default code can cope with any other registers. */
2211 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2212}
2213
fb409745 2214/* On the sh4, the DRi pseudo registers are problematic if the target
c378eb4e 2215 is little endian. When the user writes one of those registers, for
fb409745
EZ		 2216 instance with 'ser var $dr0=1', we want the double to be stored
2217 like this:
2218 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2219 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2220
2221 This corresponds to little endian byte order & big endian word
2222 order. However if we let gdb write the register w/o conversion, it
2223 will write fr0 and fr1 this way:
2224 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2225 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2226 because it will consider fr0 and fr1 as a single LE stretch of memory.
2227
2228 To achieve what we want we must force gdb to store things in
2229 floatformat_ieee_double_littlebyte_bigword (which is defined in
2230 include/floatformat.h and libiberty/floatformat.c.
2231
2232 In case the target is big endian, there is no problem, the
2233 raw bytes will look like:
2234 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2235 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2236
2237 The other pseudo registers (the FVs) also don't pose a problem
c378eb4e 2238 because they are stored as 4 individual FP elements. */
fb409745 2239
7bd872fe 2240static void
b66ba949
CV		 2241sh_register_convert_to_virtual (int regnum, struct type *type,
2242 char *from, char *to)
55ff77ac 2243{
617daa0e 2244 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2245 {
2246 DOUBLEST val;
617daa0e
CV		 2247 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2248 from, &val);
55ff77ac 2249 store_typed_floating (to, type, val);
283150cd
EZ		 2250 }
2251 else
617daa0e
CV		 2252 error
2253 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2254}
2255
2256static void
b66ba949
CV		 2257sh_register_convert_to_raw (struct type *type, int regnum,
2258 const void *from, void *to)
283150cd 2259{
617daa0e 2260 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2261 {
48db5a3c 2262 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2263 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2264 &val, to);
283150cd
EZ		 2265 }
2266 else
8a3fe4f8 2267 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2268}
2269
c378eb4e 2270/* For vectors of 4 floating point registers. */
1c0159e0 2271static int
d93859e2 2272fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
1c0159e0
CV		 2273{
2274 int fp_regnum;
2275
d93859e2 2276 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2277 + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2278 return fp_regnum;
2279}
2280
c378eb4e 2281/* For double precision floating point registers, i.e 2 fp regs. */
1c0159e0 2282static int
d93859e2 2283dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
1c0159e0
CV		 2284{
2285 int fp_regnum;
2286
d93859e2 2287 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2288 + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2289 return fp_regnum;
2290}
2291
05d1431c
PA		 2292/* Concatenate PORTIONS contiguous raw registers starting at
2293 BASE_REGNUM into BUFFER. */
2294
2295static enum register_status
2296pseudo_register_read_portions (struct gdbarch *gdbarch,
2297 struct regcache *regcache,
2298 int portions,
2299 int base_regnum, gdb_byte *buffer)
2300{
2301 int portion;
2302
2303 for (portion = 0; portion < portions; portion++)
2304 {
2305 enum register_status status;
2306 gdb_byte *b;
2307
2308 b = buffer + register_size (gdbarch, base_regnum) * portion;
2309 status = regcache_raw_read (regcache, base_regnum + portion, b);
2310 if (status != REG_VALID)
2311 return status;
2312 }
2313
2314 return REG_VALID;
2315}
2316
2317static enum register_status
d8124050 2318sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2319 int reg_nr, gdb_byte *buffer)
53116e27 2320{
05d1431c 2321 int base_regnum;
d9d9c31f 2322 char temp_buffer[MAX_REGISTER_SIZE];
05d1431c 2323 enum register_status status;
53116e27 2324
9bed62d7 2325 if (reg_nr == PSEUDO_BANK_REGNUM)
05d1431c
PA		 2326 return regcache_raw_read (regcache, BANK_REGNUM, buffer);
2327 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe 2328 {
d93859e2 2329 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
7bd872fe 2330
c378eb4e 2331 /* Build the value in the provided buffer. */
7bd872fe 2332 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2333 status = pseudo_register_read_portions (gdbarch, regcache,
2334 2, base_regnum, temp_buffer);
2335 if (status == REG_VALID)
2336 {
2337 /* We must pay attention to the endiannes. */
2338 sh_register_convert_to_virtual (reg_nr,
2339 register_type (gdbarch, reg_nr),
2340 temp_buffer, buffer);
2341 }
2342 return status;
7bd872fe 2343 }
617daa0e 2344 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2345 {
d93859e2 2346 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
7bd872fe
EZ		 2347
2348 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2349 return pseudo_register_read_portions (gdbarch, regcache,
2350 4, base_regnum, buffer);
53116e27 2351 }
05d1431c
PA		 2352 else
2353 gdb_assert_not_reached ("invalid pseudo register number");
53116e27
EZ		 2354}
2355
a78f21af 2356static void
d8124050 2357sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2358 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2359{
2360 int base_regnum, portion;
d9d9c31f 2361 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2362
9bed62d7
CV		 2363 if (reg_nr == PSEUDO_BANK_REGNUM)
2364 {
2365 /* When the bank register is written to, the whole register bank
2366 is switched and all values in the bank registers must be read
c378eb4e 2367 from the target/sim again. We're just invalidating the regcache
9bed62d7
CV		 2368 so that a re-read happens next time it's necessary. */
2369 int bregnum;
2370
2371 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2372 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2373 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2374 }
2375 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 2376 {
d93859e2 2377 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
53116e27 2378
c378eb4e 2379 /* We must pay attention to the endiannes. */
7b9ee6a8 2380 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2381 reg_nr, buffer, temp_buffer);
7bd872fe 2382
53116e27
EZ		 2383 /* Write the real regs for which this one is an alias. */
2384 for (portion = 0; portion < 2; portion++)
617daa0e 2385 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2386 (temp_buffer
617daa0e
CV		 2387 + register_size (gdbarch,
2388 base_regnum) * portion));
53116e27 2389 }
617daa0e 2390 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2391 {
d93859e2 2392 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
53116e27
EZ		 2393
2394 /* Write the real regs for which this one is an alias. */
2395 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2396 regcache_raw_write (regcache, base_regnum + portion,
2397 ((char *) buffer
617daa0e
CV		 2398 + register_size (gdbarch,
2399 base_regnum) * portion));
53116e27
EZ		 2400 }
2401}
2402
2f14585c 2403static int
e7faf938 2404sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2f14585c 2405{
e7faf938
MD		 2406 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2407 return legacy_register_sim_regno (gdbarch, nr);
f2ea0907
CV		 2408 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2409 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2410 if (nr == MOD_REGNUM)
2f14585c 2411 return SIM_SH_MOD_REGNUM;
f2ea0907 2412 if (nr == RS_REGNUM)
2f14585c 2413 return SIM_SH_RS_REGNUM;
f2ea0907 2414 if (nr == RE_REGNUM)
2f14585c 2415 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2416 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2417 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2418 return nr;
2419}
1c0159e0 2420
da962468 2421static int
e7faf938 2422sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
da962468
CV		 2423{
2424 switch (nr)
2425 {
2426 case TBR_REGNUM:
2427 return SIM_SH_TBR_REGNUM;
2428 case IBNR_REGNUM:
2429 return SIM_SH_IBNR_REGNUM;
2430 case IBCR_REGNUM:
2431 return SIM_SH_IBCR_REGNUM;
2432 case BANK_REGNUM:
2433 return SIM_SH_BANK_REGNUM;
2434 case MACLB_REGNUM:
2435 return SIM_SH_BANK_MACL_REGNUM;
2436 case GBRB_REGNUM:
2437 return SIM_SH_BANK_GBR_REGNUM;
2438 case PRB_REGNUM:
2439 return SIM_SH_BANK_PR_REGNUM;
2440 case IVNB_REGNUM:
2441 return SIM_SH_BANK_IVN_REGNUM;
2442 case MACHB_REGNUM:
2443 return SIM_SH_BANK_MACH_REGNUM;
2444 default:
2445 break;
2446 }
e7faf938 2447 return legacy_register_sim_regno (gdbarch, nr);
da962468
CV		 2448}
2449
357d3800
AS		 2450/* Set up the register unwinding such that call-clobbered registers are
2451 not displayed in frames >0 because the true value is not certain.
2452 The 'undefined' registers will show up as 'not available' unless the
2453 CFI says otherwise.
2454
2455 This function is currently set up for SH4 and compatible only. */
2456
2457static void
2458sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1 2459 struct dwarf2_frame_state_reg *reg,
4a4e5149 2460 struct frame_info *this_frame)
357d3800
AS		 2461{
2462 /* Mark the PC as the destination for the return address. */
b47193f7 2463 if (regnum == gdbarch_pc_regnum (gdbarch))
357d3800
AS		 2464 reg->how = DWARF2_FRAME_REG_RA;
2465
2466 /* Mark the stack pointer as the call frame address. */
b47193f7 2467 else if (regnum == gdbarch_sp_regnum (gdbarch))
357d3800
AS		 2468 reg->how = DWARF2_FRAME_REG_CFA;
2469
2470 /* The above was taken from the default init_reg in dwarf2-frame.c
2471 while the below is SH specific. */
2472
2473 /* Caller save registers. */
2474 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2475 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2476 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2477 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2478 || (regnum == MACH_REGNUM)
2479 || (regnum == MACL_REGNUM)
2480 || (regnum == FPUL_REGNUM)
2481 || (regnum == SR_REGNUM))
2482 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2483
2484 /* Callee save registers. */
2485 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2486 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2487 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2488 || (regnum == FV0_REGNUM+3))
2489 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2490
2491 /* Other registers. These are not in the ABI and may or may not
2492 mean anything in frames >0 so don't show them. */
2493 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2494 || (regnum == GBR_REGNUM)
2495 || (regnum == VBR_REGNUM)
2496 || (regnum == FPSCR_REGNUM)
2497 || (regnum == SSR_REGNUM)
2498 || (regnum == SPC_REGNUM))
2499 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2500}
2501
1c0159e0
CV		 2502static struct sh_frame_cache *
2503sh_alloc_frame_cache (void)
2504{
2505 struct sh_frame_cache *cache;
2506 int i;
2507
2508 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2509
2510 /* Base address. */
2511 cache->base = 0;
2512 cache->saved_sp = 0;
2513 cache->sp_offset = 0;
2514 cache->pc = 0;
2515
2516 /* Frameless until proven otherwise. */
2517 cache->uses_fp = 0;
617daa0e 2518
1c0159e0
CV		 2519 /* Saved registers. We initialize these to -1 since zero is a valid
2520 offset (that's where fp is supposed to be stored). */
2521 for (i = 0; i < SH_NUM_REGS; i++)
2522 {
2523 cache->saved_regs[i] = -1;
2524 }
617daa0e 2525
1c0159e0 2526 return cache;
617daa0e 2527}
1c0159e0
CV		 2528
2529static struct sh_frame_cache *
94afd7a6 2530sh_frame_cache (struct frame_info *this_frame, void **this_cache)
1c0159e0 2531{
e17a4113 2532 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1c0159e0
CV		 2533 struct sh_frame_cache *cache;
2534 CORE_ADDR current_pc;
2535 int i;
2536
2537 if (*this_cache)
2538 return *this_cache;
2539
2540 cache = sh_alloc_frame_cache ();
2541 *this_cache = cache;
2542
2543 /* In principle, for normal frames, fp holds the frame pointer,
2544 which holds the base address for the current stack frame.
2545 However, for functions that don't need it, the frame pointer is
2546 optional. For these "frameless" functions the frame pointer is
c378eb4e 2547 actually the frame pointer of the calling frame. */
94afd7a6 2548 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
1c0159e0
CV		 2549 if (cache->base == 0)
2550 return cache;
2551
94afd7a6
UW		 2552 cache->pc = get_frame_func (this_frame);
2553 current_pc = get_frame_pc (this_frame);
1c0159e0 2554 if (cache->pc != 0)
d2ca4222
UW		 2555 {
2556 ULONGEST fpscr;
94afd7a6 2557 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
e17a4113 2558 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
d2ca4222 2559 }
617daa0e 2560
1c0159e0
CV		 2561 if (!cache->uses_fp)
2562 {
2563 /* We didn't find a valid frame, which means that CACHE->base
2564 currently holds the frame pointer for our calling frame. If
2565 we're at the start of a function, or somewhere half-way its
2566 prologue, the function's frame probably hasn't been fully
2567 setup yet. Try to reconstruct the base address for the stack
2568 frame by looking at the stack pointer. For truly "frameless"
2569 functions this might work too. */
94afd7a6 2570 cache->base = get_frame_register_unsigned
e17a4113 2571 (this_frame, gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2572 }
2573
2574 /* Now that we have the base address for the stack frame we can
2575 calculate the value of sp in the calling frame. */
2576 cache->saved_sp = cache->base + cache->sp_offset;
2577
2578 /* Adjust all the saved registers such that they contain addresses
2579 instead of offsets. */
2580 for (i = 0; i < SH_NUM_REGS; i++)
2581 if (cache->saved_regs[i] != -1)
2582 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2583
2584 return cache;
2585}
2586
94afd7a6
UW		 2587static struct value *
2588sh_frame_prev_register (struct frame_info *this_frame,
2589 void **this_cache, int regnum)
1c0159e0 2590{
94afd7a6
UW		 2591 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2592 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2593
2594 gdb_assert (regnum >= 0);
2595
b47193f7 2596 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
94afd7a6 2597 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1c0159e0
CV		 2598
2599 /* The PC of the previous frame is stored in the PR register of
2600 the current frame. Frob regnum so that we pull the value from
2601 the correct place. */
b47193f7 2602 if (regnum == gdbarch_pc_regnum (gdbarch))
1c0159e0
CV		 2603 regnum = PR_REGNUM;
2604
2605 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
94afd7a6
UW		 2606 return frame_unwind_got_memory (this_frame, regnum,
2607 cache->saved_regs[regnum]);
1c0159e0 2608
94afd7a6 2609 return frame_unwind_got_register (this_frame, regnum, regnum);
1c0159e0
CV		 2610}
2611
2612static void
94afd7a6 2613sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
617daa0e
CV		 2614 struct frame_id *this_id)
2615{
94afd7a6 2616 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2617
2618 /* This marks the outermost frame. */
2619 if (cache->base == 0)
2620 return;
2621
2622 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2623}
1c0159e0 2624
617daa0e 2625static const struct frame_unwind sh_frame_unwind = {
1c0159e0 2626 NORMAL_FRAME,
8fbca658 2627 default_frame_unwind_stop_reason,
1c0159e0 2628 sh_frame_this_id,
94afd7a6
UW		 2629 sh_frame_prev_register,
2630 NULL,
2631 default_frame_sniffer
1c0159e0
CV		 2632};
2633
1c0159e0
CV		 2634static CORE_ADDR
2635sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2636{
3e8c568d 2637 return frame_unwind_register_unsigned (next_frame,
b47193f7 2638 gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2639}
2640
2641static CORE_ADDR
2642sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2643{
3e8c568d 2644 return frame_unwind_register_unsigned (next_frame,
b47193f7 2645 gdbarch_pc_regnum (gdbarch));
1c0159e0
CV		 2646}
2647
2648static struct frame_id
94afd7a6 2649sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1c0159e0 2650{
94afd7a6
UW		 2651 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2652 gdbarch_sp_regnum (gdbarch));
2653 return frame_id_build (sp, get_frame_pc (this_frame));
1c0159e0
CV		 2654}
2655
2656static CORE_ADDR
94afd7a6 2657sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
617daa0e 2658{
94afd7a6 2659 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
617daa0e 2660
1c0159e0
CV		 2661 return cache->base;
2662}
617daa0e
CV		 2663
2664static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2665 &sh_frame_unwind,
2666 sh_frame_base_address,
2667 sh_frame_base_address,
2668 sh_frame_base_address
617daa0e 2669};
1c0159e0 2670
cb2cf4ce
TS		 2671static struct sh_frame_cache *
2672sh_make_stub_cache (struct frame_info *this_frame)
2673{
2674 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2675 struct sh_frame_cache *cache;
2676
2677 cache = sh_alloc_frame_cache ();
2678
2679 cache->saved_sp
2680 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
2681
2682 return cache;
2683}
2684
2685static void
2686sh_stub_this_id (struct frame_info *this_frame, void **this_cache,
2687 struct frame_id *this_id)
2688{
2689 struct sh_frame_cache *cache;
2690
2691 if (*this_cache == NULL)
2692 *this_cache = sh_make_stub_cache (this_frame);
2693 cache = *this_cache;
2694
2695 *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame));
2696}
2697
2698static int
2699sh_stub_unwind_sniffer (const struct frame_unwind *self,
2700 struct frame_info *this_frame,
2701 void **this_prologue_cache)
2702{
2703 CORE_ADDR addr_in_block;
2704
2705 addr_in_block = get_frame_address_in_block (this_frame);
2706 if (in_plt_section (addr_in_block, NULL))
2707 return 1;
2708
2709 return 0;
2710}
2711
2712static const struct frame_unwind sh_stub_unwind =
2713{
2714 NORMAL_FRAME,
2715 default_frame_unwind_stop_reason,
2716 sh_stub_this_id,
2717 sh_frame_prev_register,
2718 NULL,
2719 sh_stub_unwind_sniffer
2720};
2721
1c0159e0
CV		 2722/* The epilogue is defined here as the area at the end of a function,
2723 either on the `ret' instruction itself or after an instruction which
c378eb4e 2724 destroys the function's stack frame. */
1c0159e0
CV		 2725static int
2726sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2727{
e17a4113 2728 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 2729 CORE_ADDR func_addr = 0, func_end = 0;
2730
2731 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2732 {
2733 ULONGEST inst;
2734 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2735 for a nop and some fixed data (e.g. big offsets) which are
617daa0e 2736 unfortunately also treated as part of the function (which
c378eb4e 2737 means, they are below func_end. */
1c0159e0
CV		 2738 CORE_ADDR addr = func_end - 28;
2739 if (addr < func_addr + 4)
617daa0e 2740 addr = func_addr + 4;
1c0159e0
CV		 2741 if (pc < addr)
2742 return 0;
2743
c378eb4e 2744 /* First search forward until hitting an rts. */
1c0159e0 2745 while (addr < func_end
e17a4113 2746 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
1c0159e0
CV		 2747 addr += 2;
2748 if (addr >= func_end)
617daa0e 2749 return 0;
1c0159e0
CV		 2750
2751 /* At this point we should find a mov.l @r15+,r14 instruction,
2752 either before or after the rts. If not, then the function has
c378eb4e 2753 probably no "normal" epilogue and we bail out here. */
e17a4113
UW		 2754 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2755 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2756 byte_order)))
617daa0e 2757 addr -= 2;
e17a4113
UW		 2758 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2759 byte_order)))
1c0159e0
CV		 2760 return 0;
2761
e17a4113 2762 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99 2763
c378eb4e 2764 /* Step over possible lds.l @r15+,macl. */
03131d99
CV		 2765 if (IS_MACL_LDS (inst))
2766 {
2767 addr -= 2;
e17a4113 2768 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2769 }
2770
c378eb4e 2771 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2772 if (IS_LDS (inst))
617daa0e 2773 {
1c0159e0 2774 addr -= 2;
e17a4113 2775 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2776 }
2777
c378eb4e 2778 /* Step over possible mov r14,r15. */
1c0159e0 2779 if (IS_MOV_FP_SP (inst))
617daa0e 2780 {
1c0159e0 2781 addr -= 2;
e17a4113 2782 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2783 }
2784
2785 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
c378eb4e 2786 instructions. */
1c0159e0 2787 while (addr > func_addr + 4
617daa0e 2788 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2789 {
2790 addr -= 2;
e17a4113 2791 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2792 }
2793
03131d99
CV		 2794 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2795 That's allowed for the epilogue. */
2796 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2797 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2798 && addr > func_addr + 6
e17a4113
UW		 2799 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2800 byte_order)))
03131d99
CV		 2801 addr -= 4;
2802
1c0159e0
CV		 2803 if (pc >= addr)
2804 return 1;
2805 }
2806 return 0;
2807}
c9ac0a72
AS		 2808
2809
2810/* Supply register REGNUM from the buffer specified by REGS and LEN
2811 in the register set REGSET to register cache REGCACHE.
2812 REGTABLE specifies where each register can be found in REGS.
2813 If REGNUM is -1, do this for all registers in REGSET. */
2814
2815void
2816sh_corefile_supply_regset (const struct regset *regset,
2817 struct regcache *regcache,
2818 int regnum, const void *regs, size_t len)
2819{
2820 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2821 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2822 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2823 ? tdep->core_gregmap
2824 : tdep->core_fpregmap);
2825 int i;
2826
2827 for (i = 0; regmap[i].regnum != -1; i++)
2828 {
2829 if ((regnum == -1 || regnum == regmap[i].regnum)
2830 && regmap[i].offset + 4 <= len)
2831 regcache_raw_supply (regcache, regmap[i].regnum,
2832 (char *)regs + regmap[i].offset);
2833 }
2834}
2835
2836/* Collect register REGNUM in the register set REGSET from register cache
2837 REGCACHE into the buffer specified by REGS and LEN.
2838 REGTABLE specifies where each register can be found in REGS.
2839 If REGNUM is -1, do this for all registers in REGSET. */
2840
2841void
2842sh_corefile_collect_regset (const struct regset *regset,
2843 const struct regcache *regcache,
2844 int regnum, void *regs, size_t len)
2845{
2846 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2847 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2848 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2849 ? tdep->core_gregmap
2850 : tdep->core_fpregmap);
2851 int i;
2852
2853 for (i = 0; regmap[i].regnum != -1; i++)
2854 {
2855 if ((regnum == -1 || regnum == regmap[i].regnum)
2856 && regmap[i].offset + 4 <= len)
2857 regcache_raw_collect (regcache, regmap[i].regnum,
2858 (char *)regs + regmap[i].offset);
2859 }
2860}
2861
2862/* The following two regsets have the same contents, so it is tempting to
2863 unify them, but they are distiguished by their address, so don't. */
2864
2865struct regset sh_corefile_gregset =
2866{
2867 NULL,
2868 sh_corefile_supply_regset,
2869 sh_corefile_collect_regset
2870};
2871
2872static struct regset sh_corefile_fpregset =
2873{
2874 NULL,
2875 sh_corefile_supply_regset,
2876 sh_corefile_collect_regset
2877};
2878
2879static const struct regset *
2880sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2881 size_t sect_size)
2882{
2883 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2884
2885 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2886 return &sh_corefile_gregset;
2887
2888 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2889 return &sh_corefile_fpregset;
2890
2891 return NULL;
2892}
ccf00f21 2893\f
cc17453a
EZ		 2894
2895static struct gdbarch *
fba45db2 2896sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2897{
cc17453a 2898 struct gdbarch *gdbarch;
c9ac0a72 2899 struct gdbarch_tdep *tdep;
d658f924 2900
55ff77ac
CV		 2901 sh_show_regs = sh_generic_show_regs;
2902 switch (info.bfd_arch_info->mach)
2903 {
617daa0e
CV		 2904 case bfd_mach_sh2e:
2905 sh_show_regs = sh2e_show_regs;
2906 break;
da962468
CV		 2907 case bfd_mach_sh2a:
2908 sh_show_regs = sh2a_show_regs;
2909 break;
2910 case bfd_mach_sh2a_nofpu:
2911 sh_show_regs = sh2a_nofpu_show_regs;
2912 break;
617daa0e
CV		 2913 case bfd_mach_sh_dsp:
2914 sh_show_regs = sh_dsp_show_regs;
2915 break;
55ff77ac 2916
617daa0e 2917 case bfd_mach_sh3:
46e8a76b
AS		 2918 case bfd_mach_sh3_nommu:
2919 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
617daa0e
CV		 2920 sh_show_regs = sh3_show_regs;
2921 break;
55ff77ac 2922
617daa0e 2923 case bfd_mach_sh3e:
46e8a76b 2924 case bfd_mach_sh2a_or_sh3e:
617daa0e
CV		 2925 sh_show_regs = sh3e_show_regs;
2926 break;
55ff77ac 2927
617daa0e 2928 case bfd_mach_sh3_dsp:
474e5826 2929 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2930 sh_show_regs = sh3_dsp_show_regs;
2931 break;
55ff77ac 2932
617daa0e 2933 case bfd_mach_sh4:
474e5826 2934 case bfd_mach_sh4a:
46e8a76b 2935 case bfd_mach_sh2a_or_sh4:
617daa0e
CV		 2936 sh_show_regs = sh4_show_regs;
2937 break;
55ff77ac 2938
474e5826 2939 case bfd_mach_sh4_nofpu:
46e8a76b 2940 case bfd_mach_sh4_nommu_nofpu:
474e5826 2941 case bfd_mach_sh4a_nofpu:
46e8a76b 2942 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 2943 sh_show_regs = sh4_nofpu_show_regs;
2944 break;
2945
617daa0e
CV		 2946 case bfd_mach_sh5:
2947 sh_show_regs = sh64_show_regs;
c378eb4e 2948 /* SH5 is handled entirely in sh64-tdep.c. */
617daa0e 2949 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2950 }
2951
4be87837
DJ		 2952 /* If there is already a candidate, use it. */
2953 arches = gdbarch_list_lookup_by_info (arches, &info);
2954 if (arches != NULL)
2955 return arches->gdbarch;
cc17453a
EZ		 2956
2957 /* None found, create a new architecture from the information
c378eb4e 2958 provided. */
c9ac0a72
AS		 2959 tdep = XZALLOC (struct gdbarch_tdep);
2960 gdbarch = gdbarch_alloc (&info, tdep);
cc17453a 2961
48db5a3c
CV		 2962 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2963 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2964 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2965 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2966 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2967 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2968 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2969 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2970
f2ea0907 2971 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2972 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2973 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2974 set_gdbarch_fp0_regnum (gdbarch, -1);
2975 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2976
1c0159e0 2977 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2978 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2979
eaf90c5d 2980 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2981
9dae60cc 2982 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2f14585c 2983 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 2984
c0409442 2985 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
1c0159e0 2986
48db5a3c
CV		 2987 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2988 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2989
1c0159e0
CV		 2990 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2991
48db5a3c
CV		 2992 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2993
19f59343 2994 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2995 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2996 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
94afd7a6 2997 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
1c0159e0
CV		 2998 frame_base_set_default (gdbarch, &sh_frame_base);
2999
617daa0e 3000 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 3001
357d3800
AS		 3002 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
3003
c9ac0a72
AS		 3004 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
3005
cc17453a 3006 switch (info.bfd_arch_info->mach)
8db62801 3007 {
cc17453a 3008 case bfd_mach_sh:
48db5a3c 3009 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3010 break;
1c0159e0 3011
cc17453a 3012 case bfd_mach_sh2:
48db5a3c 3013 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 3014 break;
1c0159e0 3015
2d188dd3 3016 case bfd_mach_sh2e:
c378eb4e 3017 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3018 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3019
3020 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 3021 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 3022 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3023 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3024 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 3025 break;
1c0159e0 3026
da962468
CV		 3027 case bfd_mach_sh2a:
3028 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
3029 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
3030 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3031
3032 set_gdbarch_fp0_regnum (gdbarch, 25);
3033 set_gdbarch_num_pseudo_regs (gdbarch, 9);
3034 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3035 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3036 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 3037 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3038 break;
3039
3040 case bfd_mach_sh2a_nofpu:
3041 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
3042 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3043
3044 set_gdbarch_num_pseudo_regs (gdbarch, 1);
3045 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3046 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3047 break;
3048
cc17453a 3049 case bfd_mach_sh_dsp:
48db5a3c 3050 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 3051 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3052 break;
1c0159e0 3053
cc17453a 3054 case bfd_mach_sh3:
4e6cbc38
AS		 3055 case bfd_mach_sh3_nommu:
3056 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 3057 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 3058 break;
1c0159e0 3059
cc17453a 3060 case bfd_mach_sh3e:
4e6cbc38 3061 case bfd_mach_sh2a_or_sh3e:
c378eb4e 3062 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3063 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3064
3065 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 3066 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 3067 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3068 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3069 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3070 break;
1c0159e0 3071
cc17453a 3072 case bfd_mach_sh3_dsp:
48db5a3c 3073 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 3074 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3075 break;
1c0159e0 3076
cc17453a 3077 case bfd_mach_sh4:
474e5826 3078 case bfd_mach_sh4a:
46e8a76b 3079 case bfd_mach_sh2a_or_sh4:
48db5a3c 3080 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 3081 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 3082 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 3083 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 3084 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3085 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3086 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3087 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3088 break;
1c0159e0 3089
474e5826
CV		 3090 case bfd_mach_sh4_nofpu:
3091 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 3092 case bfd_mach_sh4_nommu_nofpu:
3093 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 3094 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3095 break;
3096
3097 case bfd_mach_sh4al_dsp:
3098 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3099 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3100 break;
3101
cc17453a 3102 default:
b58cbbf2 3103 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3104 break;
8db62801 3105 }
cc17453a 3106
4be87837
DJ		 3107 /* Hook in ABI-specific overrides, if they have been registered. */
3108 gdbarch_init_osabi (info, gdbarch);
d658f924 3109
94afd7a6 3110 dwarf2_append_unwinders (gdbarch);
cb2cf4ce 3111 frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind);
94afd7a6 3112 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
1c0159e0 3113
cc17453a 3114 return gdbarch;
8db62801
EZ		 3115}
3116
c055b101
CV		 3117static void
3118show_sh_command (char *args, int from_tty)
3119{
3120 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3121}
3122
3123static void
3124set_sh_command (char *args, int from_tty)
3125{
3126 printf_unfiltered
3127 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3128 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3129}
3130
c378eb4e 3131extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 3132
c906108c 3133void
fba45db2 3134_initialize_sh_tdep (void)
c906108c
SS		 3135{
3136 struct cmd_list_element *c;
617daa0e 3137
f2ea0907 3138 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 3139
1bedd215 3140 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c055b101
CV		 3141
3142 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3143 &setshcmdlist, "set sh ", 0, &setlist);
3144 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3145 &showshcmdlist, "show sh ", 0, &showlist);
3146
3147 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3148 &sh_active_calling_convention,
3149 _("Set calling convention used when calling target "
3150 "functions from GDB."),
3151 _("Show calling convention used when calling target "
3152 "functions from GDB."),
3153 _("gcc - Use GCC calling convention (default).\n"
3154 "renesas - Enforce Renesas calling convention."),
3155 NULL, NULL,
3156 &setshcmdlist, &showshcmdlist);
c906108c 3157}
GDB Binutils - Deliverables
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