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2005-02-11 Andrew Cagney <cagney@gnu.org>
[deliverable/binutils-gdb.git] / gdb / sh64-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
cf5b2f1b
AC		 2
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
0fd88904 4 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
55ff77ac
CV		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23/*
24 Contributed by Steve Chamberlain
25 sac@cygnus.com
26 */
27
28#include "defs.h"
29#include "frame.h"
30#include "symtab.h"
9ab9195f 31#include "objfiles.h"
55ff77ac
CV		 32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h"
38#include "gdb_string.h"
39#include "arch-utils.h"
40#include "floatformat.h"
41#include "regcache.h"
42#include "doublest.h"
43#include "osabi.h"
44
45#include "elf-bfd.h"
46#include "solib-svr4.h"
47
48/* sh flags */
49#include "elf/sh.h"
50/* registers numbers shared with the simulator */
51#include "gdb/sim-sh.h"
52
7bb11558 53/* Information that is dependent on the processor variant. */
55ff77ac
CV		 54enum sh_abi
55 {
56 SH_ABI_UNKNOWN,
57 SH_ABI_32,
58 SH_ABI_64
59 };
60
61struct gdbarch_tdep
62 {
63 enum sh_abi sh_abi;
64 };
65
66/* Registers of SH5 */
67enum
68 {
69 R0_REGNUM = 0,
70 DEFAULT_RETURN_REGNUM = 2,
71 STRUCT_RETURN_REGNUM = 2,
72 ARG0_REGNUM = 2,
73 ARGLAST_REGNUM = 9,
74 FLOAT_ARGLAST_REGNUM = 11,
75 PR_REGNUM = 18,
76 SR_REGNUM = 65,
77 DR0_REGNUM = 141,
78 DR_LAST_REGNUM = 172,
79 /* FPP stands for Floating Point Pair, to avoid confusion with
80 GDB's FP0_REGNUM, which is the number of the first Floating
81 point register. Unfortunately on the sh5, the floating point
7bb11558 82 registers are called FR, and the floating point pairs are called FP. */
55ff77ac
CV		 83 FPP0_REGNUM = 173,
84 FPP_LAST_REGNUM = 204,
85 FV0_REGNUM = 205,
86 FV_LAST_REGNUM = 220,
87 R0_C_REGNUM = 221,
88 R_LAST_C_REGNUM = 236,
89 PC_C_REGNUM = 237,
90 GBR_C_REGNUM = 238,
91 MACH_C_REGNUM = 239,
92 MACL_C_REGNUM = 240,
93 PR_C_REGNUM = 241,
94 T_C_REGNUM = 242,
95 FPSCR_C_REGNUM = 243,
96 FPUL_C_REGNUM = 244,
97 FP0_C_REGNUM = 245,
98 FP_LAST_C_REGNUM = 260,
99 DR0_C_REGNUM = 261,
100 DR_LAST_C_REGNUM = 268,
101 FV0_C_REGNUM = 269,
102 FV_LAST_C_REGNUM = 272,
103 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
104 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
105 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
106 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
107 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
108 };
109
110
111/* Define other aspects of the stack frame.
112 we keep a copy of the worked out return pc lying around, since it
113 is a useful bit of info */
114
115struct frame_extra_info
116{
117 CORE_ADDR return_pc;
118 int leaf_function;
119 int f_offset;
120};
121
122static const char *
39add00a 123sh64_register_name (int reg_nr)
55ff77ac
CV		 124{
125 static char *register_names[] =
126 {
127 /* SH MEDIA MODE (ISA 32) */
128 /* general registers (64-bit) 0-63 */
129 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
130 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
131 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
132 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
133 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
134 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
135 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
136 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
137
138 /* pc (64-bit) 64 */
139 "pc",
140
141 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
142 "sr", "ssr", "spc",
143
144 /* target registers (64-bit) 68-75*/
145 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
146
147 /* floating point state control register (32-bit) 76 */
148 "fpscr",
149
150 /* single precision floating point registers (32-bit) 77-140*/
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
153 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
154 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
155 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
156 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
157 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
158 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
159
160 /* double precision registers (pseudo) 141-172 */
161 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
162 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
163 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
164 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
165
166 /* floating point pairs (pseudo) 173-204*/
167 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
168 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
169 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
170 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
171
172 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
173 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
174 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
175
176 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
177 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
178 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
179 "pc_c",
180 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
181 "fpscr_c", "fpul_c",
182 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
183 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
184 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
185 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
186 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
187 };
188
189 if (reg_nr < 0)
190 return NULL;
191 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
192 return NULL;
193 return register_names[reg_nr];
194}
195
196#define NUM_PSEUDO_REGS_SH_MEDIA 80
197#define NUM_PSEUDO_REGS_SH_COMPACT 51
198
199/* Macros and functions for setting and testing a bit in a minimal
200 symbol that marks it as 32-bit function. The MSB of the minimal
f594e5e9 201 symbol's "info" field is used for this purpose.
55ff77ac
CV		 202
203 ELF_MAKE_MSYMBOL_SPECIAL
204 tests whether an ELF symbol is "special", i.e. refers
205 to a 32-bit function, and sets a "special" bit in a
206 minimal symbol to mark it as a 32-bit function
f594e5e9 207 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
55ff77ac
CV		 208
209#define MSYMBOL_IS_SPECIAL(msym) \
210 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
211
212static void
213sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
214{
215 if (msym == NULL)
216 return;
217
218 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
219 {
220 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
221 SYMBOL_VALUE_ADDRESS (msym) |= 1;
222 }
223}
224
225/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
226 are some macros to test, set, or clear bit 0 of addresses. */
227#define IS_ISA32_ADDR(addr) ((addr) & 1)
228#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
229#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
230
231static int
232pc_is_isa32 (bfd_vma memaddr)
233{
234 struct minimal_symbol *sym;
235
236 /* If bit 0 of the address is set, assume this is a
7bb11558 237 ISA32 (shmedia) address. */
55ff77ac
CV		 238 if (IS_ISA32_ADDR (memaddr))
239 return 1;
240
241 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
242 the high bit of the info field. Use this to decide if the function is
243 ISA16 or ISA32. */
244 sym = lookup_minimal_symbol_by_pc (memaddr);
245 if (sym)
246 return MSYMBOL_IS_SPECIAL (sym);
247 else
248 return 0;
249}
250
251static const unsigned char *
39add00a 252sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
55ff77ac
CV		 253{
254 /* The BRK instruction for shmedia is
255 01101111 11110101 11111111 11110000
256 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
257 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
258
259 /* The BRK instruction for shcompact is
260 00000000 00111011
261 which translates in big endian mode to 0x0, 0x3b
262 and in little endian mode to 0x3b, 0x0*/
263
264 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
265 {
266 if (pc_is_isa32 (*pcptr))
267 {
268 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
269 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
270 *lenptr = sizeof (big_breakpoint_media);
271 return big_breakpoint_media;
272 }
273 else
274 {
275 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
276 *lenptr = sizeof (big_breakpoint_compact);
277 return big_breakpoint_compact;
278 }
279 }
280 else
281 {
282 if (pc_is_isa32 (*pcptr))
283 {
284 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
285 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
286 *lenptr = sizeof (little_breakpoint_media);
287 return little_breakpoint_media;
288 }
289 else
290 {
291 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
292 *lenptr = sizeof (little_breakpoint_compact);
293 return little_breakpoint_compact;
294 }
295 }
296}
297
298/* Prologue looks like
299 [mov.l <regs>,@-r15]...
300 [sts.l pr,@-r15]
301 [mov.l r14,@-r15]
302 [mov r15,r14]
303
304 Actually it can be more complicated than this. For instance, with
305 newer gcc's:
306
307 mov.l r14,@-r15
308 add #-12,r15
309 mov r15,r14
310 mov r4,r1
311 mov r5,r2
312 mov.l r6,@(4,r14)
313 mov.l r7,@(8,r14)
314 mov.b r1,@r14
315 mov r14,r1
316 mov r14,r1
317 add #2,r1
318 mov.w r2,@r1
319
320 */
321
322/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
323 with l=1 and n = 18 0110101111110001010010100aaa0000 */
324#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
325
326/* STS.L PR,@-r0 0100000000100010
327 r0-4-->r0, PR-->(r0) */
328#define IS_STS_R0(x) ((x) == 0x4022)
329
330/* STS PR, Rm 0000mmmm00101010
331 PR-->Rm */
332#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
333
334/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
335 Rm-->(dispx4+r15) */
336#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
337
338/* MOV.L R14,@(disp,r15) 000111111110dddd
339 R14-->(dispx4+r15) */
340#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
341
342/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
343 R18-->(dispx8+R14) */
344#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
345
346/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
347 R18-->(dispx8+R15) */
348#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
349
350/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
351 R18-->(dispx4+R15) */
352#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
353
354/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
355 R14-->(dispx8+R15) */
356#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
357
358/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
359 R14-->(dispx4+R15) */
360#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
361
362/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
363 R15 + imm --> R15 */
364#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
365
366/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
367 R15 + imm --> R15 */
368#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
369
370/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
371 R15 + R63 --> R14 */
372#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
373
374/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
375 R15 + R63 --> R14 */
376#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
377
378#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
379
380/* MOV #imm, R0 1110 0000 ssss ssss
381 #imm-->R0 */
382#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
383
384/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
385#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
386
387/* ADD r15,r0 0011 0000 1111 1100
388 r15+r0-->r0 */
389#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
390
391/* MOV.L R14 @-R0 0010 0000 1110 0110
392 R14-->(R0-4), R0-4-->R0 */
393#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
394
395/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
7bb11558 396 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 397/* FIXME: Recognize the float and double register moves too! */
398#define IS_MEDIA_IND_ARG_MOV(x) \
399((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
400
401/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
402 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
7bb11558 403 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 404#define IS_MEDIA_ARG_MOV(x) \
405(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
406 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
407
408/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
409/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
410/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
411/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
412/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
413#define IS_MEDIA_MOV_TO_R14(x) \
414((((x) & 0xfffffc0f) == 0xa0e00000) \
415|| (((x) & 0xfffffc0f) == 0xa4e00000) \
416|| (((x) & 0xfffffc0f) == 0xa8e00000) \
417|| (((x) & 0xfffffc0f) == 0xb4e00000) \
418|| (((x) & 0xfffffc0f) == 0xbce00000))
419
420/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
421 where Rm is r2-r9 */
422#define IS_COMPACT_IND_ARG_MOV(x) \
423((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
424
425/* compact direct arg move!
426 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
427#define IS_COMPACT_ARG_MOV(x) \
428(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
429
430/* MOV.B Rm, @R14 0010 1110 mmmm 0000
431 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
432#define IS_COMPACT_MOV_TO_R14(x) \
433((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
434
435#define IS_JSR_R0(x) ((x) == 0x400b)
436#define IS_NOP(x) ((x) == 0x0009)
437
438
439/* MOV r15,r14 0110111011110011
440 r15-->r14 */
441#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
442
443/* ADD #imm,r15 01111111iiiiiiii
444 r15+imm-->r15 */
445#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
446
447/* Skip any prologue before the guts of a function */
448
7bb11558
MS		 449/* Skip the prologue using the debug information. If this fails we'll
450 fall back on the 'guess' method below. */
55ff77ac
CV		 451static CORE_ADDR
452after_prologue (CORE_ADDR pc)
453{
454 struct symtab_and_line sal;
455 CORE_ADDR func_addr, func_end;
456
457 /* If we can not find the symbol in the partial symbol table, then
458 there is no hope we can determine the function's start address
459 with this code. */
460 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
461 return 0;
462
463 /* Get the line associated with FUNC_ADDR. */
464 sal = find_pc_line (func_addr, 0);
465
466 /* There are only two cases to consider. First, the end of the source line
467 is within the function bounds. In that case we return the end of the
468 source line. Second is the end of the source line extends beyond the
469 bounds of the current function. We need to use the slow code to
470 examine instructions in that case. */
471 if (sal.end < func_end)
472 return sal.end;
473 else
474 return 0;
475}
476
477static CORE_ADDR
478look_for_args_moves (CORE_ADDR start_pc, int media_mode)
479{
480 CORE_ADDR here, end;
481 int w;
482 int insn_size = (media_mode ? 4 : 2);
483
484 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
485 {
486 if (media_mode)
487 {
488 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
489 here += insn_size;
490 if (IS_MEDIA_IND_ARG_MOV (w))
491 {
492 /* This must be followed by a store to r14, so the argument
493 is where the debug info says it is. This can happen after
7bb11558 494 the SP has been saved, unfortunately. */
55ff77ac
CV		 495
496 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
497 insn_size);
498 here += insn_size;
499 if (IS_MEDIA_MOV_TO_R14 (next_insn))
500 start_pc = here;
501 }
502 else if (IS_MEDIA_ARG_MOV (w))
503 {
7bb11558 504 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 505 start_pc = here;
506 }
507 else
508 break;
509 }
510 else
511 {
512 w = read_memory_integer (here, insn_size);
513 w = w & 0xffff;
514 here += insn_size;
515 if (IS_COMPACT_IND_ARG_MOV (w))
516 {
517 /* This must be followed by a store to r14, so the argument
518 is where the debug info says it is. This can happen after
7bb11558 519 the SP has been saved, unfortunately. */
55ff77ac
CV		 520
521 int next_insn = 0xffff & read_memory_integer (here, insn_size);
522 here += insn_size;
523 if (IS_COMPACT_MOV_TO_R14 (next_insn))
524 start_pc = here;
525 }
526 else if (IS_COMPACT_ARG_MOV (w))
527 {
7bb11558 528 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 529 start_pc = here;
530 }
531 else if (IS_MOVL_R0 (w))
532 {
533 /* There is a function that gcc calls to get the arguments
534 passed correctly to the function. Only after this
535 function call the arguments will be found at the place
536 where they are supposed to be. This happens in case the
537 argument has to be stored into a 64-bit register (for
538 instance doubles, long longs). SHcompact doesn't have
539 access to the full 64-bits, so we store the register in
540 stack slot and store the address of the stack slot in
541 the register, then do a call through a wrapper that
542 loads the memory value into the register. A SHcompact
543 callee calls an argument decoder
544 (GCC_shcompact_incoming_args) that stores the 64-bit
545 value in a stack slot and stores the address of the
546 stack slot in the register. GCC thinks the argument is
547 just passed by transparent reference, but this is only
548 true after the argument decoder is called. Such a call
7bb11558 549 needs to be considered part of the prologue. */
55ff77ac
CV		 550
551 /* This must be followed by a JSR @r0 instruction and by
552 a NOP instruction. After these, the prologue is over! */
553
554 int next_insn = 0xffff & read_memory_integer (here, insn_size);
555 here += insn_size;
556 if (IS_JSR_R0 (next_insn))
557 {
558 next_insn = 0xffff & read_memory_integer (here, insn_size);
559 here += insn_size;
560
561 if (IS_NOP (next_insn))
562 start_pc = here;
563 }
564 }
565 else
566 break;
567 }
568 }
569
570 return start_pc;
571}
572
573static CORE_ADDR
574sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
575{
576 CORE_ADDR here, end;
577 int updated_fp = 0;
578 int insn_size = 4;
579 int media_mode = 1;
580
581 if (!start_pc)
582 return 0;
583
584 if (pc_is_isa32 (start_pc) == 0)
585 {
586 insn_size = 2;
587 media_mode = 0;
588 }
589
590 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
591 {
592
593 if (media_mode)
594 {
595 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
596 here += insn_size;
597 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
598 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
599 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
600 {
601 start_pc = here;
602 }
603 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
604 {
605 start_pc = here;
606 updated_fp = 1;
607 }
608 else
609 if (updated_fp)
610 {
611 /* Don't bail out yet, we may have arguments stored in
612 registers here, according to the debug info, so that
7bb11558 613 gdb can print the frames correctly. */
55ff77ac
CV		 614 start_pc = look_for_args_moves (here - insn_size, media_mode);
615 break;
616 }
617 }
618 else
619 {
620 int w = 0xffff & read_memory_integer (here, insn_size);
621 here += insn_size;
622
623 if (IS_STS_R0 (w) || IS_STS_PR (w)
624 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
625 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
626 {
627 start_pc = here;
628 }
629 else if (IS_MOV_SP_FP (w))
630 {
631 start_pc = here;
632 updated_fp = 1;
633 }
634 else
635 if (updated_fp)
636 {
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
7bb11558 639 gdb can print the frames correctly. */
55ff77ac
CV		 640 start_pc = look_for_args_moves (here - insn_size, media_mode);
641 break;
642 }
643 }
644 }
645
646 return start_pc;
647}
648
649static CORE_ADDR
650sh_skip_prologue (CORE_ADDR pc)
651{
652 CORE_ADDR post_prologue_pc;
653
654 /* See if we can determine the end of the prologue via the symbol table.
655 If so, then return either PC, or the PC after the prologue, whichever
656 is greater. */
657 post_prologue_pc = after_prologue (pc);
658
659 /* If after_prologue returned a useful address, then use it. Else
7bb11558 660 fall back on the instruction skipping code. */
55ff77ac
CV		 661 if (post_prologue_pc != 0)
662 return max (pc, post_prologue_pc);
663 else
664 return sh64_skip_prologue_hard_way (pc);
665}
666
667/* Immediately after a function call, return the saved pc.
668 Can't always go through the frames for this because on some machines
669 the new frame is not set up until the new function executes
670 some instructions.
671
672 The return address is the value saved in the PR register + 4 */
673static CORE_ADDR
674sh_saved_pc_after_call (struct frame_info *frame)
675{
676 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
677}
678
679/* Should call_function allocate stack space for a struct return? */
680static int
681sh64_use_struct_convention (int gcc_p, struct type *type)
682{
683 return (TYPE_LENGTH (type) > 8);
684}
685
686/* Store the address of the place in which to copy the structure the
687 subroutine will return. This is called from call_function.
688
689 We store structs through a pointer passed in R2 */
690static void
691sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
692{
693 write_register (STRUCT_RETURN_REGNUM, (addr));
694}
695
696/* Disassemble an instruction. */
697static int
698gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
699{
700 info->endian = TARGET_BYTE_ORDER;
701 return print_insn_sh (memaddr, info);
702}
703
704/* Given a register number RN as it appears in an assembly
705 instruction, find the corresponding register number in the GDB
7bb11558 706 scheme. */
55ff77ac
CV		 707static int
708translate_insn_rn (int rn, int media_mode)
709{
55ff77ac 710 /* FIXME: this assumes that the number rn is for a not pseudo
7bb11558 711 register only. */
55ff77ac
CV		 712 if (media_mode)
713 return rn;
714 else
715 {
7bb11558
MS		 716 /* These registers don't have a corresponding compact one. */
717 /* FIXME: This is probably not enough. */
55ff77ac
CV		 718#if 0
719 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
720 return rn;
721#endif
722 if (rn >= 0 && rn <= R0_C_REGNUM)
723 return R0_C_REGNUM + rn;
724 else
725 return rn;
726 }
727}
728
729/* Given a GDB frame, determine the address of the calling function's
730 frame. This will be used to create a new GDB frame struct, and
731 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
732 will be called for the new frame.
733
734 For us, the frame address is its stack pointer value, so we look up
735 the function prologue to determine the caller's sp value, and return it. */
736static CORE_ADDR
737sh64_frame_chain (struct frame_info *frame)
738{
30a4a8e0 739 if (deprecated_pc_in_call_dummy (get_frame_pc (frame)))
7bb11558 740 return get_frame_base (frame); /* dummy frame same as caller's frame */
2f72f850 741 if (get_frame_pc (frame))
55ff77ac
CV		 742 {
743 int media_mode = pc_is_isa32 (get_frame_pc (frame));
744 int size;
745 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
746 size = 4;
747 else
7bb11558
MS		 748 size = register_size (current_gdbarch,
749 translate_insn_rn (DEPRECATED_FP_REGNUM,
750 media_mode));
55ff77ac
CV		 751 return read_memory_integer (get_frame_base (frame)
752 + get_frame_extra_info (frame)->f_offset,
753 size);
754 }
755 else
756 return 0;
757}
758
759static CORE_ADDR
760sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
761{
762 int media_mode = 0;
763
764 for (; fi; fi = get_next_frame (fi))
30a4a8e0 765 if (deprecated_pc_in_call_dummy (get_frame_pc (fi)))
7bb11558
MS		 766 /* When the caller requests PR from the dummy frame, we return
767 PC because that's where the previous routine appears to have
768 done a call from. */
55ff77ac
CV		 769 return deprecated_read_register_dummy (get_frame_pc (fi),
770 get_frame_base (fi), pr_regnum);
771 else
772 {
773 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
774 if (!get_frame_pc (fi))
775 return 0;
776
777 media_mode = pc_is_isa32 (get_frame_pc (fi));
778
1b1d3794 779 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
55ff77ac
CV		 780 {
781 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
782 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
783 ? 4
7bb11558 784 : register_size (current_gdbarch, gdb_reg_num));
1b1d3794 785 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
55ff77ac
CV		 786 }
787 }
788 return read_register (pr_regnum);
789}
790
7bb11558 791/* For vectors of 4 floating point registers. */
55ff77ac
CV		 792static int
793fv_reg_base_num (int fv_regnum)
794{
795 int fp_regnum;
796
797 fp_regnum = FP0_REGNUM +
798 (fv_regnum - FV0_REGNUM) * 4;
799 return fp_regnum;
800}
801
802/* For double precision floating point registers, i.e 2 fp regs.*/
803static int
804dr_reg_base_num (int dr_regnum)
805{
806 int fp_regnum;
807
808 fp_regnum = FP0_REGNUM +
809 (dr_regnum - DR0_REGNUM) * 2;
810 return fp_regnum;
811}
812
813/* For pairs of floating point registers */
814static int
815fpp_reg_base_num (int fpp_regnum)
816{
817 int fp_regnum;
818
819 fp_regnum = FP0_REGNUM +
820 (fpp_regnum - FPP0_REGNUM) * 2;
821 return fp_regnum;
822}
823
824static int
825is_media_pseudo (int rn)
826{
2a314ed5 827 return (rn >= DR0_REGNUM && rn <= FV_LAST_REGNUM);
55ff77ac
CV		 828}
829
55ff77ac
CV		 830static int
831sh64_media_reg_base_num (int reg_nr)
832{
833 int base_regnum = -1;
55ff77ac
CV		 834
835 if (reg_nr >= DR0_REGNUM
836 && reg_nr <= DR_LAST_REGNUM)
837 base_regnum = dr_reg_base_num (reg_nr);
838
839 else if (reg_nr >= FPP0_REGNUM
840 && reg_nr <= FPP_LAST_REGNUM)
841 base_regnum = fpp_reg_base_num (reg_nr);
842
843 else if (reg_nr >= FV0_REGNUM
844 && reg_nr <= FV_LAST_REGNUM)
845 base_regnum = fv_reg_base_num (reg_nr);
846
847 return base_regnum;
848}
849
850/* *INDENT-OFF* */
851/*
852 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
853 GDB_REGNUM BASE_REGNUM
854 r0_c 221 0
855 r1_c 222 1
856 r2_c 223 2
857 r3_c 224 3
858 r4_c 225 4
859 r5_c 226 5
860 r6_c 227 6
861 r7_c 228 7
862 r8_c 229 8
863 r9_c 230 9
864 r10_c 231 10
865 r11_c 232 11
866 r12_c 233 12
867 r13_c 234 13
868 r14_c 235 14
869 r15_c 236 15
870
871 pc_c 237 64
872 gbr_c 238 16
873 mach_c 239 17
874 macl_c 240 17
875 pr_c 241 18
876 t_c 242 19
877 fpscr_c 243 76
878 fpul_c 244 109
879
880 fr0_c 245 77
881 fr1_c 246 78
882 fr2_c 247 79
883 fr3_c 248 80
884 fr4_c 249 81
885 fr5_c 250 82
886 fr6_c 251 83
887 fr7_c 252 84
888 fr8_c 253 85
889 fr9_c 254 86
890 fr10_c 255 87
891 fr11_c 256 88
892 fr12_c 257 89
893 fr13_c 258 90
894 fr14_c 259 91
895 fr15_c 260 92
896
897 dr0_c 261 77
898 dr2_c 262 79
899 dr4_c 263 81
900 dr6_c 264 83
901 dr8_c 265 85
902 dr10_c 266 87
903 dr12_c 267 89
904 dr14_c 268 91
905
906 fv0_c 269 77
907 fv4_c 270 81
908 fv8_c 271 85
909 fv12_c 272 91
910*/
911/* *INDENT-ON* */
912static int
913sh64_compact_reg_base_num (int reg_nr)
914{
915 int base_regnum = -1;
55ff77ac
CV		 916
917 /* general register N maps to general register N */
918 if (reg_nr >= R0_C_REGNUM
919 && reg_nr <= R_LAST_C_REGNUM)
920 base_regnum = reg_nr - R0_C_REGNUM;
921
922 /* floating point register N maps to floating point register N */
923 else if (reg_nr >= FP0_C_REGNUM
924 && reg_nr <= FP_LAST_C_REGNUM)
925 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
926
927 /* double prec register N maps to base regnum for double prec register N */
928 else if (reg_nr >= DR0_C_REGNUM
929 && reg_nr <= DR_LAST_C_REGNUM)
930 base_regnum = dr_reg_base_num (DR0_REGNUM
931 + reg_nr - DR0_C_REGNUM);
932
933 /* vector N maps to base regnum for vector register N */
934 else if (reg_nr >= FV0_C_REGNUM
935 && reg_nr <= FV_LAST_C_REGNUM)
936 base_regnum = fv_reg_base_num (FV0_REGNUM
937 + reg_nr - FV0_C_REGNUM);
938
939 else if (reg_nr == PC_C_REGNUM)
940 base_regnum = PC_REGNUM;
941
942 else if (reg_nr == GBR_C_REGNUM)
943 base_regnum = 16;
944
945 else if (reg_nr == MACH_C_REGNUM
946 || reg_nr == MACL_C_REGNUM)
947 base_regnum = 17;
948
949 else if (reg_nr == PR_C_REGNUM)
950 base_regnum = 18;
951
952 else if (reg_nr == T_C_REGNUM)
953 base_regnum = 19;
954
955 else if (reg_nr == FPSCR_C_REGNUM)
7bb11558 956 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
55ff77ac
CV		 957
958 else if (reg_nr == FPUL_C_REGNUM)
959 base_regnum = FP0_REGNUM + 32;
960
961 return base_regnum;
962}
963
964/* Given a register number RN (according to the gdb scheme) , return
965 its corresponding architectural register. In media mode, only a
966 subset of the registers is pseudo registers. For compact mode, all
7bb11558 967 the registers are pseudo. */
55ff77ac
CV		 968static int
969translate_rn_to_arch_reg_num (int rn, int media_mode)
970{
971
972 if (media_mode)
973 {
974 if (!is_media_pseudo (rn))
975 return rn;
976 else
977 return sh64_media_reg_base_num (rn);
978 }
979 else
7bb11558 980 /* All compact registers are pseudo. */
55ff77ac
CV		 981 return sh64_compact_reg_base_num (rn);
982}
983
984static int
985sign_extend (int value, int bits)
986{
987 value = value & ((1 << bits) - 1);
988 return (value & (1 << (bits - 1))
989 ? value | (~((1 << bits) - 1))
990 : value);
991}
992
993static void
994sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
995{
996 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
997 int rn;
998 int have_fp = 0;
999 int fp_regnum;
1000 int sp_regnum;
1001 int depth;
1002 int pc;
1003 int opc;
1004 int insn;
1005 int r0_val = 0;
1006 int media_mode = 0;
1007 int insn_size;
1008 int gdb_register_number;
1009 int register_number;
2a314ed5
MS		 1010 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1011 get_frame_base (fi));
7bb11558 1012 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac 1013
1b1d3794 1014 if (deprecated_get_frame_saved_regs (fi) == NULL)
55ff77ac
CV		 1015 frame_saved_regs_zalloc (fi);
1016 else
1b1d3794 1017 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1018
1019 if (dummy_regs)
1020 {
1021 /* DANGER! This is ONLY going to work if the char buffer format of
1022 the saved registers is byte-for-byte identical to the
1023 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1b1d3794 1024 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1025 return;
1026 }
1027
1028 get_frame_extra_info (fi)->leaf_function = 1;
1029 get_frame_extra_info (fi)->f_offset = 0;
1030
1031 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1032 where[rn] = -1;
1033
1034 depth = 0;
1035
1036 /* Loop around examining the prologue insns until we find something
1037 that does not appear to be part of the prologue. But give up
7bb11558 1038 after 20 of them, since we're getting silly then. */
55ff77ac
CV		 1039
1040 pc = get_frame_func (fi);
1041 if (!pc)
1042 {
1043 deprecated_update_frame_pc_hack (fi, 0);
1044 return;
1045 }
1046
1047 if (pc_is_isa32 (pc))
1048 {
1049 media_mode = 1;
1050 insn_size = 4;
1051 }
1052 else
1053 {
1054 media_mode = 0;
1055 insn_size = 2;
1056 }
1057
1058 /* The frame pointer register is general register 14 in shmedia and
1059 shcompact modes. In sh compact it is a pseudo register. Same goes
7bb11558 1060 for the stack pointer register, which is register 15. */
55ff77ac
CV		 1061 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1062 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1063
1064 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1065 {
1066 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1067 insn_size);
1068
1069 if (media_mode == 0)
1070 {
1071 if (IS_STS_PR (insn))
1072 {
1073 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1074 if (IS_MOV_TO_R15 (next_insn))
1075 {
1076 int reg_nr = PR_C_REGNUM;
1077
1078 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1079 get_frame_extra_info (fi)->leaf_function = 0;
1080 pc += insn_size;
1081 }
1082 }
1083 else if (IS_MOV_R14 (insn))
1084 {
1085 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1086 }
1087
1088 else if (IS_MOV_R0 (insn))
1089 {
1090 /* Put in R0 the offset from SP at which to store some
1091 registers. We are interested in this value, because it
1092 will tell us where the given registers are stored within
1093 the frame. */
1094 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1095 }
1096 else if (IS_ADD_SP_R0 (insn))
1097 {
1098 /* This instruction still prepares r0, but we don't care.
7bb11558 1099 We already have the offset in r0_val. */
55ff77ac
CV		 1100 }
1101 else if (IS_STS_R0 (insn))
1102 {
1103 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1104 int reg_nr = PR_C_REGNUM;
1105 where[reg_nr] = depth - (r0_val - 4);
1106 r0_val -= 4;
1107 get_frame_extra_info (fi)->leaf_function = 0;
1108 }
1109 else if (IS_MOV_R14_R0 (insn))
1110 {
1111 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1112 where[fp_regnum] = depth - (r0_val - 4);
1113 r0_val -= 4;
1114 }
1115
1116 else if (IS_ADD_SP (insn))
1117 {
1118 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1119 }
1120 else if (IS_MOV_SP_FP (insn))
1121 break;
1122 }
1123 else
1124 {
1125 if (IS_ADDIL_SP_MEDIA (insn)
1126 || IS_ADDI_SP_MEDIA (insn))
1127 {
1128 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1129 }
1130
1131 else if (IS_STQ_R18_R15 (insn))
1132 {
1133 where[PR_REGNUM] =
1134 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1135 get_frame_extra_info (fi)->leaf_function = 0;
1136 }
1137
1138 else if (IS_STL_R18_R15 (insn))
1139 {
1140 where[PR_REGNUM] =
1141 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1142 get_frame_extra_info (fi)->leaf_function = 0;
1143 }
1144
1145 else if (IS_STQ_R14_R15 (insn))
1146 {
1147 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1148 }
1149
1150 else if (IS_STL_R14_R15 (insn))
1151 {
1152 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1153 }
1154
1155 else if (IS_MOV_SP_FP_MEDIA (insn))
1156 break;
1157 }
1158 }
1159
7bb11558 1160 /* Now we know how deep things are, we can work out their addresses. */
55ff77ac
CV		 1161 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1162 {
1163 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1164
1165 if (where[rn] >= 0)
1166 {
1167 if (rn == fp_regnum)
1168 have_fp = 1;
1169
1170 /* Watch out! saved_regs is only for the real registers, and
7bb11558
MS		 1171 doesn't include space for the pseudo registers. */
1172 deprecated_get_frame_saved_regs (fi)[register_number]
1173 = get_frame_base (fi) - where[rn] + depth;
55ff77ac
CV		 1174 }
1175 else
7bb11558 1176 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
55ff77ac
CV		 1177 }
1178
1179 if (have_fp)
1180 {
1181 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1182 shcompact 15 is the arch register corresponding to the pseudo
7bb11558 1183 register r15 which still is the SP register. */
55ff77ac 1184 /* The place on the stack where fp is stored contains the sp of
7bb11558 1185 the caller. */
55ff77ac
CV		 1186 /* Again, saved_registers contains only space for the real
1187 registers, so we store in DEPRECATED_FP_REGNUM position. */
1188 int size;
1189 if (tdep->sh_abi == SH_ABI_32)
1190 size = 4;
1191 else
7bb11558
MS		 1192 size = register_size (current_gdbarch, fp_regnum);
1193 deprecated_get_frame_saved_regs (fi)[sp_regnum]
1194 = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum],
1195 size);
55ff77ac
CV		 1196 }
1197 else
1b1d3794 1198 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
55ff77ac 1199
7bb11558 1200 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
55ff77ac
CV		 1201}
1202
1203/* Initialize the extra info saved in a FRAME */
1204static void
1205sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1206{
1207 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1208
1209 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1210
1211 if (get_next_frame (fi))
1212 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1213
30a4a8e0 1214 if (deprecated_pc_in_call_dummy (get_frame_pc (fi)))
55ff77ac
CV		 1215 {
1216 /* We need to setup fi->frame here because call_function_by_hand
1217 gets it wrong by assuming it's always FP. */
1218 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1219 get_frame_extra_info (fi)->return_pc =
1220 deprecated_read_register_dummy (get_frame_pc (fi),
1221 get_frame_base (fi), PC_REGNUM);
ddc135a4 1222 get_frame_extra_info (fi)->f_offset = -4;
55ff77ac
CV		 1223 get_frame_extra_info (fi)->leaf_function = 0;
1224 return;
1225 }
1226 else
1227 {
1228 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1229 get_frame_extra_info (fi)->return_pc =
1230 sh64_get_saved_pr (fi, PR_REGNUM);
1231 }
1232}
1233
1234static void
1235sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1236 struct frame_info *frame, int regnum,
1237 enum lval_type *lval)
1238{
1239 int media_mode;
1240 int live_regnum = regnum;
7bb11558 1241 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1242
1243 if (!target_has_registers)
1244 error ("No registers.");
1245
1246 /* Normal systems don't optimize out things with register numbers. */
1247 if (optimized != NULL)
1248 *optimized = 0;
1249
1250 if (addrp) /* default assumption: not found in memory */
1251 *addrp = 0;
1252
1253 if (raw_buffer)
1254 memset (raw_buffer, 0, sizeof (raw_buffer));
1255
1256 /* We must do this here, before the following while loop changes
1257 frame, and makes it NULL. If this is a media register number,
1258 but we are in compact mode, it will become the corresponding
1259 compact pseudo register. If there is no corresponding compact
1260 pseudo-register what do we do?*/
1261 media_mode = pc_is_isa32 (get_frame_pc (frame));
1262 live_regnum = translate_insn_rn (regnum, media_mode);
1263
1264 /* Note: since the current frame's registers could only have been
1265 saved by frames INTERIOR TO the current frame, we skip examining
1266 the current frame itself: otherwise, we would be getting the
1267 previous frame's registers which were saved by the current frame. */
1268
1269 while (frame && ((frame = get_next_frame (frame)) != NULL))
1270 {
30a4a8e0 1271 if (deprecated_pc_in_call_dummy (get_frame_pc (frame)))
55ff77ac
CV		 1272 {
1273 if (lval) /* found it in a CALL_DUMMY frame */
1274 *lval = not_lval;
1275 if (raw_buffer)
1276 memcpy (raw_buffer,
1277 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
62700349 1278 + DEPRECATED_REGISTER_BYTE (regnum)),
7bb11558 1279 register_size (current_gdbarch, regnum));
55ff77ac
CV		 1280 return;
1281 }
1282
1283 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1b1d3794
AC		 1284 if (deprecated_get_frame_saved_regs (frame) != NULL
1285 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
55ff77ac
CV		 1286 {
1287 if (lval) /* found it saved on the stack */
1288 *lval = lval_memory;
1289 if (regnum == SP_REGNUM)
1290 {
1291 if (raw_buffer) /* SP register treated specially */
7bb11558
MS		 1292 store_unsigned_integer (raw_buffer,
1293 register_size (current_gdbarch,
1294 regnum),
1b1d3794 1295 deprecated_get_frame_saved_regs (frame)[regnum]);
55ff77ac
CV		 1296 }
1297 else
1298 { /* any other register */
1299
1300 if (addrp)
1b1d3794 1301 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
55ff77ac
CV		 1302 if (raw_buffer)
1303 {
1304 int size;
1305 if (tdep->sh_abi == SH_ABI_32
1306 && (live_regnum == DEPRECATED_FP_REGNUM
1307 || live_regnum == PR_REGNUM))
1308 size = 4;
1309 else
7bb11558 1310 size = register_size (current_gdbarch, live_regnum);
55ff77ac 1311 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
39add00a
MS		 1312 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
1313 raw_buffer, size);
55ff77ac 1314 else
1b1d3794 1315 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac 1316 raw_buffer
7bb11558 1317 + register_size (current_gdbarch, live_regnum)
55ff77ac
CV		 1318 - size,
1319 size);
1320 }
1321 }
1322 return;
1323 }
1324 }
1325
1326 /* If we get thru the loop to this point, it means the register was
1327 not saved in any frame. Return the actual live-register value. */
1328
1329 if (lval) /* found it in a live register */
1330 *lval = lval_register;
1331 if (addrp)
62700349 1332 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
55ff77ac
CV		 1333 if (raw_buffer)
1334 deprecated_read_register_gen (live_regnum, raw_buffer);
1335}
1336
1337static CORE_ADDR
07be497a 1338sh64_extract_struct_value_address (struct regcache *regcache)
55ff77ac 1339{
07be497a
AC		 1340 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
1341 address regster is preserved across function calls? Probably
1342 not, making this function wrong. */
1343 ULONGEST val;
1344 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
1345 return val;
55ff77ac
CV		 1346}
1347
1348static CORE_ADDR
1349sh_frame_saved_pc (struct frame_info *frame)
1350{
1351 return (get_frame_extra_info (frame)->return_pc);
1352}
1353
1354/* Discard from the stack the innermost frame, restoring all saved registers.
7bb11558 1355 Used in the 'return' command. */
55ff77ac
CV		 1356static void
1357sh64_pop_frame (void)
1358{
52f0bd74
AC		 1359 struct frame_info *frame = get_current_frame ();
1360 CORE_ADDR fp;
1361 int regnum;
7bb11558 1362 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1363
1364 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1365
30a4a8e0 1366 if (deprecated_pc_in_call_dummy (get_frame_pc (frame)))
8adf9e78 1367 deprecated_pop_dummy_frame ();
55ff77ac
CV		 1368 else
1369 {
1370 fp = get_frame_base (frame);
1371 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1372
1373 /* Copy regs from where they were saved in the frame */
1374 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1b1d3794 1375 if (deprecated_get_frame_saved_regs (frame)[regnum])
55ff77ac
CV		 1376 {
1377 int size;
1378 if (tdep->sh_abi == SH_ABI_32
1379 && (regnum == DEPRECATED_FP_REGNUM
1380 || regnum == PR_REGNUM))
1381 size = 4;
1382 else
7bb11558
MS		 1383 size = register_size (current_gdbarch,
1384 translate_insn_rn (regnum, media_mode));
55ff77ac 1385 write_register (regnum,
1b1d3794 1386 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac
CV		 1387 size));
1388 }
1389
1390 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1391 write_register (SP_REGNUM, fp + 8);
1392 }
1393 flush_cached_frames ();
1394}
1395
1396static CORE_ADDR
1397sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1398{
1399 return sp & ~3;
1400}
1401
1402/* Function: push_arguments
1403 Setup the function arguments for calling a function in the inferior.
1404
85a453d5 1405 On the Renesas SH architecture, there are four registers (R4 to R7)
55ff77ac
CV		 1406 which are dedicated for passing function arguments. Up to the first
1407 four arguments (depending on size) may go into these registers.
1408 The rest go on the stack.
1409
1410 Arguments that are smaller than 4 bytes will still take up a whole
1411 register or a whole 32-bit word on the stack, and will be
1412 right-justified in the register or the stack word. This includes
1413 chars, shorts, and small aggregate types.
1414
1415 Arguments that are larger than 4 bytes may be split between two or
1416 more registers. If there are not enough registers free, an argument
1417 may be passed partly in a register (or registers), and partly on the
1418 stack. This includes doubles, long longs, and larger aggregates.
1419 As far as I know, there is no upper limit to the size of aggregates
1420 that will be passed in this way; in other words, the convention of
1421 passing a pointer to a large aggregate instead of a copy is not used.
1422
1423 An exceptional case exists for struct arguments (and possibly other
1424 aggregates such as arrays) if the size is larger than 4 bytes but
1425 not a multiple of 4 bytes. In this case the argument is never split
1426 between the registers and the stack, but instead is copied in its
1427 entirety onto the stack, AND also copied into as many registers as
1428 there is room for. In other words, space in registers permitting,
1429 two copies of the same argument are passed in. As far as I can tell,
1430 only the one on the stack is used, although that may be a function
1431 of the level of compiler optimization. I suspect this is a compiler
1432 bug. Arguments of these odd sizes are left-justified within the
1433 word (as opposed to arguments smaller than 4 bytes, which are
1434 right-justified).
1435
1436 If the function is to return an aggregate type such as a struct, it
1437 is either returned in the normal return value register R0 (if its
1438 size is no greater than one byte), or else the caller must allocate
1439 space into which the callee will copy the return value (if the size
1440 is greater than one byte). In this case, a pointer to the return
1441 value location is passed into the callee in register R2, which does
1442 not displace any of the other arguments passed in via registers R4
1443 to R7. */
1444
1445/* R2-R9 for integer types and integer equivalent (char, pointers) and
1446 non-scalar (struct, union) elements (even if the elements are
1447 floats).
1448 FR0-FR11 for single precision floating point (float)
1449 DR0-DR10 for double precision floating point (double)
1450
1451 If a float is argument number 3 (for instance) and arguments number
1452 1,2, and 4 are integer, the mapping will be:
1453 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1454
1455 If a float is argument number 10 (for instance) and arguments number
1456 1 through 10 are integer, the mapping will be:
1457 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1458 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1459 I.e. there is hole in the stack.
1460
1461 Different rules apply for variable arguments functions, and for functions
7bb11558 1462 for which the prototype is not known. */
55ff77ac
CV		 1463
1464static CORE_ADDR
1465sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1466 int struct_return, CORE_ADDR struct_addr)
1467{
1468 int stack_offset, stack_alloc;
1469 int int_argreg;
1470 int float_argreg;
1471 int double_argreg;
1472 int float_arg_index = 0;
1473 int double_arg_index = 0;
1474 int argnum;
1475 struct type *type;
1476 CORE_ADDR regval;
1477 char *val;
1478 char valbuf[8];
1479 char valbuf_tmp[8];
1480 int len;
1481 int argreg_size;
1482 int fp_args[12];
55ff77ac
CV		 1483
1484 memset (fp_args, 0, sizeof (fp_args));
1485
1486 /* first force sp to a 8-byte alignment */
1487 sp = sp & ~7;
1488
1489 /* The "struct return pointer" pseudo-argument has its own dedicated
1490 register */
1491
1492 if (struct_return)
1493 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1494
1495 /* Now make sure there's space on the stack */
1496 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
4991999e 1497 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
55ff77ac
CV		 1498 sp -= stack_alloc; /* make room on stack for args */
1499
1500 /* Now load as many as possible of the first arguments into
1501 registers, and push the rest onto the stack. There are 64 bytes
1502 in eight registers available. Loop thru args from first to last. */
1503
1504 int_argreg = ARG0_REGNUM;
1505 float_argreg = FP0_REGNUM;
1506 double_argreg = DR0_REGNUM;
1507
1508 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1509 {
4991999e 1510 type = value_type (args[argnum]);
55ff77ac
CV		 1511 len = TYPE_LENGTH (type);
1512 memset (valbuf, 0, sizeof (valbuf));
1513
1514 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1515 {
7bb11558 1516 argreg_size = register_size (current_gdbarch, int_argreg);
55ff77ac
CV		 1517
1518 if (len < argreg_size)
1519 {
1520 /* value gets right-justified in the register or stack word */
1521 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1522 memcpy (valbuf + argreg_size - len,
0fd88904 1523 (char *) value_contents (args[argnum]), len);
55ff77ac 1524 else
0fd88904 1525 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
55ff77ac
CV		 1526
1527 val = valbuf;
1528 }
1529 else
0fd88904 1530 val = (char *) value_contents (args[argnum]);
55ff77ac
CV		 1531
1532 while (len > 0)
1533 {
1534 if (int_argreg > ARGLAST_REGNUM)
1535 {
1536 /* must go on the stack */
1537 write_memory (sp + stack_offset, val, argreg_size);
1538 stack_offset += 8;/*argreg_size;*/
1539 }
1540 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1541 That's because some *&^%$ things get passed on the stack
1542 AND in the registers! */
1543 if (int_argreg <= ARGLAST_REGNUM)
1544 {
1545 /* there's room in a register */
1546 regval = extract_unsigned_integer (val, argreg_size);
1547 write_register (int_argreg, regval);
1548 }
1549 /* Store the value 8 bytes at a time. This means that
1550 things larger than 8 bytes may go partly in registers
1551 and partly on the stack. FIXME: argreg is incremented
7bb11558 1552 before we use its size. */
55ff77ac
CV		 1553 len -= argreg_size;
1554 val += argreg_size;
1555 int_argreg++;
1556 }
1557 }
1558 else
1559 {
0fd88904 1560 val = (char *) value_contents (args[argnum]);
55ff77ac
CV		 1561 if (len == 4)
1562 {
1563 /* Where is it going to be stored? */
1564 while (fp_args[float_arg_index])
1565 float_arg_index ++;
1566
1567 /* Now float_argreg points to the register where it
1568 should be stored. Are we still within the allowed
1569 register set? */
1570 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1571 {
1572 /* Goes in FR0...FR11 */
1573 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1574 val);
1575 fp_args[float_arg_index] = 1;
7bb11558 1576 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1577 int_argreg ++;
1578 }
1579 else
1580 ;
1581 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1582 necessary spilling on the stack. */
55ff77ac
CV		 1583
1584 }
1585 else if (len == 8)
1586 {
1587 /* Where is it going to be stored? */
1588 while (fp_args[double_arg_index])
1589 double_arg_index += 2;
1590 /* Now double_argreg points to the register
1591 where it should be stored.
1592 Are we still within the allowed register set? */
1593 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1594 {
1595 /* Goes in DR0...DR10 */
1596 /* The numbering of the DRi registers is consecutive,
7bb11558 1597 i.e. includes odd numbers. */
55ff77ac
CV		 1598 int double_register_offset = double_arg_index / 2;
1599 int regnum = DR0_REGNUM +
1600 double_register_offset;
1601#if 0
1602 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1603 {
1604 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1605 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1606 type, val,
1607 valbuf_tmp);
1608 val = valbuf_tmp;
1609 }
1610#endif
1611 /* Note: must use write_register_gen here instead
1612 of regcache_raw_write, because
1613 regcache_raw_write works only for real
1614 registers, not pseudo. write_register_gen will
1615 call the gdbarch function to do register
1616 writes, and that will properly know how to deal
7bb11558 1617 with pseudoregs. */
55ff77ac
CV		 1618 deprecated_write_register_gen (regnum, val);
1619 fp_args[double_arg_index] = 1;
1620 fp_args[double_arg_index + 1] = 1;
7bb11558 1621 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1622 int_argreg ++;
1623 }
1624 else
1625 ;
1626 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1627 necessary spilling on the stack. */
55ff77ac
CV		 1628 }
1629 }
1630 }
1631 return sp;
1632}
1633
1634/* Function: push_return_address (pc)
1635 Set up the return address for the inferior function call.
1636 Needed for targets where we don't actually execute a JSR/BSR instruction */
1637
1638static CORE_ADDR
1639sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1640{
e8a7b686 1641 write_register (PR_REGNUM, entry_point_address ());
55ff77ac
CV		 1642 return sp;
1643}
1644
1645/* Find a function's return value in the appropriate registers (in
1646 regbuf), and copy it into valbuf. Extract from an array REGBUF
1647 containing the (raw) register state a function return value of type
1648 TYPE, and copy that, in virtual format, into VALBUF. */
1649static void
1650sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1651{
1652 int offset;
1653 int return_register;
1654 int len = TYPE_LENGTH (type);
55ff77ac
CV		 1655
1656 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1657 {
1658 if (len == 4)
1659 {
1660 /* Return value stored in FP0_REGNUM */
1661 return_register = FP0_REGNUM;
62700349 1662 offset = DEPRECATED_REGISTER_BYTE (return_register);
7bb11558 1663 memcpy (valbuf, (char *) regbuf + offset, len);
55ff77ac
CV		 1664 }
1665 else if (len == 8)
1666 {
1667 /* return value stored in DR0_REGNUM */
1668 DOUBLEST val;
1669
1670 return_register = DR0_REGNUM;
62700349 1671 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1672
1673 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1674 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1675 (char *) regbuf + offset, &val);
1676 else
1677 floatformat_to_doublest (&floatformat_ieee_double_big,
1678 (char *) regbuf + offset, &val);
7bb11558 1679 store_typed_floating (valbuf, type, val);
55ff77ac
CV		 1680 }
1681 }
1682 else
1683 {
1684 if (len <= 8)
1685 {
1686 /* Result is in register 2. If smaller than 8 bytes, it is padded
7bb11558 1687 at the most significant end. */
55ff77ac
CV		 1688 return_register = DEFAULT_RETURN_REGNUM;
1689 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
62700349 1690 offset = DEPRECATED_REGISTER_BYTE (return_register) +
7bb11558 1691 register_size (current_gdbarch, return_register) - len;
55ff77ac 1692 else
62700349 1693 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1694 memcpy (valbuf, (char *) regbuf + offset, len);
1695 }
1696 else
1697 error ("bad size for return value");
1698 }
1699}
1700
1701/* Write into appropriate registers a function return value
1702 of type TYPE, given in virtual format.
1703 If the architecture is sh4 or sh3e, store a function's return value
1704 in the R0 general register or in the FP0 floating point register,
1705 depending on the type of the return value. In all the other cases
7bb11558 1706 the result is stored in r0, left-justified. */
55ff77ac
CV		 1707
1708static void
1709sh64_store_return_value (struct type *type, char *valbuf)
1710{
7bb11558 1711 char buf[64]; /* more than enough... */
55ff77ac
CV		 1712 int len = TYPE_LENGTH (type);
1713
1714 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1715 {
1716 if (len == 4)
1717 {
1718 /* Return value stored in FP0_REGNUM */
1719 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1720 }
1721 if (len == 8)
1722 {
1723 /* return value stored in DR0_REGNUM */
1724 /* FIXME: Implement */
1725 }
1726 }
1727 else
1728 {
1729 int return_register = DEFAULT_RETURN_REGNUM;
1730 int offset = 0;
1731
7bb11558 1732 if (len <= register_size (current_gdbarch, return_register))
55ff77ac 1733 {
7bb11558
MS		 1734 /* Pad with zeros. */
1735 memset (buf, 0, register_size (current_gdbarch, return_register));
55ff77ac 1736 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
7bb11558
MS		 1737 offset = 0; /*register_size (current_gdbarch,
1738 return_register) - len;*/
55ff77ac 1739 else
7bb11558 1740 offset = register_size (current_gdbarch, return_register) - len;
55ff77ac
CV		 1741
1742 memcpy (buf + offset, valbuf, len);
1743 deprecated_write_register_gen (return_register, buf);
1744 }
1745 else
1746 deprecated_write_register_gen (return_register, valbuf);
1747 }
1748}
1749
1750static void
1751sh64_show_media_regs (void)
1752{
1753 int i;
55ff77ac
CV		 1754
1755 printf_filtered ("PC=%s SR=%016llx \n",
1756 paddr (read_register (PC_REGNUM)),
1757 (long long) read_register (SR_REGNUM));
1758
1759 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1760 (long long) read_register (SSR_REGNUM),
1761 (long long) read_register (SPC_REGNUM));
1762 printf_filtered ("FPSCR=%016lx\n ",
1763 (long) read_register (FPSCR_REGNUM));
1764
1765 for (i = 0; i < 64; i = i + 4)
1766 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1767 i, i + 3,
1768 (long long) read_register (i + 0),
1769 (long long) read_register (i + 1),
1770 (long long) read_register (i + 2),
1771 (long long) read_register (i + 3));
1772
1773 printf_filtered ("\n");
1774
1775 for (i = 0; i < 64; i = i + 8)
1776 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1777 i, i + 7,
1778 (long) read_register (FP0_REGNUM + i + 0),
1779 (long) read_register (FP0_REGNUM + i + 1),
1780 (long) read_register (FP0_REGNUM + i + 2),
1781 (long) read_register (FP0_REGNUM + i + 3),
1782 (long) read_register (FP0_REGNUM + i + 4),
1783 (long) read_register (FP0_REGNUM + i + 5),
1784 (long) read_register (FP0_REGNUM + i + 6),
1785 (long) read_register (FP0_REGNUM + i + 7));
1786}
1787
1788static void
1789sh64_show_compact_regs (void)
1790{
1791 int i;
55ff77ac
CV		 1792
1793 printf_filtered ("PC=%s \n",
1794 paddr (read_register (PC_C_REGNUM)));
1795
1796 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1797 (long) read_register (GBR_C_REGNUM),
1798 (long) read_register (MACH_C_REGNUM),
1799 (long) read_register (MACL_C_REGNUM),
1800 (long) read_register (PR_C_REGNUM),
1801 (long) read_register (T_C_REGNUM));
1802 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1803 (long) read_register (FPSCR_C_REGNUM),
1804 (long) read_register (FPUL_C_REGNUM));
1805
1806 for (i = 0; i < 16; i = i + 4)
1807 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1808 i, i + 3,
1809 (long) read_register (i + 0),
1810 (long) read_register (i + 1),
1811 (long) read_register (i + 2),
1812 (long) read_register (i + 3));
1813
1814 printf_filtered ("\n");
1815
1816 for (i = 0; i < 16; i = i + 8)
1817 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1818 i, i + 7,
1819 (long) read_register (FP0_REGNUM + i + 0),
1820 (long) read_register (FP0_REGNUM + i + 1),
1821 (long) read_register (FP0_REGNUM + i + 2),
1822 (long) read_register (FP0_REGNUM + i + 3),
1823 (long) read_register (FP0_REGNUM + i + 4),
1824 (long) read_register (FP0_REGNUM + i + 5),
1825 (long) read_register (FP0_REGNUM + i + 6),
1826 (long) read_register (FP0_REGNUM + i + 7));
1827}
1828
7bb11558
MS		 1829/* FIXME!!! This only shows the registers for shmedia, excluding the
1830 pseudo registers. */
55ff77ac
CV		 1831void
1832sh64_show_regs (void)
1833{
1834 if (deprecated_selected_frame
1835 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1836 sh64_show_media_regs ();
1837 else
1838 sh64_show_compact_regs ();
1839}
1840
1841/* *INDENT-OFF* */
1842/*
1843 SH MEDIA MODE (ISA 32)
1844 general registers (64-bit) 0-63
18450 r0, r1, r2, r3, r4, r5, r6, r7,
184664 r8, r9, r10, r11, r12, r13, r14, r15,
1847128 r16, r17, r18, r19, r20, r21, r22, r23,
1848192 r24, r25, r26, r27, r28, r29, r30, r31,
1849256 r32, r33, r34, r35, r36, r37, r38, r39,
1850320 r40, r41, r42, r43, r44, r45, r46, r47,
1851384 r48, r49, r50, r51, r52, r53, r54, r55,
1852448 r56, r57, r58, r59, r60, r61, r62, r63,
1853
1854 pc (64-bit) 64
1855512 pc,
1856
1857 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1858520 sr, ssr, spc,
1859
1860 target registers (64-bit) 68-75
1861544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1862
1863 floating point state control register (32-bit) 76
1864608 fpscr,
1865
1866 single precision floating point registers (32-bit) 77-140
1867612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1868644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1869676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1870708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1871740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1872772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1873804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1874836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1875
1876TOTAL SPACE FOR REGISTERS: 868 bytes
1877
1878From here on they are all pseudo registers: no memory allocated.
1879REGISTER_BYTE returns the register byte for the base register.
1880
1881 double precision registers (pseudo) 141-172
1882 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1883 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1884 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1885 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1886
1887 floating point pairs (pseudo) 173-204
1888 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1889 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1890 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1891 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1892
1893 floating point vectors (4 floating point regs) (pseudo) 205-220
1894 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1895 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1896
1897 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1898 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1899 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1900 pc_c,
1901 gbr_c, mach_c, macl_c, pr_c, t_c,
1902 fpscr_c, fpul_c,
1903 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1904 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1905 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1906 fv0_c, fv4_c, fv8_c, fv12_c
1907*/
1908/* *INDENT-ON* */
1909static int
39add00a 1910sh64_register_byte (int reg_nr)
55ff77ac
CV		 1911{
1912 int base_regnum = -1;
55ff77ac
CV		 1913
1914 /* If it is a pseudo register, get the number of the first floating
7bb11558 1915 point register that is part of it. */
55ff77ac
CV		 1916 if (reg_nr >= DR0_REGNUM
1917 && reg_nr <= DR_LAST_REGNUM)
1918 base_regnum = dr_reg_base_num (reg_nr);
1919
1920 else if (reg_nr >= FPP0_REGNUM
1921 && reg_nr <= FPP_LAST_REGNUM)
1922 base_regnum = fpp_reg_base_num (reg_nr);
1923
1924 else if (reg_nr >= FV0_REGNUM
1925 && reg_nr <= FV_LAST_REGNUM)
1926 base_regnum = fv_reg_base_num (reg_nr);
1927
1928 /* sh compact pseudo register. FPSCR is a pathological case, need to
7bb11558 1929 treat it as special. */
55ff77ac
CV		 1930 else if ((reg_nr >= R0_C_REGNUM
1931 && reg_nr <= FV_LAST_C_REGNUM)
1932 && reg_nr != FPSCR_C_REGNUM)
1933 base_regnum = sh64_compact_reg_base_num (reg_nr);
1934
7bb11558
MS		 1935 /* Now return the offset in bytes within the register cache. */
1936 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
55ff77ac
CV		 1937 if (reg_nr >= DR0_REGNUM
1938 && reg_nr <= FV_LAST_REGNUM)
1939 return (base_regnum - FP0_REGNUM + 1) * 4
1940 + (TR7_REGNUM + 1) * 8;
1941
1942 /* sh compact pseudo register: general register */
1943 if ((reg_nr >= R0_C_REGNUM
1944 && reg_nr <= R_LAST_C_REGNUM))
1945 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1946 ? base_regnum * 8 + 4
1947 : base_regnum * 8);
1948
1949 /* sh compact pseudo register: */
1950 if (reg_nr == PC_C_REGNUM
1951 || reg_nr == GBR_C_REGNUM
1952 || reg_nr == MACL_C_REGNUM
1953 || reg_nr == PR_C_REGNUM)
1954 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1955 ? base_regnum * 8 + 4
1956 : base_regnum * 8);
1957
1958 if (reg_nr == MACH_C_REGNUM)
1959 return base_regnum * 8;
1960
1961 if (reg_nr == T_C_REGNUM)
1962 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1963
1964 /* sh compact pseudo register: floating point register */
1965 else if (reg_nr >= FP0_C_REGNUM
1966 && reg_nr <= FV_LAST_C_REGNUM)
1967 return (base_regnum - FP0_REGNUM) * 4
1968 + (TR7_REGNUM + 1) * 8 + 4;
1969
1970 else if (reg_nr == FPSCR_C_REGNUM)
1971 /* This is complicated, for now return the beginning of the
7bb11558 1972 architectural FPSCR register. */
55ff77ac
CV		 1973 return (TR7_REGNUM + 1) * 8;
1974
1975 else if (reg_nr == FPUL_C_REGNUM)
1976 return ((base_regnum - FP0_REGNUM) * 4 +
1977 (TR7_REGNUM + 1) * 8 + 4);
1978
7bb11558
MS		 1979 /* It is not a pseudo register. */
1980 /* It is a 64 bit register. */
55ff77ac
CV		 1981 else if (reg_nr <= TR7_REGNUM)
1982 return reg_nr * 8;
1983
7bb11558 1984 /* It is a 32 bit register. */
55ff77ac
CV		 1985 else if (reg_nr == FPSCR_REGNUM)
1986 return (FPSCR_REGNUM * 8);
1987
1988 /* It is floating point 32-bit register */
1989 else
1990 return ((TR7_REGNUM + 1) * 8
1991 + (reg_nr - FP0_REGNUM + 1) * 4);
1992}
1993
55ff77ac 1994static struct type *
39add00a 1995sh64_build_float_register_type (int high)
55ff77ac
CV		 1996{
1997 struct type *temp;
1998
1999 temp = create_range_type (NULL, builtin_type_int, 0, high);
2000 return create_array_type (NULL, builtin_type_float, temp);
2001}
2002
7bb11558
MS		 2003/* Return the GDB type object for the "standard" data type
2004 of data in register REG_NR. */
55ff77ac 2005static struct type *
7bb11558 2006sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
55ff77ac 2007{
55ff77ac
CV		 2008 if ((reg_nr >= FP0_REGNUM
2009 && reg_nr <= FP_LAST_REGNUM)
2010 || (reg_nr >= FP0_C_REGNUM
2011 && reg_nr <= FP_LAST_C_REGNUM))
2012 return builtin_type_float;
2013 else if ((reg_nr >= DR0_REGNUM
2014 && reg_nr <= DR_LAST_REGNUM)
2015 || (reg_nr >= DR0_C_REGNUM
2016 && reg_nr <= DR_LAST_C_REGNUM))
2017 return builtin_type_double;
2018 else if (reg_nr >= FPP0_REGNUM
2019 && reg_nr <= FPP_LAST_REGNUM)
39add00a 2020 return sh64_build_float_register_type (1);
55ff77ac
CV		 2021 else if ((reg_nr >= FV0_REGNUM
2022 && reg_nr <= FV_LAST_REGNUM)
2023 ||(reg_nr >= FV0_C_REGNUM
2024 && reg_nr <= FV_LAST_C_REGNUM))
39add00a 2025 return sh64_build_float_register_type (3);
55ff77ac
CV		 2026 else if (reg_nr == FPSCR_REGNUM)
2027 return builtin_type_int;
2028 else if (reg_nr >= R0_C_REGNUM
2029 && reg_nr < FP0_C_REGNUM)
2030 return builtin_type_int;
2031 else
2032 return builtin_type_long_long;
2033}
2034
2035static void
39add00a 2036sh64_register_convert_to_virtual (int regnum, struct type *type,
55ff77ac
CV		 2037 char *from, char *to)
2038{
55ff77ac
CV		 2039 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2040 {
7bb11558
MS		 2041 /* It is a no-op. */
2042 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2043 return;
2044 }
2045
2046 if ((regnum >= DR0_REGNUM
2047 && regnum <= DR_LAST_REGNUM)
2048 || (regnum >= DR0_C_REGNUM
2049 && regnum <= DR_LAST_C_REGNUM))
2050 {
2051 DOUBLEST val;
7bb11558
MS		 2052 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2053 from, &val);
39add00a 2054 store_typed_floating (to, type, val);
55ff77ac
CV		 2055 }
2056 else
39add00a 2057 error ("sh64_register_convert_to_virtual called with non DR register number");
55ff77ac
CV		 2058}
2059
2060static void
39add00a 2061sh64_register_convert_to_raw (struct type *type, int regnum,
55ff77ac
CV		 2062 const void *from, void *to)
2063{
55ff77ac
CV		 2064 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2065 {
7bb11558
MS		 2066 /* It is a no-op. */
2067 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2068 return;
2069 }
2070
2071 if ((regnum >= DR0_REGNUM
2072 && regnum <= DR_LAST_REGNUM)
2073 || (regnum >= DR0_C_REGNUM
2074 && regnum <= DR_LAST_C_REGNUM))
2075 {
2076 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
7bb11558
MS		 2077 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2078 &val, to);
55ff77ac
CV		 2079 }
2080 else
39add00a 2081 error ("sh64_register_convert_to_raw called with non DR register number");
55ff77ac
CV		 2082}
2083
2084static void
2085sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2086 int reg_nr, void *buffer)
2087{
2088 int base_regnum;
2089 int portion;
2090 int offset = 0;
2091 char temp_buffer[MAX_REGISTER_SIZE];
55ff77ac
CV		 2092
2093 if (reg_nr >= DR0_REGNUM
2094 && reg_nr <= DR_LAST_REGNUM)
2095 {
2096 base_regnum = dr_reg_base_num (reg_nr);
2097
7bb11558 2098 /* Build the value in the provided buffer. */
55ff77ac 2099 /* DR regs are double precision registers obtained by
7bb11558 2100 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2101 for (portion = 0; portion < 2; portion++)
2102 regcache_raw_read (regcache, base_regnum + portion,
2103 (temp_buffer
7bb11558 2104 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2105
7bb11558 2106 /* We must pay attention to the endianness. */
39add00a
MS		 2107 sh64_register_convert_to_virtual (reg_nr,
2108 gdbarch_register_type (gdbarch,
2109 reg_nr),
2110 temp_buffer, buffer);
55ff77ac
CV		 2111
2112 }
2113
2114 else if (reg_nr >= FPP0_REGNUM
2115 && reg_nr <= FPP_LAST_REGNUM)
2116 {
2117 base_regnum = fpp_reg_base_num (reg_nr);
2118
7bb11558 2119 /* Build the value in the provided buffer. */
55ff77ac 2120 /* FPP regs are pairs of single precision registers obtained by
7bb11558 2121 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2122 for (portion = 0; portion < 2; portion++)
2123 regcache_raw_read (regcache, base_regnum + portion,
2124 ((char *) buffer
7bb11558 2125 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2126 }
2127
2128 else if (reg_nr >= FV0_REGNUM
2129 && reg_nr <= FV_LAST_REGNUM)
2130 {
2131 base_regnum = fv_reg_base_num (reg_nr);
2132
7bb11558 2133 /* Build the value in the provided buffer. */
55ff77ac 2134 /* FV regs are vectors of single precision registers obtained by
7bb11558 2135 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2136 for (portion = 0; portion < 4; portion++)
2137 regcache_raw_read (regcache, base_regnum + portion,
2138 ((char *) buffer
7bb11558 2139 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2140 }
2141
2142 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2143 else if (reg_nr >= R0_C_REGNUM
2144 && reg_nr <= T_C_REGNUM)
2145 {
2146 base_regnum = sh64_compact_reg_base_num (reg_nr);
2147
7bb11558 2148 /* Build the value in the provided buffer. */
55ff77ac
CV		 2149 regcache_raw_read (regcache, base_regnum, temp_buffer);
2150 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2151 offset = 4;
2152 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2153 }
2154
2155 else if (reg_nr >= FP0_C_REGNUM
2156 && reg_nr <= FP_LAST_C_REGNUM)
2157 {
2158 base_regnum = sh64_compact_reg_base_num (reg_nr);
2159
7bb11558 2160 /* Build the value in the provided buffer. */
55ff77ac 2161 /* Floating point registers map 1-1 to the media fp regs,
7bb11558 2162 they have the same size and endianness. */
55ff77ac
CV		 2163 regcache_raw_read (regcache, base_regnum, buffer);
2164 }
2165
2166 else if (reg_nr >= DR0_C_REGNUM
2167 && reg_nr <= DR_LAST_C_REGNUM)
2168 {
2169 base_regnum = sh64_compact_reg_base_num (reg_nr);
2170
2171 /* DR_C regs are double precision registers obtained by
7bb11558 2172 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2173 for (portion = 0; portion < 2; portion++)
2174 regcache_raw_read (regcache, base_regnum + portion,
2175 (temp_buffer
7bb11558 2176 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2177
7bb11558 2178 /* We must pay attention to the endianness. */
39add00a
MS		 2179 sh64_register_convert_to_virtual (reg_nr,
2180 gdbarch_register_type (gdbarch,
2181 reg_nr),
2182 temp_buffer, buffer);
55ff77ac
CV		 2183 }
2184
2185 else if (reg_nr >= FV0_C_REGNUM
2186 && reg_nr <= FV_LAST_C_REGNUM)
2187 {
2188 base_regnum = sh64_compact_reg_base_num (reg_nr);
2189
7bb11558 2190 /* Build the value in the provided buffer. */
55ff77ac 2191 /* FV_C regs are vectors of single precision registers obtained by
7bb11558 2192 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2193 for (portion = 0; portion < 4; portion++)
2194 regcache_raw_read (regcache, base_regnum + portion,
2195 ((char *) buffer
7bb11558 2196 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2197 }
2198
2199 else if (reg_nr == FPSCR_C_REGNUM)
2200 {
2201 int fpscr_base_regnum;
2202 int sr_base_regnum;
2203 unsigned int fpscr_value;
2204 unsigned int sr_value;
2205 unsigned int fpscr_c_value;
2206 unsigned int fpscr_c_part1_value;
2207 unsigned int fpscr_c_part2_value;
2208
2209 fpscr_base_regnum = FPSCR_REGNUM;
2210 sr_base_regnum = SR_REGNUM;
2211
7bb11558 2212 /* Build the value in the provided buffer. */
55ff77ac
CV		 2213 /* FPSCR_C is a very weird register that contains sparse bits
2214 from the FPSCR and the SR architectural registers.
2215 Specifically: */
2216 /* *INDENT-OFF* */
2217 /*
2218 FPSRC_C bit
2219 0 Bit 0 of FPSCR
2220 1 reserved
2221 2-17 Bit 2-18 of FPSCR
2222 18-20 Bits 12,13,14 of SR
2223 21-31 reserved
2224 */
2225 /* *INDENT-ON* */
2226 /* Get FPSCR into a local buffer */
2227 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
7bb11558 2228 /* Get value as an int. */
55ff77ac
CV		 2229 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2230 /* Get SR into a local buffer */
2231 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
7bb11558 2232 /* Get value as an int. */
55ff77ac 2233 sr_value = extract_unsigned_integer (temp_buffer, 4);
7bb11558 2234 /* Build the new value. */
55ff77ac
CV		 2235 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2236 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2237 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2238 /* Store that in out buffer!!! */
2239 store_unsigned_integer (buffer, 4, fpscr_c_value);
7bb11558 2240 /* FIXME There is surely an endianness gotcha here. */
55ff77ac
CV		 2241 }
2242
2243 else if (reg_nr == FPUL_C_REGNUM)
2244 {
2245 base_regnum = sh64_compact_reg_base_num (reg_nr);
2246
2247 /* FPUL_C register is floating point register 32,
7bb11558 2248 same size, same endianness. */
55ff77ac
CV		 2249 regcache_raw_read (regcache, base_regnum, buffer);
2250 }
2251}
2252
2253static void
2254sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2255 int reg_nr, const void *buffer)
2256{
2257 int base_regnum, portion;
2258 int offset;
2259 char temp_buffer[MAX_REGISTER_SIZE];
55ff77ac
CV		 2260
2261 if (reg_nr >= DR0_REGNUM
2262 && reg_nr <= DR_LAST_REGNUM)
2263 {
2264 base_regnum = dr_reg_base_num (reg_nr);
7bb11558 2265 /* We must pay attention to the endianness. */
39add00a
MS		 2266 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
2267 reg_nr,
2268 buffer, temp_buffer);
55ff77ac
CV		 2269
2270 /* Write the real regs for which this one is an alias. */
2271 for (portion = 0; portion < 2; portion++)
2272 regcache_raw_write (regcache, base_regnum + portion,
2273 (temp_buffer
7bb11558
MS		 2274 + register_size (gdbarch,
2275 base_regnum) * portion));
55ff77ac
CV		 2276 }
2277
2278 else if (reg_nr >= FPP0_REGNUM
2279 && reg_nr <= FPP_LAST_REGNUM)
2280 {
2281 base_regnum = fpp_reg_base_num (reg_nr);
2282
2283 /* Write the real regs for which this one is an alias. */
2284 for (portion = 0; portion < 2; portion++)
2285 regcache_raw_write (regcache, base_regnum + portion,
2286 ((char *) buffer
7bb11558
MS		 2287 + register_size (gdbarch,
2288 base_regnum) * portion));
55ff77ac
CV		 2289 }
2290
2291 else if (reg_nr >= FV0_REGNUM
2292 && reg_nr <= FV_LAST_REGNUM)
2293 {
2294 base_regnum = fv_reg_base_num (reg_nr);
2295
2296 /* Write the real regs for which this one is an alias. */
2297 for (portion = 0; portion < 4; portion++)
2298 regcache_raw_write (regcache, base_regnum + portion,
2299 ((char *) buffer
7bb11558
MS		 2300 + register_size (gdbarch,
2301 base_regnum) * portion));
55ff77ac
CV		 2302 }
2303
2304 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2305 register but only 4 bytes of it. */
2306 else if (reg_nr >= R0_C_REGNUM
2307 && reg_nr <= T_C_REGNUM)
2308 {
2309 base_regnum = sh64_compact_reg_base_num (reg_nr);
7bb11558 2310 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
55ff77ac
CV		 2311 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2312 offset = 4;
2313 else
2314 offset = 0;
2315 /* Let's read the value of the base register into a temporary
2316 buffer, so that overwriting the last four bytes with the new
7bb11558 2317 value of the pseudo will leave the upper 4 bytes unchanged. */
55ff77ac
CV		 2318 regcache_raw_read (regcache, base_regnum, temp_buffer);
2319 /* Write as an 8 byte quantity */
2320 memcpy (temp_buffer + offset, buffer, 4);
2321 regcache_raw_write (regcache, base_regnum, temp_buffer);
2322 }
2323
2324 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
7bb11558 2325 registers. Both are 4 bytes. */
55ff77ac
CV		 2326 else if (reg_nr >= FP0_C_REGNUM
2327 && reg_nr <= FP_LAST_C_REGNUM)
2328 {
2329 base_regnum = sh64_compact_reg_base_num (reg_nr);
2330 regcache_raw_write (regcache, base_regnum, buffer);
2331 }
2332
2333 else if (reg_nr >= DR0_C_REGNUM
2334 && reg_nr <= DR_LAST_C_REGNUM)
2335 {
2336 base_regnum = sh64_compact_reg_base_num (reg_nr);
2337 for (portion = 0; portion < 2; portion++)
2338 {
7bb11558 2339 /* We must pay attention to the endianness. */
39add00a
MS		 2340 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2341 reg_nr),
2342 reg_nr,
2343 buffer, temp_buffer);
55ff77ac
CV		 2344
2345 regcache_raw_write (regcache, base_regnum + portion,
2346 (temp_buffer
7bb11558
MS		 2347 + register_size (gdbarch,
2348 base_regnum) * portion));
55ff77ac
CV		 2349 }
2350 }
2351
2352 else if (reg_nr >= FV0_C_REGNUM
2353 && reg_nr <= FV_LAST_C_REGNUM)
2354 {
2355 base_regnum = sh64_compact_reg_base_num (reg_nr);
2356
2357 for (portion = 0; portion < 4; portion++)
2358 {
2359 regcache_raw_write (regcache, base_regnum + portion,
2360 ((char *) buffer
7bb11558
MS		 2361 + register_size (gdbarch,
2362 base_regnum) * portion));
55ff77ac
CV		 2363 }
2364 }
2365
2366 else if (reg_nr == FPSCR_C_REGNUM)
2367 {
2368 int fpscr_base_regnum;
2369 int sr_base_regnum;
2370 unsigned int fpscr_value;
2371 unsigned int sr_value;
2372 unsigned int old_fpscr_value;
2373 unsigned int old_sr_value;
2374 unsigned int fpscr_c_value;
2375 unsigned int fpscr_mask;
2376 unsigned int sr_mask;
2377
2378 fpscr_base_regnum = FPSCR_REGNUM;
2379 sr_base_regnum = SR_REGNUM;
2380
2381 /* FPSCR_C is a very weird register that contains sparse bits
2382 from the FPSCR and the SR architectural registers.
2383 Specifically: */
2384 /* *INDENT-OFF* */
2385 /*
2386 FPSRC_C bit
2387 0 Bit 0 of FPSCR
2388 1 reserved
2389 2-17 Bit 2-18 of FPSCR
2390 18-20 Bits 12,13,14 of SR
2391 21-31 reserved
2392 */
2393 /* *INDENT-ON* */
7bb11558 2394 /* Get value as an int. */
55ff77ac
CV		 2395 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2396
7bb11558 2397 /* Build the new values. */
55ff77ac
CV		 2398 fpscr_mask = 0x0003fffd;
2399 sr_mask = 0x001c0000;
2400
2401 fpscr_value = fpscr_c_value & fpscr_mask;
2402 sr_value = (fpscr_value & sr_mask) >> 6;
2403
2404 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2405 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2406 old_fpscr_value &= 0xfffc0002;
2407 fpscr_value |= old_fpscr_value;
2408 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2409 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2410
2411 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2412 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2413 old_sr_value &= 0xffff8fff;
2414 sr_value |= old_sr_value;
2415 store_unsigned_integer (temp_buffer, 4, sr_value);
2416 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2417 }
2418
2419 else if (reg_nr == FPUL_C_REGNUM)
2420 {
2421 base_regnum = sh64_compact_reg_base_num (reg_nr);
2422 regcache_raw_write (regcache, base_regnum, buffer);
2423 }
2424}
2425
7bb11558 2426/* Floating point vector of 4 float registers. */
55ff77ac
CV		 2427static void
2428do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2429 int fv_regnum)
2430{
2431 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2432 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2433 fv_regnum - FV0_REGNUM,
2434 (int) read_register (first_fp_reg_num),
2435 (int) read_register (first_fp_reg_num + 1),
2436 (int) read_register (first_fp_reg_num + 2),
2437 (int) read_register (first_fp_reg_num + 3));
2438}
2439
7bb11558 2440/* Floating point vector of 4 float registers, compact mode. */
55ff77ac
CV		 2441static void
2442do_fv_c_register_info (int fv_regnum)
2443{
2444 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2445 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2446 fv_regnum - FV0_C_REGNUM,
2447 (int) read_register (first_fp_reg_num),
2448 (int) read_register (first_fp_reg_num + 1),
2449 (int) read_register (first_fp_reg_num + 2),
2450 (int) read_register (first_fp_reg_num + 3));
2451}
2452
2453/* Pairs of single regs. The DR are instead double precision
7bb11558 2454 registers. */
55ff77ac
CV		 2455static void
2456do_fpp_register_info (int fpp_regnum)
2457{
2458 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2459
2460 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2461 fpp_regnum - FPP0_REGNUM,
2462 (int) read_register (first_fp_reg_num),
2463 (int) read_register (first_fp_reg_num + 1));
2464}
2465
7bb11558 2466/* Double precision registers. */
55ff77ac
CV		 2467static void
2468do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2469 int dr_regnum)
2470{
2471 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2472
2473 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2474 dr_regnum - DR0_REGNUM,
2475 (int) read_register (first_fp_reg_num),
2476 (int) read_register (first_fp_reg_num + 1));
2477}
2478
7bb11558 2479/* Double precision registers, compact mode. */
55ff77ac
CV		 2480static void
2481do_dr_c_register_info (int dr_regnum)
2482{
2483 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2484
2485 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2486 dr_regnum - DR0_C_REGNUM,
2487 (int) read_register (first_fp_reg_num),
2488 (int) read_register (first_fp_reg_num +1));
2489}
2490
7bb11558 2491/* General register in compact mode. */
55ff77ac
CV		 2492static void
2493do_r_c_register_info (int r_c_regnum)
2494{
2495 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2496
2497 printf_filtered ("r%d_c\t0x%08x\n",
2498 r_c_regnum - R0_C_REGNUM,
2499 /*FIXME!!!*/ (int) read_register (regnum));
2500}
2501
2502/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
7bb11558
MS		 2503 shmedia REGISTERS. */
2504/* Control registers, compact mode. */
55ff77ac
CV		 2505static void
2506do_cr_c_register_info (int cr_c_regnum)
2507{
2508 switch (cr_c_regnum)
2509 {
2510 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2511 break;
2512 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2513 break;
2514 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2515 break;
2516 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2517 break;
2518 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2519 break;
2520 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2521 break;
2522 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2523 break;
2524 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2525 break;
2526 }
2527}
2528
2529static void
2530sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2531{ /* do values for FP (float) regs */
2532 char *raw_buffer;
2533 double flt; /* double extracted from raw hex data */
2534 int inv;
2535 int j;
2536
7bb11558 2537 /* Allocate space for the float. */
55ff77ac
CV		 2538 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2539
2540 /* Get the data in raw format. */
b04f3ab4 2541 if (!frame_register_read (get_selected_frame (NULL), regnum, raw_buffer))
55ff77ac
CV		 2542 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2543
2544 /* Get the register as a number */
2545 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2546
7bb11558 2547 /* Print the name and some spaces. */
55ff77ac
CV		 2548 fputs_filtered (REGISTER_NAME (regnum), file);
2549 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2550
7bb11558 2551 /* Print the value. */
55ff77ac
CV		 2552 if (inv)
2553 fprintf_filtered (file, "<invalid float>");
2554 else
2555 fprintf_filtered (file, "%-10.9g", flt);
2556
7bb11558 2557 /* Print the fp register as hex. */
55ff77ac
CV		 2558 fprintf_filtered (file, "\t(raw 0x");
2559 for (j = 0; j < register_size (gdbarch, regnum); j++)
2560 {
aa1ee363 2561 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
55ff77ac
CV		 2562 : register_size (gdbarch, regnum) - 1 - j;
2563 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2564 }
2565 fprintf_filtered (file, ")");
2566 fprintf_filtered (file, "\n");
2567}
2568
2569static void
2570sh64_do_pseudo_register (int regnum)
2571{
7bb11558 2572 /* All the sh64-compact mode registers are pseudo registers. */
55ff77ac
CV		 2573
2574 if (regnum < NUM_REGS
2575 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2576 internal_error (__FILE__, __LINE__,
e2e0b3e5 2577 _("Invalid pseudo register number %d\n"), regnum);
55ff77ac
CV		 2578
2579 else if ((regnum >= DR0_REGNUM
2580 && regnum <= DR_LAST_REGNUM))
2581 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2582
2583 else if ((regnum >= DR0_C_REGNUM
2584 && regnum <= DR_LAST_C_REGNUM))
2585 do_dr_c_register_info (regnum);
2586
2587 else if ((regnum >= FV0_REGNUM
2588 && regnum <= FV_LAST_REGNUM))
2589 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2590
2591 else if ((regnum >= FV0_C_REGNUM
2592 && regnum <= FV_LAST_C_REGNUM))
2593 do_fv_c_register_info (regnum);
2594
2595 else if (regnum >= FPP0_REGNUM
2596 && regnum <= FPP_LAST_REGNUM)
2597 do_fpp_register_info (regnum);
2598
2599 else if (regnum >= R0_C_REGNUM
2600 && regnum <= R_LAST_C_REGNUM)
7bb11558
MS		 2601 /* FIXME, this function will not print the right format. */
2602 do_r_c_register_info (regnum);
55ff77ac
CV		 2603 else if (regnum >= FP0_C_REGNUM
2604 && regnum <= FP_LAST_C_REGNUM)
7bb11558
MS		 2605 /* This should work also for pseudoregs. */
2606 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum);
55ff77ac
CV		 2607 else if (regnum >= PC_C_REGNUM
2608 && regnum <= FPUL_C_REGNUM)
2609 do_cr_c_register_info (regnum);
55ff77ac
CV		 2610}
2611
2612static void
2613sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2614{
2615 char raw_buffer[MAX_REGISTER_SIZE];
2616
2617 fputs_filtered (REGISTER_NAME (regnum), file);
2618 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2619
2620 /* Get the data in raw format. */
b04f3ab4 2621 if (!frame_register_read (get_selected_frame (NULL), regnum, raw_buffer))
55ff77ac
CV		 2622 fprintf_filtered (file, "*value not available*\n");
2623
2624 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2625 file, 'x', 1, 0, Val_pretty_default);
2626 fprintf_filtered (file, "\t");
2627 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2628 file, 0, 1, 0, Val_pretty_default);
2629 fprintf_filtered (file, "\n");
2630}
2631
2632static void
2633sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2634{
2635 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2636 internal_error (__FILE__, __LINE__,
e2e0b3e5 2637 _("Invalid register number %d\n"), regnum);
55ff77ac
CV		 2638
2639 else if (regnum >= 0 && regnum < NUM_REGS)
2640 {
2641 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2642 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2643 else
2644 sh_do_register (gdbarch, file, regnum); /* All other regs */
2645 }
2646
2647 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2648 sh64_do_pseudo_register (regnum);
2649}
2650
2651static void
2652sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2653 struct frame_info *frame, int regnum, int fpregs)
2654{
2655 if (regnum != -1) /* do one specified register */
2656 {
2657 if (*(REGISTER_NAME (regnum)) == '\0')
2658 error ("Not a valid register for the current processor type");
2659
2660 sh_print_register (gdbarch, file, regnum);
2661 }
2662 else
2663 /* do all (or most) registers */
2664 {
2665 regnum = 0;
2666 while (regnum < NUM_REGS)
2667 {
2668 /* If the register name is empty, it is undefined for this
2669 processor, so don't display anything. */
2670 if (REGISTER_NAME (regnum) == NULL
2671 || *(REGISTER_NAME (regnum)) == '\0')
2672 {
2673 regnum++;
2674 continue;
2675 }
2676
2677 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2678 {
2679 if (fpregs)
2680 {
2681 /* true for "INFO ALL-REGISTERS" command */
2682 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2683 regnum ++;
2684 }
2685 else
2686 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2687 }
2688 else
2689 {
2690 sh_do_register (gdbarch, file, regnum); /* All other regs */
2691 regnum++;
2692 }
2693 }
2694
2695 if (fpregs)
2696 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2697 {
2698 sh64_do_pseudo_register (regnum);
2699 regnum++;
2700 }
2701 }
2702}
2703
2704static void
2705sh_compact_do_registers_info (int regnum, int fpregs)
2706{
55ff77ac
CV		 2707 if (regnum != -1) /* do one specified register */
2708 {
2709 if (*(REGISTER_NAME (regnum)) == '\0')
2710 error ("Not a valid register for the current processor type");
2711
2712 if (regnum >= 0 && regnum < R0_C_REGNUM)
2713 error ("Not a valid register for the current processor mode.");
2714
2715 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2716 }
2717 else
2718 /* do all compact registers */
2719 {
2720 regnum = R0_C_REGNUM;
2721 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2722 {
2723 sh64_do_pseudo_register (regnum);
2724 regnum++;
2725 }
2726 }
2727}
2728
2729static void
2730sh64_do_registers_info (int regnum, int fpregs)
2731{
2732 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2733 sh_print_registers_info (current_gdbarch, gdb_stdout,
2734 deprecated_selected_frame, regnum, fpregs);
2735 else
7bb11558 2736 sh_compact_do_registers_info (regnum, fpregs);
55ff77ac
CV		 2737}
2738
55ff77ac
CV		 2739/* Fetch (and possibly build) an appropriate link_map_offsets structure
2740 for native i386 linux targets using the struct offsets defined in
2741 link.h (but without actual reference to that file).
2742
2743 This makes it possible to access i386-linux shared libraries from
2744 a gdb that was not built on an i386-linux host (for cross debugging).
2745 */
2746
2747struct link_map_offsets *
2748sh_linux_svr4_fetch_link_map_offsets (void)
2749{
2750 static struct link_map_offsets lmo;
2751 static struct link_map_offsets *lmp = 0;
2752
2753 if (lmp == 0)
2754 {
2755 lmp = &lmo;
2756
2757 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2758
2759 lmo.r_map_offset = 4;
2760 lmo.r_map_size = 4;
2761
2762 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2763
2764 lmo.l_addr_offset = 0;
2765 lmo.l_addr_size = 4;
2766
2767 lmo.l_name_offset = 4;
2768 lmo.l_name_size = 4;
2769
2770 lmo.l_next_offset = 12;
2771 lmo.l_next_size = 4;
2772
2773 lmo.l_prev_offset = 16;
2774 lmo.l_prev_size = 4;
2775 }
2776
2777 return lmp;
2778}
55ff77ac
CV		 2779
2780gdbarch_init_ftype sh64_gdbarch_init;
2781
2782struct gdbarch *
2783sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2784{
55ff77ac
CV		 2785 struct gdbarch *gdbarch;
2786 struct gdbarch_tdep *tdep;
2787
2788 /* If there is already a candidate, use it. */
2789 arches = gdbarch_list_lookup_by_info (arches, &info);
2790 if (arches != NULL)
2791 return arches->gdbarch;
2792
2793 /* None found, create a new architecture from the information
7bb11558 2794 provided. */
55ff77ac
CV		 2795 tdep = XMALLOC (struct gdbarch_tdep);
2796 gdbarch = gdbarch_alloc (&info, tdep);
2797
2798 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2799 ready to unwind the PC first (see frame.c:get_prev_frame()). */
0968aa8c 2800 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
55ff77ac
CV		 2801
2802 /* Determine the ABI */
2803 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2804 {
7bb11558 2805 /* If the ABI is the 64-bit one, it can only be sh-media. */
55ff77ac
CV		 2806 tdep->sh_abi = SH_ABI_64;
2807 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2808 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2809 }
2810 else
2811 {
2812 /* If the ABI is the 32-bit one it could be either media or
7bb11558 2813 compact. */
55ff77ac
CV		 2814 tdep->sh_abi = SH_ABI_32;
2815 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2816 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2817 }
2818
2819 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2820 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2821 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2822 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2823 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2824 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2825
2826 set_gdbarch_sp_regnum (gdbarch, 15);
2827 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2828
2829 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2830 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2831
2832 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2833
2834 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2835 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
55ff77ac 2836
55ff77ac
CV		 2837 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2838
2839 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2840 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2841 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2842
2843 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2844 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2845 set_gdbarch_pc_regnum (gdbarch, 64);
2846
7bb11558
MS		 2847 /* The number of real registers is the same whether we are in
2848 ISA16(compact) or ISA32(media). */
55ff77ac 2849 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
55ff77ac 2850
39add00a 2851 set_gdbarch_register_name (gdbarch, sh64_register_name);
7bb11558 2852 set_gdbarch_register_type (gdbarch, sh64_register_type);
55ff77ac 2853 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
39add00a 2854 set_gdbarch_deprecated_register_byte (gdbarch, sh64_register_byte);
55ff77ac
CV		 2855 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2856 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2857
2858 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2859 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
39add00a 2860 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
55ff77ac
CV		 2861
2862 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2863 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2864 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2865 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2866 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2867 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2868 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2869 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
74055713 2870 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
b5622e8d 2871 set_gdbarch_deprecated_use_struct_convention (gdbarch, sh64_use_struct_convention);
55ff77ac
CV		 2872 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2873 set_gdbarch_elf_make_msymbol_special (gdbarch,
2874 sh64_elf_make_msymbol_special);
2875
2876 /* Hook in ABI-specific overrides, if they have been registered. */
2877 gdbarch_init_osabi (info, gdbarch);
2878
2879 return gdbarch;
2880}
GDB Binutils - Deliverables
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