Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
0fb0cc75 | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
9b254dd1 | 4 | Free Software Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 11 | (at your option) any later version. |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b | 18 | You should have received a copy of the GNU General Public License |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 20 | |
c906108c | 21 | #include "defs.h" |
5af923b0 | 22 | #include "arch-utils.h" |
386c036b | 23 | #include "dis-asm.h" |
f5a9b87d | 24 | #include "dwarf2-frame.h" |
386c036b | 25 | #include "floatformat.h" |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c SS |
36 | #include "target.h" |
37 | #include "value.h" | |
c906108c | 38 | |
43bd9a9e | 39 | #include "gdb_assert.h" |
386c036b | 40 | #include "gdb_string.h" |
c906108c | 41 | |
386c036b | 42 | #include "sparc-tdep.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
66 | big-endian IA-64 Quad-recision format. */ | |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 90 | |
386c036b MK |
91 | /* Fetch the instruction at PC. Instructions are always big-endian |
92 | even if the processor operates in little-endian mode. */ | |
93 | ||
94 | unsigned long | |
95 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 96 | { |
e1613aba | 97 | gdb_byte buf[4]; |
386c036b MK |
98 | unsigned long insn; |
99 | int i; | |
100 | ||
690668cc | 101 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 102 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 103 | return 0; |
c906108c | 104 | |
386c036b MK |
105 | insn = 0; |
106 | for (i = 0; i < sizeof (buf); i++) | |
107 | insn = (insn << 8) | buf[i]; | |
108 | return insn; | |
109 | } | |
42cdca6c MK |
110 | \f |
111 | ||
5465445a JB |
112 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
113 | instruction. */ | |
114 | ||
115 | static int | |
116 | sparc_is_unimp_insn (CORE_ADDR pc) | |
117 | { | |
118 | const unsigned long insn = sparc_fetch_instruction (pc); | |
119 | ||
120 | return ((insn & 0xc1c00000) == 0); | |
121 | } | |
122 | ||
42cdca6c MK |
123 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
124 | website http://stackghost.cerias.purdue.edu "... transparently and | |
125 | automatically protects applications' stack frames; more | |
126 | specifically, it guards the return pointers. The protection | |
127 | mechanisms require no application source or binary modification and | |
128 | imposes only a negligible performance penalty." | |
129 | ||
130 | The same website provides the following description of how | |
131 | StackGhost works: | |
132 | ||
133 | "StackGhost interfaces with the kernel trap handler that would | |
134 | normally write out registers to the stack and the handler that | |
135 | would read them back in. By XORing a cookie into the | |
136 | return-address saved in the user stack when it is actually written | |
137 | to the stack, and then XOR it out when the return-address is pulled | |
138 | from the stack, StackGhost can cause attacker corrupted return | |
139 | pointers to behave in a manner the attacker cannot predict. | |
140 | StackGhost can also use several unused bits in the return pointer | |
141 | to detect a smashed return pointer and abort the process." | |
142 | ||
143 | For GDB this means that whenever we're reading %i7 from a stack | |
144 | frame's window save area, we'll have to XOR the cookie. | |
145 | ||
146 | More information on StackGuard can be found on in: | |
147 | ||
148 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
149 | Stack Protection." 2001. Published in USENIX Security Symposium | |
150 | '01. */ | |
151 | ||
152 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
153 | ||
154 | ULONGEST | |
155 | sparc_fetch_wcookie (void) | |
156 | { | |
baf92889 | 157 | struct target_ops *ops = ¤t_target; |
e1613aba | 158 | gdb_byte buf[8]; |
baf92889 MK |
159 | int len; |
160 | ||
13547ab6 | 161 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
162 | if (len == -1) |
163 | return 0; | |
42cdca6c | 164 | |
baf92889 MK |
165 | /* We should have either an 32-bit or an 64-bit cookie. */ |
166 | gdb_assert (len == 4 || len == 8); | |
167 | ||
168 | return extract_unsigned_integer (buf, len); | |
169 | } | |
386c036b | 170 | \f |
baf92889 | 171 | |
386c036b MK |
172 | /* The functions on this page are intended to be used to classify |
173 | function arguments. */ | |
c906108c | 174 | |
386c036b | 175 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 176 | |
386c036b MK |
177 | static int |
178 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 179 | { |
80ad1639 MK |
180 | int len = TYPE_LENGTH (type); |
181 | ||
386c036b | 182 | switch (TYPE_CODE (type)) |
c906108c | 183 | { |
386c036b MK |
184 | case TYPE_CODE_INT: |
185 | case TYPE_CODE_BOOL: | |
186 | case TYPE_CODE_CHAR: | |
187 | case TYPE_CODE_ENUM: | |
188 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
189 | /* We have byte, half-word, word and extended-word/doubleword |
190 | integral types. The doubleword is an extension to the | |
191 | original 32-bit ABI by the SCD 2.4.x. */ | |
192 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
193 | case TYPE_CODE_PTR: |
194 | case TYPE_CODE_REF: | |
80ad1639 MK |
195 | /* Allow either 32-bit or 64-bit pointers. */ |
196 | return (len == 4 || len == 8); | |
386c036b MK |
197 | default: |
198 | break; | |
199 | } | |
c906108c | 200 | |
386c036b MK |
201 | return 0; |
202 | } | |
c906108c | 203 | |
386c036b | 204 | /* Check whether TYPE is "Floating". */ |
c906108c | 205 | |
386c036b MK |
206 | static int |
207 | sparc_floating_p (const struct type *type) | |
208 | { | |
209 | switch (TYPE_CODE (type)) | |
c906108c | 210 | { |
386c036b MK |
211 | case TYPE_CODE_FLT: |
212 | { | |
213 | int len = TYPE_LENGTH (type); | |
214 | return (len == 4 || len == 8 || len == 16); | |
215 | } | |
216 | default: | |
217 | break; | |
218 | } | |
219 | ||
220 | return 0; | |
221 | } | |
c906108c | 222 | |
386c036b | 223 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 224 | |
386c036b MK |
225 | static int |
226 | sparc_structure_or_union_p (const struct type *type) | |
227 | { | |
228 | switch (TYPE_CODE (type)) | |
229 | { | |
230 | case TYPE_CODE_STRUCT: | |
231 | case TYPE_CODE_UNION: | |
232 | return 1; | |
233 | default: | |
234 | break; | |
c906108c | 235 | } |
386c036b MK |
236 | |
237 | return 0; | |
c906108c | 238 | } |
386c036b MK |
239 | |
240 | /* Register information. */ | |
241 | ||
242 | static const char *sparc32_register_names[] = | |
5af923b0 | 243 | { |
386c036b MK |
244 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
245 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
246 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
247 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
248 | ||
249 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
250 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
251 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
252 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
253 | ||
254 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
255 | }; |
256 | ||
386c036b MK |
257 | /* Total number of registers. */ |
258 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 259 | |
386c036b MK |
260 | /* We provide the aliases %d0..%d30 for the floating registers as |
261 | "psuedo" registers. */ | |
262 | ||
263 | static const char *sparc32_pseudo_register_names[] = | |
264 | { | |
265 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
266 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
267 | }; | |
268 | ||
269 | /* Total number of pseudo registers. */ | |
270 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
271 | ||
272 | /* Return the name of register REGNUM. */ | |
273 | ||
274 | static const char * | |
d93859e2 | 275 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
276 | { |
277 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
278 | return sparc32_register_names[regnum]; | |
279 | ||
280 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
281 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
282 | ||
283 | return NULL; | |
284 | } | |
2d457077 | 285 | \f |
209bd28e | 286 | /* Construct types for ISA-specific registers. */ |
2d457077 | 287 | |
209bd28e UW |
288 | static struct type * |
289 | sparc_psr_type (struct gdbarch *gdbarch) | |
290 | { | |
291 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 292 | |
209bd28e UW |
293 | if (!tdep->sparc_psr_type) |
294 | { | |
295 | struct type *type; | |
2d457077 | 296 | |
e9bb382b | 297 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
298 | append_flags_type_flag (type, 5, "ET"); |
299 | append_flags_type_flag (type, 6, "PS"); | |
300 | append_flags_type_flag (type, 7, "S"); | |
301 | append_flags_type_flag (type, 12, "EF"); | |
302 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 303 | |
209bd28e UW |
304 | tdep->sparc_psr_type = type; |
305 | } | |
306 | ||
307 | return tdep->sparc_psr_type; | |
308 | } | |
309 | ||
310 | static struct type * | |
311 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 312 | { |
209bd28e UW |
313 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
314 | ||
315 | if (!tdep->sparc_fsr_type) | |
316 | { | |
317 | struct type *type; | |
318 | ||
e9bb382b | 319 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
320 | append_flags_type_flag (type, 0, "NXA"); |
321 | append_flags_type_flag (type, 1, "DZA"); | |
322 | append_flags_type_flag (type, 2, "UFA"); | |
323 | append_flags_type_flag (type, 3, "OFA"); | |
324 | append_flags_type_flag (type, 4, "NVA"); | |
325 | append_flags_type_flag (type, 5, "NXC"); | |
326 | append_flags_type_flag (type, 6, "DZC"); | |
327 | append_flags_type_flag (type, 7, "UFC"); | |
328 | append_flags_type_flag (type, 8, "OFC"); | |
329 | append_flags_type_flag (type, 9, "NVC"); | |
330 | append_flags_type_flag (type, 22, "NS"); | |
331 | append_flags_type_flag (type, 23, "NXM"); | |
332 | append_flags_type_flag (type, 24, "DZM"); | |
333 | append_flags_type_flag (type, 25, "UFM"); | |
334 | append_flags_type_flag (type, 26, "OFM"); | |
335 | append_flags_type_flag (type, 27, "NVM"); | |
336 | ||
337 | tdep->sparc_fsr_type = type; | |
338 | } | |
339 | ||
340 | return tdep->sparc_fsr_type; | |
2d457077 | 341 | } |
386c036b MK |
342 | |
343 | /* Return the GDB type object for the "standard" data type of data in | |
344 | register REGNUM. */ | |
345 | ||
346 | static struct type * | |
347 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
348 | { | |
349 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 350 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
351 | |
352 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 353 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
354 | |
355 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 356 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
357 | |
358 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 359 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 360 | |
2d457077 | 361 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 362 | return sparc_psr_type (gdbarch); |
2d457077 MK |
363 | |
364 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 365 | return sparc_fsr_type (gdbarch); |
2d457077 | 366 | |
df4df182 | 367 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
368 | } |
369 | ||
370 | static void | |
371 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
372 | struct regcache *regcache, | |
e1613aba | 373 | int regnum, gdb_byte *buf) |
386c036b MK |
374 | { |
375 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
376 | ||
377 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
378 | regcache_raw_read (regcache, regnum, buf); | |
e1613aba | 379 | regcache_raw_read (regcache, regnum + 1, buf + 4); |
386c036b MK |
380 | } |
381 | ||
382 | static void | |
383 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
384 | struct regcache *regcache, | |
e1613aba | 385 | int regnum, const gdb_byte *buf) |
386c036b MK |
386 | { |
387 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
388 | ||
389 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
390 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 391 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
392 | } |
393 | \f | |
394 | ||
395 | static CORE_ADDR | |
396 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 397 | CORE_ADDR funcaddr, |
386c036b MK |
398 | struct value **args, int nargs, |
399 | struct type *value_type, | |
e4fd649a UW |
400 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
401 | struct regcache *regcache) | |
c906108c | 402 | { |
386c036b MK |
403 | *bp_addr = sp - 4; |
404 | *real_pc = funcaddr; | |
405 | ||
d80b854b | 406 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 407 | { |
e1613aba | 408 | gdb_byte buf[4]; |
386c036b MK |
409 | |
410 | /* This is an UNIMP instruction. */ | |
411 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
412 | write_memory (sp - 8, buf, 4); | |
413 | return sp - 8; | |
c906108c SS |
414 | } |
415 | ||
386c036b MK |
416 | return sp - 4; |
417 | } | |
418 | ||
419 | static CORE_ADDR | |
420 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
421 | struct value **args, CORE_ADDR sp, | |
422 | int struct_return, CORE_ADDR struct_addr) | |
423 | { | |
df4df182 | 424 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
386c036b MK |
425 | /* Number of words in the "parameter array". */ |
426 | int num_elements = 0; | |
427 | int element = 0; | |
428 | int i; | |
429 | ||
430 | for (i = 0; i < nargs; i++) | |
c906108c | 431 | { |
4991999e | 432 | struct type *type = value_type (args[i]); |
386c036b MK |
433 | int len = TYPE_LENGTH (type); |
434 | ||
435 | if (sparc_structure_or_union_p (type) | |
436 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 437 | { |
386c036b MK |
438 | /* Structure, Union and Quad-Precision Arguments. */ |
439 | sp -= len; | |
440 | ||
441 | /* Use doubleword alignment for these values. That's always | |
442 | correct, and wasting a few bytes shouldn't be a problem. */ | |
443 | sp &= ~0x7; | |
444 | ||
0fd88904 | 445 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
446 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
447 | num_elements++; | |
448 | } | |
449 | else if (sparc_floating_p (type)) | |
450 | { | |
451 | /* Floating arguments. */ | |
452 | gdb_assert (len == 4 || len == 8); | |
453 | num_elements += (len / 4); | |
c906108c | 454 | } |
c5aa993b JM |
455 | else |
456 | { | |
386c036b MK |
457 | /* Integral and pointer arguments. */ |
458 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
459 | ||
460 | if (len < 4) | |
df4df182 UW |
461 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
462 | args[i]); | |
386c036b | 463 | num_elements += ((len + 3) / 4); |
c5aa993b | 464 | } |
c906108c | 465 | } |
c906108c | 466 | |
386c036b MK |
467 | /* Always allocate at least six words. */ |
468 | sp -= max (6, num_elements) * 4; | |
c906108c | 469 | |
386c036b MK |
470 | /* The psABI says that "Software convention requires space for the |
471 | struct/union return value pointer, even if the word is unused." */ | |
472 | sp -= 4; | |
c906108c | 473 | |
386c036b MK |
474 | /* The psABI says that "Although software convention and the |
475 | operating system require every stack frame to be doubleword | |
476 | aligned." */ | |
477 | sp &= ~0x7; | |
c906108c | 478 | |
386c036b | 479 | for (i = 0; i < nargs; i++) |
c906108c | 480 | { |
0fd88904 | 481 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 482 | struct type *type = value_type (args[i]); |
386c036b | 483 | int len = TYPE_LENGTH (type); |
c906108c | 484 | |
386c036b | 485 | gdb_assert (len == 4 || len == 8); |
c906108c | 486 | |
386c036b MK |
487 | if (element < 6) |
488 | { | |
489 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 490 | |
386c036b MK |
491 | regcache_cooked_write (regcache, regnum, valbuf); |
492 | if (len > 4 && element < 5) | |
493 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
494 | } | |
5af923b0 | 495 | |
386c036b MK |
496 | /* Always store the argument in memory. */ |
497 | write_memory (sp + 4 + element * 4, valbuf, len); | |
498 | element += len / 4; | |
499 | } | |
c906108c | 500 | |
386c036b | 501 | gdb_assert (element == num_elements); |
c906108c | 502 | |
386c036b | 503 | if (struct_return) |
c906108c | 504 | { |
e1613aba | 505 | gdb_byte buf[4]; |
c906108c | 506 | |
386c036b MK |
507 | store_unsigned_integer (buf, 4, struct_addr); |
508 | write_memory (sp, buf, 4); | |
509 | } | |
c906108c | 510 | |
386c036b | 511 | return sp; |
c906108c SS |
512 | } |
513 | ||
386c036b | 514 | static CORE_ADDR |
7d9b040b | 515 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
516 | struct regcache *regcache, CORE_ADDR bp_addr, |
517 | int nargs, struct value **args, CORE_ADDR sp, | |
518 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 519 | { |
386c036b MK |
520 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
521 | ||
522 | /* Set return address. */ | |
523 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
524 | ||
525 | /* Set up function arguments. */ | |
526 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
527 | struct_return, struct_addr); | |
528 | ||
529 | /* Allocate the 16-word window save area. */ | |
530 | sp -= 16 * 4; | |
c906108c | 531 | |
386c036b MK |
532 | /* Stack should be doubleword aligned at this point. */ |
533 | gdb_assert (sp % 8 == 0); | |
c906108c | 534 | |
386c036b MK |
535 | /* Finally, update the stack pointer. */ |
536 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
537 | ||
538 | return sp; | |
539 | } | |
540 | \f | |
c906108c | 541 | |
386c036b MK |
542 | /* Use the program counter to determine the contents and size of a |
543 | breakpoint instruction. Return a pointer to a string of bytes that | |
544 | encode a breakpoint instruction, store the length of the string in | |
545 | *LEN and optionally adjust *PC to point to the correct memory | |
546 | location for inserting the breakpoint. */ | |
547 | ||
e1613aba | 548 | static const gdb_byte * |
67d57894 | 549 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 550 | { |
864a1a37 | 551 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 552 | |
386c036b MK |
553 | *len = sizeof (break_insn); |
554 | return break_insn; | |
c906108c | 555 | } |
386c036b | 556 | \f |
c906108c | 557 | |
386c036b | 558 | /* Allocate and initialize a frame cache. */ |
c906108c | 559 | |
386c036b MK |
560 | static struct sparc_frame_cache * |
561 | sparc_alloc_frame_cache (void) | |
562 | { | |
563 | struct sparc_frame_cache *cache; | |
564 | int i; | |
c906108c | 565 | |
386c036b | 566 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 567 | |
386c036b MK |
568 | /* Base address. */ |
569 | cache->base = 0; | |
570 | cache->pc = 0; | |
c906108c | 571 | |
386c036b MK |
572 | /* Frameless until proven otherwise. */ |
573 | cache->frameless_p = 1; | |
574 | ||
575 | cache->struct_return_p = 0; | |
576 | ||
577 | return cache; | |
578 | } | |
579 | ||
b0b92586 JB |
580 | /* GCC generates several well-known sequences of instructions at the begining |
581 | of each function prologue when compiling with -fstack-check. If one of | |
582 | such sequences starts at START_PC, then return the address of the | |
583 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
584 | ||
585 | static CORE_ADDR | |
586 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
587 | { | |
588 | CORE_ADDR pc = start_pc; | |
589 | unsigned long insn; | |
590 | int offset_stack_checking_sequence = 0; | |
591 | ||
592 | /* With GCC, all stack checking sequences begin with the same two | |
593 | instructions. */ | |
594 | ||
595 | /* sethi <some immediate>,%g1 */ | |
596 | insn = sparc_fetch_instruction (pc); | |
597 | pc = pc + 4; | |
598 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
599 | return start_pc; | |
600 | ||
601 | /* sub %sp, %g1, %g1 */ | |
602 | insn = sparc_fetch_instruction (pc); | |
603 | pc = pc + 4; | |
604 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
605 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
606 | return start_pc; | |
607 | ||
608 | insn = sparc_fetch_instruction (pc); | |
609 | pc = pc + 4; | |
610 | ||
611 | /* First possible sequence: | |
612 | [first two instructions above] | |
613 | clr [%g1 - some immediate] */ | |
614 | ||
615 | /* clr [%g1 - some immediate] */ | |
616 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
617 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
618 | { | |
619 | /* Valid stack-check sequence, return the new PC. */ | |
620 | return pc; | |
621 | } | |
622 | ||
623 | /* Second possible sequence: A small number of probes. | |
624 | [first two instructions above] | |
625 | clr [%g1] | |
626 | add %g1, -<some immediate>, %g1 | |
627 | clr [%g1] | |
628 | [repeat the two instructions above any (small) number of times] | |
629 | clr [%g1 - some immediate] */ | |
630 | ||
631 | /* clr [%g1] */ | |
632 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
633 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
634 | { | |
635 | while (1) | |
636 | { | |
637 | /* add %g1, -<some immediate>, %g1 */ | |
638 | insn = sparc_fetch_instruction (pc); | |
639 | pc = pc + 4; | |
640 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
641 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
642 | break; | |
643 | ||
644 | /* clr [%g1] */ | |
645 | insn = sparc_fetch_instruction (pc); | |
646 | pc = pc + 4; | |
647 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
648 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
649 | return start_pc; | |
650 | } | |
651 | ||
652 | /* clr [%g1 - some immediate] */ | |
653 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
654 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
655 | return start_pc; | |
656 | ||
657 | /* We found a valid stack-check sequence, return the new PC. */ | |
658 | return pc; | |
659 | } | |
660 | ||
661 | /* Third sequence: A probing loop. | |
662 | [first two instructions above] | |
663 | sethi <some immediate>, %g4 | |
664 | sub %g1, %g4, %g4 | |
665 | cmp %g1, %g4 | |
666 | be <disp> | |
667 | add %g1, -<some immediate>, %g1 | |
668 | ba <disp> | |
669 | clr [%g1] | |
670 | clr [%g4 - some immediate] */ | |
671 | ||
672 | /* sethi <some immediate>, %g4 */ | |
673 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
674 | { | |
675 | /* sub %g1, %g4, %g4 */ | |
676 | insn = sparc_fetch_instruction (pc); | |
677 | pc = pc + 4; | |
678 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
679 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
680 | return start_pc; | |
681 | ||
682 | /* cmp %g1, %g4 */ | |
683 | insn = sparc_fetch_instruction (pc); | |
684 | pc = pc + 4; | |
685 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
686 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
687 | return start_pc; | |
688 | ||
689 | /* be <disp> */ | |
690 | insn = sparc_fetch_instruction (pc); | |
691 | pc = pc + 4; | |
692 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
693 | return start_pc; | |
694 | ||
695 | /* add %g1, -<some immediate>, %g1 */ | |
696 | insn = sparc_fetch_instruction (pc); | |
697 | pc = pc + 4; | |
698 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
699 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
700 | return start_pc; | |
701 | ||
702 | /* ba <disp> */ | |
703 | insn = sparc_fetch_instruction (pc); | |
704 | pc = pc + 4; | |
705 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
706 | return start_pc; | |
707 | ||
708 | /* clr [%g1] */ | |
709 | insn = sparc_fetch_instruction (pc); | |
710 | pc = pc + 4; | |
711 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
712 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
713 | return start_pc; | |
714 | ||
715 | /* clr [%g4 - some immediate] */ | |
716 | insn = sparc_fetch_instruction (pc); | |
717 | pc = pc + 4; | |
718 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
719 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
720 | return start_pc; | |
721 | ||
722 | /* We found a valid stack-check sequence, return the new PC. */ | |
723 | return pc; | |
724 | } | |
725 | ||
726 | /* No stack check code in our prologue, return the start_pc. */ | |
727 | return start_pc; | |
728 | } | |
729 | ||
386c036b | 730 | CORE_ADDR |
be8626e0 MD |
731 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
732 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 733 | { |
be8626e0 | 734 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
735 | unsigned long insn; |
736 | int offset = 0; | |
c906108c | 737 | int dest = -1; |
c906108c | 738 | |
b0b92586 JB |
739 | pc = sparc_skip_stack_check (pc); |
740 | ||
386c036b MK |
741 | if (current_pc <= pc) |
742 | return current_pc; | |
743 | ||
744 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
745 | SPARC the linker usually defines a symbol (typically | |
746 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
747 | This symbol makes us end up here with PC pointing at the start of | |
748 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
749 | would do our normal prologue analysis, we would probably conclude | |
750 | that we've got a frame when in reality we don't, since the | |
751 | dynamic linker patches up the first PLT with some code that | |
752 | starts with a SAVE instruction. Patch up PC such that it points | |
753 | at the start of our PLT entry. */ | |
754 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
755 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 756 | |
386c036b MK |
757 | insn = sparc_fetch_instruction (pc); |
758 | ||
759 | /* Recognize a SETHI insn and record its destination. */ | |
760 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
761 | { |
762 | dest = X_RD (insn); | |
386c036b MK |
763 | offset += 4; |
764 | ||
765 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
766 | } |
767 | ||
386c036b MK |
768 | /* Allow for an arithmetic operation on DEST or %g1. */ |
769 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
770 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
771 | { | |
386c036b | 772 | offset += 4; |
c906108c | 773 | |
386c036b | 774 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 775 | } |
c906108c | 776 | |
386c036b MK |
777 | /* Check for the SAVE instruction that sets up the frame. */ |
778 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 779 | { |
386c036b MK |
780 | cache->frameless_p = 0; |
781 | return pc + offset + 4; | |
c906108c SS |
782 | } |
783 | ||
784 | return pc; | |
785 | } | |
786 | ||
386c036b | 787 | static CORE_ADDR |
236369e7 | 788 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
789 | { |
790 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 791 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
792 | } |
793 | ||
794 | /* Return PC of first real instruction of the function starting at | |
795 | START_PC. */ | |
f510d44e | 796 | |
386c036b | 797 | static CORE_ADDR |
6093d2eb | 798 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 799 | { |
f510d44e DM |
800 | struct symtab_and_line sal; |
801 | CORE_ADDR func_start, func_end; | |
386c036b | 802 | struct sparc_frame_cache cache; |
f510d44e DM |
803 | |
804 | /* This is the preferred method, find the end of the prologue by | |
805 | using the debugging information. */ | |
806 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
807 | { | |
808 | sal = find_pc_line (func_start, 0); | |
809 | ||
810 | if (sal.end < func_end | |
811 | && start_pc <= sal.end) | |
812 | return sal.end; | |
813 | } | |
814 | ||
be8626e0 | 815 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
816 | |
817 | /* The psABI says that "Although the first 6 words of arguments | |
818 | reside in registers, the standard stack frame reserves space for | |
819 | them.". It also suggests that a function may use that space to | |
820 | "write incoming arguments 0 to 5" into that space, and that's | |
821 | indeed what GCC seems to be doing. In that case GCC will | |
822 | generate debug information that points to the stack slots instead | |
823 | of the registers, so we should consider the instructions that | |
824 | write out these incoming arguments onto the stack. Of course we | |
825 | only need to do this if we have a stack frame. */ | |
826 | ||
827 | while (!cache.frameless_p) | |
828 | { | |
829 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
830 | ||
831 | /* Recognize instructions that store incoming arguments in | |
832 | %i0...%i5 into the corresponding stack slot. */ | |
833 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) | |
834 | && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30 | |
835 | && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4) | |
836 | { | |
837 | start_pc += 4; | |
838 | continue; | |
839 | } | |
840 | ||
841 | break; | |
842 | } | |
843 | ||
844 | return start_pc; | |
c906108c SS |
845 | } |
846 | ||
386c036b | 847 | /* Normal frames. */ |
9319a2fe | 848 | |
386c036b | 849 | struct sparc_frame_cache * |
236369e7 | 850 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 851 | { |
386c036b | 852 | struct sparc_frame_cache *cache; |
9319a2fe | 853 | |
386c036b MK |
854 | if (*this_cache) |
855 | return *this_cache; | |
c906108c | 856 | |
386c036b MK |
857 | cache = sparc_alloc_frame_cache (); |
858 | *this_cache = cache; | |
c906108c | 859 | |
236369e7 | 860 | cache->pc = get_frame_func (this_frame); |
386c036b | 861 | if (cache->pc != 0) |
236369e7 JB |
862 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
863 | get_frame_pc (this_frame), cache); | |
386c036b MK |
864 | |
865 | if (cache->frameless_p) | |
c906108c | 866 | { |
cbeae229 MK |
867 | /* This function is frameless, so %fp (%i6) holds the frame |
868 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
869 | base address. */ | |
870 | cache->base = | |
236369e7 | 871 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
872 | } |
873 | else | |
874 | { | |
875 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
876 | base address for the current stack frame. */ | |
877 | cache->base = | |
236369e7 | 878 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 879 | } |
c906108c | 880 | |
5b2d44a0 MK |
881 | if (cache->base & 1) |
882 | cache->base += BIAS; | |
883 | ||
386c036b | 884 | return cache; |
c906108c | 885 | } |
c906108c | 886 | |
aff37fc1 DM |
887 | static int |
888 | sparc32_struct_return_from_sym (struct symbol *sym) | |
889 | { | |
890 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
891 | enum type_code code = TYPE_CODE (type); | |
892 | ||
893 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
894 | { | |
895 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
896 | if (sparc_structure_or_union_p (type) | |
897 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
898 | return 1; | |
899 | } | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
386c036b | 904 | struct sparc_frame_cache * |
236369e7 | 905 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 906 | { |
386c036b MK |
907 | struct sparc_frame_cache *cache; |
908 | struct symbol *sym; | |
c906108c | 909 | |
386c036b MK |
910 | if (*this_cache) |
911 | return *this_cache; | |
c906108c | 912 | |
236369e7 | 913 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 914 | |
386c036b MK |
915 | sym = find_pc_function (cache->pc); |
916 | if (sym) | |
c906108c | 917 | { |
aff37fc1 | 918 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 919 | } |
5465445a JB |
920 | else |
921 | { | |
922 | /* There is no debugging information for this function to | |
923 | help us determine whether this function returns a struct | |
924 | or not. So we rely on another heuristic which is to check | |
925 | the instruction at the return address and see if this is | |
926 | an "unimp" instruction. If it is, then it is a struct-return | |
927 | function. */ | |
928 | CORE_ADDR pc; | |
929 | int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
930 | ||
236369e7 | 931 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
932 | if (sparc_is_unimp_insn (pc)) |
933 | cache->struct_return_p = 1; | |
934 | } | |
c906108c | 935 | |
386c036b MK |
936 | return cache; |
937 | } | |
938 | ||
939 | static void | |
236369e7 | 940 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
941 | struct frame_id *this_id) |
942 | { | |
943 | struct sparc_frame_cache *cache = | |
236369e7 | 944 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
945 | |
946 | /* This marks the outermost frame. */ | |
947 | if (cache->base == 0) | |
948 | return; | |
949 | ||
950 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
951 | } | |
c906108c | 952 | |
236369e7 JB |
953 | static struct value * |
954 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
955 | void **this_cache, int regnum) | |
386c036b MK |
956 | { |
957 | struct sparc_frame_cache *cache = | |
236369e7 | 958 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 959 | |
386c036b | 960 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 961 | { |
236369e7 | 962 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 963 | |
236369e7 JB |
964 | /* If this functions has a Structure, Union or Quad-Precision |
965 | return value, we have to skip the UNIMP instruction that encodes | |
966 | the size of the structure. */ | |
967 | if (cache->struct_return_p) | |
968 | pc += 4; | |
386c036b | 969 | |
236369e7 JB |
970 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; |
971 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; | |
972 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
973 | } |
974 | ||
42cdca6c MK |
975 | /* Handle StackGhost. */ |
976 | { | |
977 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
978 | ||
979 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
980 | { | |
236369e7 JB |
981 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
982 | ULONGEST i7; | |
983 | ||
984 | /* Read the value in from memory. */ | |
985 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
986 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
987 | } |
988 | } | |
989 | ||
386c036b MK |
990 | /* The previous frame's `local' and `in' registers have been saved |
991 | in the register save area. */ | |
992 | if (!cache->frameless_p | |
993 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 994 | { |
236369e7 | 995 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 996 | |
236369e7 | 997 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 998 | } |
c906108c | 999 | |
236369e7 | 1000 | /* The previous frame's `out' registers are accessible as the |
386c036b MK |
1001 | current frame's `in' registers. */ |
1002 | if (!cache->frameless_p | |
1003 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
1004 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 1005 | |
236369e7 | 1006 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1007 | } |
c906108c | 1008 | |
386c036b MK |
1009 | static const struct frame_unwind sparc32_frame_unwind = |
1010 | { | |
1011 | NORMAL_FRAME, | |
1012 | sparc32_frame_this_id, | |
236369e7 JB |
1013 | sparc32_frame_prev_register, |
1014 | NULL, | |
1015 | default_frame_sniffer | |
386c036b | 1016 | }; |
386c036b | 1017 | \f |
c906108c | 1018 | |
386c036b | 1019 | static CORE_ADDR |
236369e7 | 1020 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1021 | { |
1022 | struct sparc_frame_cache *cache = | |
236369e7 | 1023 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1024 | |
386c036b MK |
1025 | return cache->base; |
1026 | } | |
c906108c | 1027 | |
386c036b MK |
1028 | static const struct frame_base sparc32_frame_base = |
1029 | { | |
1030 | &sparc32_frame_unwind, | |
1031 | sparc32_frame_base_address, | |
1032 | sparc32_frame_base_address, | |
1033 | sparc32_frame_base_address | |
1034 | }; | |
c906108c | 1035 | |
386c036b | 1036 | static struct frame_id |
236369e7 | 1037 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1038 | { |
1039 | CORE_ADDR sp; | |
5af923b0 | 1040 | |
236369e7 | 1041 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1042 | if (sp & 1) |
1043 | sp += BIAS; | |
236369e7 | 1044 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1045 | } |
1046 | \f | |
c906108c | 1047 | |
3923a2b2 MK |
1048 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1049 | that into VALBUF. */ | |
5af923b0 | 1050 | |
386c036b MK |
1051 | static void |
1052 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1053 | gdb_byte *valbuf) |
386c036b MK |
1054 | { |
1055 | int len = TYPE_LENGTH (type); | |
e1613aba | 1056 | gdb_byte buf[8]; |
c906108c | 1057 | |
386c036b MK |
1058 | gdb_assert (!sparc_structure_or_union_p (type)); |
1059 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1060 | |
386c036b | 1061 | if (sparc_floating_p (type)) |
5af923b0 | 1062 | { |
386c036b MK |
1063 | /* Floating return values. */ |
1064 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1065 | if (len > 4) | |
1066 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
1067 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
1068 | } |
1069 | else | |
1070 | { | |
386c036b MK |
1071 | /* Integral and pointer return values. */ |
1072 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1073 | |
386c036b MK |
1074 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1075 | if (len > 4) | |
1076 | { | |
1077 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1078 | gdb_assert (len == 8); | |
1079 | memcpy (valbuf, buf, 8); | |
1080 | } | |
1081 | else | |
1082 | { | |
1083 | /* Just stripping off any unused bytes should preserve the | |
1084 | signed-ness just fine. */ | |
1085 | memcpy (valbuf, buf + 4 - len, len); | |
1086 | } | |
1087 | } | |
1088 | } | |
c906108c | 1089 | |
3923a2b2 MK |
1090 | /* Store the function return value of type TYPE from VALBUF into |
1091 | REGCACHE. */ | |
c906108c | 1092 | |
386c036b MK |
1093 | static void |
1094 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1095 | const gdb_byte *valbuf) |
386c036b MK |
1096 | { |
1097 | int len = TYPE_LENGTH (type); | |
e1613aba | 1098 | gdb_byte buf[8]; |
c906108c | 1099 | |
386c036b MK |
1100 | gdb_assert (!sparc_structure_or_union_p (type)); |
1101 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1102 | |
386c036b MK |
1103 | if (sparc_floating_p (type)) |
1104 | { | |
1105 | /* Floating return values. */ | |
1106 | memcpy (buf, valbuf, len); | |
1107 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1108 | if (len > 4) | |
1109 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
1110 | } | |
1111 | else | |
c906108c | 1112 | { |
386c036b MK |
1113 | /* Integral and pointer return values. */ |
1114 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1115 | ||
1116 | if (len > 4) | |
2757dd86 | 1117 | { |
386c036b MK |
1118 | gdb_assert (len == 8); |
1119 | memcpy (buf, valbuf, 8); | |
1120 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1121 | } |
1122 | else | |
1123 | { | |
386c036b MK |
1124 | /* ??? Do we need to do any sign-extension here? */ |
1125 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1126 | } |
386c036b | 1127 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1128 | } |
1129 | } | |
1130 | ||
b9d4c5ed | 1131 | static enum return_value_convention |
c055b101 CV |
1132 | sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1133 | struct type *type, struct regcache *regcache, | |
1134 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1135 | { |
0a8f48b9 MK |
1136 | /* The psABI says that "...every stack frame reserves the word at |
1137 | %fp+64. If a function returns a structure, union, or | |
1138 | quad-precision value, this word should hold the address of the | |
1139 | object into which the return value should be copied." This | |
1140 | guarantees that we can always find the return value, not just | |
1141 | before the function returns. */ | |
1142 | ||
b9d4c5ed MK |
1143 | if (sparc_structure_or_union_p (type) |
1144 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1145 | { |
1146 | if (readbuf) | |
1147 | { | |
1148 | ULONGEST sp; | |
1149 | CORE_ADDR addr; | |
1150 | ||
1151 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1152 | addr = read_memory_unsigned_integer (sp + 64, 4); | |
1153 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1154 | } | |
1155 | ||
1156 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1157 | } | |
b9d4c5ed MK |
1158 | |
1159 | if (readbuf) | |
1160 | sparc32_extract_return_value (type, regcache, readbuf); | |
1161 | if (writebuf) | |
1162 | sparc32_store_return_value (type, regcache, writebuf); | |
1163 | ||
1164 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1165 | } | |
1166 | ||
386c036b MK |
1167 | static int |
1168 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1169 | { |
386c036b MK |
1170 | return (sparc_structure_or_union_p (type) |
1171 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1172 | } | |
c906108c | 1173 | |
aff37fc1 | 1174 | static int |
4a4e5149 | 1175 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1176 | { |
236369e7 | 1177 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1178 | struct symbol *sym = find_pc_function (pc); |
1179 | ||
1180 | if (sym) | |
1181 | return sparc32_struct_return_from_sym (sym); | |
1182 | return 0; | |
1183 | } | |
1184 | ||
f5a9b87d DM |
1185 | static void |
1186 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1187 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1188 | struct frame_info *this_frame) |
f5a9b87d | 1189 | { |
aff37fc1 DM |
1190 | int off; |
1191 | ||
f5a9b87d DM |
1192 | switch (regnum) |
1193 | { | |
1194 | case SPARC_G0_REGNUM: | |
1195 | /* Since %g0 is always zero, there is no point in saving it, and | |
1196 | people will be inclined omit it from the CFI. Make sure we | |
1197 | don't warn about that. */ | |
1198 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1199 | break; | |
1200 | case SPARC_SP_REGNUM: | |
1201 | reg->how = DWARF2_FRAME_REG_CFA; | |
1202 | break; | |
1203 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1204 | case SPARC32_NPC_REGNUM: |
1205 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1206 | off = 8; |
4a4e5149 | 1207 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1208 | off += 4; |
1209 | if (regnum == SPARC32_NPC_REGNUM) | |
1210 | off += 4; | |
1211 | reg->loc.offset = off; | |
f5a9b87d DM |
1212 | break; |
1213 | } | |
1214 | } | |
1215 | ||
386c036b MK |
1216 | \f |
1217 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1218 | and most operating systems don't implement it either, so we provide | |
1219 | software single-step mechanism. */ | |
c906108c | 1220 | |
386c036b | 1221 | static CORE_ADDR |
0b1b3e42 | 1222 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1223 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1224 | { |
1225 | unsigned long insn = sparc_fetch_instruction (pc); | |
1226 | int conditional_p = X_COND (insn) & 0x7; | |
1227 | int branch_p = 0; | |
1228 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1229 | |
386c036b | 1230 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1231 | { |
386c036b MK |
1232 | /* Branch on Integer Register with Prediction (BPr). */ |
1233 | branch_p = 1; | |
1234 | conditional_p = 1; | |
c906108c | 1235 | } |
386c036b | 1236 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1237 | { |
386c036b MK |
1238 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1239 | branch_p = 1; | |
1240 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1241 | } |
386c036b MK |
1242 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1243 | { | |
1244 | /* Branch on Floating-Point Condition Codes with Prediction | |
1245 | (FBPfcc). */ | |
1246 | branch_p = 1; | |
1247 | offset = 4 * X_DISP19 (insn); | |
1248 | } | |
1249 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1250 | { | |
1251 | /* Branch on Integer Condition Codes (Bicc). */ | |
1252 | branch_p = 1; | |
1253 | offset = 4 * X_DISP22 (insn); | |
1254 | } | |
1255 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1256 | { |
386c036b MK |
1257 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1258 | branch_p = 1; | |
1259 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1260 | } |
c893be75 MK |
1261 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1262 | { | |
1263 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1264 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1265 | } |
386c036b MK |
1266 | |
1267 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1268 | ||
386c036b | 1269 | if (branch_p) |
c906108c | 1270 | { |
386c036b | 1271 | if (conditional_p) |
c906108c | 1272 | { |
386c036b MK |
1273 | /* For conditional branches, return nPC + 4 iff the annul |
1274 | bit is 1. */ | |
1275 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1276 | } |
1277 | else | |
1278 | { | |
386c036b MK |
1279 | /* For unconditional branches, return the target if its |
1280 | specified condition is "always" and return nPC + 4 if the | |
1281 | condition is "never". If the annul bit is 1, set *NPC to | |
1282 | zero. */ | |
1283 | if (X_COND (insn) == 0x0) | |
1284 | pc = *npc, offset = 4; | |
1285 | if (X_A (insn)) | |
1286 | *npc = 0; | |
1287 | ||
1288 | gdb_assert (offset != 0); | |
1289 | return pc + offset; | |
c906108c SS |
1290 | } |
1291 | } | |
386c036b MK |
1292 | |
1293 | return 0; | |
c906108c SS |
1294 | } |
1295 | ||
c893be75 | 1296 | static CORE_ADDR |
0b1b3e42 | 1297 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1298 | { |
1299 | return 0; | |
1300 | } | |
1301 | ||
e6590a1b | 1302 | int |
0b1b3e42 | 1303 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1304 | { |
0b1b3e42 | 1305 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1306 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1307 | CORE_ADDR npc, nnpc; |
c906108c | 1308 | |
e0cd558a | 1309 | CORE_ADDR pc, orig_npc; |
c906108c | 1310 | |
0b1b3e42 UW |
1311 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1312 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1313 | |
e0cd558a | 1314 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1315 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1316 | if (npc != 0) |
a6d9a66e | 1317 | insert_single_step_breakpoint (arch, npc); |
8181d85f | 1318 | |
e0cd558a | 1319 | if (nnpc != 0) |
a6d9a66e | 1320 | insert_single_step_breakpoint (arch, nnpc); |
c906108c | 1321 | |
e0cd558a UW |
1322 | /* Assert that we have set at least one breakpoint, and that |
1323 | they're not set at the same spot - unless we're going | |
1324 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1325 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1326 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1327 | |
1328 | return 1; | |
386c036b MK |
1329 | } |
1330 | ||
1331 | static void | |
61a1198a | 1332 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1333 | { |
61a1198a | 1334 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1335 | |
61a1198a UW |
1336 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1337 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1338 | } |
1339 | \f | |
5af923b0 | 1340 | |
a54124c5 MK |
1341 | /* Return the appropriate register set for the core section identified |
1342 | by SECT_NAME and SECT_SIZE. */ | |
1343 | ||
63807e1d | 1344 | static const struct regset * |
a54124c5 MK |
1345 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1346 | const char *sect_name, size_t sect_size) | |
1347 | { | |
1348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1349 | ||
c558d81a | 1350 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1351 | return tdep->gregset; |
1352 | ||
c558d81a | 1353 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1354 | return tdep->fpregset; |
1355 | ||
1356 | return NULL; | |
1357 | } | |
1358 | \f | |
1359 | ||
386c036b MK |
1360 | static struct gdbarch * |
1361 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1362 | { | |
1363 | struct gdbarch_tdep *tdep; | |
1364 | struct gdbarch *gdbarch; | |
c906108c | 1365 | |
386c036b MK |
1366 | /* If there is already a candidate, use it. */ |
1367 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1368 | if (arches != NULL) | |
1369 | return arches->gdbarch; | |
c906108c | 1370 | |
386c036b MK |
1371 | /* Allocate space for the new architecture. */ |
1372 | tdep = XMALLOC (struct gdbarch_tdep); | |
1373 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1374 | |
386c036b MK |
1375 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1376 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1377 | tdep->gregset = NULL; |
c558d81a | 1378 | tdep->sizeof_gregset = 0; |
a54124c5 | 1379 | tdep->fpregset = NULL; |
c558d81a | 1380 | tdep->sizeof_fpregset = 0; |
386c036b | 1381 | tdep->plt_entry_size = 0; |
c893be75 | 1382 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1383 | |
1384 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1385 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1386 | |
1387 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1388 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1389 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1390 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1391 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1392 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1393 | ||
1394 | /* Register numbers of various important registers. */ | |
1395 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1396 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1397 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1398 | ||
1399 | /* Call dummy code. */ | |
1400 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1401 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1402 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1403 | ||
b9d4c5ed | 1404 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1405 | set_gdbarch_stabs_argument_has_addr |
1406 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1407 | ||
1408 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1409 | ||
1410 | /* Stack grows downward. */ | |
1411 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1412 | |
386c036b | 1413 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1414 | |
386c036b | 1415 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1416 | |
386c036b | 1417 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1418 | |
386c036b MK |
1419 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1420 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1421 | |
236369e7 | 1422 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1423 | |
386c036b | 1424 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1425 | |
386c036b MK |
1426 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1427 | ||
f5a9b87d DM |
1428 | /* Hook in the DWARF CFI frame unwinder. */ |
1429 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1430 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1431 | StackGhost issues have been resolved. */ | |
1432 | ||
b2a0b9b2 DM |
1433 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1434 | gdbarch_init_osabi (info, gdbarch); | |
1435 | ||
236369e7 | 1436 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1437 | |
a54124c5 | 1438 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1439 | if (tdep->gregset) |
a54124c5 MK |
1440 | set_gdbarch_regset_from_core_section (gdbarch, |
1441 | sparc_regset_from_core_section); | |
1442 | ||
386c036b MK |
1443 | return gdbarch; |
1444 | } | |
1445 | \f | |
1446 | /* Helper functions for dealing with register windows. */ | |
1447 | ||
1448 | void | |
1449 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1450 | { |
386c036b | 1451 | int offset = 0; |
e1613aba | 1452 | gdb_byte buf[8]; |
386c036b MK |
1453 | int i; |
1454 | ||
1455 | if (sp & 1) | |
1456 | { | |
1457 | /* Registers are 64-bit. */ | |
1458 | sp += BIAS; | |
c906108c | 1459 | |
386c036b MK |
1460 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1461 | { | |
1462 | if (regnum == i || regnum == -1) | |
1463 | { | |
1464 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1465 | |
1466 | /* Handle StackGhost. */ | |
1467 | if (i == SPARC_I7_REGNUM) | |
1468 | { | |
1469 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1470 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1471 | ||
1472 | store_unsigned_integer (buf + offset, 8, i7 ^ wcookie); | |
1473 | } | |
1474 | ||
386c036b MK |
1475 | regcache_raw_supply (regcache, i, buf); |
1476 | } | |
1477 | } | |
1478 | } | |
1479 | else | |
c906108c | 1480 | { |
386c036b MK |
1481 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1482 | pointer. */ | |
1483 | sp &= 0xffffffffUL; | |
c906108c | 1484 | |
386c036b MK |
1485 | /* Clear out the top half of the temporary buffer, and put the |
1486 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1487 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1488 | { |
386c036b MK |
1489 | memset (buf, 0, 4); |
1490 | offset = 4; | |
1491 | } | |
c906108c | 1492 | |
386c036b MK |
1493 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1494 | { | |
1495 | if (regnum == i || regnum == -1) | |
1496 | { | |
1497 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1498 | buf + offset, 4); | |
42cdca6c MK |
1499 | |
1500 | /* Handle StackGhost. */ | |
1501 | if (i == SPARC_I7_REGNUM) | |
1502 | { | |
1503 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1504 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1505 | |
7d34766b | 1506 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1507 | } |
1508 | ||
386c036b MK |
1509 | regcache_raw_supply (regcache, i, buf); |
1510 | } | |
c906108c SS |
1511 | } |
1512 | } | |
c906108c | 1513 | } |
c906108c SS |
1514 | |
1515 | void | |
386c036b MK |
1516 | sparc_collect_rwindow (const struct regcache *regcache, |
1517 | CORE_ADDR sp, int regnum) | |
c906108c | 1518 | { |
386c036b | 1519 | int offset = 0; |
e1613aba | 1520 | gdb_byte buf[8]; |
386c036b | 1521 | int i; |
5af923b0 | 1522 | |
386c036b | 1523 | if (sp & 1) |
5af923b0 | 1524 | { |
386c036b MK |
1525 | /* Registers are 64-bit. */ |
1526 | sp += BIAS; | |
c906108c | 1527 | |
386c036b MK |
1528 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1529 | { | |
1530 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1531 | { | |
1532 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1533 | |
1534 | /* Handle StackGhost. */ | |
1535 | if (i == SPARC_I7_REGNUM) | |
1536 | { | |
1537 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1538 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1539 | ||
1540 | store_unsigned_integer (buf, 8, i7 ^ wcookie); | |
1541 | } | |
1542 | ||
386c036b MK |
1543 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1544 | } | |
1545 | } | |
5af923b0 MS |
1546 | } |
1547 | else | |
1548 | { | |
386c036b MK |
1549 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1550 | pointer. */ | |
1551 | sp &= 0xffffffffUL; | |
1552 | ||
1553 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1554 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1555 | offset = 4; |
1556 | ||
1557 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1558 | { | |
1559 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1560 | { | |
1561 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1562 | |
1563 | /* Handle StackGhost. */ | |
1564 | if (i == SPARC_I7_REGNUM) | |
1565 | { | |
1566 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1567 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1568 | |
7d34766b | 1569 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1570 | } |
1571 | ||
386c036b MK |
1572 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1573 | buf + offset, 4); | |
1574 | } | |
1575 | } | |
5af923b0 | 1576 | } |
c906108c SS |
1577 | } |
1578 | ||
386c036b MK |
1579 | /* Helper functions for dealing with register sets. */ |
1580 | ||
c906108c | 1581 | void |
386c036b MK |
1582 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1583 | struct regcache *regcache, | |
1584 | int regnum, const void *gregs) | |
c906108c | 1585 | { |
e1613aba | 1586 | const gdb_byte *regs = gregs; |
386c036b | 1587 | int i; |
5af923b0 | 1588 | |
386c036b MK |
1589 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1590 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1591 | regs + gregset->r_psr_offset); | |
c906108c | 1592 | |
386c036b MK |
1593 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1594 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1595 | regs + gregset->r_pc_offset); | |
5af923b0 | 1596 | |
386c036b MK |
1597 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1598 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1599 | regs + gregset->r_npc_offset); | |
5af923b0 | 1600 | |
386c036b MK |
1601 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1602 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1603 | regs + gregset->r_y_offset); | |
5af923b0 | 1604 | |
386c036b MK |
1605 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1606 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1607 | |
386c036b | 1608 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1609 | { |
386c036b MK |
1610 | int offset = gregset->r_g1_offset; |
1611 | ||
1612 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1613 | { | |
1614 | if (regnum == i || regnum == -1) | |
1615 | regcache_raw_supply (regcache, i, regs + offset); | |
1616 | offset += 4; | |
1617 | } | |
c906108c | 1618 | } |
386c036b MK |
1619 | |
1620 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1621 | { |
386c036b MK |
1622 | /* Not all of the register set variants include Locals and |
1623 | Inputs. For those that don't, we read them off the stack. */ | |
1624 | if (gregset->r_l0_offset == -1) | |
1625 | { | |
1626 | ULONGEST sp; | |
1627 | ||
1628 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1629 | sparc_supply_rwindow (regcache, sp, regnum); | |
1630 | } | |
1631 | else | |
1632 | { | |
1633 | int offset = gregset->r_l0_offset; | |
1634 | ||
1635 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1636 | { | |
1637 | if (regnum == i || regnum == -1) | |
1638 | regcache_raw_supply (regcache, i, regs + offset); | |
1639 | offset += 4; | |
1640 | } | |
1641 | } | |
c906108c SS |
1642 | } |
1643 | } | |
1644 | ||
c5aa993b | 1645 | void |
386c036b MK |
1646 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1647 | const struct regcache *regcache, | |
1648 | int regnum, void *gregs) | |
c906108c | 1649 | { |
e1613aba | 1650 | gdb_byte *regs = gregs; |
386c036b | 1651 | int i; |
c5aa993b | 1652 | |
386c036b MK |
1653 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1654 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1655 | regs + gregset->r_psr_offset); | |
60054393 | 1656 | |
386c036b MK |
1657 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1658 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1659 | regs + gregset->r_pc_offset); | |
1660 | ||
1661 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1662 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1663 | regs + gregset->r_npc_offset); | |
5af923b0 | 1664 | |
386c036b MK |
1665 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1666 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1667 | regs + gregset->r_y_offset); | |
1668 | ||
1669 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1670 | { |
386c036b MK |
1671 | int offset = gregset->r_g1_offset; |
1672 | ||
1673 | /* %g0 is always zero. */ | |
1674 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1675 | { | |
1676 | if (regnum == i || regnum == -1) | |
1677 | regcache_raw_collect (regcache, i, regs + offset); | |
1678 | offset += 4; | |
1679 | } | |
5af923b0 | 1680 | } |
386c036b MK |
1681 | |
1682 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1683 | { |
386c036b MK |
1684 | /* Not all of the register set variants include Locals and |
1685 | Inputs. For those that don't, we read them off the stack. */ | |
1686 | if (gregset->r_l0_offset != -1) | |
1687 | { | |
1688 | int offset = gregset->r_l0_offset; | |
1689 | ||
1690 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1691 | { | |
1692 | if (regnum == i || regnum == -1) | |
1693 | regcache_raw_collect (regcache, i, regs + offset); | |
1694 | offset += 4; | |
1695 | } | |
1696 | } | |
5af923b0 | 1697 | } |
c906108c SS |
1698 | } |
1699 | ||
c906108c | 1700 | void |
386c036b MK |
1701 | sparc32_supply_fpregset (struct regcache *regcache, |
1702 | int regnum, const void *fpregs) | |
c906108c | 1703 | { |
e1613aba | 1704 | const gdb_byte *regs = fpregs; |
386c036b | 1705 | int i; |
60054393 | 1706 | |
386c036b | 1707 | for (i = 0; i < 32; i++) |
c906108c | 1708 | { |
386c036b MK |
1709 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1710 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1711 | } |
5af923b0 | 1712 | |
386c036b MK |
1713 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1714 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1715 | } |
1716 | ||
386c036b MK |
1717 | void |
1718 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1719 | int regnum, void *fpregs) | |
c906108c | 1720 | { |
e1613aba | 1721 | gdb_byte *regs = fpregs; |
386c036b | 1722 | int i; |
c906108c | 1723 | |
386c036b MK |
1724 | for (i = 0; i < 32; i++) |
1725 | { | |
1726 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1727 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1728 | } | |
c906108c | 1729 | |
386c036b MK |
1730 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1731 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1732 | } |
c906108c | 1733 | \f |
c906108c | 1734 | |
386c036b | 1735 | /* SunOS 4. */ |
c906108c | 1736 | |
386c036b MK |
1737 | /* From <machine/reg.h>. */ |
1738 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1739 | { |
386c036b MK |
1740 | 0 * 4, /* %psr */ |
1741 | 1 * 4, /* %pc */ | |
1742 | 2 * 4, /* %npc */ | |
1743 | 3 * 4, /* %y */ | |
1744 | -1, /* %wim */ | |
1745 | -1, /* %tbr */ | |
1746 | 4 * 4, /* %g1 */ | |
1747 | -1 /* %l0 */ | |
1748 | }; | |
1749 | \f | |
c906108c | 1750 | |
386c036b MK |
1751 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1752 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1753 | |
1754 | void | |
386c036b | 1755 | _initialize_sparc_tdep (void) |
c906108c | 1756 | { |
386c036b | 1757 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1758 | } |