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2004-01-02 Michael Chastain <mec.gnu@mindspring.com>
[deliverable/binutils-gdb.git] / gdb / sparc64-tdep.c
CommitLineData
8b39fe56
MK		 1/* Target-dependent code for UltraSPARC.
2
3 Copyright 2003 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "floatformat.h"
25#include "frame.h"
26#include "frame-base.h"
27#include "frame-unwind.h"
28#include "gdbcore.h"
29#include "gdbtypes.h"
30#include "osabi.h"
31#include "regcache.h"
32#include "target.h"
33#include "value.h"
34
35#include "gdb_assert.h"
36#include "gdb_string.h"
37
38#include "sparc64-tdep.h"
39
40/* This file implements the The SPARC 64-bit ABI as defined by the
41 section "Low-Level System Information" of the SPARC Compliance
42 Definition (SCD) 2.4.1, which is the 64-bit System V psABI for
43 SPARC. */
44
45/* Please use the sparc32_-prefix for 32-bit specific code, the
46 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
47 code can handle both. */
48
49/* The stack pointer is offset from the stack frame by a BIAS of 2047
50 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
51 hosts, so undefine it first. */
52#undef BIAS
53#define BIAS 2047
54
55/* Macros to extract fields from SPARC instructions. */
56#define X_OP(i) (((i) >> 30) & 0x3)
57#define X_A(i) (((i) >> 29) & 1)
58#define X_COND(i) (((i) >> 25) & 0xf)
59#define X_OP2(i) (((i) >> 22) & 0x7)
60#define X_IMM22(i) ((i) & 0x3fffff)
61#define X_OP3(i) (((i) >> 19) & 0x3f)
62/* Sign extension macros. */
63#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
64#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
65
66/* Fetch the instruction at PC. Instructions are always big-endian
67 even if the processor operates in little-endian mode. */
68
69static unsigned long
70sparc_fetch_instruction (CORE_ADDR pc)
71{
72 unsigned char buf[4];
73 unsigned long insn;
74 int i;
75
76 read_memory (pc, buf, sizeof (buf));
77
78 insn = 0;
79 for (i = 0; i < sizeof (buf); i++)
80 insn = (insn << 8) | buf[i];
81 return insn;
82}
83\f
84/* The functions on this page are intended to be used to classify
85 function arguments. */
86
87/* Return the contents if register REGNUM as an address. */
88
89static CORE_ADDR
90sparc_address_from_register (int regnum)
91{
92 ULONGEST addr;
93
94 regcache_cooked_read_unsigned (current_regcache, regnum, &addr);
95 return addr;
96}
97
98/* Check whether TYPE is "Integral or Pointer". */
99
100static int
101sparc64_integral_or_pointer_p (const struct type *type)
102{
103 switch (TYPE_CODE (type))
104 {
105 case TYPE_CODE_INT:
106 case TYPE_CODE_BOOL:
107 case TYPE_CODE_CHAR:
108 case TYPE_CODE_ENUM:
109 case TYPE_CODE_RANGE:
110 {
111 int len = TYPE_LENGTH (type);
112 gdb_assert (len == 1 || len == 2 || len == 4 || len == 8);
113 }
114 return 1;
115 case TYPE_CODE_PTR:
116 case TYPE_CODE_REF:
117 {
118 int len = TYPE_LENGTH (type);
119 gdb_assert (len == 8);
120 }
121 return 1;
122 default:
123 break;
124 }
125
126 return 0;
127}
128
129/* Check whether TYPE is "Floating". */
130
131static int
132sparc64_floating_p (const struct type *type)
133{
134 switch (TYPE_CODE (type))
135 {
136 case TYPE_CODE_FLT:
137 {
138 int len = TYPE_LENGTH (type);
139 gdb_assert (len == 4 || len == 8 || len == 16);
140 }
141 return 1;
142 default:
143 break;
144 }
145
146 return 0;
147}
148
149/* Check whether TYPE is "Structure or Union". */
150
151static int
152sparc64_structure_or_union_p (const struct type *type)
153{
154 switch (TYPE_CODE (type))
155 {
156 case TYPE_CODE_STRUCT:
157 case TYPE_CODE_UNION:
158 return 1;
159 default:
160 break;
161 }
162
163 return 0;
164}
165
166/* UltraSPARC architecture specific information. */
167
168struct gdbarch_tdep
169{
170 /* Offset of saved PC in jmp_buf. */
171 int jb_pc_offset;
172};
173
174/* Register information. */
175
176struct sparc64_register_info
177{
178 char *name;
179 struct type **type;
180};
181
182static struct sparc64_register_info sparc64_register_info[] =
183{
184 { "g0", &builtin_type_int64 },
185 { "g1", &builtin_type_int64 },
186 { "g2", &builtin_type_int64 },
187 { "g3", &builtin_type_int64 },
188 { "g4", &builtin_type_int64 },
189 { "g5", &builtin_type_int64 },
190 { "g6", &builtin_type_int64 },
191 { "g7", &builtin_type_int64 },
192
193 { "o0", &builtin_type_int64 },
194 { "o1", &builtin_type_int64 },
195 { "o2", &builtin_type_int64 },
196 { "o3", &builtin_type_int64 },
197 { "o4", &builtin_type_int64 },
198 { "o5", &builtin_type_int64 },
199 { "sp", &builtin_type_void_data_ptr },
200 { "o7", &builtin_type_int64 },
201
202 { "l0", &builtin_type_int64 },
203 { "l1", &builtin_type_int64 },
204 { "l2", &builtin_type_int64 },
205 { "l3", &builtin_type_int64 },
206 { "l4", &builtin_type_int64 },
207 { "l5", &builtin_type_int64 },
208 { "l6", &builtin_type_int64 },
209 { "l7", &builtin_type_int64 },
210
211 { "i0", &builtin_type_int64 },
212 { "i1", &builtin_type_int64 },
213 { "i2", &builtin_type_int64 },
214 { "i3", &builtin_type_int64 },
215 { "i4", &builtin_type_int64 },
216 { "i5", &builtin_type_int64 },
217 { "fp", &builtin_type_void_data_ptr },
218 { "i7", &builtin_type_int64 },
219
220 { "f0", &builtin_type_float },
221 { "f1", &builtin_type_float },
222 { "f2", &builtin_type_float },
223 { "f3", &builtin_type_float },
224 { "f4", &builtin_type_float },
225 { "f5", &builtin_type_float },
226 { "f6", &builtin_type_float },
227 { "f7", &builtin_type_float },
228 { "f8", &builtin_type_float },
229 { "f9", &builtin_type_float },
230 { "f10", &builtin_type_float },
231 { "f11", &builtin_type_float },
232 { "f12", &builtin_type_float },
233 { "f13", &builtin_type_float },
234 { "f14", &builtin_type_float },
235 { "f15", &builtin_type_float },
236 { "f16", &builtin_type_float },
237 { "f17", &builtin_type_float },
238 { "f18", &builtin_type_float },
239 { "f19", &builtin_type_float },
240 { "f20", &builtin_type_float },
241 { "f21", &builtin_type_float },
242 { "f22", &builtin_type_float },
243 { "f23", &builtin_type_float },
244 { "f24", &builtin_type_float },
245 { "f25", &builtin_type_float },
246 { "f26", &builtin_type_float },
247 { "f27", &builtin_type_float },
248 { "f28", &builtin_type_float },
249 { "f29", &builtin_type_float },
250 { "f30", &builtin_type_float },
251 { "f31", &builtin_type_float },
252 { "f32", &builtin_type_double },
253 { "f34", &builtin_type_double },
254 { "f36", &builtin_type_double },
255 { "f38", &builtin_type_double },
256 { "f40", &builtin_type_double },
257 { "f42", &builtin_type_double },
258 { "f44", &builtin_type_double },
259 { "f46", &builtin_type_double },
260 { "f48", &builtin_type_double },
261 { "f50", &builtin_type_double },
262 { "f52", &builtin_type_double },
263 { "f54", &builtin_type_double },
264 { "f56", &builtin_type_double },
265 { "f58", &builtin_type_double },
266 { "f60", &builtin_type_double },
267 { "f62", &builtin_type_double },
268
269 { "pc", &builtin_type_void_func_ptr },
270 { "npc", &builtin_type_void_func_ptr },
271
272 /* This raw register contains the contents of %cwp, %pstate, %asi
273 and %ccr as laid out in a %tstate register. */
3567a8ea
MK		 274 /* FIXME: Give it a name until we start using register groups. */
275 { "state", &builtin_type_int64 },
8b39fe56
MK		 276
277 { "fsr", &builtin_type_int64 },
278 { "fprs", &builtin_type_int64 },
279
280 /* "Although Y is a 64-bit register, its high-order 32 bits are
281 reserved and always read as 0." */
282 { "y", &builtin_type_int64 }
283};
284
285/* Total number of registers. */
286#define SPARC64_NUM_REGS \
287 (sizeof (sparc64_register_info) / sizeof (sparc64_register_info[0]))
288
289/* We provide the aliases %d0..%d62 and %q0..%q60 for the floating
290 registers as "psuedo" registers. */
291
292static struct sparc64_register_info sparc64_pseudo_register_info[] =
293{
294 { "cwp", &builtin_type_int64 },
295 { "pstate", &builtin_type_int64 },
296 { "asi", &builtin_type_int64 },
297 { "ccr", &builtin_type_int64 },
298
299 { "d0", &builtin_type_double },
300 { "d2", &builtin_type_double },
301 { "d4", &builtin_type_double },
302 { "d6", &builtin_type_double },
303 { "d8", &builtin_type_double },
304 { "d10", &builtin_type_double },
305 { "d12", &builtin_type_double },
306 { "d14", &builtin_type_double },
307 { "d16", &builtin_type_double },
308 { "d18", &builtin_type_double },
309 { "d20", &builtin_type_double },
310 { "d22", &builtin_type_double },
311 { "d24", &builtin_type_double },
312 { "d26", &builtin_type_double },
313 { "d28", &builtin_type_double },
314 { "d30", &builtin_type_double },
315 { "d32", &builtin_type_double },
316 { "d34", &builtin_type_double },
317 { "d36", &builtin_type_double },
318 { "d38", &builtin_type_double },
319 { "d40", &builtin_type_double },
320 { "d42", &builtin_type_double },
321 { "d44", &builtin_type_double },
322 { "d46", &builtin_type_double },
323 { "d48", &builtin_type_double },
324 { "d50", &builtin_type_double },
325 { "d52", &builtin_type_double },
326 { "d54", &builtin_type_double },
327 { "d56", &builtin_type_double },
328 { "d58", &builtin_type_double },
329 { "d60", &builtin_type_double },
330 { "d62", &builtin_type_double },
331
332 { "q0", &builtin_type_long_double },
333 { "q4", &builtin_type_long_double },
334 { "q8", &builtin_type_long_double },
335 { "q12", &builtin_type_long_double },
336 { "q16", &builtin_type_long_double },
337 { "q20", &builtin_type_long_double },
338 { "q24", &builtin_type_long_double },
339 { "q28", &builtin_type_long_double },
340 { "q32", &builtin_type_long_double },
341 { "q36", &builtin_type_long_double },
342 { "q40", &builtin_type_long_double },
343 { "q44", &builtin_type_long_double },
344 { "q48", &builtin_type_long_double },
345 { "q52", &builtin_type_long_double },
346 { "q56", &builtin_type_long_double },
347 { "q60", &builtin_type_long_double }
348};
349
350/* Total number of pseudo registers. */
351#define SPARC64_NUM_PSEUDO_REGS \
352 (sizeof (sparc64_pseudo_register_info) \
353 / sizeof (sparc64_pseudo_register_info[0]))
354
355/* Return the name of register REGNUM. */
356
357static const char *
358sparc64_register_name (int regnum)
359{
360 if (regnum >= 0 && regnum < SPARC64_NUM_REGS)
361 return sparc64_register_info[regnum].name;
362
363 if (regnum >= SPARC64_NUM_REGS
364 && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS)
365 return sparc64_pseudo_register_info[regnum - SPARC64_NUM_REGS].name;
366
367 return NULL;
368}
369
370/* Return the GDB type object for the "standard" data type of data in
371 register REGNUM. */
372
373static struct type *
374sparc64_register_type (struct gdbarch *gdbarch, int regnum)
375{
376 if (regnum >= SPARC64_NUM_REGS
377 && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS)
378 return *sparc64_pseudo_register_info[regnum - SPARC64_NUM_REGS].type;
379
380 gdb_assert (regnum >= 0 && regnum < SPARC64_NUM_REGS);
381 return *sparc64_register_info[regnum].type;
382}
383
384static void
385sparc64_pseudo_register_read (struct gdbarch *gdbarch,
386 struct regcache *regcache,
387 int regnum, void *buf)
388{
389 gdb_assert (regnum >= SPARC64_NUM_REGS);
390
391 if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM)
392 {
393 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC64_D0_REGNUM);
394 regcache_raw_read (regcache, regnum, buf);
395 regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4);
396 }
397 else if (regnum >= SPARC64_D32_REGNUM && regnum <= SPARC64_D62_REGNUM)
398 {
399 regnum = SPARC64_F32_REGNUM + (regnum - SPARC64_D32_REGNUM);
400 regcache_raw_read (regcache, regnum, buf);
401 }
402 else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q28_REGNUM)
403 {
404 regnum = SPARC_F0_REGNUM + 4 * (regnum - SPARC64_Q0_REGNUM);
405 regcache_raw_read (regcache, regnum, buf);
406 regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4);
407 regcache_raw_read (regcache, regnum + 2, ((char *)buf) + 8);
408 regcache_raw_read (regcache, regnum + 3, ((char *)buf) + 12);
409 }
410 else if (regnum >= SPARC64_Q32_REGNUM && regnum <= SPARC64_Q60_REGNUM)
411 {
412 regnum = SPARC64_F32_REGNUM + 2 * (regnum - SPARC64_Q32_REGNUM);
413 regcache_raw_read (regcache, regnum, buf);
414 regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 8);
415 }
416 else if (regnum == SPARC64_CWP_REGNUM
417 || regnum == SPARC64_PSTATE_REGNUM
418 || regnum == SPARC64_ASI_REGNUM
419 || regnum == SPARC64_CCR_REGNUM)
420 {
421 ULONGEST state;
422
423 regcache_raw_read_unsigned (regcache, SPARC64_STATE_REGNUM, &state);
424 switch (regnum)
425 {
3567a8ea 426 case SPARC64_CWP_REGNUM:
8b39fe56
MK		 427 state = (state >> 0) & ((1 << 5) - 1);
428 break;
3567a8ea 429 case SPARC64_PSTATE_REGNUM:
8b39fe56
MK		 430 state = (state >> 8) & ((1 << 12) - 1);
431 break;
3567a8ea 432 case SPARC64_ASI_REGNUM:
8b39fe56
MK		 433 state = (state >> 24) & ((1 << 8) - 1);
434 break;
3567a8ea 435 case SPARC64_CCR_REGNUM:
8b39fe56
MK		 436 state = (state >> 32) & ((1 << 8) - 1);
437 break;
438 }
439 store_unsigned_integer (buf, 8, state);
440 }
441}
442
443static void
444sparc64_pseudo_register_write (struct gdbarch *gdbarch,
445 struct regcache *regcache,
446 int regnum, const void *buf)
447{
448 gdb_assert (regnum >= SPARC64_NUM_REGS);
449
450 if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM)
451 {
452 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC64_D0_REGNUM);
453 regcache_raw_write (regcache, regnum, buf);
454 regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4);
455 }
456 else if (regnum >= SPARC64_D32_REGNUM && regnum <= SPARC64_D62_REGNUM)
457 {
458 regnum = SPARC64_F32_REGNUM + (regnum - SPARC64_D32_REGNUM);
459 regcache_raw_write (regcache, regnum, buf);
460 }
461 else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q28_REGNUM)
462 {
463 regnum = SPARC_F0_REGNUM + 4 * (regnum - SPARC64_Q0_REGNUM);
464 regcache_raw_write (regcache, regnum, buf);
465 regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4);
466 regcache_raw_write (regcache, regnum + 2, ((const char *)buf) + 8);
467 regcache_raw_write (regcache, regnum + 3, ((const char *)buf) + 12);
468 }
469 else if (regnum >= SPARC64_Q32_REGNUM && regnum <= SPARC64_Q60_REGNUM)
470 {
471 regnum = SPARC64_F32_REGNUM + 2 * (regnum - SPARC64_Q32_REGNUM);
472 regcache_raw_write (regcache, regnum, buf);
473 regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 8);
474 }
3567a8ea
MK		 475 else if (regnum == SPARC64_CWP_REGNUM
476 || regnum == SPARC64_PSTATE_REGNUM
477 || regnum == SPARC64_ASI_REGNUM
478 || regnum == SPARC64_CCR_REGNUM)
479 {
480 ULONGEST state, bits;
481
482 regcache_raw_read_unsigned (regcache, SPARC64_STATE_REGNUM, &state);
483 bits = extract_unsigned_integer (buf, 8);
484 switch (regnum)
485 {
486 case SPARC64_CWP_REGNUM:
487 state |= ((bits & ((1 << 5) - 1)) << 0);
488 break;
489 case SPARC64_PSTATE_REGNUM:
490 state |= ((bits & ((1 << 12) - 1)) << 8);
491 break;
492 case SPARC64_ASI_REGNUM:
493 state |= ((bits & ((1 << 8) - 1)) << 24);
494 break;
495 case SPARC64_CCR_REGNUM:
496 state |= ((bits & ((1 << 8) - 1)) << 32);
497 break;
498 }
499 regcache_raw_write_unsigned (regcache, SPARC64_STATE_REGNUM, state);
500 }
8b39fe56
MK		 501}
502
503/* Use the program counter to determine the contents and size of a
504 breakpoint instruction. Return a pointer to a string of bytes that
505 encode a breakpoint instruction, store the length of the string in
506 *LEN and optionally adjust *PC to point to the correct memory
507 location for inserting the breakpoint. */
508
509static const unsigned char *
510sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
511{
512 static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
513
514 *len = sizeof (break_insn);
515 return break_insn;
516}
517\f
518
519struct sparc64_frame_cache
520{
521 /* Base address. */
522 CORE_ADDR base;
523 CORE_ADDR pc;
524
525 /* Do we have a frame? */
526 int frameless_p;
527};
528
529/* Allocate and initialize a frame cache. */
530
531static struct sparc64_frame_cache *
532sparc64_alloc_frame_cache (void)
533{
534 struct sparc64_frame_cache *cache;
535 int i;
536
537 cache = FRAME_OBSTACK_ZALLOC (struct sparc64_frame_cache);
538
539 /* Base address. */
540 cache->base = 0;
541 cache->pc = 0;
542
543 /* Frameless until proven otherwise. */
544 cache->frameless_p = 1;
545
546 return cache;
547}
548
549static CORE_ADDR
550sparc64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
551 struct sparc64_frame_cache *cache)
552{
553 unsigned long insn;
554
555 if (current_pc <= pc)
556 return current_pc;
557
558 /* Check whether the function starts with a SAVE instruction. */
559 insn = sparc_fetch_instruction (pc);
560 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
561 {
562 cache->frameless_p = 0;
563 return pc + 4;
564 }
565
566 return pc;
567}
568
569static CORE_ADDR
570sparc64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
571{
572 return frame_unwind_register_unsigned (next_frame, SPARC64_PC_REGNUM);
573}
574
575/* Return PC of first real instruction of the function starting at
576 START_PC. */
577
578static CORE_ADDR
579sparc64_skip_prologue (CORE_ADDR start_pc)
580{
581 struct symtab_and_line sal;
582 CORE_ADDR func_start, func_end;
583 struct sparc64_frame_cache cache;
584
585 /* This is the preferred method, find the end of the prologue by
586 using the debugging information. */
587 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
588 {
589 sal = find_pc_line (func_start, 0);
590
591 if (sal.end < func_end
592 && start_pc <= sal.end)
593 return sal.end;
594 }
595
596 return sparc64_analyze_prologue (start_pc, 0xffffffffffffffffUL, &cache);
597}
598
599/* Normal frames. */
600
601static struct sparc64_frame_cache *
602sparc64_frame_cache (struct frame_info *next_frame, void **this_cache)
603{
604 struct sparc64_frame_cache *cache;
605
606 if (*this_cache)
607 return *this_cache;
608
609 cache = sparc64_alloc_frame_cache ();
610 *this_cache = cache;
611
612 /* In priciple, for normal frames, %fp (%i6) holds the frame
613 pointer, which holds the base address for the current stack
614 frame. */
615
616 cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
617 if (cache->base == 0)
618 return cache;
619
620 cache->pc = frame_func_unwind (next_frame);
621 if (cache->pc != 0)
622 sparc64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
623
624 if (cache->frameless_p)
625 {
626 /* We didn't find a valid frame, which means that CACHE->base
627 currently holds the frame pointer for our calling frame. */
628 cache->base = frame_unwind_register_unsigned (next_frame,
629 SPARC_SP_REGNUM);
630 }
631
632 return cache;
633}
634
635static void
636sparc64_frame_this_id (struct frame_info *next_frame, void **this_cache,
637 struct frame_id *this_id)
638{
639 struct sparc64_frame_cache *cache =
640 sparc64_frame_cache (next_frame, this_cache);
641
642 /* This marks the outermost frame. */
643 if (cache->base == 0)
644 return;
645
646 (*this_id) = frame_id_build (cache->base, cache->pc);
647}
648
649static void
650sparc64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
651 int regnum, int *optimizedp,
652 enum lval_type *lvalp, CORE_ADDR *addrp,
653 int *realnump, void *valuep)
654{
655 struct sparc64_frame_cache *cache =
656 sparc64_frame_cache (next_frame, this_cache);
657
658 if (regnum == SPARC64_PC_REGNUM || regnum == SPARC64_NPC_REGNUM)
659 {
660 *optimizedp = 0;
661 *lvalp = not_lval;
662 *addrp = 0;
663 *realnump = -1;
664 if (valuep)
665 {
666 CORE_ADDR pc = (regnum == SPARC64_NPC_REGNUM) ? 4 : 0;
667
668 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
669 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
670 store_unsigned_integer (valuep, 8, pc);
671 }
672 return;
673 }
674
675 /* The previous frame's `local' and `in' registers have been saved
676 in the register save area. */
677 if (!cache->frameless_p
678 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
679 {
680 *optimizedp = 0;
681 *lvalp = lval_memory;
682 *addrp = cache->base + BIAS + (regnum - SPARC_L0_REGNUM) * 8;
683 *realnump = -1;
684 if (valuep)
685 {
686 struct gdbarch *gdbarch = get_frame_arch (next_frame);
687
688 /* Read the value in from memory. */
689 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
690 }
691 return;
692 }
693
694 /* The previous frame's `out' registers are accessable as the
695 current frame's `in' registers. */
696 if (!cache->frameless_p
697 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
698 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
699
700 frame_register_unwind (next_frame, regnum,
701 optimizedp, lvalp, addrp, realnump, valuep);
702}
703
704static const struct frame_unwind sparc64_frame_unwind =
705{
706 NORMAL_FRAME,
707 sparc64_frame_this_id,
708 sparc64_frame_prev_register
709};
710
711static const struct frame_unwind *
712sparc64_frame_sniffer (struct frame_info *next_frame)
713{
714 return &sparc64_frame_unwind;
715}
716\f
717
718static CORE_ADDR
719sparc64_frame_base_address (struct frame_info *next_frame, void **this_cache)
720{
721 struct sparc64_frame_cache *cache =
722 sparc64_frame_cache (next_frame, this_cache);
723
724 /* ??? Should we take BIAS into account here? */
725 return cache->base;
726}
727
728static const struct frame_base sparc64_frame_base =
729{
730 &sparc64_frame_unwind,
731 sparc64_frame_base_address,
732 sparc64_frame_base_address,
733 sparc64_frame_base_address
734};
735
736static struct frame_id
737sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
738{
739 CORE_ADDR sp;
740
741 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
742 return frame_id_build (sp, frame_pc_unwind (next_frame));
743}
744\f
745/* Check whether TYPE must be 16-byte aligned. */
746
747static int
748sparc64_16_byte_align_p (struct type *type)
749{
750 if (sparc64_floating_p (type) && TYPE_LENGTH (type) == 16)
751 return 1;
752
753 if (sparc64_structure_or_union_p (type))
754 {
755 int i;
756
757 for (i = 0; i < TYPE_NFIELDS (type); i++)
758 if (sparc64_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
759 return 1;
760 }
761
762 return 0;
763}
764
765/* Store floating fields of element ELEMENT of an "parameter array"
766 that has type TYPE and is stored at BITPOS in VALBUF in the
767 apropriate registers of REGCACHE. This function can be called
768 recursively and therefore handles floating types in addition to
769 structures. */
770
771static void
772sparc64_store_floating_fields (struct regcache *regcache, struct type *type,
773 char *valbuf, int element, int bitpos)
774{
775 gdb_assert (element < 16);
776
777 if (sparc64_floating_p (type))
778 {
779 int len = TYPE_LENGTH (type);
780 int regnum;
781
782 if (len == 16)
783 {
784 gdb_assert (bitpos == 0);
785 gdb_assert ((element % 2) == 0);
786
787 regnum = SPARC64_Q0_REGNUM + element / 2;
788 regcache_cooked_write (regcache, regnum, valbuf);
789 }
790 else if (len == 8)
791 {
792 gdb_assert (bitpos == 0 || bitpos == 64);
793
794 regnum = SPARC64_D0_REGNUM + element + bitpos / 64;
795 regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8));
796 }
797 else
798 {
799 gdb_assert (len == 4);
800 gdb_assert (bitpos % 32 == 0 && bitpos >= 0 && bitpos < 128);
801
802 regnum = SPARC_F0_REGNUM + element * 2 + bitpos / 32;
803 regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8));
804 }
805 }
806 else if (sparc64_structure_or_union_p (type))
807 {
808 int i;
809
810 for (i = 0; i < TYPE_NFIELDS (type); i++)
811 sparc64_store_floating_fields (regcache, TYPE_FIELD_TYPE (type, i),
812 valbuf, element,
813 bitpos + TYPE_FIELD_BITPOS (type, i));
814 }
815}
816
817/* Fetch floating fields from a variable of type TYPE from the
818 appropriate registers for BITPOS in REGCACHE and store it at BITPOS
819 in VALBUF. This function can be called recursively and therefore
820 handles floating types in addition to structures. */
821
822static void
823sparc64_extract_floating_fields (struct regcache *regcache, struct type *type,
824 char *valbuf, int bitpos)
825{
826 if (sparc64_floating_p (type))
827 {
828 int len = TYPE_LENGTH (type);
829 int regnum;
830
831 if (len == 16)
832 {
833 gdb_assert (bitpos == 0 || bitpos == 128);
834
835 regnum = SPARC64_Q0_REGNUM + bitpos / 128;
836 regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8));
837 }
838 else if (len == 8)
839 {
840 gdb_assert (bitpos % 64 == 0 && bitpos >= 0 && bitpos < 256);
841
842 regnum = SPARC64_D0_REGNUM + bitpos / 64;
843 regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8));
844 }
845 else
846 {
847 gdb_assert (len == 4);
848 gdb_assert (bitpos % 32 == 0 && bitpos >= 0 && bitpos < 256);
849
850 regnum = SPARC_F0_REGNUM + bitpos / 32;
851 regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8));
852 }
853 }
854 else if (sparc64_structure_or_union_p (type))
855 {
856 int i;
857
858 for (i = 0; i < TYPE_NFIELDS (type); i++)
859 sparc64_extract_floating_fields (regcache, TYPE_FIELD_TYPE (type, i),
860 valbuf,
861 bitpos + TYPE_FIELD_BITPOS (type, i));
862 }
863}
864
865/* Store the NARGS arguments ARGS and STRUCT_ADDR (if STRUCT_RETURN is
866 non-zero) in REGCACHE and on the stack (starting from address SP). */
867
868static CORE_ADDR
869sparc64_store_arguments (struct regcache *regcache, int nargs,
870 struct value **args, CORE_ADDR sp,
871 int struct_return, CORE_ADDR struct_addr)
872{
873 /* Number of extended words in the "parameter array". */
874 int num_elements = 0;
875 int element = 0;
876 int i;
877
878 /* Take BIAS into account. */
879 sp += BIAS;
880
881 /* First we calculate the number of extended words in the "parameter
882 array". While doing so we also convert some of the arguments. */
883
884 if (struct_return)
885 num_elements++;
886
887 for (i = 0; i < nargs; i++)
888 {
889 struct type *type = VALUE_TYPE (args[i]);
890 int len = TYPE_LENGTH (type);
891
892 if (sparc64_structure_or_union_p (type))
893 {
894 /* Structure or Union arguments. */
895 if (len <= 16)
896 {
897 if (num_elements % 2 && sparc64_16_byte_align_p (type))
898 num_elements++;
899 num_elements += ((len + 7) / 8);
900 }
901 else
902 {
903 /* The psABI says that "Structures or unions larger than
904 sixteen bytes are copied by the caller and passed
905 indirectly; the caller will pass the address of a
906 correctly aligned structure value. This sixty-four
907 bit address will occupy one word in the parameter
908 array, and may be promoted to an %o register like any
909 other pointer value." Allocate memory for these
910 values on the stack. */
911 sp -= len;
912
913 /* Use 16-byte alignment for these values. That's
914 always correct, and wasting a few bytes shouldn't be
915 a problem. */
916 sp &= ~0xf;
917
918 write_memory (sp, VALUE_CONTENTS (args[i]), len);
919 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
920 num_elements++;
921 }
922 }
923 else if (sparc64_floating_p (type))
924 {
925 /* Floating arguments. */
926
927 if (len == 16)
928 {
929 /* The psABI says that "Each quad-precision parameter
930 value will be assigned to two extended words in the
931 parameter array. */
932 num_elements += 2;
933
934 /* The psABI says that "Long doubles must be
935 quad-aligned, and thus a hole might be introduced
936 into the parameter array to force alignment." Skip
937 an element if necessary. */
938 if (num_elements % 2)
939 num_elements++;
940 }
941 else
942 num_elements++;
943 }
944 else
945 {
946 /* Integral and pointer arguments. */
947 gdb_assert (sparc64_integral_or_pointer_p (type));
948
949 /* The psABI says that "Each argument value of integral type
950 smaller than an extended word will be widened by the
951 caller to an extended word according to the signed-ness
952 of the argument type." */
953 if (len < 8)
954 args[i] = value_cast (builtin_type_int64, args[i]);
955 num_elements++;
956 }
957 }
958
959 /* Allocate the "parameter array". */
960 sp -= num_elements * 8;
961
962 /* The psABI says that "Every stack frame must be 16-byte aligned." */
963 sp &= ~0xf;
964
965 /* Now we store the arguments in to the "paramater array". Some
966 Integer or Pointer arguments and Structure or Union arguments
967 will be passed in %o registers. Some Floating arguments and
968 floating members of structures are passed in floating-point
969 registers. However, for functions with variable arguments,
970 floating arguments are stored in an %0 register, and for
971 functions without a prototype floating arguments are stored in
972 both a floating-point and an %o registers, or a floating-point
973 register and memory. To simplify the logic here we always pass
974 arguments in memory, an %o register, and a floating-point
975 register if appropriate. This should be no problem since the
976 contents of any unused memory or registers in the "parameter
977 array" are undefined. */
978
979 if (struct_return)
980 {
981 regcache_cooked_write_unsigned (regcache, SPARC_O0_REGNUM, struct_addr);
982 element++;
983 }
984
985 for (i = 0; i < nargs; i++)
986 {
987 char *valbuf = VALUE_CONTENTS (args[i]);
988 struct type *type = VALUE_TYPE (args[i]);
989 int len = TYPE_LENGTH (type);
990 int regnum = -1;
991 char buf[16];
992
993 if (sparc64_structure_or_union_p (type))
994 {
995 /* Structure or Union arguments. */
996 gdb_assert (len <= 16);
997 memset (buf, 0, sizeof (buf));
998 valbuf = memcpy (buf, valbuf, len);
999
1000 if (element % 2 && sparc64_16_byte_align_p (type))
1001 element++;
1002
1003 if (element < 6)
1004 {
1005 regnum = SPARC_O0_REGNUM + element;
1006 if (len > 8 && element < 5)
1007 regcache_cooked_write (regcache, regnum + 1, valbuf + 8);
1008 }
1009
1010 if (element < 16)
1011 sparc64_store_floating_fields (regcache, type, valbuf, element, 0);
1012 }
1013 else if (sparc64_floating_p (type))
1014 {
1015 /* Floating arguments. */
1016 if (len == 16)
1017 {
1018 if (element % 2)
1019 element++;
1020 if (element < 16)
1021 regnum = SPARC64_Q0_REGNUM + element / 2;
1022 }
1023 else if (len == 8)
1024 {
1025 if (element < 16)
1026 regnum = SPARC64_D0_REGNUM + element;
1027 }
1028 else
1029 {
1030 /* The psABI says "Each single-precision parameter value
1031 will be assigned to one extended word in the
1032 parameter array, and right-justified within that
1033 word; the left half (even floatregister) is
1034 undefined." Even though the psABI says that "the
1035 left half is undefined", set it to zero here. */
1036 memset (buf, 0, 4);
1037 valbuf = memcpy (buf + 4, valbuf, 4);
1038 len = 8;
1039 if (element < 16)
1040 regnum = SPARC64_D0_REGNUM;
1041 }
1042 }
1043 else
1044 {
1045 /* Integral and pointer arguments. */
1046 gdb_assert (len == 8);
1047 if (element < 6)
1048 regnum = SPARC_O0_REGNUM + element;
1049 }
1050
1051 if (regnum != -1)
1052 {
1053 regcache_cooked_write (regcache, regnum, valbuf);
1054
1055 /* If we're storing the value in a floating-point register,
1056 also store it in the corresponding %0 register(s). */
1057 if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D10_REGNUM)
1058 {
1059 gdb_assert (element < 6);
1060 regnum = SPARC_O0_REGNUM + element;
1061 regcache_cooked_write (regcache, regnum, valbuf);
1062 }
1063 else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q8_REGNUM)
1064 {
1065 gdb_assert (element < 6);
1066 regnum = SPARC_O0_REGNUM + element;
1067 regcache_cooked_write (regcache, regnum, valbuf);
1068 regcache_cooked_write (regcache, regnum + 1, valbuf);
1069 }
1070 }
1071
1072 /* Always store the argument in memeory. */
1073 write_memory (sp + element * 8, valbuf, len);
1074 element += ((len + 7) / 8);
1075 }
1076
1077 gdb_assert (element == num_elements);
1078
1079 /* Take BIAS into account. */
1080 sp -= BIAS;
1081 return sp;
1082}
1083
1084static CORE_ADDR
1085sparc64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1086 struct regcache *regcache, CORE_ADDR bp_addr,
1087 int nargs, struct value **args, CORE_ADDR sp,
1088 int struct_return, CORE_ADDR struct_addr)
1089{
1090 /* Set return address. */
1091 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, bp_addr - 8);
1092
1093 /* Set up function arguments. */
1094 sp = sparc64_store_arguments (regcache, nargs, args, sp,
1095 struct_return, struct_addr);
1096
1097 /* Allocate the register save area. */
1098 sp -= 16 * 8;
1099
1100 /* Stack should be 16-byte aligned at this point. */
3567a8ea 1101 gdb_assert ((sp + BIAS) % 16 == 0);
8b39fe56
MK		 1102
1103 /* Finally, update the stack pointer. */
1104 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
1105
1106 return sp;
1107}
1108\f
1109
1110/* Extract from an array REGBUF containing the (raw) register state, a
1111 function return value of TYPE, and copy that into VALBUF. */
1112
1113static void
1114sparc64_extract_return_value (struct type *type, struct regcache *regcache,
1115 void *valbuf)
1116{
1117 int len = TYPE_LENGTH (type);
1118 char buf[32];
1119 int i;
1120
1121 if (sparc64_structure_or_union_p (type))
1122 {
1123 /* Structure or Union return values. */
1124 gdb_assert (len <= 32);
1125
1126 for (i = 0; i < ((len + 7) / 8); i++)
1127 regcache_cooked_read (regcache, SPARC_O0_REGNUM + i, buf + i * 8);
1128 if (TYPE_CODE (type) != TYPE_CODE_UNION)
1129 sparc64_extract_floating_fields (regcache, type, buf, 0);
1130 memcpy (valbuf, buf, len);
1131 }
1132 else if (sparc64_floating_p (type))
1133 {
1134 /* Floating return values. */
1135 for (i = 0; i < len / 4; i++)
1136 regcache_cooked_read (regcache, SPARC_F0_REGNUM + i, buf + i * 4);
1137 memcpy (valbuf, buf, len);
1138 }
1139 else
1140 {
1141 /* Integral and pointer return values. */
1142 gdb_assert (sparc64_integral_or_pointer_p (type));
1143
1144 /* Just stripping off any unused bytes should preserve the
1145 signed-ness just fine. */
1146 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1147 memcpy (valbuf, buf + 8 - len, len);
1148 }
1149}
1150
1151/* Write into the appropriate registers a function return value stored
1152 in VALBUF of type TYPE. */
1153
1154static void
1155sparc64_store_return_value (struct type *type, struct regcache *regcache,
1156 const void *valbuf)
1157{
1158 int len = TYPE_LENGTH (type);
1159 char buf[16];
1160 int i;
1161
1162 if (sparc64_structure_or_union_p (type))
1163 {
1164 /* Structure or Union return values. */
1165 gdb_assert (len <= 32);
1166
1167 /* Simplify matters by storing the complete value (including
1168 floating members) into %o0 and %o1. Floating members are
1169 also store in the appropriate floating-point registers. */
1170 memset (buf, 0, sizeof (buf));
1171 memcpy (buf, valbuf, len);
1172 for (i = 0; i < ((len + 7) / 8); i++)
1173 regcache_cooked_write (regcache, SPARC_O0_REGNUM + i, buf + i * 4);
1174 if (TYPE_CODE (type) != TYPE_CODE_UNION)
1175 sparc64_store_floating_fields (regcache, type, buf, 0, 0);
1176 }
1177 else if (sparc64_floating_p (type))
1178 {
1179 /* Floating return values. */
1180 memcpy (buf, valbuf, len);
1181 for (i = 0; i < len / 4; i++)
1182 regcache_cooked_write (regcache, SPARC_F0_REGNUM + i, buf + i * 4);
1183 }
1184 else
1185 {
1186 /* Integral and pointer return values. */
1187 gdb_assert (sparc64_integral_or_pointer_p (type));
1188
1189 /* ??? Do we need to do any sign-extension here? */
1190 memset (buf, 0, 8);
1191 memcpy (buf + 8 - len, valbuf, len);
1192 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1193 }
1194}
1195
1196/* Extract from REGCACHE, which contains the (raw) register state, the
1197 address in which a function should return its structure value, as a
1198 CORE_ADDR. */
1199
1200static CORE_ADDR
1201sparc_extract_struct_value_address (struct regcache *regcache)
1202{
1203 ULONGEST addr;
1204
1205 regcache_cooked_read_unsigned (regcache, SPARC_O0_REGNUM, &addr);
1206 return addr;
1207}
1208
1209static int
1210sparc64_use_struct_convention (int gcc_p, struct type *type)
1211{
1212 /* Structure and union types up to 32 bytes in size are returned in
1213 registers. */
1214 return (TYPE_LENGTH (type) > 32);
1215}
1216
1217\f
1218/* The SPARC Architecture doesn't have hardware single-step support,
1219 and most operating systems don't implement it either, so we provide
1220 software single-step mechanism. */
1221
1222static CORE_ADDR
1223sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
1224{
1225 unsigned long insn = sparc_fetch_instruction (pc);
1226 int conditional_p = X_COND (insn) & 0x7;
1227 int branch_p = 0;
1228 long offset = 0; /* Must be signed for sign-extend. */
1229
1230 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1231 {
1232 /* Branch on Integer Register with Prediction (BPr). */
1233 branch_p = 1;
1234 conditional_p = 1;
1235 }
1236 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1237 {
1238 /* Branch on Floating-Point Condition Codes (FBfcc). */
1239 branch_p = 1;
1240 offset = 4 * X_DISP22 (insn);
1241 }
1242 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1243 {
1244 /* Branch on Floating-Point Condition Codes with Prediction
1245 (FBPfcc). */
1246 branch_p = 1;
1247 offset = 4 * X_DISP19 (insn);
1248 }
1249 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1250 {
1251 /* Branch on Integer Condition Codes (Bicc). */
1252 branch_p = 1;
1253 offset = 4 * X_DISP22 (insn);
1254 }
1255 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1256 {
1257 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1258 branch_p = 1;
1259 offset = 4 * X_DISP19 (insn);
1260 }
1261
1262 /* FIXME: Handle DONE and RETRY instructions. */
1263
1264 /* FIXME: Handle the Trap instruction. */
1265
1266 if (branch_p)
1267 {
1268 if (conditional_p)
1269 {
1270 /* For conditional branches, return nPC + 4 iff the annul
1271 bit is 1. */
1272 return (X_A (insn) ? *npc + 4 : 0);
1273 }
1274 else
1275 {
1276 /* For unconditional branches, return the target if its
1277 specified condition is "always" and return nPC + 4 if the
1278 condition is "never". If the annul bit is 1, set *NPC to
1279 zero. */
1280 if (X_COND (insn) == 0x0)
1281 pc = *npc, offset = 4;
1282 if (X_A (insn))
1283 *npc = 0;
1284
1285 gdb_assert (offset != 0);
1286 return pc + offset;
1287 }
1288 }
1289
1290 return 0;
1291}
1292
1293void
1294sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1295{
1296 static CORE_ADDR npc, nnpc;
1297 static char npc_save[4], nnpc_save[4];
1298
1299 if (insert_breakpoints_p)
1300 {
1301 CORE_ADDR pc;
1302
8b39fe56
MK		 1303 pc = sparc_address_from_register (SPARC64_PC_REGNUM);
1304 npc = sparc_address_from_register (SPARC64_NPC_REGNUM);
1305
1306 /* Analyze the instruction at PC. */
1307 nnpc = sparc_analyze_control_transfer (pc, &npc);
1308 if (npc != 0)
1309 target_insert_breakpoint (npc, npc_save);
1310 if (nnpc != 0)
1311 target_insert_breakpoint (nnpc, nnpc_save);
1312
1313 /* Assert that we have set at least one breakpoint. */
1314 gdb_assert (npc != 0 || nnpc != 0);
1315 }
1316 else
1317 {
1318 if (npc != 0)
1319 target_remove_breakpoint (npc, npc_save);
1320 if (nnpc != 0)
1321 target_remove_breakpoint (nnpc, nnpc_save);
1322
1323 npc = 0;
1324 nnpc = 0;
1325 }
1326}
1327\f
1328
1329static struct gdbarch *
1330sparc64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1331{
1332 struct gdbarch_tdep *tdep;
1333 struct gdbarch *gdbarch;
1334
1335 /* If there is already a candidate, use it. */
1336 arches = gdbarch_list_lookup_by_info (arches, &info);
1337 if (arches != NULL)
1338 return arches->gdbarch;
1339
1340 /* Allocate space for the new architecture. */
1341 tdep = XMALLOC (struct gdbarch_tdep);
1342 gdbarch = gdbarch_alloc (&info, tdep);
1343
1344 set_gdbarch_long_bit (gdbarch, 64);
1345 set_gdbarch_long_long_bit (gdbarch, 64);
1346 set_gdbarch_ptr_bit (gdbarch, 64);
1347 set_gdbarch_long_double_bit (gdbarch, 128);
1348
1349 set_gdbarch_num_regs (gdbarch, SPARC64_NUM_REGS);
1350 set_gdbarch_register_name (gdbarch, sparc64_register_name);
1351 set_gdbarch_register_type (gdbarch, sparc64_register_type);
1352 set_gdbarch_num_pseudo_regs (gdbarch, SPARC64_NUM_PSEUDO_REGS);
1353 set_gdbarch_pseudo_register_read (gdbarch, sparc64_pseudo_register_read);
1354 set_gdbarch_pseudo_register_write (gdbarch, sparc64_pseudo_register_write);
1355
1356 /* Register numbers of various important registers. */
1357 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1358 set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); /* %pc */
efe59759 1359 set_gdbarch_deprecated_npc_regnum (gdbarch, SPARC64_NPC_REGNUM);
8b39fe56
MK		 1360 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1361
1362 /* Call dummy code. */
1363 set_gdbarch_push_dummy_call (gdbarch, sparc64_push_dummy_call);
1364
1365 set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value);
1366 set_gdbarch_store_return_value (gdbarch, sparc64_store_return_value);
1367 set_gdbarch_extract_struct_value_address
1368 (gdbarch, sparc_extract_struct_value_address);
1369 set_gdbarch_use_struct_convention (gdbarch, sparc64_use_struct_convention);
1370
1371 set_gdbarch_skip_prologue (gdbarch, sparc64_skip_prologue);
1372
1373 /* Stack grows downward. */
1374 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1375
1376 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1377 set_gdbarch_decr_pc_after_break (gdbarch, 0);
1378 set_gdbarch_function_start_offset (gdbarch, 0);
1379
1380 set_gdbarch_frame_args_skip (gdbarch, 8);
1381
1382 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1383
1384 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1385
1386 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1387
1388 set_gdbarch_unwind_pc (gdbarch, sparc64_unwind_pc);
1389
1390 frame_base_set_default (gdbarch, &sparc64_frame_base);
1391
1392 /* Hook in ABI-specific overrides, if they have been registered. */
1393 gdbarch_init_osabi (info, gdbarch);
1394
1395 frame_unwind_append_sniffer (gdbarch, sparc64_frame_sniffer);
1396
1397 return gdbarch;
1398}
1399\f
1400/* Helper functions for dealing with register windows. */
1401
3567a8ea 1402void
8b39fe56
MK		 1403sparc_supply_rwindow (CORE_ADDR sp, int regnum)
1404{
1405 int offset = 0;
1406 char buf[8];
1407 int i;
1408
8b39fe56
MK		 1409 if (sp & 1)
1410 {
8b39fe56
MK		 1411 /* Registers are 64-bit. */
1412 sp += BIAS;
1413
1414 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1415 {
1416 if (regnum == i || regnum == -1)
1417 {
3567a8ea 1418 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
8b39fe56
MK		 1419 supply_register (i, buf);
1420 }
1421 }
1422 }
1423 else
1424 {
1425 /* Registers are 32-bit. Toss any sign-extension of the stack
1426 pointer. */
3567a8ea 1427 sp &= 0xffffffffUL;
8b39fe56 1428
3567a8ea
MK		 1429 /* Clear out the top half of the temporary buffer, and put the
1430 register value in the bottom half if we're in 64-bit mode. */
1431 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1432 {
1433 memset (buf, 0, 4);
1434 offset = 4;
1435 }
8b39fe56 1436
3567a8ea 1437 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
8b39fe56 1438 {
3567a8ea
MK		 1439 if (regnum == i || regnum == -1)
1440 {
1441 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1442 buf + offset, 4);
1443 supply_register (i, buf);
1444 }
8b39fe56
MK		 1445 }
1446 }
1447}
1448
1449void
3567a8ea 1450sparc_fill_rwindow (CORE_ADDR sp, int regnum)
8b39fe56 1451{
3567a8ea
MK		 1452 int offset = 0;
1453 char buf[8];
1454 int i;
1455
8b39fe56
MK		 1456 if (sp & 1)
1457 {
8b39fe56
MK		 1458 /* Registers are 64-bit. */
1459 sp += BIAS;
1460
1461 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1462 {
1463 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1464 {
1465 regcache_collect (i, buf);
3567a8ea 1466 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
8b39fe56
MK		 1467 }
1468 }
1469 }
1470 else
1471 {
1472 /* Registers are 32-bit. Toss any sign-extension of the stack
1473 pointer. */
3567a8ea
MK		 1474 sp &= 0xffffffffUL;
1475
1476 /* Only use the bottom half if we're in 64-bit mode. */
1477 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1478 offset = 4;
1479
1480 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1481 {
1482 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1483 {
1484 regcache_collect (i, buf);
1485 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1486 buf + offset, 4);
1487 }
1488 }
8b39fe56
MK		 1489 }
1490}
1491\f
1492
1493/* Provide a prototype to silence -Wmissing-prototypes. */
1494void _initialize_sparc64_tdep (void);
1495
1496void
1497_initialize_sparc64_tdep (void)
1498{
1499 register_gdbarch_init (bfd_arch_sparc, sparc64_gdbarch_init);
1500}
GDB Binutils - Deliverables
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