Commit | Line | Data |
---|---|---|
88b9d363 | 1 | # Copyright (C) 2008-2022 Free Software Foundation, Inc. |
604c2f83 LM |
2 | # |
3 | # This program is free software; you can redistribute it and/or modify | |
4 | # it under the terms of the GNU General Public License as published by | |
5 | # the Free Software Foundation; either version 3 of the License, or | |
6 | # (at your option) any later version. | |
7 | # | |
8 | # This program is distributed in the hope that it will be useful, | |
9 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | # GNU General Public License for more details. | |
12 | # | |
13 | # You should have received a copy of the GNU General Public License | |
14 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | # | |
604c2f83 | 16 | |
604c2f83 LM |
17 | # |
18 | # Test the use of VSX registers, for Powerpc. | |
19 | # | |
20 | ||
604c2f83 LM |
21 | |
22 | if {![istarget "powerpc*"] || [skip_vsx_tests]} then { | |
23 | verbose "Skipping vsx register tests." | |
604c2f83 LM |
24 | return |
25 | } | |
26 | ||
20c2c024 | 27 | standard_testfile |
604c2f83 LM |
28 | |
29 | set compile_flags {debug nowarnings quiet} | |
4c93b1db | 30 | if [get_compiler_info] { |
604c2f83 LM |
31 | warning "get_compiler failed" |
32 | return -1 | |
33 | } | |
34 | ||
35 | if [test_compiler_info gcc*] { | |
36 | set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" | |
37 | } elseif [test_compiler_info xlc*] { | |
38 | set compile_flags "$compile_flags additional_flags=-qaltivec" | |
39 | } else { | |
40 | warning "unknown compiler" | |
41 | return -1 | |
42 | } | |
43 | ||
44 | if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { | |
5b362f04 | 45 | untested "failed to compile" |
604c2f83 LM |
46 | return -1 |
47 | } | |
48 | ||
49 | gdb_start | |
50 | gdb_reinitialize_dir $srcdir/$subdir | |
51 | gdb_load ${binfile} | |
52 | ||
53 | # Run to `main' where we begin our tests. | |
54 | ||
55 | if ![runto_main] then { | |
c8ee3f04 PW |
56 | fail "can't run to main" |
57 | return 0 | |
604c2f83 LM |
58 | } |
59 | ||
805acca0 | 60 | set endianness [get_endianness] |
084ee545 | 61 | |
604c2f83 LM |
62 | # Data sets used throughout the test |
63 | ||
084ee545 | 64 | if {$endianness == "big"} { |
7a26362d | 65 | set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." |
084ee545 | 66 | |
7a26362d | 67 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
4572cbac | 68 | |
7a26362d | 69 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
d9492458 | 70 | |
084ee545 | 71 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
604c2f83 | 72 | |
30a25466 | 73 | set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
084ee545 | 74 | |
30a25466 | 75 | set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
084ee545 | 76 | } else { |
7a26362d | 77 | set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." |
d9492458 | 78 | |
7a26362d | 79 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." |
604c2f83 | 80 | |
7a26362d | 81 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." |
084ee545 UW |
82 | |
83 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." | |
84 | ||
30a25466 | 85 | set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." |
084ee545 | 86 | |
30a25466 | 87 | set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." |
084ee545 | 88 | } |
604c2f83 LM |
89 | |
90 | set float_register ".raw 0xdeadbeefdeadbeef." | |
91 | ||
6b142048 WS |
92 | # Note that the F0-F31 registers are shared with the doubleword 0 portion of |
93 | # the VS0-VS31 registers, the doubleword 1 portions of VS* remain unchanged | |
94 | # after updates to F*. | |
95 | # Since dl_main uses some VS* registers, and per inspection their values are | |
96 | # no longer zero when our test reaches main(), we need to explicitly | |
97 | # initialize the doubleword1 portions before we run our tests against | |
98 | # values currently in those registers. | |
99 | ||
100 | # 0: Initialize the (doubleword 1) portion of the VS0-VS31 registers. | |
101 | for {set i 0} {$i < 32} {incr i 1} { | |
6645c8ce | 102 | gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0" |
6b142048 | 103 | } |
604c2f83 LM |
104 | |
105 | # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. | |
106 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 107 | gdb_test_no_output "set \$f$i = 1\.3" |
604c2f83 LM |
108 | } |
109 | ||
110 | for {set i 0} {$i < 32} {incr i 1} { | |
111 | gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)" | |
112 | } | |
113 | ||
114 | # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. | |
115 | for {set i 0} {$i < 32} {incr i 1} { | |
116 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 117 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" |
604c2f83 LM |
118 | } |
119 | } | |
120 | ||
121 | for {set i 0} {$i < 32} {incr i 1} { | |
122 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
123 | } | |
124 | ||
125 | for {set i 0} {$i < 32} {incr i 1} { | |
126 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)" | |
127 | } | |
128 | ||
129 | # Now run the VR0~VR31/VS32~VS63 tests | |
130 | ||
131 | # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. | |
132 | for {set i 0} {$i < 32} {incr i 1} { | |
133 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 134 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
135 | } |
136 | } | |
137 | ||
138 | for {set i 32} {$i < 64} {incr i 1} { | |
139 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i" | |
140 | } | |
141 | # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. | |
142 | for {set i 32} {$i < 64} {incr i 1} { | |
143 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 144 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
145 | } |
146 | } | |
147 | ||
148 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 149 | gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" |
6f072a10 | 150 | gdb_test "info reg v$i" "v$i.*$vector_register3_vr" "info reg v$i" |
604c2f83 LM |
151 | } |
152 | ||
d9492458 TJB |
153 | # Create a core file. We create the core file before the F32~F63/VR0~VR31 test |
154 | # below because then we'll have more interesting register values to verify | |
155 | # later when loading the core file (i.e., different register values for different | |
156 | # vector register banks). | |
157 | ||
16c85b5d | 158 | set corefile [standard_output_file vsx-core.test] |
fac51dd9 | 159 | set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"] |
604c2f83 | 160 | |
d9492458 TJB |
161 | # Now run the F32~F63/VR0~VR31 tests. |
162 | ||
163 | # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. | |
164 | for {set i 32} {$i < 64} {incr i 1} { | |
165 | gdb_test_no_output "set \$f$i = 1\.3" | |
166 | } | |
167 | ||
168 | for {set i 0} {$i < 32} {incr i 1} { | |
169 | gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)" | |
6f072a10 | 170 | gdb_test "info reg v$i" "v$i.*$vector_register1_vr" "info reg v$i (doubleword 0)" |
d9492458 TJB |
171 | } |
172 | ||
173 | # 2: Set VR0~VR31 registers and check if it reflects on F32~F63. | |
174 | for {set i 0} {$i < 32} {incr i 1} { | |
175 | for {set j 0} {$j < 4} {incr j 1} { | |
176 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef" | |
177 | } | |
178 | } | |
179 | ||
180 | for {set i 32} {$i < 64} {incr i 1} { | |
181 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
182 | } | |
183 | ||
184 | for {set i 0} {$i < 32} {incr i 1} { | |
185 | gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)" | |
6f072a10 | 186 | gdb_test "info reg v$i" "v$i.*$vector_register2_vr" "info reg v$i (doubleword 1)" |
d9492458 TJB |
187 | } |
188 | ||
189 | # Test reading the core file. | |
190 | ||
604c2f83 LM |
191 | if {!$core_supported} { |
192 | return -1 | |
193 | } | |
194 | ||
195 | gdb_exit | |
196 | gdb_start | |
197 | gdb_reinitialize_dir $srcdir/$subdir | |
198 | gdb_load ${binfile} | |
199 | ||
fac51dd9 DE |
200 | set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"] |
201 | if { $core_loaded == -1 } { | |
202 | # No use proceeding from here. | |
203 | return | |
604c2f83 LM |
204 | } |
205 | ||
206 | for {set i 0} {$i < 32} {incr i 1} { | |
cdc7edd7 | 207 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file" |
604c2f83 LM |
208 | } |
209 | ||
210 | for {set i 32} {$i < 64} {incr i 1} { | |
cdc7edd7 | 211 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file" |
604c2f83 | 212 | } |