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[gdb/testsuite] Fix dwo path in fission-*.S
[deliverable/binutils-gdb.git] / gdb / tic6x-tdep.c
CommitLineData
8cd64e00
YQ		 1/* Target dependent code for GDB on TI C6x systems.
2
3666a048 3 Copyright (C) 2010-2021 Free Software Foundation, Inc.
8cd64e00
YQ		 4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "frame.h"
24#include "frame-unwind.h"
25#include "frame-base.h"
26#include "trad-frame.h"
82ca8957 27#include "dwarf2/frame.h"
8cd64e00
YQ		 28#include "symtab.h"
29#include "inferior.h"
30#include "gdbtypes.h"
31#include "gdbcore.h"
32#include "gdbcmd.h"
33#include "target.h"
34#include "dis-asm.h"
35#include "regcache.h"
36#include "value.h"
37#include "symfile.h"
38#include "arch-utils.h"
8cd64e00
YQ		 39#include "glibc-tdep.h"
40#include "infcall.h"
41#include "regset.h"
42#include "tramp-frame.h"
43#include "linux-tdep.h"
44#include "solib.h"
45#include "objfiles.h"
8cd64e00
YQ		 46#include "osabi.h"
47#include "tic6x-tdep.h"
48#include "language.h"
49#include "target-descriptions.h"
325fac50 50#include <algorithm>
8cd64e00 51
8cd64e00
YQ		 52#define TIC6X_OPCODE_SIZE 4
53#define TIC6X_FETCH_PACKET_SIZE 32
54
55#define INST_S_BIT(INST) ((INST >> 1) & 1)
56#define INST_X_BIT(INST) ((INST >> 12) & 1)
57
85661b1e
YQ		 58const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
59const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };
60
8cd64e00
YQ		 61struct tic6x_unwind_cache
62{
63 /* The frame's base, optionally used by the high-level debug info. */
64 CORE_ADDR base;
65
66 /* The previous frame's inner most stack address. Used as this
67 frame ID's stack_addr. */
68 CORE_ADDR cfa;
69
70 /* The address of the first instruction in this function */
71 CORE_ADDR pc;
72
73 /* Which register holds the return address for the frame. */
74 int return_regnum;
75
76 /* The offset of register saved on stack. If register is not saved, the
77 corresponding element is -1. */
78 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
79};
80
81
82/* Name of TI C6x core registers. */
83static const char *const tic6x_register_names[] =
84{
85 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
86 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
87 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
88 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
89 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
90 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
91 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
92 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
93 "CSR", "PC", /* 32 33 */
94};
95
96/* This array maps the arguments to the register number which passes argument
97 in function call according to C6000 ELF ABI. */
98static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
99
100/* This is the implementation of gdbarch method register_name. */
101
102static const char *
103tic6x_register_name (struct gdbarch *gdbarch, int regno)
104{
105 if (regno < 0)
106 return NULL;
107
108 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
109 return tdesc_register_name (gdbarch, regno);
110 else if (regno >= ARRAY_SIZE (tic6x_register_names))
111 return "";
112 else
113 return tic6x_register_names[regno];
114}
115
116/* This is the implementation of gdbarch method register_type. */
117
118static struct type *
119tic6x_register_type (struct gdbarch *gdbarch, int regno)
120{
121
122 if (regno == TIC6X_PC_REGNUM)
123 return builtin_type (gdbarch)->builtin_func_ptr;
124 else
125 return builtin_type (gdbarch)->builtin_uint32;
126}
127
128static void
129tic6x_setup_default (struct tic6x_unwind_cache *cache)
130{
131 int i;
132
133 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
134 cache->reg_saved[i] = -1;
135}
136
137static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
138static int tic6x_register_number (int reg, int side, int crosspath);
139
140/* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
141 Bail out early if CURRENT_PC is reached. Returns the address of the first
142 instruction after the prologue. */
143
693be288 144static CORE_ADDR
8cd64e00
YQ		 145tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
146 const CORE_ADDR current_pc,
147 struct tic6x_unwind_cache *cache,
148 struct frame_info *this_frame)
149{
8cd64e00
YQ		 150 unsigned int src_reg, base_reg, dst_reg;
151 int i;
152 CORE_ADDR pc = start_pc;
153 CORE_ADDR return_pc = start_pc;
154 int frame_base_offset_to_sp = 0;
155 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
156 int non_stw_insn_counter = 0;
157
158 if (start_pc >= current_pc)
159 return_pc = current_pc;
160
161 cache->base = 0;
162
163 /* The landmarks in prologue is one or two SUB instructions to SP.
164 Instructions on setting up dsbt are in the last part of prologue, if
165 needed. In maxim, prologue can be divided to three parts by two
166 `sub sp, xx, sp' insns. */
167
168 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
169 2nd one is optional. */
170 while (pc < current_pc)
171 {
8cd64e00
YQ		 172 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
173
174 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
175 || (inst & 0x0ffc) == 0x9c0)
176 {
177 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
178 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
179 INST_S_BIT (inst), 0);
180 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
181 INST_S_BIT (inst), 0);
182
183 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
184 {
185 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
186 offset. The constant offset is decoded in bit 13-17 in all
187 these three kinds of instructions. */
188 unsigned int ucst5 = (inst >> 13) & 0x1f;
189
190 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */
191 frame_base_offset_to_sp += ucst5 << 2;
192 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */
193 frame_base_offset_to_sp += ucst5 << 1;
194 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */
195 frame_base_offset_to_sp += ucst5;
196 else
197 gdb_assert_not_reached ("unexpected instruction");
198
199 return_pc = pc + 4;
200 }
201 }
202 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
203 {
204 /* The y bit determines which file base is read from. */
205 base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
206 (inst >> 7) & 1, 0);
207
208 if (base_reg == TIC6X_SP_REGNUM)
209 {
210 src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
211 INST_S_BIT (inst), 0);
212
213 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;
214
215 return_pc = pc + 4;
216 }
217 non_stw_insn_counter = 0;
218 }
219 else
220 {
221 non_stw_insn_counter++;
222 /* Following instruction sequence may be emitted in prologue:
223
224 <+0>: subah .D2 b15,28,b15
225 <+4>: or .L2X 0,a4,b0
226 <+8>: || stw .D2T2 b14,*+b15(56)
227 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
228 <+16>:|| stw .D2T1 a10,*+b15(48)
229 <+20>:stw .D2T2 b3,*+b15(52)
230 <+24>:stw .D2T1 a4,*+b15(40)
231
232 we should look forward for next instruction instead of breaking loop
233 here. So far, we allow almost two sequential non-stw instructions
234 in prologue. */
235 if (non_stw_insn_counter >= 2)
236 break;
237 }
238
239
240 pc += 4;
241 }
242 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
243 ldw .D2T2 *+b14(0),b14 */
b926417a 244 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
8cd64e00
YQ		 245 /* The s bit determines which file dst will be loaded into, same effect as
246 other places. */
247 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
248 /* The y bit (bit 7), instead of s bit, determines which file base be
249 used. */
250 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);
251
252 if ((inst & 0x164) == 0x64 /* ldw */
253 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */
254 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */
255 {
256 return_pc = pc + 4;
257 }
258
259 if (this_frame)
260 {
261 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
262
263 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
264 {
265 /* If the FP now holds an offset from the CFA then this is a frame
266 which uses the frame pointer. */
267
268 cache->cfa = get_frame_register_unsigned (this_frame,
269 TIC6X_FP_REGNUM);
270 }
271 else
272 {
273 /* FP doesn't hold an offset from the CFA. If SP still holds an
274 offset from the CFA then we might be in a function which omits
275 the frame pointer. */
276
277 cache->cfa = cache->base + frame_base_offset_to_sp;
278 }
279 }
280
281 /* Adjust all the saved registers such that they contain addresses
282 instead of offsets. */
283 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
284 if (cache->reg_saved[i] != -1)
285 cache->reg_saved[i] = cache->base + cache->reg_saved[i];
286
287 return return_pc;
288}
289
290/* This is the implementation of gdbarch method skip_prologue. */
291
693be288 292static CORE_ADDR
8cd64e00
YQ		 293tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
294{
8cd64e00
YQ		 295 CORE_ADDR func_addr;
296 struct tic6x_unwind_cache cache;
297
298 /* See if we can determine the end of the prologue via the symbol table.
299 If so, then return either PC, or the PC after the prologue, whichever is
300 greater. */
301 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
302 {
303 CORE_ADDR post_prologue_pc
304 = skip_prologue_using_sal (gdbarch, func_addr);
305 if (post_prologue_pc != 0)
325fac50 306 return std::max (start_pc, post_prologue_pc);
8cd64e00
YQ		 307 }
308
309 /* Can't determine prologue from the symbol table, need to examine
310 instructions. */
311 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
312 NULL);
313}
314
cd6c3b4f
YQ		 315/* Implement the breakpoint_kind_from_pc gdbarch method. */
316
d19280ad
YQ		 317static int
318tic6x_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
319{
320 return 4;
321}
8cd64e00 322
cd6c3b4f
YQ		 323/* Implement the sw_breakpoint_from_kind gdbarch method. */
324
948f8e3d 325static const gdb_byte *
d19280ad 326tic6x_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
8cd64e00
YQ		 327{
328 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
329
d19280ad 330 *size = kind;
8cd64e00
YQ		 331
332 if (tdep == NULL || tdep->breakpoint == NULL)
333 {
334 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
335 return tic6x_bkpt_illegal_opcode_be;
336 else
337 return tic6x_bkpt_illegal_opcode_le;
338 }
339 else
340 return tdep->breakpoint;
341}
342
8cd64e00
YQ		 343static void
344tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
345 struct dwarf2_frame_state_reg *reg,
346 struct frame_info *this_frame)
347{
348 /* Mark the PC as the destination for the return address. */
349 if (regnum == gdbarch_pc_regnum (gdbarch))
350 reg->how = DWARF2_FRAME_REG_RA;
351
352 /* Mark the stack pointer as the call frame address. */
353 else if (regnum == gdbarch_sp_regnum (gdbarch))
354 reg->how = DWARF2_FRAME_REG_CFA;
355
356 /* The above was taken from the default init_reg in dwarf2-frame.c
357 while the below is c6x specific. */
358
359 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
360 callee-save. */
361 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
362 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
363 else
364 /* All other registers are caller-save. */
365 reg->how = DWARF2_FRAME_REG_UNDEFINED;
366}
367
368/* This is the implementation of gdbarch method unwind_pc. */
369
370static CORE_ADDR
371tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
372{
373 gdb_byte buf[8];
374
375 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf);
376 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
377}
378
8cd64e00
YQ		 379/* Frame base handling. */
380
693be288 381static struct tic6x_unwind_cache*
8cd64e00
YQ		 382tic6x_frame_unwind_cache (struct frame_info *this_frame,
383 void **this_prologue_cache)
384{
385 struct gdbarch *gdbarch = get_frame_arch (this_frame);
386 CORE_ADDR current_pc;
387 struct tic6x_unwind_cache *cache;
8cd64e00
YQ		 388
389 if (*this_prologue_cache)
19ba03f4 390 return (struct tic6x_unwind_cache *) *this_prologue_cache;
8cd64e00
YQ		 391
392 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
393 (*this_prologue_cache) = cache;
394
395 cache->return_regnum = TIC6X_RA_REGNUM;
396
397 tic6x_setup_default (cache);
398
399 cache->pc = get_frame_func (this_frame);
400 current_pc = get_frame_pc (this_frame);
401
402 /* Prologue analysis does the rest... */
403 if (cache->pc != 0)
404 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
405
406 return cache;
407}
408
409static void
410tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
411 struct frame_id *this_id)
412{
413 struct tic6x_unwind_cache *cache =
414 tic6x_frame_unwind_cache (this_frame, this_cache);
415
416 /* This marks the outermost frame. */
417 if (cache->base == 0)
418 return;
419
420 (*this_id) = frame_id_build (cache->cfa, cache->pc);
421}
422
423static struct value *
424tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
425 int regnum)
426{
427 struct tic6x_unwind_cache *cache =
428 tic6x_frame_unwind_cache (this_frame, this_cache);
429
430 gdb_assert (regnum >= 0);
431
432 /* The PC of the previous frame is stored in the RA register of
433 the current frame. Frob regnum so that we pull the value from
434 the correct place. */
435 if (regnum == TIC6X_PC_REGNUM)
436 regnum = cache->return_regnum;
437
438 if (regnum == TIC6X_SP_REGNUM && cache->cfa)
439 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
440
441 /* If we've worked out where a register is stored then load it from
442 there. */
443 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
444 return frame_unwind_got_memory (this_frame, regnum,
445 cache->reg_saved[regnum]);
446
447 return frame_unwind_got_register (this_frame, regnum, regnum);
448}
449
450static CORE_ADDR
451tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
452{
453 struct tic6x_unwind_cache *info
454 = tic6x_frame_unwind_cache (this_frame, this_cache);
455 return info->base;
456}
457
458static const struct frame_unwind tic6x_frame_unwind =
459{
a154d838 460 "tic6x prologue",
8cd64e00
YQ		 461 NORMAL_FRAME,
462 default_frame_unwind_stop_reason,
463 tic6x_frame_this_id,
464 tic6x_frame_prev_register,
465 NULL,
466 default_frame_sniffer
467};
468
469static const struct frame_base tic6x_frame_base =
470{
471 &tic6x_frame_unwind,
472 tic6x_frame_base_address,
473 tic6x_frame_base_address,
474 tic6x_frame_base_address
475};
476
477
478static struct tic6x_unwind_cache *
479tic6x_make_stub_cache (struct frame_info *this_frame)
480{
481 struct tic6x_unwind_cache *cache;
482
483 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
484
485 cache->return_regnum = TIC6X_RA_REGNUM;
486
487 tic6x_setup_default (cache);
488
489 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
490
491 return cache;
492}
493
494static void
495tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
496 struct frame_id *this_id)
497{
498 struct tic6x_unwind_cache *cache;
499
500 if (*this_cache == NULL)
501 *this_cache = tic6x_make_stub_cache (this_frame);
19ba03f4 502 cache = (struct tic6x_unwind_cache *) *this_cache;
8cd64e00
YQ		 503
504 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
505}
506
507static int
508tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
509 struct frame_info *this_frame,
510 void **this_prologue_cache)
511{
512 CORE_ADDR addr_in_block;
513
514 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 515 if (in_plt_section (addr_in_block))
8cd64e00
YQ		 516 return 1;
517
518 return 0;
519}
520
521static const struct frame_unwind tic6x_stub_unwind =
522{
a154d838 523 "tic6x stub",
8cd64e00
YQ		 524 NORMAL_FRAME,
525 default_frame_unwind_stop_reason,
526 tic6x_stub_this_id,
527 tic6x_frame_prev_register,
528 NULL,
529 tic6x_stub_unwind_sniffer
530};
531
532/* Return the instruction on address PC. */
533
534static unsigned long
535tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
536{
537 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
538 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
539}
540
541/* Compute the condition of INST if it is a conditional instruction. Always
542 return 1 if INST is not a conditional instruction. */
543
544static int
fb090cfa 545tic6x_condition_true (struct regcache *regcache, unsigned long inst)
8cd64e00
YQ		 546{
547 int register_number;
548 int register_value;
549 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
550
551 register_number = register_numbers[(inst >> 29) & 7];
552 if (register_number == -1)
553 return 1;
554
fb090cfa 555 register_value = regcache_raw_get_signed (regcache, register_number);
8cd64e00
YQ		 556 if ((inst & 0x10000000) != 0)
557 return register_value == 0;
558 return register_value != 0;
559}
560
561/* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
562 instruction. */
563
564static int
565tic6x_register_number (int reg, int side, int crosspath)
566{
567 int r = (reg & 15) | ((crosspath ^ side) << 4);
568 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
569 r += 37;
570 return r;
571}
572
573static int
574tic6x_extract_signed_field (int value, int low_bit, int bits)
575{
576 int mask = (1 << bits) - 1;
577 int r = (value >> low_bit) & mask;
578 if ((r & (1 << (bits - 1))) != 0)
579 r -= mask + 1;
580 return r;
581}
582
583/* Determine where to set a single step breakpoint. */
584
585static CORE_ADDR
fb090cfa 586tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
8cd64e00 587{
ac7936df 588 struct gdbarch *gdbarch = regcache->arch ();
8cd64e00 589 unsigned long inst;
8cd64e00
YQ		 590 int register_number;
591 int last = 0;
592
593 do
594 {
595 inst = tic6x_fetch_instruction (gdbarch, pc);
596
597 last = !(inst & 1);
598
599 if (inst == TIC6X_INST_SWE)
600 {
601 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
602
603 if (tdep->syscall_next_pc != NULL)
fb090cfa 604 return tdep->syscall_next_pc (get_current_frame ());
8cd64e00
YQ		 605 }
606
fb090cfa 607 if (tic6x_condition_true (regcache, inst))
8cd64e00
YQ		 608 {
609 if ((inst & 0x0000007c) == 0x00000010)
610 {
611 /* B with displacement */
612 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
613 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
614 break;
615 }
616 if ((inst & 0x0f83effc) == 0x00000360)
617 {
618 /* B with register */
619
620 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
621 INST_S_BIT (inst),
622 INST_X_BIT (inst));
fb090cfa 623 pc = regcache_raw_get_unsigned (regcache, register_number);
8cd64e00
YQ		 624 break;
625 }
626 if ((inst & 0x00001ffc) == 0x00001020)
627 {
628 /* BDEC */
629 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
630 INST_S_BIT (inst), 0);
fb090cfa 631 if (regcache_raw_get_signed (regcache, register_number) >= 0)
8cd64e00
YQ		 632 {
633 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
634 pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
635 }
636 break;
637 }
638 if ((inst & 0x00001ffc) == 0x00000120)
639 {
640 /* BNOP with displacement */
641 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
642 pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
643 break;
644 }
645 if ((inst & 0x0f830ffe) == 0x00800362)
646 {
647 /* BNOP with register */
648 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
649 1, INST_X_BIT (inst));
fb090cfa 650 pc = regcache_raw_get_unsigned (regcache, register_number);
8cd64e00
YQ		 651 break;
652 }
653 if ((inst & 0x00001ffc) == 0x00000020)
654 {
655 /* BPOS */
656 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
657 INST_S_BIT (inst), 0);
fb090cfa 658 if (regcache_raw_get_signed (regcache, register_number) >= 0)
8cd64e00
YQ		 659 {
660 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
661 pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
662 }
663 break;
664 }
665 if ((inst & 0xf000007c) == 0x10000010)
666 {
667 /* CALLP */
668 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
669 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
670 break;
671 }
672 }
673 pc += TIC6X_OPCODE_SIZE;
674 }
675 while (!last);
676 return pc;
677}
678
679/* This is the implementation of gdbarch method software_single_step. */
680
a0ff9e1a 681static std::vector<CORE_ADDR>
f5ea389a 682tic6x_software_single_step (struct regcache *regcache)
8cd64e00 683{
fb090cfa 684 CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache));
8cd64e00 685
a0ff9e1a 686 return {next_pc};
8cd64e00
YQ		 687}
688
689/* This is the implementation of gdbarch method frame_align. */
690
691static CORE_ADDR
692tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
693{
694 return align_down (addr, 8);
695}
696
8cd64e00
YQ		 697/* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
698 value into VALBUF. */
699
700static void
701tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
702 enum bfd_endian byte_order, gdb_byte *valbuf)
703{
704 int len = TYPE_LENGTH (valtype);
705
706 /* pointer types are returned in register A4,
707 up to 32-bit types in A4
708 up to 64-bit types in A5:A4 */
709 if (len <= 4)
710 {
711 /* In big-endian,
712 - one-byte structure or union occupies the LSB of single even register.
713 - for two-byte structure or union, the first byte occupies byte 1 of
714 register and the second byte occupies byte 0.
715 so, we read the contents in VAL from the LSBs of register. */
716 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
73bb0000 717 regcache->cooked_read_part (TIC6X_A4_REGNUM, 4 - len, len, valbuf);
8cd64e00 718 else
dca08e1f 719 regcache->cooked_read (TIC6X_A4_REGNUM, valbuf);
8cd64e00
YQ		 720 }
721 else if (len <= 8)
722 {
723 /* For a 5-8 byte structure or union in big-endian, the first byte
724 occupies byte 3 (the MSB) of the upper (odd) register and the
725 remaining bytes fill the decreasingly significant bytes. 5-7
726 byte structures or unions have padding in the LSBs of the
727 lower (even) register. */
728 if (byte_order == BFD_ENDIAN_BIG)
729 {
dca08e1f
SM		 730 regcache->cooked_read (TIC6X_A4_REGNUM, valbuf + 4);
731 regcache->cooked_read (TIC6X_A5_REGNUM, valbuf);
8cd64e00
YQ		 732 }
733 else
734 {
dca08e1f
SM		 735 regcache->cooked_read (TIC6X_A4_REGNUM, valbuf);
736 regcache->cooked_read (TIC6X_A5_REGNUM, valbuf + 4);
8cd64e00
YQ		 737 }
738 }
739}
740
741/* Write into appropriate registers a function return value
742 of type TYPE, given in virtual format. */
743
744static void
745tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
746 enum bfd_endian byte_order, const gdb_byte *valbuf)
747{
748 int len = TYPE_LENGTH (valtype);
749
750 /* return values of up to 8 bytes are returned in A5:A4 */
751
752 if (len <= 4)
753 {
754 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
e4c4a59b 755 regcache->cooked_write_part (TIC6X_A4_REGNUM, 4 - len, len, valbuf);
8cd64e00 756 else
b66f5587 757 regcache->cooked_write (TIC6X_A4_REGNUM, valbuf);
8cd64e00
YQ		 758 }
759 else if (len <= 8)
760 {
761 if (byte_order == BFD_ENDIAN_BIG)
762 {
b66f5587
SM		 763 regcache->cooked_write (TIC6X_A4_REGNUM, valbuf + 4);
764 regcache->cooked_write (TIC6X_A5_REGNUM, valbuf);
8cd64e00
YQ		 765 }
766 else
767 {
b66f5587
SM		 768 regcache->cooked_write (TIC6X_A4_REGNUM, valbuf);
769 regcache->cooked_write (TIC6X_A5_REGNUM, valbuf + 4);
8cd64e00
YQ		 770 }
771 }
772}
773
774/* This is the implementation of gdbarch method return_value. */
775
776static enum return_value_convention
6a3a010b 777tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
8cd64e00
YQ		 778 struct type *type, struct regcache *regcache,
779 gdb_byte *readbuf, const gdb_byte *writebuf)
780{
18648a37
YQ		 781 /* In C++, when function returns an object, even its size is small
782 enough, it stii has to be passed via reference, pointed by register
783 A3. */
784 if (current_language->la_language == language_cplus)
785 {
786 if (type != NULL)
787 {
f168693b 788 type = check_typedef (type);
9d084466 789 if (!(language_pass_by_reference (type).trivially_copyable))
18648a37
YQ		 790 return RETURN_VALUE_STRUCT_CONVENTION;
791 }
792 }
793
8cd64e00
YQ		 794 if (TYPE_LENGTH (type) > 8)
795 return RETURN_VALUE_STRUCT_CONVENTION;
796
797 if (readbuf)
798 tic6x_extract_return_value (type, regcache,
799 gdbarch_byte_order (gdbarch), readbuf);
800 if (writebuf)
801 tic6x_store_return_value (type, regcache,
802 gdbarch_byte_order (gdbarch), writebuf);
803
804 return RETURN_VALUE_REGISTER_CONVENTION;
805}
806
8cd64e00
YQ		 807/* Get the alignment requirement of TYPE. */
808
809static int
810tic6x_arg_type_alignment (struct type *type)
811{
812 int len = TYPE_LENGTH (check_typedef (type));
78134374 813 enum type_code typecode = check_typedef (type)->code ();
8cd64e00
YQ		 814
815 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
816 {
817 /* The stack alignment of a structure (and union) passed by value is the
818 smallest power of two greater than or equal to its size.
819 This cannot exceed 8 bytes, which is the largest allowable size for
820 a structure passed by value. */
821
822 if (len <= 2)
823 return len;
824 else if (len <= 4)
825 return 4;
826 else if (len <= 8)
827 return 8;
828 else
829 gdb_assert_not_reached ("unexpected length of data");
830 }
831 else
832 {
833 if (len <= 4)
834 return 4;
835 else if (len == 8)
836 {
837 if (typecode == TYPE_CODE_COMPLEX)
838 return 4;
839 else
840 return 8;
841 }
842 else if (len == 16)
843 {
844 if (typecode == TYPE_CODE_COMPLEX)
845 return 8;
846 else
847 return 16;
848 }
849 else
850 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
851 len);
852 }
853}
854
855/* This is the implementation of gdbarch method push_dummy_call. */
856
857static CORE_ADDR
858tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
859 struct regcache *regcache, CORE_ADDR bp_addr,
860 int nargs, struct value **args, CORE_ADDR sp,
cf84fa6b
AH		 861 function_call_return_method return_method,
862 CORE_ADDR struct_addr)
8cd64e00
YQ		 863{
864 int argreg = 0;
865 int argnum;
8cd64e00
YQ		 866 int stack_offset = 4;
867 int references_offset = 4;
8cd64e00
YQ		 868 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
869 struct type *func_type = value_type (function);
870 /* The first arg passed on stack. Mostly the first 10 args are passed by
871 registers. */
872 int first_arg_on_stack = 10;
8cd64e00 873
8cd64e00
YQ		 874 /* Set the return address register to point to the entry point of
875 the program, where a breakpoint lies in wait. */
876 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);
877
878 /* The caller must pass an argument in A3 containing a destination address
879 for the returned value. The callee returns the object by copying it to
880 the address in A3. */
cf84fa6b 881 if (return_method == return_method_struct)
8cd64e00 882 regcache_cooked_write_unsigned (regcache, 3, struct_addr);
8cd64e00
YQ		 883
884 /* Determine the type of this function. */
885 func_type = check_typedef (func_type);
78134374 886 if (func_type->code () == TYPE_CODE_PTR)
8cd64e00
YQ		 887 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
888
78134374
SM		 889 gdb_assert (func_type->code () == TYPE_CODE_FUNC
890 || func_type->code () == TYPE_CODE_METHOD);
8cd64e00
YQ		 891
892 /* For a variadic C function, the last explicitly declared argument and all
893 remaining arguments are passed on the stack. */
a409645d 894 if (func_type->has_varargs ())
1f704f76 895 first_arg_on_stack = func_type->num_fields () - 1;
8cd64e00 896
18648a37
YQ		 897 /* Now make space on the stack for the args. */
898 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 899 {
900 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
901 if (argnum >= 10 - argreg)
902 references_offset += len;
903 stack_offset += len;
904 }
905 sp -= stack_offset;
906 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
907 Stack Alignment. */
908 sp = align_down (sp, 8);
909 stack_offset = 4;
910
911 /* Now load as many as possible of the first arguments into
912 registers, and push the rest onto the stack. Loop through args
913 from first to last. */
18648a37 914 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 915 {
916 const gdb_byte *val;
917 struct value *arg = args[argnum];
918 struct type *arg_type = check_typedef (value_type (arg));
919 int len = TYPE_LENGTH (arg_type);
78134374 920 enum type_code typecode = arg_type->code ();
8cd64e00
YQ		 921
922 val = value_contents (arg);
923
924 /* Copy the argument to general registers or the stack in
dda83cd7 925 register-sized pieces. */
8cd64e00
YQ		 926 if (argreg < first_arg_on_stack)
927 {
928 if (len <= 4)
929 {
930 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
931 {
932 /* In big-endian,
933 - one-byte structure or union occupies the LSB of single
934 even register.
935 - for two-byte structure or union, the first byte
936 occupies byte 1 of register and the second byte occupies
937 byte 0.
938 so, we write the contents in VAL to the lsp of
939 register. */
940 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
e4c4a59b
SM		 941 regcache->cooked_write_part (arg_regs[argreg], 4 - len, len,
942 val);
8cd64e00 943 else
b66f5587 944 regcache->cooked_write (arg_regs[argreg], val);
8cd64e00
YQ		 945 }
946 else
947 {
948 /* The argument is being passed by value in a single
949 register. */
950 CORE_ADDR regval = extract_unsigned_integer (val, len,
951 byte_order);
952
953 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
954 regval);
955 }
956 }
957 else
958 {
959 if (len <= 8)
960 {
961 if (typecode == TYPE_CODE_STRUCT
962 || typecode == TYPE_CODE_UNION)
963 {
964 /* For a 5-8 byte structure or union in big-endian, the
dda83cd7
SM		 965 first byte occupies byte 3 (the MSB) of the upper (odd)
966 register and the remaining bytes fill the decreasingly
967 significant bytes. 5-7 byte structures or unions have
968 padding in the LSBs of the lower (even) register. */
8cd64e00
YQ		 969 if (byte_order == BFD_ENDIAN_BIG)
970 {
b66f5587 971 regcache->cooked_write (arg_regs[argreg] + 1, val);
e4c4a59b
SM		 972 regcache->cooked_write_part (arg_regs[argreg], 0,
973 len - 4, val + 4);
8cd64e00
YQ		 974 }
975 else
976 {
b66f5587 977 regcache->cooked_write (arg_regs[argreg], val);
e4c4a59b
SM		 978 regcache->cooked_write_part (arg_regs[argreg] + 1, 0,
979 len - 4, val + 4);
8cd64e00
YQ		 980 }
981 }
982 else
983 {
984 /* The argument is being passed by value in a pair of
dda83cd7 985 registers. */
8cd64e00
YQ		 986 ULONGEST regval = extract_unsigned_integer (val, len,
987 byte_order);
988
989 regcache_cooked_write_unsigned (regcache,
990 arg_regs[argreg],
991 regval);
992 regcache_cooked_write_unsigned (regcache,
993 arg_regs[argreg] + 1,
994 regval >> 32);
995 }
996 }
997 else
998 {
999 /* The argument is being passed by reference in a single
1000 register. */
1001 CORE_ADDR addr;
1002
1003 /* It is not necessary to adjust REFERENCES_OFFSET to
1004 8-byte aligned in some cases, in which 4-byte alignment
1005 is sufficient. For simplicity, we adjust
1006 REFERENCES_OFFSET to 8-byte aligned. */
1007 references_offset = align_up (references_offset, 8);
1008
1009 addr = sp + references_offset;
1010 write_memory (addr, val, len);
1011 references_offset += align_up (len, 4);
1012 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
1013 addr);
1014 }
1015 }
1016 argreg++;
1017 }
1018 else
1019 {
1020 /* The argument is being passed on the stack. */
1021 CORE_ADDR addr;
1022
1023 /* There are six different cases of alignment, and these rules can
1024 be found in tic6x_arg_type_alignment:
1025
1026 1) 4-byte aligned if size is less than or equal to 4 byte, such
1027 as short, int, struct, union etc.
1028 2) 8-byte aligned if size is less than or equal to 8-byte, such
1029 as double, long long,
1030 3) 4-byte aligned if it is of type _Complex float, even its size
1031 is 8-byte.
1032 4) 8-byte aligned if it is of type _Complex double or _Complex
1033 long double, even its size is 16-byte. Because, the address of
1034 variable is passed as reference.
1035 5) struct and union larger than 8-byte are passed by reference, so
1036 it is 4-byte aligned.
1037 6) struct and union of size between 4 byte and 8 byte varies.
1038 alignment of struct variable is the alignment of its first field,
1039 while alignment of union variable is the max of all its fields'
1040 alignment. */
1041
1042 if (len <= 4)
1043 ; /* Default is 4-byte aligned. Nothing to be done. */
1044 else if (len <= 8)
1045 stack_offset = align_up (stack_offset,
1046 tic6x_arg_type_alignment (arg_type));
1047 else if (len == 16)
1048 {
1049 /* _Complex double or _Complex long double */
1050 if (typecode == TYPE_CODE_COMPLEX)
1051 {
1052 /* The argument is being passed by reference on stack. */
8cd64e00
YQ		 1053 references_offset = align_up (references_offset, 8);
1054
1055 addr = sp + references_offset;
1056 /* Store variable on stack. */
1057 write_memory (addr, val, len);
1058
1059 references_offset += align_up (len, 4);
1060
1061 /* Pass the address of variable on stack as reference. */
1062 store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
1063 addr);
1064 len = 4;
1065
1066 }
1067 else
1068 internal_error (__FILE__, __LINE__,
1069 _("unexpected type %d of arg %d"),
1070 typecode, argnum);
1071 }
1072 else
1073 internal_error (__FILE__, __LINE__,
1074 _("unexpected length %d of arg %d"), len, argnum);
1075
1076 addr = sp + stack_offset;
1077 write_memory (addr, val, len);
1078 stack_offset += align_up (len, 4);
1079 }
1080 }
1081
1082 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);
1083
1084 /* Return adjusted stack pointer. */
1085 return sp;
1086}
1087
c9cf6e20 1088/* This is the implementation of gdbarch method stack_frame_destroyed_p. */
8cd64e00
YQ		 1089
1090static int
c9cf6e20 1091tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
8cd64e00
YQ		 1092{
1093 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
1094 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1095 if ((inst & 0x0f83effc) == 0x360)
1096 {
1097 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
1098 INST_S_BIT (inst),
1099 INST_X_BIT (inst));
1100 if (src2 == TIC6X_RA_REGNUM)
1101 return 1;
1102 }
1103
1104 return 0;
1105}
1106
1107/* This is the implementation of gdbarch method get_longjmp_target. */
1108
1109static int
1110tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1111{
1112 struct gdbarch *gdbarch = get_frame_arch (frame);
1113 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1114 CORE_ADDR jb_addr;
e362b510 1115 gdb_byte buf[4];
8cd64e00
YQ		 1116
1117 /* JMP_BUF is passed by reference in A4. */
1118 jb_addr = get_frame_register_unsigned (frame, 4);
1119
1120 /* JMP_BUF contains 13 elements of type int, and return address is stored
1121 in the last slot. */
1122 if (target_read_memory (jb_addr + 12 * 4, buf, 4))
1123 return 0;
1124
1125 *pc = extract_unsigned_integer (buf, 4, byte_order);
1126
1127 return 1;
1128}
1129
18648a37
YQ		 1130/* This is the implementation of gdbarch method
1131 return_in_first_hidden_param_p. */
1132
1133static int
1134tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
1135 struct type *type)
1136{
1137 return 0;
1138}
1139
8cd64e00
YQ		 1140static struct gdbarch *
1141tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1142{
1143 struct gdbarch *gdbarch;
1144 struct gdbarch_tdep *tdep;
c1e1314d 1145 tdesc_arch_data_up tdesc_data;
8cd64e00
YQ		 1146 const struct target_desc *tdesc = info.target_desc;
1147 int has_gp = 0;
1148
1149 /* Check any target description for validity. */
1150 if (tdesc_has_registers (tdesc))
1151 {
1152 const struct tdesc_feature *feature;
1153 int valid_p, i;
1154
1155 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");
1156
1157 if (feature == NULL)
1158 return NULL;
1159
1160 tdesc_data = tdesc_data_alloc ();
1161
1162 valid_p = 1;
1163 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */
c1e1314d 1164 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
8cd64e00
YQ		 1165 tic6x_register_names[i]);
1166
1167 /* CSR */
c1e1314d 1168 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i++,
8cd64e00 1169 tic6x_register_names[TIC6X_CSR_REGNUM]);
c1e1314d 1170 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i++,
8cd64e00
YQ		 1171 tic6x_register_names[TIC6X_PC_REGNUM]);
1172
1173 if (!valid_p)
c1e1314d 1174 return NULL;
8cd64e00
YQ		 1175
1176 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
1177 if (feature)
1178 {
1179 int j = 0;
1180 static const char *const gp[] =
1181 {
1182 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1183 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1184 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1185 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1186 };
1187
1188 has_gp = 1;
1189 valid_p = 1;
1190 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */
c1e1314d
TT		 1191 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
1192 i++, gp[j]);
8cd64e00
YQ		 1193
1194 if (!valid_p)
c1e1314d 1195 return NULL;
8cd64e00
YQ		 1196 }
1197
1198 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
1199 if (feature)
1200 {
c1e1314d
TT		 1201 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
1202 i++, "TSR");
1203 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
1204 i++, "ILC");
1205 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
1206 i++, "RILC");
8cd64e00
YQ		 1207
1208 if (!valid_p)
c1e1314d 1209 return NULL;
8cd64e00
YQ		 1210 }
1211
1212 }
1213
1214 /* Find a candidate among extant architectures. */
1215 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1216 arches != NULL;
1217 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1218 {
1219 tdep = gdbarch_tdep (arches->gdbarch);
1220
1221 if (has_gp != tdep->has_gp)
1222 continue;
1223
1224 if (tdep && tdep->breakpoint)
1225 return arches->gdbarch;
1226 }
1227
8d749320 1228 tdep = XCNEW (struct gdbarch_tdep);
8cd64e00
YQ		 1229
1230 tdep->has_gp = has_gp;
1231 gdbarch = gdbarch_alloc (&info, tdep);
1232
1233 /* Data type sizes. */
1234 set_gdbarch_ptr_bit (gdbarch, 32);
1235 set_gdbarch_addr_bit (gdbarch, 32);
1236 set_gdbarch_short_bit (gdbarch, 16);
1237 set_gdbarch_int_bit (gdbarch, 32);
1238 set_gdbarch_long_bit (gdbarch, 32);
1239 set_gdbarch_long_long_bit (gdbarch, 64);
1240 set_gdbarch_float_bit (gdbarch, 32);
1241 set_gdbarch_double_bit (gdbarch, 64);
1242
1243 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1244 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1245
1246 /* The register set. */
1247 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
1248 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
1249 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);
1250
1251 set_gdbarch_register_name (gdbarch, tic6x_register_name);
1252 set_gdbarch_register_type (gdbarch, tic6x_register_type);
1253
1254 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1255
1256 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
04180708
YQ		 1257 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1258 tic6x_breakpoint_kind_from_pc);
1259 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1260 tic6x_sw_breakpoint_from_kind);
8cd64e00
YQ		 1261
1262 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
8cd64e00
YQ		 1263
1264 /* Unwinding. */
1265 dwarf2_append_unwinders (gdbarch);
1266
1267 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
1268 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
195abc10 1269 frame_base_set_default (gdbarch, &tic6x_frame_base);
8cd64e00
YQ		 1270
1271 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);
1272
1273 /* Single stepping. */
1274 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);
1275
8cd64e00
YQ		 1276 /* Call dummy code. */
1277 set_gdbarch_frame_align (gdbarch, tic6x_frame_align);
1278
8cd64e00
YQ		 1279 set_gdbarch_return_value (gdbarch, tic6x_return_value);
1280
8cd64e00
YQ		 1281 /* Enable inferior call support. */
1282 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);
1283
1284 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);
1285
c9cf6e20 1286 set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p);
8cd64e00 1287
18648a37
YQ		 1288 set_gdbarch_return_in_first_hidden_param_p (gdbarch,
1289 tic6x_return_in_first_hidden_param_p);
1290
8cd64e00
YQ		 1291 /* Hook in ABI-specific overrides, if they have been registered. */
1292 gdbarch_init_osabi (info, gdbarch);
1293
c1e1314d
TT		 1294 if (tdesc_data != nullptr)
1295 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
8cd64e00
YQ		 1296
1297 return gdbarch;
1298}
1299
6c265988 1300void _initialize_tic6x_tdep ();
8cd64e00 1301void
6c265988 1302_initialize_tic6x_tdep ()
8cd64e00
YQ		 1303{
1304 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);
8cd64e00 1305}
GDB Binutils - Deliverables
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