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Use enum for return method for dummy calls
[deliverable/binutils-gdb.git] / gdb / tic6x-tdep.c
CommitLineData
8cd64e00
YQ		 1/* Target dependent code for GDB on TI C6x systems.
2
e2882c85 3 Copyright (C) 2010-2018 Free Software Foundation, Inc.
8cd64e00
YQ		 4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "frame.h"
24#include "frame-unwind.h"
25#include "frame-base.h"
26#include "trad-frame.h"
27#include "dwarf2-frame.h"
28#include "symtab.h"
29#include "inferior.h"
30#include "gdbtypes.h"
31#include "gdbcore.h"
32#include "gdbcmd.h"
33#include "target.h"
34#include "dis-asm.h"
35#include "regcache.h"
36#include "value.h"
37#include "symfile.h"
38#include "arch-utils.h"
8cd64e00
YQ		 39#include "glibc-tdep.h"
40#include "infcall.h"
41#include "regset.h"
42#include "tramp-frame.h"
43#include "linux-tdep.h"
44#include "solib.h"
45#include "objfiles.h"
8cd64e00
YQ		 46#include "osabi.h"
47#include "tic6x-tdep.h"
48#include "language.h"
49#include "target-descriptions.h"
325fac50 50#include <algorithm>
8cd64e00 51
8cd64e00
YQ		 52#define TIC6X_OPCODE_SIZE 4
53#define TIC6X_FETCH_PACKET_SIZE 32
54
55#define INST_S_BIT(INST) ((INST >> 1) & 1)
56#define INST_X_BIT(INST) ((INST >> 12) & 1)
57
85661b1e
YQ		 58const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
59const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };
60
8cd64e00
YQ		 61struct tic6x_unwind_cache
62{
63 /* The frame's base, optionally used by the high-level debug info. */
64 CORE_ADDR base;
65
66 /* The previous frame's inner most stack address. Used as this
67 frame ID's stack_addr. */
68 CORE_ADDR cfa;
69
70 /* The address of the first instruction in this function */
71 CORE_ADDR pc;
72
73 /* Which register holds the return address for the frame. */
74 int return_regnum;
75
76 /* The offset of register saved on stack. If register is not saved, the
77 corresponding element is -1. */
78 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
79};
80
81
82/* Name of TI C6x core registers. */
83static const char *const tic6x_register_names[] =
84{
85 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
86 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
87 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
88 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
89 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
90 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
91 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
92 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
93 "CSR", "PC", /* 32 33 */
94};
95
96/* This array maps the arguments to the register number which passes argument
97 in function call according to C6000 ELF ABI. */
98static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
99
100/* This is the implementation of gdbarch method register_name. */
101
102static const char *
103tic6x_register_name (struct gdbarch *gdbarch, int regno)
104{
105 if (regno < 0)
106 return NULL;
107
108 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
109 return tdesc_register_name (gdbarch, regno);
110 else if (regno >= ARRAY_SIZE (tic6x_register_names))
111 return "";
112 else
113 return tic6x_register_names[regno];
114}
115
116/* This is the implementation of gdbarch method register_type. */
117
118static struct type *
119tic6x_register_type (struct gdbarch *gdbarch, int regno)
120{
121
122 if (regno == TIC6X_PC_REGNUM)
123 return builtin_type (gdbarch)->builtin_func_ptr;
124 else
125 return builtin_type (gdbarch)->builtin_uint32;
126}
127
128static void
129tic6x_setup_default (struct tic6x_unwind_cache *cache)
130{
131 int i;
132
133 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
134 cache->reg_saved[i] = -1;
135}
136
137static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
138static int tic6x_register_number (int reg, int side, int crosspath);
139
140/* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
141 Bail out early if CURRENT_PC is reached. Returns the address of the first
142 instruction after the prologue. */
143
693be288 144static CORE_ADDR
8cd64e00
YQ		 145tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
146 const CORE_ADDR current_pc,
147 struct tic6x_unwind_cache *cache,
148 struct frame_info *this_frame)
149{
8cd64e00
YQ		 150 unsigned int src_reg, base_reg, dst_reg;
151 int i;
152 CORE_ADDR pc = start_pc;
153 CORE_ADDR return_pc = start_pc;
154 int frame_base_offset_to_sp = 0;
155 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
156 int non_stw_insn_counter = 0;
157
158 if (start_pc >= current_pc)
159 return_pc = current_pc;
160
161 cache->base = 0;
162
163 /* The landmarks in prologue is one or two SUB instructions to SP.
164 Instructions on setting up dsbt are in the last part of prologue, if
165 needed. In maxim, prologue can be divided to three parts by two
166 `sub sp, xx, sp' insns. */
167
168 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
169 2nd one is optional. */
170 while (pc < current_pc)
171 {
8cd64e00
YQ		 172 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
173
174 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
175 || (inst & 0x0ffc) == 0x9c0)
176 {
177 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
178 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
179 INST_S_BIT (inst), 0);
180 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
181 INST_S_BIT (inst), 0);
182
183 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
184 {
185 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
186 offset. The constant offset is decoded in bit 13-17 in all
187 these three kinds of instructions. */
188 unsigned int ucst5 = (inst >> 13) & 0x1f;
189
190 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */
191 frame_base_offset_to_sp += ucst5 << 2;
192 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */
193 frame_base_offset_to_sp += ucst5 << 1;
194 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */
195 frame_base_offset_to_sp += ucst5;
196 else
197 gdb_assert_not_reached ("unexpected instruction");
198
199 return_pc = pc + 4;
200 }
201 }
202 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
203 {
204 /* The y bit determines which file base is read from. */
205 base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
206 (inst >> 7) & 1, 0);
207
208 if (base_reg == TIC6X_SP_REGNUM)
209 {
210 src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
211 INST_S_BIT (inst), 0);
212
213 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;
214
215 return_pc = pc + 4;
216 }
217 non_stw_insn_counter = 0;
218 }
219 else
220 {
221 non_stw_insn_counter++;
222 /* Following instruction sequence may be emitted in prologue:
223
224 <+0>: subah .D2 b15,28,b15
225 <+4>: or .L2X 0,a4,b0
226 <+8>: || stw .D2T2 b14,*+b15(56)
227 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
228 <+16>:|| stw .D2T1 a10,*+b15(48)
229 <+20>:stw .D2T2 b3,*+b15(52)
230 <+24>:stw .D2T1 a4,*+b15(40)
231
232 we should look forward for next instruction instead of breaking loop
233 here. So far, we allow almost two sequential non-stw instructions
234 in prologue. */
235 if (non_stw_insn_counter >= 2)
236 break;
237 }
238
239
240 pc += 4;
241 }
242 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
243 ldw .D2T2 *+b14(0),b14 */
b926417a 244 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
8cd64e00
YQ		 245 /* The s bit determines which file dst will be loaded into, same effect as
246 other places. */
247 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
248 /* The y bit (bit 7), instead of s bit, determines which file base be
249 used. */
250 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);
251
252 if ((inst & 0x164) == 0x64 /* ldw */
253 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */
254 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */
255 {
256 return_pc = pc + 4;
257 }
258
259 if (this_frame)
260 {
261 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
262
263 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
264 {
265 /* If the FP now holds an offset from the CFA then this is a frame
266 which uses the frame pointer. */
267
268 cache->cfa = get_frame_register_unsigned (this_frame,
269 TIC6X_FP_REGNUM);
270 }
271 else
272 {
273 /* FP doesn't hold an offset from the CFA. If SP still holds an
274 offset from the CFA then we might be in a function which omits
275 the frame pointer. */
276
277 cache->cfa = cache->base + frame_base_offset_to_sp;
278 }
279 }
280
281 /* Adjust all the saved registers such that they contain addresses
282 instead of offsets. */
283 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
284 if (cache->reg_saved[i] != -1)
285 cache->reg_saved[i] = cache->base + cache->reg_saved[i];
286
287 return return_pc;
288}
289
290/* This is the implementation of gdbarch method skip_prologue. */
291
693be288 292static CORE_ADDR
8cd64e00
YQ		 293tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
294{
8cd64e00
YQ		 295 CORE_ADDR func_addr;
296 struct tic6x_unwind_cache cache;
297
298 /* See if we can determine the end of the prologue via the symbol table.
299 If so, then return either PC, or the PC after the prologue, whichever is
300 greater. */
301 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
302 {
303 CORE_ADDR post_prologue_pc
304 = skip_prologue_using_sal (gdbarch, func_addr);
305 if (post_prologue_pc != 0)
325fac50 306 return std::max (start_pc, post_prologue_pc);
8cd64e00
YQ		 307 }
308
309 /* Can't determine prologue from the symbol table, need to examine
310 instructions. */
311 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
312 NULL);
313}
314
cd6c3b4f
YQ		 315/* Implement the breakpoint_kind_from_pc gdbarch method. */
316
d19280ad
YQ		 317static int
318tic6x_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
319{
320 return 4;
321}
8cd64e00 322
cd6c3b4f
YQ		 323/* Implement the sw_breakpoint_from_kind gdbarch method. */
324
948f8e3d 325static const gdb_byte *
d19280ad 326tic6x_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
8cd64e00
YQ		 327{
328 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
329
d19280ad 330 *size = kind;
8cd64e00
YQ		 331
332 if (tdep == NULL || tdep->breakpoint == NULL)
333 {
334 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
335 return tic6x_bkpt_illegal_opcode_be;
336 else
337 return tic6x_bkpt_illegal_opcode_le;
338 }
339 else
340 return tdep->breakpoint;
341}
342
8cd64e00
YQ		 343static void
344tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
345 struct dwarf2_frame_state_reg *reg,
346 struct frame_info *this_frame)
347{
348 /* Mark the PC as the destination for the return address. */
349 if (regnum == gdbarch_pc_regnum (gdbarch))
350 reg->how = DWARF2_FRAME_REG_RA;
351
352 /* Mark the stack pointer as the call frame address. */
353 else if (regnum == gdbarch_sp_regnum (gdbarch))
354 reg->how = DWARF2_FRAME_REG_CFA;
355
356 /* The above was taken from the default init_reg in dwarf2-frame.c
357 while the below is c6x specific. */
358
359 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
360 callee-save. */
361 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
362 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
363 else
364 /* All other registers are caller-save. */
365 reg->how = DWARF2_FRAME_REG_UNDEFINED;
366}
367
368/* This is the implementation of gdbarch method unwind_pc. */
369
370static CORE_ADDR
371tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
372{
373 gdb_byte buf[8];
374
375 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf);
376 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
377}
378
379/* This is the implementation of gdbarch method unwind_sp. */
380
381static CORE_ADDR
382tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
383{
384 return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM);
385}
386
387
388/* Frame base handling. */
389
693be288 390static struct tic6x_unwind_cache*
8cd64e00
YQ		 391tic6x_frame_unwind_cache (struct frame_info *this_frame,
392 void **this_prologue_cache)
393{
394 struct gdbarch *gdbarch = get_frame_arch (this_frame);
395 CORE_ADDR current_pc;
396 struct tic6x_unwind_cache *cache;
8cd64e00
YQ		 397
398 if (*this_prologue_cache)
19ba03f4 399 return (struct tic6x_unwind_cache *) *this_prologue_cache;
8cd64e00
YQ		 400
401 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
402 (*this_prologue_cache) = cache;
403
404 cache->return_regnum = TIC6X_RA_REGNUM;
405
406 tic6x_setup_default (cache);
407
408 cache->pc = get_frame_func (this_frame);
409 current_pc = get_frame_pc (this_frame);
410
411 /* Prologue analysis does the rest... */
412 if (cache->pc != 0)
413 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
414
415 return cache;
416}
417
418static void
419tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
420 struct frame_id *this_id)
421{
422 struct tic6x_unwind_cache *cache =
423 tic6x_frame_unwind_cache (this_frame, this_cache);
424
425 /* This marks the outermost frame. */
426 if (cache->base == 0)
427 return;
428
429 (*this_id) = frame_id_build (cache->cfa, cache->pc);
430}
431
432static struct value *
433tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
434 int regnum)
435{
436 struct tic6x_unwind_cache *cache =
437 tic6x_frame_unwind_cache (this_frame, this_cache);
438
439 gdb_assert (regnum >= 0);
440
441 /* The PC of the previous frame is stored in the RA register of
442 the current frame. Frob regnum so that we pull the value from
443 the correct place. */
444 if (regnum == TIC6X_PC_REGNUM)
445 regnum = cache->return_regnum;
446
447 if (regnum == TIC6X_SP_REGNUM && cache->cfa)
448 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
449
450 /* If we've worked out where a register is stored then load it from
451 there. */
452 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
453 return frame_unwind_got_memory (this_frame, regnum,
454 cache->reg_saved[regnum]);
455
456 return frame_unwind_got_register (this_frame, regnum, regnum);
457}
458
459static CORE_ADDR
460tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
461{
462 struct tic6x_unwind_cache *info
463 = tic6x_frame_unwind_cache (this_frame, this_cache);
464 return info->base;
465}
466
467static const struct frame_unwind tic6x_frame_unwind =
468{
469 NORMAL_FRAME,
470 default_frame_unwind_stop_reason,
471 tic6x_frame_this_id,
472 tic6x_frame_prev_register,
473 NULL,
474 default_frame_sniffer
475};
476
477static const struct frame_base tic6x_frame_base =
478{
479 &tic6x_frame_unwind,
480 tic6x_frame_base_address,
481 tic6x_frame_base_address,
482 tic6x_frame_base_address
483};
484
485
486static struct tic6x_unwind_cache *
487tic6x_make_stub_cache (struct frame_info *this_frame)
488{
489 struct tic6x_unwind_cache *cache;
490
491 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
492
493 cache->return_regnum = TIC6X_RA_REGNUM;
494
495 tic6x_setup_default (cache);
496
497 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
498
499 return cache;
500}
501
502static void
503tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
504 struct frame_id *this_id)
505{
506 struct tic6x_unwind_cache *cache;
507
508 if (*this_cache == NULL)
509 *this_cache = tic6x_make_stub_cache (this_frame);
19ba03f4 510 cache = (struct tic6x_unwind_cache *) *this_cache;
8cd64e00
YQ		 511
512 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
513}
514
515static int
516tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
517 struct frame_info *this_frame,
518 void **this_prologue_cache)
519{
520 CORE_ADDR addr_in_block;
521
522 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 523 if (in_plt_section (addr_in_block))
8cd64e00
YQ		 524 return 1;
525
526 return 0;
527}
528
529static const struct frame_unwind tic6x_stub_unwind =
530{
531 NORMAL_FRAME,
532 default_frame_unwind_stop_reason,
533 tic6x_stub_this_id,
534 tic6x_frame_prev_register,
535 NULL,
536 tic6x_stub_unwind_sniffer
537};
538
539/* Return the instruction on address PC. */
540
541static unsigned long
542tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
543{
544 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
545 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
546}
547
548/* Compute the condition of INST if it is a conditional instruction. Always
549 return 1 if INST is not a conditional instruction. */
550
551static int
fb090cfa 552tic6x_condition_true (struct regcache *regcache, unsigned long inst)
8cd64e00
YQ		 553{
554 int register_number;
555 int register_value;
556 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
557
558 register_number = register_numbers[(inst >> 29) & 7];
559 if (register_number == -1)
560 return 1;
561
fb090cfa 562 register_value = regcache_raw_get_signed (regcache, register_number);
8cd64e00
YQ		 563 if ((inst & 0x10000000) != 0)
564 return register_value == 0;
565 return register_value != 0;
566}
567
568/* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
569 instruction. */
570
571static int
572tic6x_register_number (int reg, int side, int crosspath)
573{
574 int r = (reg & 15) | ((crosspath ^ side) << 4);
575 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
576 r += 37;
577 return r;
578}
579
580static int
581tic6x_extract_signed_field (int value, int low_bit, int bits)
582{
583 int mask = (1 << bits) - 1;
584 int r = (value >> low_bit) & mask;
585 if ((r & (1 << (bits - 1))) != 0)
586 r -= mask + 1;
587 return r;
588}
589
590/* Determine where to set a single step breakpoint. */
591
592static CORE_ADDR
fb090cfa 593tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
8cd64e00 594{
ac7936df 595 struct gdbarch *gdbarch = regcache->arch ();
8cd64e00 596 unsigned long inst;
8cd64e00
YQ		 597 int register_number;
598 int last = 0;
599
600 do
601 {
602 inst = tic6x_fetch_instruction (gdbarch, pc);
603
604 last = !(inst & 1);
605
606 if (inst == TIC6X_INST_SWE)
607 {
608 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
609
610 if (tdep->syscall_next_pc != NULL)
fb090cfa 611 return tdep->syscall_next_pc (get_current_frame ());
8cd64e00
YQ		 612 }
613
fb090cfa 614 if (tic6x_condition_true (regcache, inst))
8cd64e00
YQ		 615 {
616 if ((inst & 0x0000007c) == 0x00000010)
617 {
618 /* B with displacement */
619 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
620 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
621 break;
622 }
623 if ((inst & 0x0f83effc) == 0x00000360)
624 {
625 /* B with register */
626
627 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
628 INST_S_BIT (inst),
629 INST_X_BIT (inst));
fb090cfa 630 pc = regcache_raw_get_unsigned (regcache, register_number);
8cd64e00
YQ		 631 break;
632 }
633 if ((inst & 0x00001ffc) == 0x00001020)
634 {
635 /* BDEC */
636 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
637 INST_S_BIT (inst), 0);
fb090cfa 638 if (regcache_raw_get_signed (regcache, register_number) >= 0)
8cd64e00
YQ		 639 {
640 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
641 pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
642 }
643 break;
644 }
645 if ((inst & 0x00001ffc) == 0x00000120)
646 {
647 /* BNOP with displacement */
648 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
649 pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
650 break;
651 }
652 if ((inst & 0x0f830ffe) == 0x00800362)
653 {
654 /* BNOP with register */
655 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
656 1, INST_X_BIT (inst));
fb090cfa 657 pc = regcache_raw_get_unsigned (regcache, register_number);
8cd64e00
YQ		 658 break;
659 }
660 if ((inst & 0x00001ffc) == 0x00000020)
661 {
662 /* BPOS */
663 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
664 INST_S_BIT (inst), 0);
fb090cfa 665 if (regcache_raw_get_signed (regcache, register_number) >= 0)
8cd64e00
YQ		 666 {
667 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
668 pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
669 }
670 break;
671 }
672 if ((inst & 0xf000007c) == 0x10000010)
673 {
674 /* CALLP */
675 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
676 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
677 break;
678 }
679 }
680 pc += TIC6X_OPCODE_SIZE;
681 }
682 while (!last);
683 return pc;
684}
685
686/* This is the implementation of gdbarch method software_single_step. */
687
a0ff9e1a 688static std::vector<CORE_ADDR>
f5ea389a 689tic6x_software_single_step (struct regcache *regcache)
8cd64e00 690{
fb090cfa 691 CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache));
8cd64e00 692
a0ff9e1a 693 return {next_pc};
8cd64e00
YQ		 694}
695
696/* This is the implementation of gdbarch method frame_align. */
697
698static CORE_ADDR
699tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
700{
701 return align_down (addr, 8);
702}
703
8cd64e00
YQ		 704/* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
705 value into VALBUF. */
706
707static void
708tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
709 enum bfd_endian byte_order, gdb_byte *valbuf)
710{
711 int len = TYPE_LENGTH (valtype);
712
713 /* pointer types are returned in register A4,
714 up to 32-bit types in A4
715 up to 64-bit types in A5:A4 */
716 if (len <= 4)
717 {
718 /* In big-endian,
719 - one-byte structure or union occupies the LSB of single even register.
720 - for two-byte structure or union, the first byte occupies byte 1 of
721 register and the second byte occupies byte 0.
722 so, we read the contents in VAL from the LSBs of register. */
723 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
73bb0000 724 regcache->cooked_read_part (TIC6X_A4_REGNUM, 4 - len, len, valbuf);
8cd64e00 725 else
dca08e1f 726 regcache->cooked_read (TIC6X_A4_REGNUM, valbuf);
8cd64e00
YQ		 727 }
728 else if (len <= 8)
729 {
730 /* For a 5-8 byte structure or union in big-endian, the first byte
731 occupies byte 3 (the MSB) of the upper (odd) register and the
732 remaining bytes fill the decreasingly significant bytes. 5-7
733 byte structures or unions have padding in the LSBs of the
734 lower (even) register. */
735 if (byte_order == BFD_ENDIAN_BIG)
736 {
dca08e1f
SM		 737 regcache->cooked_read (TIC6X_A4_REGNUM, valbuf + 4);
738 regcache->cooked_read (TIC6X_A5_REGNUM, valbuf);
8cd64e00
YQ		 739 }
740 else
741 {
dca08e1f
SM		 742 regcache->cooked_read (TIC6X_A4_REGNUM, valbuf);
743 regcache->cooked_read (TIC6X_A5_REGNUM, valbuf + 4);
8cd64e00
YQ		 744 }
745 }
746}
747
748/* Write into appropriate registers a function return value
749 of type TYPE, given in virtual format. */
750
751static void
752tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
753 enum bfd_endian byte_order, const gdb_byte *valbuf)
754{
755 int len = TYPE_LENGTH (valtype);
756
757 /* return values of up to 8 bytes are returned in A5:A4 */
758
759 if (len <= 4)
760 {
761 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
e4c4a59b 762 regcache->cooked_write_part (TIC6X_A4_REGNUM, 4 - len, len, valbuf);
8cd64e00 763 else
b66f5587 764 regcache->cooked_write (TIC6X_A4_REGNUM, valbuf);
8cd64e00
YQ		 765 }
766 else if (len <= 8)
767 {
768 if (byte_order == BFD_ENDIAN_BIG)
769 {
b66f5587
SM		 770 regcache->cooked_write (TIC6X_A4_REGNUM, valbuf + 4);
771 regcache->cooked_write (TIC6X_A5_REGNUM, valbuf);
8cd64e00
YQ		 772 }
773 else
774 {
b66f5587
SM		 775 regcache->cooked_write (TIC6X_A4_REGNUM, valbuf);
776 regcache->cooked_write (TIC6X_A5_REGNUM, valbuf + 4);
8cd64e00
YQ		 777 }
778 }
779}
780
781/* This is the implementation of gdbarch method return_value. */
782
783static enum return_value_convention
6a3a010b 784tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
8cd64e00
YQ		 785 struct type *type, struct regcache *regcache,
786 gdb_byte *readbuf, const gdb_byte *writebuf)
787{
18648a37
YQ		 788 /* In C++, when function returns an object, even its size is small
789 enough, it stii has to be passed via reference, pointed by register
790 A3. */
791 if (current_language->la_language == language_cplus)
792 {
793 if (type != NULL)
794 {
f168693b 795 type = check_typedef (type);
18648a37
YQ		 796 if (language_pass_by_reference (type))
797 return RETURN_VALUE_STRUCT_CONVENTION;
798 }
799 }
800
8cd64e00
YQ		 801 if (TYPE_LENGTH (type) > 8)
802 return RETURN_VALUE_STRUCT_CONVENTION;
803
804 if (readbuf)
805 tic6x_extract_return_value (type, regcache,
806 gdbarch_byte_order (gdbarch), readbuf);
807 if (writebuf)
808 tic6x_store_return_value (type, regcache,
809 gdbarch_byte_order (gdbarch), writebuf);
810
811 return RETURN_VALUE_REGISTER_CONVENTION;
812}
813
814/* This is the implementation of gdbarch method dummy_id. */
815
816static struct frame_id
817tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
818{
819 return frame_id_build
820 (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM),
821 get_frame_pc (this_frame));
822}
823
824/* Get the alignment requirement of TYPE. */
825
826static int
827tic6x_arg_type_alignment (struct type *type)
828{
829 int len = TYPE_LENGTH (check_typedef (type));
830 enum type_code typecode = TYPE_CODE (check_typedef (type));
831
832 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
833 {
834 /* The stack alignment of a structure (and union) passed by value is the
835 smallest power of two greater than or equal to its size.
836 This cannot exceed 8 bytes, which is the largest allowable size for
837 a structure passed by value. */
838
839 if (len <= 2)
840 return len;
841 else if (len <= 4)
842 return 4;
843 else if (len <= 8)
844 return 8;
845 else
846 gdb_assert_not_reached ("unexpected length of data");
847 }
848 else
849 {
850 if (len <= 4)
851 return 4;
852 else if (len == 8)
853 {
854 if (typecode == TYPE_CODE_COMPLEX)
855 return 4;
856 else
857 return 8;
858 }
859 else if (len == 16)
860 {
861 if (typecode == TYPE_CODE_COMPLEX)
862 return 8;
863 else
864 return 16;
865 }
866 else
867 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
868 len);
869 }
870}
871
872/* This is the implementation of gdbarch method push_dummy_call. */
873
874static CORE_ADDR
875tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
876 struct regcache *regcache, CORE_ADDR bp_addr,
877 int nargs, struct value **args, CORE_ADDR sp,
878 int struct_return, CORE_ADDR struct_addr)
879{
880 int argreg = 0;
881 int argnum;
8cd64e00
YQ		 882 int stack_offset = 4;
883 int references_offset = 4;
8cd64e00
YQ		 884 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
885 struct type *func_type = value_type (function);
886 /* The first arg passed on stack. Mostly the first 10 args are passed by
887 registers. */
888 int first_arg_on_stack = 10;
8cd64e00 889
8cd64e00
YQ		 890 /* Set the return address register to point to the entry point of
891 the program, where a breakpoint lies in wait. */
892 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);
893
894 /* The caller must pass an argument in A3 containing a destination address
895 for the returned value. The callee returns the object by copying it to
896 the address in A3. */
897 if (struct_return)
898 regcache_cooked_write_unsigned (regcache, 3, struct_addr);
8cd64e00
YQ		 899
900 /* Determine the type of this function. */
901 func_type = check_typedef (func_type);
902 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
903 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
904
905 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
906 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
907
908 /* For a variadic C function, the last explicitly declared argument and all
909 remaining arguments are passed on the stack. */
910 if (TYPE_VARARGS (func_type))
911 first_arg_on_stack = TYPE_NFIELDS (func_type) - 1;
912
18648a37
YQ		 913 /* Now make space on the stack for the args. */
914 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 915 {
916 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
917 if (argnum >= 10 - argreg)
918 references_offset += len;
919 stack_offset += len;
920 }
921 sp -= stack_offset;
922 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
923 Stack Alignment. */
924 sp = align_down (sp, 8);
925 stack_offset = 4;
926
927 /* Now load as many as possible of the first arguments into
928 registers, and push the rest onto the stack. Loop through args
929 from first to last. */
18648a37 930 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 931 {
932 const gdb_byte *val;
933 struct value *arg = args[argnum];
934 struct type *arg_type = check_typedef (value_type (arg));
935 int len = TYPE_LENGTH (arg_type);
936 enum type_code typecode = TYPE_CODE (arg_type);
937
938 val = value_contents (arg);
939
940 /* Copy the argument to general registers or the stack in
941 register-sized pieces. */
942 if (argreg < first_arg_on_stack)
943 {
944 if (len <= 4)
945 {
946 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
947 {
948 /* In big-endian,
949 - one-byte structure or union occupies the LSB of single
950 even register.
951 - for two-byte structure or union, the first byte
952 occupies byte 1 of register and the second byte occupies
953 byte 0.
954 so, we write the contents in VAL to the lsp of
955 register. */
956 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
e4c4a59b
SM		 957 regcache->cooked_write_part (arg_regs[argreg], 4 - len, len,
958 val);
8cd64e00 959 else
b66f5587 960 regcache->cooked_write (arg_regs[argreg], val);
8cd64e00
YQ		 961 }
962 else
963 {
964 /* The argument is being passed by value in a single
965 register. */
966 CORE_ADDR regval = extract_unsigned_integer (val, len,
967 byte_order);
968
969 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
970 regval);
971 }
972 }
973 else
974 {
975 if (len <= 8)
976 {
977 if (typecode == TYPE_CODE_STRUCT
978 || typecode == TYPE_CODE_UNION)
979 {
980 /* For a 5-8 byte structure or union in big-endian, the
981 first byte occupies byte 3 (the MSB) of the upper (odd)
982 register and the remaining bytes fill the decreasingly
983 significant bytes. 5-7 byte structures or unions have
984 padding in the LSBs of the lower (even) register. */
985 if (byte_order == BFD_ENDIAN_BIG)
986 {
b66f5587 987 regcache->cooked_write (arg_regs[argreg] + 1, val);
e4c4a59b
SM		 988 regcache->cooked_write_part (arg_regs[argreg], 0,
989 len - 4, val + 4);
8cd64e00
YQ		 990 }
991 else
992 {
b66f5587 993 regcache->cooked_write (arg_regs[argreg], val);
e4c4a59b
SM		 994 regcache->cooked_write_part (arg_regs[argreg] + 1, 0,
995 len - 4, val + 4);
8cd64e00
YQ		 996 }
997 }
998 else
999 {
1000 /* The argument is being passed by value in a pair of
1001 registers. */
1002 ULONGEST regval = extract_unsigned_integer (val, len,
1003 byte_order);
1004
1005 regcache_cooked_write_unsigned (regcache,
1006 arg_regs[argreg],
1007 regval);
1008 regcache_cooked_write_unsigned (regcache,
1009 arg_regs[argreg] + 1,
1010 regval >> 32);
1011 }
1012 }
1013 else
1014 {
1015 /* The argument is being passed by reference in a single
1016 register. */
1017 CORE_ADDR addr;
1018
1019 /* It is not necessary to adjust REFERENCES_OFFSET to
1020 8-byte aligned in some cases, in which 4-byte alignment
1021 is sufficient. For simplicity, we adjust
1022 REFERENCES_OFFSET to 8-byte aligned. */
1023 references_offset = align_up (references_offset, 8);
1024
1025 addr = sp + references_offset;
1026 write_memory (addr, val, len);
1027 references_offset += align_up (len, 4);
1028 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
1029 addr);
1030 }
1031 }
1032 argreg++;
1033 }
1034 else
1035 {
1036 /* The argument is being passed on the stack. */
1037 CORE_ADDR addr;
1038
1039 /* There are six different cases of alignment, and these rules can
1040 be found in tic6x_arg_type_alignment:
1041
1042 1) 4-byte aligned if size is less than or equal to 4 byte, such
1043 as short, int, struct, union etc.
1044 2) 8-byte aligned if size is less than or equal to 8-byte, such
1045 as double, long long,
1046 3) 4-byte aligned if it is of type _Complex float, even its size
1047 is 8-byte.
1048 4) 8-byte aligned if it is of type _Complex double or _Complex
1049 long double, even its size is 16-byte. Because, the address of
1050 variable is passed as reference.
1051 5) struct and union larger than 8-byte are passed by reference, so
1052 it is 4-byte aligned.
1053 6) struct and union of size between 4 byte and 8 byte varies.
1054 alignment of struct variable is the alignment of its first field,
1055 while alignment of union variable is the max of all its fields'
1056 alignment. */
1057
1058 if (len <= 4)
1059 ; /* Default is 4-byte aligned. Nothing to be done. */
1060 else if (len <= 8)
1061 stack_offset = align_up (stack_offset,
1062 tic6x_arg_type_alignment (arg_type));
1063 else if (len == 16)
1064 {
1065 /* _Complex double or _Complex long double */
1066 if (typecode == TYPE_CODE_COMPLEX)
1067 {
1068 /* The argument is being passed by reference on stack. */
8cd64e00
YQ		 1069 references_offset = align_up (references_offset, 8);
1070
1071 addr = sp + references_offset;
1072 /* Store variable on stack. */
1073 write_memory (addr, val, len);
1074
1075 references_offset += align_up (len, 4);
1076
1077 /* Pass the address of variable on stack as reference. */
1078 store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
1079 addr);
1080 len = 4;
1081
1082 }
1083 else
1084 internal_error (__FILE__, __LINE__,
1085 _("unexpected type %d of arg %d"),
1086 typecode, argnum);
1087 }
1088 else
1089 internal_error (__FILE__, __LINE__,
1090 _("unexpected length %d of arg %d"), len, argnum);
1091
1092 addr = sp + stack_offset;
1093 write_memory (addr, val, len);
1094 stack_offset += align_up (len, 4);
1095 }
1096 }
1097
1098 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);
1099
1100 /* Return adjusted stack pointer. */
1101 return sp;
1102}
1103
c9cf6e20 1104/* This is the implementation of gdbarch method stack_frame_destroyed_p. */
8cd64e00
YQ		 1105
1106static int
c9cf6e20 1107tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
8cd64e00
YQ		 1108{
1109 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
1110 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1111 if ((inst & 0x0f83effc) == 0x360)
1112 {
1113 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
1114 INST_S_BIT (inst),
1115 INST_X_BIT (inst));
1116 if (src2 == TIC6X_RA_REGNUM)
1117 return 1;
1118 }
1119
1120 return 0;
1121}
1122
1123/* This is the implementation of gdbarch method get_longjmp_target. */
1124
1125static int
1126tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1127{
1128 struct gdbarch *gdbarch = get_frame_arch (frame);
1129 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1130 CORE_ADDR jb_addr;
e362b510 1131 gdb_byte buf[4];
8cd64e00
YQ		 1132
1133 /* JMP_BUF is passed by reference in A4. */
1134 jb_addr = get_frame_register_unsigned (frame, 4);
1135
1136 /* JMP_BUF contains 13 elements of type int, and return address is stored
1137 in the last slot. */
1138 if (target_read_memory (jb_addr + 12 * 4, buf, 4))
1139 return 0;
1140
1141 *pc = extract_unsigned_integer (buf, 4, byte_order);
1142
1143 return 1;
1144}
1145
18648a37
YQ		 1146/* This is the implementation of gdbarch method
1147 return_in_first_hidden_param_p. */
1148
1149static int
1150tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
1151 struct type *type)
1152{
1153 return 0;
1154}
1155
8cd64e00
YQ		 1156static struct gdbarch *
1157tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1158{
1159 struct gdbarch *gdbarch;
1160 struct gdbarch_tdep *tdep;
1161 struct tdesc_arch_data *tdesc_data = NULL;
1162 const struct target_desc *tdesc = info.target_desc;
1163 int has_gp = 0;
1164
1165 /* Check any target description for validity. */
1166 if (tdesc_has_registers (tdesc))
1167 {
1168 const struct tdesc_feature *feature;
1169 int valid_p, i;
1170
1171 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");
1172
1173 if (feature == NULL)
1174 return NULL;
1175
1176 tdesc_data = tdesc_data_alloc ();
1177
1178 valid_p = 1;
1179 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */
1180 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1181 tic6x_register_names[i]);
1182
1183 /* CSR */
1184 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1185 tic6x_register_names[TIC6X_CSR_REGNUM]);
1186 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1187 tic6x_register_names[TIC6X_PC_REGNUM]);
1188
1189 if (!valid_p)
1190 {
1191 tdesc_data_cleanup (tdesc_data);
1192 return NULL;
1193 }
1194
1195 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
1196 if (feature)
1197 {
1198 int j = 0;
1199 static const char *const gp[] =
1200 {
1201 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1202 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1203 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1204 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1205 };
1206
1207 has_gp = 1;
1208 valid_p = 1;
1209 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */
1210 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1211 gp[j]);
1212
1213 if (!valid_p)
1214 {
1215 tdesc_data_cleanup (tdesc_data);
1216 return NULL;
1217 }
1218 }
1219
1220 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
1221 if (feature)
1222 {
1223 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR");
1224 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC");
1225 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC");
1226
1227 if (!valid_p)
1228 {
1229 tdesc_data_cleanup (tdesc_data);
1230 return NULL;
1231 }
1232 }
1233
1234 }
1235
1236 /* Find a candidate among extant architectures. */
1237 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1238 arches != NULL;
1239 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1240 {
1241 tdep = gdbarch_tdep (arches->gdbarch);
1242
1243 if (has_gp != tdep->has_gp)
1244 continue;
1245
1246 if (tdep && tdep->breakpoint)
1247 return arches->gdbarch;
1248 }
1249
8d749320 1250 tdep = XCNEW (struct gdbarch_tdep);
8cd64e00
YQ		 1251
1252 tdep->has_gp = has_gp;
1253 gdbarch = gdbarch_alloc (&info, tdep);
1254
1255 /* Data type sizes. */
1256 set_gdbarch_ptr_bit (gdbarch, 32);
1257 set_gdbarch_addr_bit (gdbarch, 32);
1258 set_gdbarch_short_bit (gdbarch, 16);
1259 set_gdbarch_int_bit (gdbarch, 32);
1260 set_gdbarch_long_bit (gdbarch, 32);
1261 set_gdbarch_long_long_bit (gdbarch, 64);
1262 set_gdbarch_float_bit (gdbarch, 32);
1263 set_gdbarch_double_bit (gdbarch, 64);
1264
1265 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1266 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1267
1268 /* The register set. */
1269 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
1270 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
1271 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);
1272
1273 set_gdbarch_register_name (gdbarch, tic6x_register_name);
1274 set_gdbarch_register_type (gdbarch, tic6x_register_type);
1275
1276 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1277
1278 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
04180708
YQ		 1279 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1280 tic6x_breakpoint_kind_from_pc);
1281 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1282 tic6x_sw_breakpoint_from_kind);
8cd64e00
YQ		 1283
1284 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
1285 set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp);
1286
1287 /* Unwinding. */
1288 dwarf2_append_unwinders (gdbarch);
1289
1290 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
1291 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
195abc10 1292 frame_base_set_default (gdbarch, &tic6x_frame_base);
8cd64e00
YQ		 1293
1294 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);
1295
1296 /* Single stepping. */
1297 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);
1298
8cd64e00
YQ		 1299 /* Call dummy code. */
1300 set_gdbarch_frame_align (gdbarch, tic6x_frame_align);
1301
8cd64e00
YQ		 1302 set_gdbarch_return_value (gdbarch, tic6x_return_value);
1303
1304 set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id);
1305
1306 /* Enable inferior call support. */
1307 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);
1308
1309 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);
1310
c9cf6e20 1311 set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p);
8cd64e00 1312
18648a37
YQ		 1313 set_gdbarch_return_in_first_hidden_param_p (gdbarch,
1314 tic6x_return_in_first_hidden_param_p);
1315
8cd64e00
YQ		 1316 /* Hook in ABI-specific overrides, if they have been registered. */
1317 gdbarch_init_osabi (info, gdbarch);
1318
1319 if (tdesc_data)
1320 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1321
1322 return gdbarch;
1323}
1324
1325void
1326_initialize_tic6x_tdep (void)
1327{
1328 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);
8cd64e00 1329}
GDB Binutils - Deliverables
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