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S390: Hardware breakpoint support
[deliverable/binutils-gdb.git] / gdb / tilegx-tdep.c
CommitLineData
ade64f0e
PA		 1/* Target-dependent code for the Tilera TILE-Gx processor.
2
618f726f 3 Copyright (C) 2012-2016 Free Software Foundation, Inc.
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PA		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "frame-base.h"
23#include "frame-unwind.h"
24#include "dwarf2-frame.h"
25#include "trad-frame.h"
26#include "symtab.h"
27#include "gdbtypes.h"
28#include "gdbcmd.h"
29#include "gdbcore.h"
30#include "value.h"
31#include "dis-asm.h"
32#include "inferior.h"
ade64f0e
PA		 33#include "arch-utils.h"
34#include "floatformat.h"
35#include "regcache.h"
36#include "regset.h"
37#include "doublest.h"
38#include "osabi.h"
39#include "linux-tdep.h"
40#include "objfiles.h"
41#include "solib-svr4.h"
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PA		 42#include "tilegx-tdep.h"
43#include "opcode/tilegx.h"
44
45struct tilegx_frame_cache
46{
47 /* Base address. */
48 CORE_ADDR base;
49 /* Function start. */
50 CORE_ADDR start_pc;
51
52 /* Table of saved registers. */
53 struct trad_frame_saved_reg *saved_regs;
54};
55
56/* Register state values used by analyze_prologue. */
57enum reverse_state
58 {
59 REVERSE_STATE_REGISTER,
60 REVERSE_STATE_VALUE,
61 REVERSE_STATE_UNKNOWN
62 };
63
64/* Register state used by analyze_prologue(). */
65struct tilegx_reverse_regs
66{
67 LONGEST value;
68 enum reverse_state state;
69};
70
71static const struct tilegx_reverse_regs
72template_reverse_regs[TILEGX_NUM_PHYS_REGS] =
73 {
74 { TILEGX_R0_REGNUM, REVERSE_STATE_REGISTER },
75 { TILEGX_R1_REGNUM, REVERSE_STATE_REGISTER },
76 { TILEGX_R2_REGNUM, REVERSE_STATE_REGISTER },
77 { TILEGX_R3_REGNUM, REVERSE_STATE_REGISTER },
78 { TILEGX_R4_REGNUM, REVERSE_STATE_REGISTER },
79 { TILEGX_R5_REGNUM, REVERSE_STATE_REGISTER },
80 { TILEGX_R6_REGNUM, REVERSE_STATE_REGISTER },
81 { TILEGX_R7_REGNUM, REVERSE_STATE_REGISTER },
82 { TILEGX_R8_REGNUM, REVERSE_STATE_REGISTER },
83 { TILEGX_R9_REGNUM, REVERSE_STATE_REGISTER },
84 { TILEGX_R10_REGNUM, REVERSE_STATE_REGISTER },
85 { TILEGX_R11_REGNUM, REVERSE_STATE_REGISTER },
86 { TILEGX_R12_REGNUM, REVERSE_STATE_REGISTER },
87 { TILEGX_R13_REGNUM, REVERSE_STATE_REGISTER },
88 { TILEGX_R14_REGNUM, REVERSE_STATE_REGISTER },
89 { TILEGX_R15_REGNUM, REVERSE_STATE_REGISTER },
90 { TILEGX_R16_REGNUM, REVERSE_STATE_REGISTER },
91 { TILEGX_R17_REGNUM, REVERSE_STATE_REGISTER },
92 { TILEGX_R18_REGNUM, REVERSE_STATE_REGISTER },
93 { TILEGX_R19_REGNUM, REVERSE_STATE_REGISTER },
94 { TILEGX_R20_REGNUM, REVERSE_STATE_REGISTER },
95 { TILEGX_R21_REGNUM, REVERSE_STATE_REGISTER },
96 { TILEGX_R22_REGNUM, REVERSE_STATE_REGISTER },
97 { TILEGX_R23_REGNUM, REVERSE_STATE_REGISTER },
98 { TILEGX_R24_REGNUM, REVERSE_STATE_REGISTER },
99 { TILEGX_R25_REGNUM, REVERSE_STATE_REGISTER },
100 { TILEGX_R26_REGNUM, REVERSE_STATE_REGISTER },
101 { TILEGX_R27_REGNUM, REVERSE_STATE_REGISTER },
102 { TILEGX_R28_REGNUM, REVERSE_STATE_REGISTER },
103 { TILEGX_R29_REGNUM, REVERSE_STATE_REGISTER },
104 { TILEGX_R30_REGNUM, REVERSE_STATE_REGISTER },
105 { TILEGX_R31_REGNUM, REVERSE_STATE_REGISTER },
106 { TILEGX_R32_REGNUM, REVERSE_STATE_REGISTER },
107 { TILEGX_R33_REGNUM, REVERSE_STATE_REGISTER },
108 { TILEGX_R34_REGNUM, REVERSE_STATE_REGISTER },
109 { TILEGX_R35_REGNUM, REVERSE_STATE_REGISTER },
110 { TILEGX_R36_REGNUM, REVERSE_STATE_REGISTER },
111 { TILEGX_R37_REGNUM, REVERSE_STATE_REGISTER },
112 { TILEGX_R38_REGNUM, REVERSE_STATE_REGISTER },
113 { TILEGX_R39_REGNUM, REVERSE_STATE_REGISTER },
114 { TILEGX_R40_REGNUM, REVERSE_STATE_REGISTER },
115 { TILEGX_R41_REGNUM, REVERSE_STATE_REGISTER },
116 { TILEGX_R42_REGNUM, REVERSE_STATE_REGISTER },
117 { TILEGX_R43_REGNUM, REVERSE_STATE_REGISTER },
118 { TILEGX_R44_REGNUM, REVERSE_STATE_REGISTER },
119 { TILEGX_R45_REGNUM, REVERSE_STATE_REGISTER },
120 { TILEGX_R46_REGNUM, REVERSE_STATE_REGISTER },
121 { TILEGX_R47_REGNUM, REVERSE_STATE_REGISTER },
122 { TILEGX_R48_REGNUM, REVERSE_STATE_REGISTER },
123 { TILEGX_R49_REGNUM, REVERSE_STATE_REGISTER },
124 { TILEGX_R50_REGNUM, REVERSE_STATE_REGISTER },
125 { TILEGX_R51_REGNUM, REVERSE_STATE_REGISTER },
126 { TILEGX_R52_REGNUM, REVERSE_STATE_REGISTER },
127 { TILEGX_TP_REGNUM, REVERSE_STATE_REGISTER },
128 { TILEGX_SP_REGNUM, REVERSE_STATE_REGISTER },
129 { TILEGX_LR_REGNUM, REVERSE_STATE_REGISTER },
130 { 0, REVERSE_STATE_UNKNOWN },
131 { 0, REVERSE_STATE_UNKNOWN },
132 { 0, REVERSE_STATE_UNKNOWN },
133 { 0, REVERSE_STATE_UNKNOWN },
134 { 0, REVERSE_STATE_UNKNOWN },
135 { 0, REVERSE_STATE_UNKNOWN },
136 { 0, REVERSE_STATE_UNKNOWN },
137 { TILEGX_ZERO_REGNUM, REVERSE_STATE_VALUE }
138 };
139
140/* Implement the "register_name" gdbarch method. */
141
142static const char *
143tilegx_register_name (struct gdbarch *gdbarch, int regnum)
144{
145 static const char *const register_names[TILEGX_NUM_REGS] =
146 {
147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
149 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
150 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
151 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
152 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
153 "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
154 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero",
4aaf2503 155 "pc", "faultnum",
ade64f0e
PA		 156 };
157
158 if (regnum < 0 || regnum >= TILEGX_NUM_REGS)
159 internal_error (__FILE__, __LINE__,
160 "tilegx_register_name: invalid register number %d",
161 regnum);
162
163 return register_names[regnum];
164}
165
166/* This is the implementation of gdbarch method register_type. */
167
168static struct type *
169tilegx_register_type (struct gdbarch *gdbarch, int regnum)
170{
171 if (regnum == TILEGX_PC_REGNUM)
172 return builtin_type (gdbarch)->builtin_func_ptr;
173 else
174 return builtin_type (gdbarch)->builtin_uint64;
175}
176
177/* This is the implementation of gdbarch method dwarf2_reg_to_regnum. */
178
179static int
180tilegx_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
181{
182 return num;
183}
184
185/* Makes the decision of whether a given type is a scalar type.
186 Scalar types are returned in the registers r2-r11 as they fit. */
187
188static int
189tilegx_type_is_scalar (struct type *t)
190{
191 return (TYPE_CODE(t) != TYPE_CODE_STRUCT
192 && TYPE_CODE(t) != TYPE_CODE_UNION
193 && TYPE_CODE(t) != TYPE_CODE_ARRAY);
194}
195
196/* Returns non-zero if the given struct type will be returned using
197 a special convention, rather than the normal function return method.
198 Used in the context of the "return" command, and target function
199 calls from the debugger. */
200
201static int
202tilegx_use_struct_convention (struct type *type)
203{
204 /* Only scalars which fit in R0 - R9 can be returned in registers.
205 Otherwise, they are returned via a pointer passed in R0. */
206 return (!tilegx_type_is_scalar (type)
207 && (TYPE_LENGTH (type) > (1 + TILEGX_R9_REGNUM - TILEGX_R0_REGNUM)
208 * tilegx_reg_size));
209}
210
211/* Find a function's return value in the appropriate registers (in
212 REGCACHE), and copy it into VALBUF. */
213
214static void
215tilegx_extract_return_value (struct type *type, struct regcache *regcache,
216 gdb_byte *valbuf)
217{
218 int len = TYPE_LENGTH (type);
219 int i, regnum = TILEGX_R0_REGNUM;
220
221 for (i = 0; i < len; i += tilegx_reg_size)
222 regcache_raw_read (regcache, regnum++, valbuf + i);
223}
224
225/* Copy the function return value from VALBUF into the proper
226 location for a function return.
227 Called only in the context of the "return" command. */
228
229static void
230tilegx_store_return_value (struct type *type, struct regcache *regcache,
231 const void *valbuf)
232{
233 if (TYPE_LENGTH (type) < tilegx_reg_size)
234 {
235 /* Add leading zeros to the (little-endian) value. */
236 gdb_byte buf[tilegx_reg_size] = { 0 };
237
238 memcpy (buf, valbuf, TYPE_LENGTH (type));
239 regcache_raw_write (regcache, TILEGX_R0_REGNUM, buf);
240 }
241 else
242 {
243 int len = TYPE_LENGTH (type);
244 int i, regnum = TILEGX_R0_REGNUM;
245
246 for (i = 0; i < len; i += tilegx_reg_size)
247 regcache_raw_write (regcache, regnum++, (gdb_byte *) valbuf + i);
248 }
249}
250
251/* This is the implementation of gdbarch method return_value. */
252
253static enum return_value_convention
254tilegx_return_value (struct gdbarch *gdbarch, struct value *function,
255 struct type *type, struct regcache *regcache,
256 gdb_byte *readbuf, const gdb_byte *writebuf)
257{
258 if (tilegx_use_struct_convention (type))
259 return RETURN_VALUE_STRUCT_CONVENTION;
260 if (writebuf)
261 tilegx_store_return_value (type, regcache, writebuf);
262 else if (readbuf)
263 tilegx_extract_return_value (type, regcache, readbuf);
264 return RETURN_VALUE_REGISTER_CONVENTION;
265}
266
267/* This is the implementation of gdbarch method frame_align. */
268
269static CORE_ADDR
270tilegx_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
271{
272 return addr & -8;
273}
274
275
276/* Implement the "push_dummy_call" gdbarch method. */
277
278static CORE_ADDR
279tilegx_push_dummy_call (struct gdbarch *gdbarch,
280 struct value *function,
281 struct regcache *regcache,
282 CORE_ADDR bp_addr, int nargs,
283 struct value **args,
284 CORE_ADDR sp, int struct_return,
285 CORE_ADDR struct_addr)
286{
287 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
288 CORE_ADDR stack_dest = sp;
289 int argreg = TILEGX_R0_REGNUM;
290 int i, j;
870f88f7 291 int typelen, slacklen;
bc23a956 292 static const gdb_byte four_zero_words[16] = { 0 };
ade64f0e
PA		 293
294 /* If struct_return is 1, then the struct return address will
295 consume one argument-passing register. */
296 if (struct_return)
297 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
298
299 /* Arguments are passed in R0 - R9, and as soon as an argument
300 will not fit completely in the remaining registers, then it,
301 and all remaining arguments, are put on the stack. */
302 for (i = 0; i < nargs && argreg <= TILEGX_R9_REGNUM; i++)
303 {
304 const gdb_byte *val;
305 typelen = TYPE_LENGTH (value_enclosing_type (args[i]));
306
307 if (typelen > (TILEGX_R9_REGNUM - argreg + 1) * tilegx_reg_size)
308 break;
309
310 /* Put argument into registers wordwise. */
311 val = value_contents (args[i]);
312 for (j = 0; j < typelen; j += tilegx_reg_size)
313 {
314 /* ISSUE: Why special handling for "typelen = 4x + 1"?
315 I don't ever see "typelen" values except 4 and 8. */
316 int n = (typelen - j == 1) ? 1 : tilegx_reg_size;
317 ULONGEST w = extract_unsigned_integer (val + j, n, byte_order);
318
319 regcache_cooked_write_unsigned (regcache, argreg++, w);
320 }
321 }
322
323 /* Align SP. */
324 stack_dest = tilegx_frame_align (gdbarch, stack_dest);
325
ade64f0e
PA		 326 /* Loop backwards through remaining arguments and push them on
327 the stack, word aligned. */
328 for (j = nargs - 1; j >= i; j--)
329 {
330 gdb_byte *val;
ecfb0d68
SP		 331 struct cleanup *back_to;
332 const gdb_byte *contents = value_contents (args[j]);
ade64f0e
PA		 333
334 typelen = TYPE_LENGTH (value_enclosing_type (args[j]));
bc23a956 335 slacklen = align_up (typelen, 8) - typelen;
224c3ddb 336 val = (gdb_byte *) xmalloc (typelen + slacklen);
ecfb0d68
SP		 337 back_to = make_cleanup (xfree, val);
338 memcpy (val, contents, typelen);
ade64f0e
PA		 339 memset (val + typelen, 0, slacklen);
340
341 /* Now write data to the stack. The stack grows downwards. */
342 stack_dest -= typelen + slacklen;
343 write_memory (stack_dest, val, typelen + slacklen);
ecfb0d68 344 do_cleanups (back_to);
ade64f0e
PA		 345 }
346
bc23a956
WL		 347 /* Add 16 bytes for linkage space to the stack. */
348 stack_dest = stack_dest - 16;
349 write_memory (stack_dest, four_zero_words, 16);
ade64f0e
PA		 350
351 /* Update stack pointer. */
352 regcache_cooked_write_unsigned (regcache, TILEGX_SP_REGNUM, stack_dest);
353
354 /* Set the return address register to point to the entry point of
355 the program, where a breakpoint lies in wait. */
356 regcache_cooked_write_unsigned (regcache, TILEGX_LR_REGNUM, bp_addr);
357
358 return stack_dest;
359}
360
361
362/* Decode the instructions within the given address range.
363 Decide when we must have reached the end of the function prologue.
364 If a frame_info pointer is provided, fill in its saved_regs etc.
365 Returns the address of the first instruction after the prologue.
366 NOTE: This is often called with start_addr being the start of some
367 function, and end_addr being the current PC. */
368
369static CORE_ADDR
370tilegx_analyze_prologue (struct gdbarch* gdbarch,
371 CORE_ADDR start_addr, CORE_ADDR end_addr,
372 struct tilegx_frame_cache *cache,
373 struct frame_info *next_frame)
374{
375 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
376 CORE_ADDR next_addr;
377 CORE_ADDR prolog_end = end_addr;
ade64f0e
PA		 378 gdb_byte instbuf[32 * TILEGX_BUNDLE_SIZE_IN_BYTES];
379 CORE_ADDR instbuf_start;
380 unsigned int instbuf_size;
381 int status;
382 bfd_uint64_t bundle;
383 struct tilegx_decoded_instruction
384 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
385 int num_insns;
386 struct tilegx_reverse_regs reverse_frame[TILEGX_NUM_PHYS_REGS];
387 struct tilegx_reverse_regs
388 new_reverse_frame[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
389 int dest_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
3361b059 390 int reverse_frame_valid, prolog_done, branch_seen, lr_saved_on_stack_p;
ade64f0e
PA		 391 LONGEST prev_sp_value;
392 int i, j;
393
394 if (start_addr >= end_addr
395 || (start_addr % TILEGX_BUNDLE_ALIGNMENT_IN_BYTES) != 0)
396 return end_addr;
397
398 /* Initialize the reverse frame. This maps the CURRENT frame's
399 registers to the outer frame's registers (the frame on the
400 stack goes the other way). */
401 memcpy (&reverse_frame, &template_reverse_regs, sizeof (reverse_frame));
402
403 prolog_done = 0;
404 branch_seen = 0;
405 prev_sp_value = 0;
3361b059 406 lr_saved_on_stack_p = 0;
ade64f0e
PA		 407
408 /* To cut down on round-trip overhead, we fetch multiple bundles
409 at once. These variables describe the range of memory we have
410 prefetched. */
411 instbuf_start = 0;
412 instbuf_size = 0;
413
414 for (next_addr = start_addr;
415 next_addr < end_addr;
416 next_addr += TILEGX_BUNDLE_SIZE_IN_BYTES)
417 {
418 /* Retrieve the next instruction. */
419 if (next_addr - instbuf_start >= instbuf_size)
420 {
421 /* Figure out how many bytes to fetch. Don't span a page
422 boundary since that might cause an unnecessary memory
423 error. */
424 unsigned int size_on_same_page = 4096 - (next_addr & 4095);
425
426 instbuf_size = sizeof instbuf;
427
428 if (instbuf_size > size_on_same_page)
429 instbuf_size = size_on_same_page;
d79e58d8
JW		 430
431 instbuf_size = min (instbuf_size, (end_addr - next_addr));
ade64f0e
PA		 432 instbuf_start = next_addr;
433
434 status = safe_frame_unwind_memory (next_frame, instbuf_start,
435 instbuf, instbuf_size);
436 if (status == 0)
f486487f 437 memory_error (TARGET_XFER_E_IO, next_addr);
ade64f0e
PA		 438 }
439
440 reverse_frame_valid = 0;
441
442 bundle = extract_unsigned_integer (&instbuf[next_addr - instbuf_start],
443 8, byte_order);
444
445 num_insns = parse_insn_tilegx (bundle, next_addr, decoded);
446
447 for (i = 0; i < num_insns; i++)
448 {
449 struct tilegx_decoded_instruction *this_insn = &decoded[i];
450 int64_t *operands = (int64_t *) this_insn->operand_values;
451 const struct tilegx_opcode *opcode = this_insn->opcode;
452
453 switch (opcode->mnemonic)
454 {
455 case TILEGX_OPC_ST:
456 if (cache
457 && reverse_frame[operands[0]].state == REVERSE_STATE_VALUE
458 && reverse_frame[operands[1]].state
459 == REVERSE_STATE_REGISTER)
460 {
461 LONGEST saved_address = reverse_frame[operands[0]].value;
462 unsigned saved_register
463 = (unsigned) reverse_frame[operands[1]].value;
464
465 /* realreg >= 0 and addr != -1 indicates that the
466 value of saved_register is in memory location
467 saved_address. The value of realreg is not
468 meaningful in this case but it must be >= 0.
469 See trad-frame.h. */
470 cache->saved_regs[saved_register].realreg = saved_register;
471 cache->saved_regs[saved_register].addr = saved_address;
3361b059
WL		 472 }
473 else if (cache
474 && (operands[0] == TILEGX_SP_REGNUM)
475 && (operands[1] == TILEGX_LR_REGNUM))
476 lr_saved_on_stack_p = 1;
ade64f0e
PA		 477 break;
478 case TILEGX_OPC_ADDI:
479 case TILEGX_OPC_ADDLI:
480 if (cache
481 && operands[0] == TILEGX_SP_REGNUM
482 && operands[1] == TILEGX_SP_REGNUM
483 && reverse_frame[operands[1]].state == REVERSE_STATE_REGISTER)
484 {
485 /* Special case. We're fixing up the stack frame. */
486 uint64_t hopefully_sp
487 = (unsigned) reverse_frame[operands[1]].value;
488 short op2_as_short = (short) operands[2];
489 signed char op2_as_char = (signed char) operands[2];
490
491 /* Fix up the sign-extension. */
492 if (opcode->mnemonic == TILEGX_OPC_ADDI)
493 op2_as_short = op2_as_char;
494 prev_sp_value = (cache->saved_regs[hopefully_sp].addr
495 - op2_as_short);
496
497 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
498 new_reverse_frame[i].value
499 = cache->saved_regs[hopefully_sp].addr;
500 trad_frame_set_value (cache->saved_regs,
501 hopefully_sp, prev_sp_value);
502 }
503 else
504 {
505 short op2_as_short = (short) operands[2];
506 signed char op2_as_char = (signed char) operands[2];
507
508 /* Fix up the sign-extension. */
509 if (opcode->mnemonic == TILEGX_OPC_ADDI)
510 op2_as_short = op2_as_char;
511
512 new_reverse_frame[i] = reverse_frame[operands[1]];
513 if (new_reverse_frame[i].state == REVERSE_STATE_VALUE)
514 new_reverse_frame[i].value += op2_as_short;
515 else
516 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
517 }
518 reverse_frame_valid |= 1 << i;
519 dest_regs[i] = operands[0];
520 break;
521 case TILEGX_OPC_ADD:
522 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
523 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
524 {
525 /* We have values -- we can do this. */
526 new_reverse_frame[i] = reverse_frame[operands[2]];
527 new_reverse_frame[i].value
528 += reverse_frame[operands[i]].value;
529 }
530 else
531 {
532 /* We don't know anything about the values. Punt. */
533 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
534 }
535 reverse_frame_valid |= 1 << i;
536 dest_regs[i] = operands[0];
537 break;
538 case TILEGX_OPC_MOVE:
539 new_reverse_frame[i] = reverse_frame[operands[1]];
540 reverse_frame_valid |= 1 << i;
541 dest_regs[i] = operands[0];
542 break;
543 case TILEGX_OPC_MOVEI:
544 case TILEGX_OPC_MOVELI:
545 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
546 new_reverse_frame[i].value = operands[1];
547 reverse_frame_valid |= 1 << i;
548 dest_regs[i] = operands[0];
549 break;
550 case TILEGX_OPC_ORI:
551 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE)
552 {
553 /* We have a value in A -- we can do this. */
554 new_reverse_frame[i] = reverse_frame[operands[1]];
555 new_reverse_frame[i].value
556 = reverse_frame[operands[1]].value | operands[2];
557 }
558 else if (operands[2] == 0)
559 {
560 /* This is a move. */
561 new_reverse_frame[i] = reverse_frame[operands[1]];
562 }
563 else
564 {
565 /* We don't know anything about the values. Punt. */
566 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
567 }
568 reverse_frame_valid |= 1 << i;
569 dest_regs[i] = operands[0];
570 break;
571 case TILEGX_OPC_OR:
572 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
573 && reverse_frame[operands[1]].value == 0)
574 {
575 /* This is a move. */
576 new_reverse_frame[i] = reverse_frame[operands[2]];
577 }
578 else if (reverse_frame[operands[2]].state == REVERSE_STATE_VALUE
579 && reverse_frame[operands[2]].value == 0)
580 {
581 /* This is a move. */
582 new_reverse_frame[i] = reverse_frame[operands[1]];
583 }
584 else
585 {
586 /* We don't know anything about the values. Punt. */
587 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
588 }
589 reverse_frame_valid |= 1 << i;
590 dest_regs[i] = operands[0];
591 break;
592 case TILEGX_OPC_SUB:
593 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
594 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
595 {
596 /* We have values -- we can do this. */
597 new_reverse_frame[i] = reverse_frame[operands[1]];
598 new_reverse_frame[i].value
599 -= reverse_frame[operands[2]].value;
600 }
601 else
602 {
603 /* We don't know anything about the values. Punt. */
604 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
605 }
606 reverse_frame_valid |= 1 << i;
607 dest_regs[i] = operands[0];
608 break;
609
610 case TILEGX_OPC_FNOP:
611 case TILEGX_OPC_INFO:
612 case TILEGX_OPC_INFOL:
613 /* Nothing to see here, move on.
614 Note that real NOP is treated as a 'real' instruction
615 because someone must have intended that it be there.
616 It therefore terminates the prolog. */
617 break;
618
619 case TILEGX_OPC_J:
620 case TILEGX_OPC_JAL:
621
622 case TILEGX_OPC_BEQZ:
623 case TILEGX_OPC_BEQZT:
624 case TILEGX_OPC_BGEZ:
625 case TILEGX_OPC_BGEZT:
626 case TILEGX_OPC_BGTZ:
627 case TILEGX_OPC_BGTZT:
628 case TILEGX_OPC_BLBC:
629 case TILEGX_OPC_BLBCT:
630 case TILEGX_OPC_BLBS:
631 case TILEGX_OPC_BLBST:
632 case TILEGX_OPC_BLEZ:
633 case TILEGX_OPC_BLEZT:
634 case TILEGX_OPC_BLTZ:
635 case TILEGX_OPC_BLTZT:
636 case TILEGX_OPC_BNEZ:
637 case TILEGX_OPC_BNEZT:
638
639 case TILEGX_OPC_IRET:
640 case TILEGX_OPC_JALR:
641 case TILEGX_OPC_JALRP:
642 case TILEGX_OPC_JR:
643 case TILEGX_OPC_JRP:
644 case TILEGX_OPC_SWINT0:
645 case TILEGX_OPC_SWINT1:
646 case TILEGX_OPC_SWINT2:
647 case TILEGX_OPC_SWINT3:
648 /* We're really done -- this is a branch. */
649 branch_seen = 1;
650 prolog_done = 1;
651 break;
652 default:
653 /* We don't know or care what this instruction is.
654 All we know is that it isn't part of a prolog, and if
655 there's a destination register, we're trashing it. */
656 prolog_done = 1;
657 for (j = 0; j < opcode->num_operands; j++)
658 {
659 if (this_insn->operands[j]->is_dest_reg)
660 {
661 dest_regs[i] = operands[j];
662 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
663 reverse_frame_valid |= 1 << i;
664 break;
665 }
666 }
667 break;
668 }
669 }
670
671 /* Now update the reverse frames. */
672 for (i = 0; i < num_insns; i++)
673 {
674 /* ISSUE: Does this properly handle "network" registers? */
675 if ((reverse_frame_valid & (1 << i))
676 && dest_regs[i] != TILEGX_ZERO_REGNUM)
677 reverse_frame[dest_regs[i]] = new_reverse_frame[i];
678 }
679
680 if (prev_sp_value != 0)
681 {
682 /* GCC uses R52 as a frame pointer. Have we seen "move r52, sp"? */
683 if (reverse_frame[TILEGX_R52_REGNUM].state == REVERSE_STATE_REGISTER
684 && reverse_frame[TILEGX_R52_REGNUM].value == TILEGX_SP_REGNUM)
685 {
686 reverse_frame[TILEGX_R52_REGNUM].state = REVERSE_STATE_VALUE;
687 reverse_frame[TILEGX_R52_REGNUM].value = prev_sp_value;
688 }
689
690 prev_sp_value = 0;
691 }
692
693 if (prolog_done && prolog_end == end_addr)
694 {
695 /* We found non-prolog code. As such, _this_ instruction
696 is the one after the prolog. We keep processing, because
697 there may be more prolog code in there, but this is what
698 we'll return. */
699 /* ISSUE: There may not have actually been a prologue, and
700 we may have simply skipped some random instructions. */
701 prolog_end = next_addr;
702 }
703 if (branch_seen)
704 {
705 /* We saw a branch. The prolog absolutely must be over. */
706 break;
707 }
708 }
709
710 if (prolog_end == end_addr && cache)
711 {
712 /* We may have terminated the prolog early, and we're certainly
713 at THIS point right now. It's possible that the values of
714 registers we need are currently actually in other registers
715 (and haven't been written to memory yet). Go find them. */
716 for (i = 0; i < TILEGX_NUM_PHYS_REGS; i++)
717 {
718 if (reverse_frame[i].state == REVERSE_STATE_REGISTER
719 && reverse_frame[i].value != i)
720 {
721 unsigned saved_register = (unsigned) reverse_frame[i].value;
722
723 cache->saved_regs[saved_register].realreg = i;
724 cache->saved_regs[saved_register].addr = (LONGEST) -1;
725 }
726 }
727 }
728
3361b059
WL		 729 if (lr_saved_on_stack_p)
730 {
731 cache->saved_regs[TILEGX_LR_REGNUM].realreg = TILEGX_LR_REGNUM;
732 cache->saved_regs[TILEGX_LR_REGNUM].addr =
733 cache->saved_regs[TILEGX_SP_REGNUM].addr;
734 }
735
ade64f0e
PA		 736 return prolog_end;
737}
738
739/* This is the implementation of gdbarch method skip_prologue. */
740
741static CORE_ADDR
3e9d5130 742tilegx_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
ade64f0e 743{
d79e58d8
JW		 744 CORE_ADDR func_start, end_pc;
745 struct obj_section *s;
ade64f0e
PA		 746
747 /* This is the preferred method, find the end of the prologue by
748 using the debugging information. */
3e9d5130 749 if (find_pc_partial_function (start_pc, NULL, &func_start, NULL))
ade64f0e 750 {
3e9d5130
WL		 751 CORE_ADDR post_prologue_pc
752 = skip_prologue_using_sal (gdbarch, func_start);
ade64f0e 753
3e9d5130
WL		 754 if (post_prologue_pc != 0)
755 return max (start_pc, post_prologue_pc);
ade64f0e
PA		 756 }
757
d79e58d8
JW		 758 /* Don't straddle a section boundary. */
759 s = find_pc_section (start_pc);
760 end_pc = start_pc + 8 * TILEGX_BUNDLE_SIZE_IN_BYTES;
761 if (s != NULL)
762 end_pc = min (end_pc, obj_section_endaddr (s));
763
ade64f0e
PA		 764 /* Otherwise, try to skip prologue the hard way. */
765 return tilegx_analyze_prologue (gdbarch,
3e9d5130 766 start_pc,
d79e58d8 767 end_pc,
ade64f0e
PA		 768 NULL, NULL);
769}
770
c9cf6e20 771/* This is the implementation of gdbarch method stack_frame_destroyed_p. */
ade64f0e
PA		 772
773static int
c9cf6e20 774tilegx_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
ade64f0e
PA		 775{
776 CORE_ADDR func_addr = 0, func_end = 0;
777
778 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
779 {
ade64f0e
PA		 780 CORE_ADDR addr = func_end - TILEGX_BUNDLE_SIZE_IN_BYTES;
781
782 /* FIXME: Find the actual epilogue. */
783 /* HACK: Just assume the final bundle is the "ret" instruction". */
784 if (pc > addr)
785 return 1;
786 }
787 return 0;
788}
789
61d8bd0e
JW		 790/* This is the implementation of gdbarch method get_longjmp_target. */
791
792static int
793tilegx_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
794{
795 struct gdbarch *gdbarch = get_frame_arch (frame);
796 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
797 CORE_ADDR jb_addr;
798 gdb_byte buf[8];
799
800 jb_addr = get_frame_register_unsigned (frame, TILEGX_R0_REGNUM);
801
802 /* TileGX jmp_buf contains 32 elements of type __uint_reg_t which
803 has a size of 8 bytes. The return address is stored in the 25th
804 slot. */
805 if (target_read_memory (jb_addr + 25 * 8, buf, 8))
806 return 0;
807
808 *pc = extract_unsigned_integer (buf, 8, byte_order);
809
810 return 1;
811}
812
4aaf2503
WL		 813/* by assigning the 'faultnum' reg in kernel pt_regs with this value,
814 kernel do_signal will not check r0. see tilegx kernel/signal.c
815 for details. */
816#define INT_SWINT_1_SIGRETURN (~0)
817
818/* Implement the "write_pc" gdbarch method. */
819
820static void
821tilegx_write_pc (struct regcache *regcache, CORE_ADDR pc)
822{
823 regcache_cooked_write_unsigned (regcache, TILEGX_PC_REGNUM, pc);
824
825 /* We must be careful with modifying the program counter. If we
826 just interrupted a system call, the kernel might try to restart
827 it when we resume the inferior. On restarting the system call,
828 the kernel will try backing up the program counter even though it
829 no longer points at the system call. This typically results in a
830 SIGSEGV or SIGILL. We can prevent this by writing INT_SWINT_1_SIGRETURN
831 in the "faultnum" pseudo-register.
832
833 Note that "faultnum" is saved when setting up a dummy call frame.
834 This means that it is properly restored when that frame is
835 popped, and that the interrupted system call will be restarted
836 when we resume the inferior on return from a function call from
837 within GDB. In all other cases the system call will not be
838 restarted. */
839 regcache_cooked_write_unsigned (regcache, TILEGX_FAULTNUM_REGNUM,
840 INT_SWINT_1_SIGRETURN);
841}
842
ade64f0e
PA		 843/* This is the implementation of gdbarch method breakpoint_from_pc. */
844
845static const unsigned char *
846tilegx_breakpoint_from_pc (struct gdbarch *gdbarch,
847 CORE_ADDR *pcptr, int *lenptr)
848{
849 /* 64-bit pattern for a { bpt ; nop } bundle. */
850 static const unsigned char breakpoint[] =
851 { 0x00, 0x50, 0x48, 0x51, 0xae, 0x44, 0x6a, 0x28 };
852
853 *lenptr = sizeof (breakpoint);
854 return breakpoint;
855}
856
857/* Normal frames. */
858
859static struct tilegx_frame_cache *
860tilegx_frame_cache (struct frame_info *this_frame, void **this_cache)
861{
862 struct gdbarch *gdbarch = get_frame_arch (this_frame);
863 struct tilegx_frame_cache *cache;
864 CORE_ADDR current_pc;
ade64f0e
PA		 865
866 if (*this_cache)
19ba03f4 867 return (struct tilegx_frame_cache *) *this_cache;
ade64f0e
PA		 868
869 cache = FRAME_OBSTACK_ZALLOC (struct tilegx_frame_cache);
870 *this_cache = cache;
871 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
872 cache->base = 0;
873 cache->start_pc = get_frame_func (this_frame);
874 current_pc = get_frame_pc (this_frame);
875
876 cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
877 trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base);
878
ade64f0e
PA		 879 if (cache->start_pc)
880 tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc,
881 cache, this_frame);
882
3361b059
WL		 883 cache->saved_regs[TILEGX_PC_REGNUM] = cache->saved_regs[TILEGX_LR_REGNUM];
884
ade64f0e
PA		 885 return cache;
886}
887
888/* Retrieve the value of REGNUM in FRAME. */
889
890static struct value*
891tilegx_frame_prev_register (struct frame_info *this_frame,
892 void **this_cache,
893 int regnum)
894{
895 struct tilegx_frame_cache *info =
896 tilegx_frame_cache (this_frame, this_cache);
897
898 return trad_frame_get_prev_register (this_frame, info->saved_regs,
899 regnum);
900}
901
902/* Build frame id. */
903
904static void
905tilegx_frame_this_id (struct frame_info *this_frame, void **this_cache,
906 struct frame_id *this_id)
907{
908 struct tilegx_frame_cache *info =
909 tilegx_frame_cache (this_frame, this_cache);
910
911 /* This marks the outermost frame. */
912 if (info->base == 0)
913 return;
914
915 (*this_id) = frame_id_build (info->base, info->start_pc);
916}
917
918static CORE_ADDR
919tilegx_frame_base_address (struct frame_info *this_frame, void **this_cache)
920{
921 struct tilegx_frame_cache *cache =
922 tilegx_frame_cache (this_frame, this_cache);
923
924 return cache->base;
925}
926
927static const struct frame_unwind tilegx_frame_unwind = {
928 NORMAL_FRAME,
929 default_frame_unwind_stop_reason,
930 tilegx_frame_this_id,
931 tilegx_frame_prev_register,
932 NULL, /* const struct frame_data *unwind_data */
933 default_frame_sniffer, /* frame_sniffer_ftype *sniffer */
934 NULL /* frame_prev_pc_ftype *prev_pc */
935};
936
937static const struct frame_base tilegx_frame_base = {
938 &tilegx_frame_unwind,
939 tilegx_frame_base_address,
940 tilegx_frame_base_address,
941 tilegx_frame_base_address
942};
943
944static CORE_ADDR
945tilegx_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
946{
947 return frame_unwind_register_unsigned (next_frame, TILEGX_SP_REGNUM);
948}
949
950static CORE_ADDR
951tilegx_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
952{
953 return frame_unwind_register_unsigned (next_frame, TILEGX_PC_REGNUM);
954}
955
956static struct frame_id
957tilegx_unwind_dummy_id (struct gdbarch *gdbarch,
958 struct frame_info *this_frame)
959{
960 CORE_ADDR sp;
961
962 sp = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
963 return frame_id_build (sp, get_frame_pc (this_frame));
964}
965
966
967/* We cannot read/write the "special" registers. */
968
969static int
970tilegx_cannot_reference_register (struct gdbarch *gdbarch, int regno)
971{
972 if (regno >= 0 && regno < TILEGX_NUM_EASY_REGS)
973 return 0;
4aaf2503
WL		 974 else if (regno == TILEGX_PC_REGNUM
975 || regno == TILEGX_FAULTNUM_REGNUM)
ade64f0e
PA		 976 return 0;
977 else
978 return 1;
979}
980
981static struct gdbarch *
982tilegx_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
983{
984 struct gdbarch *gdbarch;
985 int arch_size = 64;
986
987 /* Handle arch_size == 32 or 64. Default to 64. */
988 if (info.abfd)
989 arch_size = bfd_get_arch_size (info.abfd);
990
991 /* Try to find a pre-existing architecture. */
992 for (arches = gdbarch_list_lookup_by_info (arches, &info);
993 arches != NULL;
994 arches = gdbarch_list_lookup_by_info (arches->next, &info))
995 {
996 /* We only have two flavors -- just make sure arch_size matches. */
997 if (gdbarch_ptr_bit (arches->gdbarch) == arch_size)
998 return (arches->gdbarch);
999 }
1000
1001 gdbarch = gdbarch_alloc (&info, NULL);
1002
1003 /* Basic register fields and methods, datatype sizes and stuff. */
1004
1005 /* There are 64 physical registers which can be referenced by
1006 instructions (although only 56 of them can actually be
1007 debugged) and 1 magic register (the PC). The other three
1008 magic registers (ex1, syscall, orig_r0) which are known to
1009 "ptrace" are ignored by "gdb". Note that we simply pretend
1010 that there are 65 registers, and no "pseudo registers". */
1011 set_gdbarch_num_regs (gdbarch, TILEGX_NUM_REGS);
1012 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1013
1014 set_gdbarch_sp_regnum (gdbarch, TILEGX_SP_REGNUM);
1015 set_gdbarch_pc_regnum (gdbarch, TILEGX_PC_REGNUM);
1016
1017 set_gdbarch_register_name (gdbarch, tilegx_register_name);
1018 set_gdbarch_register_type (gdbarch, tilegx_register_type);
1019
ade64f0e
PA		 1020 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1021 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1022 set_gdbarch_long_bit (gdbarch, arch_size);
1023 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1024
1025 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1026 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1027 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1028
1029 set_gdbarch_ptr_bit (gdbarch, arch_size);
1030 set_gdbarch_addr_bit (gdbarch, arch_size);
1031
1032 set_gdbarch_cannot_fetch_register (gdbarch,
1033 tilegx_cannot_reference_register);
1034 set_gdbarch_cannot_store_register (gdbarch,
1035 tilegx_cannot_reference_register);
1036
1037 /* Stack grows down. */
1038 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1039
1040 /* Frame Info. */
1041 set_gdbarch_unwind_sp (gdbarch, tilegx_unwind_sp);
1042 set_gdbarch_unwind_pc (gdbarch, tilegx_unwind_pc);
1043 set_gdbarch_dummy_id (gdbarch, tilegx_unwind_dummy_id);
1044 set_gdbarch_frame_align (gdbarch, tilegx_frame_align);
1045 frame_base_set_default (gdbarch, &tilegx_frame_base);
1046
1047 set_gdbarch_skip_prologue (gdbarch, tilegx_skip_prologue);
1048
c9cf6e20 1049 set_gdbarch_stack_frame_destroyed_p (gdbarch, tilegx_stack_frame_destroyed_p);
ade64f0e
PA		 1050
1051 /* Map debug registers into internal register numbers. */
1052 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, tilegx_dwarf2_reg_to_regnum);
1053
1054 /* These values and methods are used when gdb calls a target function. */
1055 set_gdbarch_push_dummy_call (gdbarch, tilegx_push_dummy_call);
61d8bd0e 1056 set_gdbarch_get_longjmp_target (gdbarch, tilegx_get_longjmp_target);
4aaf2503 1057 set_gdbarch_write_pc (gdbarch, tilegx_write_pc);
ade64f0e
PA		 1058 set_gdbarch_breakpoint_from_pc (gdbarch, tilegx_breakpoint_from_pc);
1059 set_gdbarch_return_value (gdbarch, tilegx_return_value);
1060
1061 set_gdbarch_print_insn (gdbarch, print_insn_tilegx);
1062
1063 gdbarch_init_osabi (info, gdbarch);
1064
1065 dwarf2_append_unwinders (gdbarch);
1066 frame_unwind_append_unwinder (gdbarch, &tilegx_frame_unwind);
1067
1068 return gdbarch;
1069}
1070
1071/* Provide a prototype to silence -Wmissing-prototypes. */
1072extern initialize_file_ftype _initialize_tilegx_tdep;
1073
1074void
1075_initialize_tilegx_tdep (void)
1076{
1077 register_gdbarch_init (bfd_arch_tilegx, tilegx_gdbarch_init);
1078}
GDB Binutils - Deliverables
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