Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
aa8d21c9 TBA |
63 | const regs_info *get_regs_info () override; |
64 | ||
06250e4e TBA |
65 | int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; |
66 | ||
67 | int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; | |
68 | ||
3ca4edb6 TBA |
69 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
70 | ||
7582c77c TBA |
71 | bool supports_software_single_step () override; |
72 | ||
007c9b97 TBA |
73 | bool supports_z_point_type (char z_type) override; |
74 | ||
797bcff5 TBA |
75 | protected: |
76 | ||
77 | void low_arch_setup () override; | |
daca57a7 TBA |
78 | |
79 | bool low_cannot_fetch_register (int regno) override; | |
80 | ||
81 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
82 | |
83 | bool low_supports_breakpoints () override; | |
84 | ||
85 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
86 | ||
87 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
7582c77c TBA |
88 | |
89 | std::vector<CORE_ADDR> low_get_next_pcs (regcache *regcache) override; | |
d7146cda TBA |
90 | |
91 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
ef0478f6 TBA |
92 | }; |
93 | ||
94 | /* The singleton target ops object. */ | |
95 | ||
96 | static arm_target the_arm_target; | |
97 | ||
bf9ae9d8 TBA |
98 | bool |
99 | arm_target::low_supports_breakpoints () | |
100 | { | |
101 | return true; | |
102 | } | |
103 | ||
104 | CORE_ADDR | |
105 | arm_target::low_get_pc (regcache *regcache) | |
106 | { | |
107 | return linux_get_pc_32bit (regcache); | |
108 | } | |
109 | ||
110 | void | |
111 | arm_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
112 | { | |
113 | linux_set_pc_32bit (regcache, pc); | |
114 | } | |
115 | ||
06250e4e TBA |
116 | int |
117 | arm_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
118 | { | |
119 | return arm_breakpoint_kind_from_pc (pcptr); | |
120 | } | |
121 | ||
122 | int | |
123 | arm_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
124 | { | |
125 | return arm_breakpoint_kind_from_current_state (pcptr); | |
126 | } | |
127 | ||
3ca4edb6 TBA |
128 | const gdb_byte * |
129 | arm_target::sw_breakpoint_from_kind (int kind, int *size) | |
130 | { | |
131 | return arm_sw_breakpoint_from_kind (kind, size); | |
132 | } | |
133 | ||
d7146cda TBA |
134 | bool |
135 | arm_target::low_breakpoint_at (CORE_ADDR pc) | |
136 | { | |
137 | return arm_breakpoint_at (pc); | |
138 | } | |
139 | ||
09b4ad9f | 140 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 141 | static struct |
09b4ad9f UW |
142 | { |
143 | unsigned char arch; | |
144 | unsigned char max_wp_length; | |
145 | unsigned char wp_count; | |
146 | unsigned char bp_count; | |
71487fd7 | 147 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
148 | |
149 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
150 | typedef enum | |
151 | { | |
152 | arm_hwbp_break = 0, | |
153 | arm_hwbp_load = 1, | |
154 | arm_hwbp_store = 2, | |
155 | arm_hwbp_access = 3 | |
156 | } arm_hwbp_type; | |
157 | ||
158 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
159 | typedef unsigned int arm_hwbp_control_t; | |
160 | ||
161 | /* Structure used to keep track of hardware break-/watch-points. */ | |
162 | struct arm_linux_hw_breakpoint | |
163 | { | |
164 | /* Address to break on, or being watched. */ | |
165 | unsigned int address; | |
166 | /* Control register for break-/watch- point. */ | |
167 | arm_hwbp_control_t control; | |
168 | }; | |
169 | ||
170 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
171 | assume a maximum number of supported break-/watchpoints. */ | |
172 | #define MAX_BPTS 32 | |
173 | #define MAX_WPTS 32 | |
174 | ||
175 | /* Per-process arch-specific data we want to keep. */ | |
176 | struct arch_process_info | |
177 | { | |
178 | /* Hardware breakpoints for this process. */ | |
179 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
180 | /* Hardware watchpoints for this process. */ | |
181 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
182 | }; | |
183 | ||
184 | /* Per-thread arch-specific data we want to keep. */ | |
185 | struct arch_lwp_info | |
186 | { | |
187 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
188 | char bpts_changed[MAX_BPTS]; | |
189 | char wpts_changed[MAX_WPTS]; | |
190 | /* Cached stopped data address. */ | |
191 | CORE_ADDR stopped_data_address; | |
192 | }; | |
193 | ||
58d6951d DJ |
194 | /* These are in <asm/elf.h> in current kernels. */ |
195 | #define HWCAP_VFP 64 | |
196 | #define HWCAP_IWMMXT 512 | |
197 | #define HWCAP_NEON 4096 | |
198 | #define HWCAP_VFPv3 8192 | |
199 | #define HWCAP_VFPv3D16 16384 | |
200 | ||
0a30fbc4 DJ |
201 | #ifdef HAVE_SYS_REG_H |
202 | #include <sys/reg.h> | |
203 | #endif | |
204 | ||
23ce3b1c | 205 | #define arm_num_regs 26 |
0a30fbc4 | 206 | |
2ec06d2e | 207 | static int arm_regmap[] = { |
0a30fbc4 DJ |
208 | 0, 4, 8, 12, 16, 20, 24, 28, |
209 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
210 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
211 | 64 | |
0a30fbc4 DJ |
212 | }; |
213 | ||
d9311bfa AT |
214 | /* Forward declarations needed for get_next_pcs ops. */ |
215 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
216 | int len, | |
217 | int byte_order); | |
218 | ||
219 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
220 | CORE_ADDR val); | |
221 | ||
553cb527 | 222 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
223 | |
224 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
225 | ||
226 | /* get_next_pcs operations. */ | |
227 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
228 | get_next_pcs_read_memory_unsigned_integer, | |
229 | get_next_pcs_syscall_next_pc, | |
230 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
231 | get_next_pcs_is_thumb, |
232 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
233 | }; |
234 | ||
daca57a7 TBA |
235 | bool |
236 | arm_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 237 | { |
2ec06d2e | 238 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
239 | } |
240 | ||
daca57a7 TBA |
241 | bool |
242 | arm_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 243 | { |
2ec06d2e | 244 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
245 | } |
246 | ||
fb1e4ffc | 247 | static void |
442ea881 | 248 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 249 | { |
7cc17433 | 250 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
251 | return; |
252 | ||
166a82be | 253 | for (int i = 0; i < 16; i++) |
442ea881 | 254 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
255 | |
256 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 257 | for (int i = 0; i < 6; i++) |
442ea881 PA |
258 | collect_register (regcache, arm_num_regs + i + 16, |
259 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
260 | } |
261 | ||
262 | static void | |
442ea881 | 263 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 264 | { |
7cc17433 | 265 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
266 | return; |
267 | ||
166a82be | 268 | for (int i = 0; i < 16; i++) |
442ea881 | 269 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
270 | |
271 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 272 | for (int i = 0; i < 6; i++) |
442ea881 PA |
273 | supply_register (regcache, arm_num_regs + i + 16, |
274 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
275 | } |
276 | ||
58d6951d | 277 | static void |
442ea881 | 278 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 279 | { |
bd9e6534 | 280 | int num; |
58d6951d | 281 | |
7cc17433 | 282 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 283 | num = 32; |
89abb039 | 284 | else |
7cc17433 AH |
285 | { |
286 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
287 | ||
288 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
289 | num = 32; | |
290 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
291 | num = 16; | |
292 | else | |
293 | return; | |
294 | } | |
58d6951d | 295 | |
bd9e6534 | 296 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
297 | } |
298 | ||
d9311bfa AT |
299 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
300 | static CORE_ADDR | |
301 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
302 | { | |
303 | return UNMAKE_THUMB_ADDR (val); | |
304 | } | |
305 | ||
58d6951d | 306 | static void |
442ea881 | 307 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 308 | { |
bd9e6534 | 309 | int num; |
58d6951d | 310 | |
7cc17433 | 311 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 312 | num = 32; |
89abb039 | 313 | else |
7cc17433 AH |
314 | { |
315 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
316 | ||
317 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
318 | num = 32; | |
319 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
320 | num = 16; | |
321 | else | |
322 | return; | |
323 | } | |
58d6951d | 324 | |
bd9e6534 | 325 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 326 | } |
fb1e4ffc | 327 | |
d9311bfa AT |
328 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
329 | static int | |
330 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
331 | { | |
332 | return arm_is_thumb_mode (); | |
333 | } | |
334 | ||
30baf67b | 335 | /* Read memory from the inferior. |
d9311bfa AT |
336 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
337 | read_memory_unsigned_integer. */ | |
338 | static ULONGEST | |
339 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
340 | int len, | |
341 | int byte_order) | |
342 | { | |
343 | ULONGEST res; | |
344 | ||
9e784964 | 345 | res = 0; |
694b382c AT |
346 | target_read_memory (memaddr, (unsigned char *) &res, len); |
347 | ||
d9311bfa AT |
348 | return res; |
349 | } | |
350 | ||
9308fc88 DJ |
351 | /* Fetch the thread-local storage pointer for libthread_db. */ |
352 | ||
353 | ps_err_e | |
754653a7 | 354 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 355 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
356 | { |
357 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
358 | return PS_ERR; | |
359 | ||
360 | /* IDX is the bias from the thread pointer to the beginning of the | |
361 | thread descriptor. It has to be subtracted due to implementation | |
362 | quirks in libthread_db. */ | |
363 | *base = (void *) ((char *)*base - idx); | |
364 | ||
365 | return PS_OK; | |
366 | } | |
367 | ||
09b4ad9f | 368 | |
71487fd7 UW |
369 | /* Query Hardware Breakpoint information for the target we are attached to |
370 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
371 | static void | |
372 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 373 | { |
71487fd7 | 374 | unsigned int val; |
09b4ad9f | 375 | |
71487fd7 UW |
376 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
377 | return; | |
09b4ad9f | 378 | |
71487fd7 UW |
379 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
380 | if (arm_linux_hwbp_cap.arch == 0) | |
381 | return; | |
09b4ad9f | 382 | |
71487fd7 UW |
383 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
384 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
385 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 386 | |
71487fd7 UW |
387 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
388 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
389 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
390 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
391 | } |
392 | ||
393 | /* How many hardware breakpoints are available? */ | |
394 | static int | |
395 | arm_linux_get_hw_breakpoint_count (void) | |
396 | { | |
71487fd7 | 397 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
398 | } |
399 | ||
400 | /* How many hardware watchpoints are available? */ | |
401 | static int | |
402 | arm_linux_get_hw_watchpoint_count (void) | |
403 | { | |
71487fd7 | 404 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
405 | } |
406 | ||
407 | /* Maximum length of area watched by hardware watchpoint. */ | |
408 | static int | |
409 | arm_linux_get_hw_watchpoint_max_length (void) | |
410 | { | |
71487fd7 | 411 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
412 | } |
413 | ||
414 | /* Initialize an ARM hardware break-/watch-point control register value. | |
415 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
416 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
417 | */ | |
418 | static arm_hwbp_control_t | |
419 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
420 | arm_hwbp_type hwbp_type, | |
421 | int enable) | |
422 | { | |
423 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
424 | gdb_assert (hwbp_type != arm_hwbp_break | |
425 | || ((byte_address_select & 0xfU) != 0)); | |
426 | ||
427 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
428 | } | |
429 | ||
430 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
431 | static int | |
432 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
433 | { | |
434 | return control & 0x1; | |
435 | } | |
436 | ||
437 | /* Is the breakpoint control value CONTROL initialized? */ | |
438 | static int | |
439 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
440 | { | |
441 | return control != 0; | |
442 | } | |
443 | ||
444 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
445 | static arm_hwbp_control_t | |
446 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
447 | { | |
448 | return control & ~0x1; | |
449 | } | |
450 | ||
451 | /* Are two break-/watch-points equal? */ | |
452 | static int | |
453 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
454 | const struct arm_linux_hw_breakpoint *p2) | |
455 | { | |
456 | return p1->address == p2->address && p1->control == p2->control; | |
457 | } | |
458 | ||
802e8e6d PA |
459 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
460 | ||
171de4b8 | 461 | static arm_hwbp_type |
802e8e6d PA |
462 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
463 | { | |
464 | switch (raw_type) | |
465 | { | |
466 | case raw_bkpt_type_hw: | |
467 | return arm_hwbp_break; | |
468 | case raw_bkpt_type_write_wp: | |
469 | return arm_hwbp_store; | |
470 | case raw_bkpt_type_read_wp: | |
471 | return arm_hwbp_load; | |
472 | case raw_bkpt_type_access_wp: | |
473 | return arm_hwbp_access; | |
474 | default: | |
475 | gdb_assert_not_reached ("unhandled raw type"); | |
476 | } | |
477 | } | |
478 | ||
09b4ad9f UW |
479 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
480 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
481 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
482 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
483 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 484 | static int |
802e8e6d PA |
485 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
486 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
487 | { |
488 | arm_hwbp_type hwbp_type; | |
489 | unsigned mask; | |
490 | ||
802e8e6d | 491 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
492 | |
493 | if (hwbp_type == arm_hwbp_break) | |
494 | { | |
495 | /* For breakpoints, the length field encodes the mode. */ | |
496 | switch (len) | |
497 | { | |
498 | case 2: /* 16-bit Thumb mode breakpoint */ | |
499 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
500 | mask = 0x3; |
501 | addr &= ~1; | |
09b4ad9f UW |
502 | break; |
503 | case 4: /* 32-bit ARM mode breakpoint */ | |
504 | mask = 0xf; | |
fcf303ab | 505 | addr &= ~3; |
09b4ad9f UW |
506 | break; |
507 | default: | |
508 | /* Unsupported. */ | |
b62e2b27 | 509 | return -2; |
09b4ad9f | 510 | } |
09b4ad9f UW |
511 | } |
512 | else | |
513 | { | |
514 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
515 | CORE_ADDR aligned_addr; | |
516 | ||
517 | /* Can not set watchpoints for zero or negative lengths. */ | |
518 | if (len <= 0) | |
b62e2b27 | 519 | return -2; |
09b4ad9f UW |
520 | /* The current ptrace interface can only handle watchpoints that are a |
521 | power of 2. */ | |
522 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 523 | return -2; |
09b4ad9f UW |
524 | |
525 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
526 | range covered by a watchpoint. */ | |
527 | aligned_addr = addr & ~(max_wp_length - 1); | |
528 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 529 | return -2; |
09b4ad9f UW |
530 | |
531 | mask = (1 << len) - 1; | |
532 | } | |
533 | ||
534 | p->address = (unsigned int) addr; | |
535 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
536 | ||
537 | return hwbp_type != arm_hwbp_break; | |
538 | } | |
539 | ||
540 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
541 | the current process. */ | |
542 | ||
00192f77 SM |
543 | static void |
544 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 545 | { |
d86d4aaf | 546 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 547 | |
00192f77 SM |
548 | /* The actual update is done later just before resuming the lwp, |
549 | we just mark that the registers need updating. */ | |
550 | if (watch) | |
551 | lwp->arch_private->wpts_changed[i] = 1; | |
552 | else | |
553 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 554 | |
00192f77 SM |
555 | /* If the lwp isn't stopped, force it to momentarily pause, so |
556 | we can update its breakpoint registers. */ | |
557 | if (!lwp->stopped) | |
558 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
559 | } |
560 | ||
007c9b97 TBA |
561 | bool |
562 | arm_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
563 | { |
564 | switch (z_type) | |
565 | { | |
abeead09 | 566 | case Z_PACKET_SW_BP: |
802e8e6d PA |
567 | case Z_PACKET_HW_BP: |
568 | case Z_PACKET_WRITE_WP: | |
569 | case Z_PACKET_READ_WP: | |
570 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 571 | return true; |
802e8e6d PA |
572 | default: |
573 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
007c9b97 | 574 | return false; |
802e8e6d PA |
575 | } |
576 | } | |
577 | ||
09b4ad9f UW |
578 | /* Insert hardware break-/watchpoint. */ |
579 | static int | |
802e8e6d PA |
580 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
581 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
582 | { |
583 | struct process_info *proc = current_process (); | |
584 | struct arm_linux_hw_breakpoint p, *pts; | |
585 | int watch, i, count; | |
586 | ||
587 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
588 | if (watch < 0) | |
589 | { | |
590 | /* Unsupported. */ | |
b62e2b27 | 591 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
592 | } |
593 | ||
594 | if (watch) | |
595 | { | |
596 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 597 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
598 | } |
599 | else | |
600 | { | |
601 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 602 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
603 | } |
604 | ||
605 | for (i = 0; i < count; i++) | |
606 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
607 | { | |
09b4ad9f | 608 | pts[i] = p; |
00192f77 SM |
609 | |
610 | /* Only update the threads of the current process. */ | |
611 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
612 | { | |
613 | update_registers_callback (thread, watch, i); | |
614 | }); | |
615 | ||
09b4ad9f UW |
616 | return 0; |
617 | } | |
618 | ||
619 | /* We're out of watchpoints. */ | |
620 | return -1; | |
621 | } | |
622 | ||
623 | /* Remove hardware break-/watchpoint. */ | |
624 | static int | |
802e8e6d PA |
625 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
626 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
627 | { |
628 | struct process_info *proc = current_process (); | |
629 | struct arm_linux_hw_breakpoint p, *pts; | |
630 | int watch, i, count; | |
631 | ||
632 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
633 | if (watch < 0) | |
634 | { | |
635 | /* Unsupported. */ | |
636 | return -1; | |
637 | } | |
638 | ||
639 | if (watch) | |
640 | { | |
641 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 642 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
643 | } |
644 | else | |
645 | { | |
646 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 647 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
648 | } |
649 | ||
650 | for (i = 0; i < count; i++) | |
651 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
652 | { | |
09b4ad9f | 653 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
654 | |
655 | /* Only update the threads of the current process. */ | |
656 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
657 | { | |
658 | update_registers_callback (thread, watch, i); | |
659 | }); | |
660 | ||
09b4ad9f UW |
661 | return 0; |
662 | } | |
663 | ||
664 | /* No watchpoint matched. */ | |
665 | return -1; | |
666 | } | |
667 | ||
668 | /* Return whether current thread is stopped due to a watchpoint. */ | |
669 | static int | |
670 | arm_stopped_by_watchpoint (void) | |
671 | { | |
0bfdf32f | 672 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 673 | siginfo_t siginfo; |
09b4ad9f UW |
674 | |
675 | /* We must be able to set hardware watchpoints. */ | |
676 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
677 | return 0; | |
678 | ||
679 | /* Retrieve siginfo. */ | |
680 | errno = 0; | |
0bfdf32f | 681 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
682 | if (errno != 0) |
683 | return 0; | |
684 | ||
685 | /* This must be a hardware breakpoint. */ | |
686 | if (siginfo.si_signo != SIGTRAP | |
687 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
688 | return 0; | |
689 | ||
690 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
691 | a watchpoint. */ | |
692 | if (siginfo.si_errno >= 0) | |
693 | return 0; | |
694 | ||
695 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
696 | lwp->arch_private->stopped_data_address | |
697 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
698 | ||
699 | return 1; | |
700 | } | |
701 | ||
702 | /* Return data address that triggered watchpoint. Called only if | |
703 | arm_stopped_by_watchpoint returned true. */ | |
704 | static CORE_ADDR | |
705 | arm_stopped_data_address (void) | |
706 | { | |
0bfdf32f | 707 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
708 | return lwp->arch_private->stopped_data_address; |
709 | } | |
710 | ||
711 | /* Called when a new process is created. */ | |
712 | static struct arch_process_info * | |
713 | arm_new_process (void) | |
714 | { | |
8d749320 | 715 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
716 | return info; |
717 | } | |
718 | ||
04ec7890 SM |
719 | /* Called when a process is being deleted. */ |
720 | ||
721 | static void | |
722 | arm_delete_process (struct arch_process_info *info) | |
723 | { | |
724 | xfree (info); | |
725 | } | |
726 | ||
09b4ad9f | 727 | /* Called when a new thread is detected. */ |
34c703da GB |
728 | static void |
729 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 730 | { |
8d749320 | 731 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
732 | int i; |
733 | ||
734 | for (i = 0; i < MAX_BPTS; i++) | |
735 | info->bpts_changed[i] = 1; | |
736 | for (i = 0; i < MAX_WPTS; i++) | |
737 | info->wpts_changed[i] = 1; | |
738 | ||
34c703da | 739 | lwp->arch_private = info; |
09b4ad9f UW |
740 | } |
741 | ||
466eecee SM |
742 | /* Function to call when a thread is being deleted. */ |
743 | ||
744 | static void | |
745 | arm_delete_thread (struct arch_lwp_info *arch_lwp) | |
746 | { | |
747 | xfree (arch_lwp); | |
748 | } | |
749 | ||
3a8a0396 DB |
750 | static void |
751 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
752 | { | |
69291610 HW |
753 | struct arch_process_info *parent_proc_info; |
754 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
755 | struct lwp_info *child_lwp; |
756 | struct arch_lwp_info *child_lwp_info; | |
757 | int i; | |
758 | ||
759 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
760 | gdb_assert (parent->priv != NULL |
761 | && parent->priv->arch_private != NULL); | |
762 | gdb_assert (child->priv != NULL | |
763 | && child->priv->arch_private != NULL); | |
3a8a0396 | 764 | |
69291610 HW |
765 | parent_proc_info = parent->priv->arch_private; |
766 | child_proc_info = child->priv->arch_private; | |
767 | ||
3a8a0396 DB |
768 | /* Linux kernel before 2.6.33 commit |
769 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
770 | will inherit hardware debug registers from parent | |
771 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
772 | zeroed debug registers. | |
773 | ||
774 | GDB core assumes the child inherits the watchpoints/hw | |
775 | breakpoints of the parent, and will remove them all from the | |
776 | forked off process. Copy the debug registers mirrors into the | |
777 | new process so that all breakpoints and watchpoints can be | |
778 | removed together. The debug registers mirror will become zeroed | |
779 | in the end before detaching the forked off process, thus making | |
780 | this compatible with older Linux kernels too. */ | |
781 | ||
782 | *child_proc_info = *parent_proc_info; | |
783 | ||
784 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
785 | make sure that the registers will be updated. */ | |
9179355e | 786 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
787 | child_lwp_info = child_lwp->arch_private; |
788 | for (i = 0; i < MAX_BPTS; i++) | |
789 | child_lwp_info->bpts_changed[i] = 1; | |
790 | for (i = 0; i < MAX_WPTS; i++) | |
791 | child_lwp_info->wpts_changed[i] = 1; | |
792 | } | |
793 | ||
09b4ad9f UW |
794 | /* Called when resuming a thread. |
795 | If the debug regs have changed, update the thread's copies. */ | |
796 | static void | |
797 | arm_prepare_to_resume (struct lwp_info *lwp) | |
798 | { | |
d86d4aaf DE |
799 | struct thread_info *thread = get_lwp_thread (lwp); |
800 | int pid = lwpid_of (thread); | |
801 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 802 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
803 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
804 | int i; | |
805 | ||
806 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
807 | if (lwp_info->bpts_changed[i]) | |
808 | { | |
809 | errno = 0; | |
810 | ||
811 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 812 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 813 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 814 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 815 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
816 | |
817 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 818 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 819 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 820 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 821 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
822 | |
823 | lwp_info->bpts_changed[i] = 0; | |
824 | } | |
825 | ||
826 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
827 | if (lwp_info->wpts_changed[i]) | |
828 | { | |
829 | errno = 0; | |
830 | ||
831 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 832 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 833 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 834 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 835 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
836 | |
837 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 838 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 839 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 840 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 841 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
842 | |
843 | lwp_info->wpts_changed[i] = 0; | |
844 | } | |
845 | } | |
846 | ||
f7a6a40d YQ |
847 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
848 | addition, set IS_THUMB depending on whether we will return to ARM | |
849 | or Thumb code. | |
d9311bfa AT |
850 | See arm-linux.h for stack layout details. */ |
851 | static CORE_ADDR | |
f7a6a40d YQ |
852 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
853 | int *is_thumb) | |
d9311bfa AT |
854 | { |
855 | unsigned long sp; | |
856 | unsigned long sp_data; | |
857 | /* Offset of PC register. */ | |
858 | int pc_offset = 0; | |
859 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 860 | uint32_t cpsr; |
d9311bfa AT |
861 | |
862 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
863 | ||
864 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 865 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
866 | |
867 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
868 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
869 | ||
52405d85 | 870 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 871 | |
f7a6a40d | 872 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 873 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
874 | *is_thumb = ((cpsr & CPSR_T) != 0); |
875 | ||
d9311bfa AT |
876 | return next_pc; |
877 | } | |
878 | ||
879 | /* When PC is at a syscall instruction, return the PC of the next | |
880 | instruction to be executed. */ | |
881 | static CORE_ADDR | |
553cb527 | 882 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
883 | { |
884 | CORE_ADDR next_pc = 0; | |
553cb527 | 885 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
886 | int is_thumb = arm_is_thumb_mode (); |
887 | ULONGEST svc_number = 0; | |
888 | struct regcache *regcache = self->regcache; | |
889 | ||
890 | if (is_thumb) | |
891 | { | |
892 | collect_register (regcache, 7, &svc_number); | |
893 | next_pc = pc + 2; | |
894 | } | |
895 | else | |
896 | { | |
897 | unsigned long this_instr; | |
898 | unsigned long svc_operand; | |
899 | ||
694b382c | 900 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
901 | svc_operand = (0x00ffffff & this_instr); |
902 | ||
903 | if (svc_operand) /* OABI. */ | |
904 | { | |
905 | svc_number = svc_operand - 0x900000; | |
906 | } | |
907 | else /* EABI. */ | |
908 | { | |
909 | collect_register (regcache, 7, &svc_number); | |
910 | } | |
911 | ||
912 | next_pc = pc + 4; | |
913 | } | |
914 | ||
915 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
916 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
917 | { | |
f7a6a40d YQ |
918 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
919 | update IS_THUMB. */ | |
920 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
921 | } |
922 | ||
923 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
924 | if (is_thumb) | |
925 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
926 | ||
927 | return next_pc; | |
928 | } | |
09b4ad9f | 929 | |
3aee8918 PA |
930 | static const struct target_desc * |
931 | arm_read_description (void) | |
58d6951d | 932 | { |
974c89e0 | 933 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 934 | |
58d6951d | 935 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 936 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
937 | |
938 | if (arm_hwcap & HWCAP_VFP) | |
939 | { | |
166a82be AH |
940 | /* Make sure that the kernel supports reading VFP registers. Support was |
941 | added in 2.6.30. */ | |
942 | int pid = lwpid_of (current_thread); | |
943 | errno = 0; | |
944 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
945 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 946 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
947 | |
948 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
949 | it with VFP. */ | |
950 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 951 | return aarch32_linux_read_description (); |
58d6951d | 952 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 953 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 954 | else |
7cc17433 | 955 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
956 | } |
957 | ||
958 | /* The default configuration uses legacy FPA registers, probably | |
959 | simulated. */ | |
7cc17433 | 960 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
961 | } |
962 | ||
797bcff5 TBA |
963 | void |
964 | arm_target::low_arch_setup () | |
3aee8918 | 965 | { |
bd9e6534 YQ |
966 | int tid = lwpid_of (current_thread); |
967 | int gpregs[18]; | |
968 | struct iovec iov; | |
969 | ||
166a82be AH |
970 | /* Query hardware watchpoint/breakpoint capabilities. */ |
971 | arm_linux_init_hwbp_cap (tid); | |
972 | ||
3aee8918 | 973 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
974 | |
975 | iov.iov_base = gpregs; | |
976 | iov.iov_len = sizeof (gpregs); | |
977 | ||
978 | /* Check if PTRACE_GETREGSET works. */ | |
979 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
980 | have_ptrace_getregset = 1; | |
981 | else | |
982 | have_ptrace_getregset = 0; | |
3aee8918 PA |
983 | } |
984 | ||
7582c77c TBA |
985 | bool |
986 | arm_target::supports_software_single_step () | |
987 | { | |
988 | return true; | |
989 | } | |
990 | ||
d9311bfa AT |
991 | /* Fetch the next possible PCs after the current instruction executes. */ |
992 | ||
7582c77c TBA |
993 | std::vector<CORE_ADDR> |
994 | arm_target::low_get_next_pcs (regcache *regcache) | |
d9311bfa AT |
995 | { |
996 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
997 | |
998 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
999 | &get_next_pcs_ops, | |
1000 | /* Byte order is ignored assumed as host. */ | |
1001 | 0, | |
1002 | 0, | |
1b451dda | 1003 | 1, |
d9311bfa AT |
1004 | regcache); |
1005 | ||
a0ff9e1a | 1006 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
1007 | } |
1008 | ||
7d00775e AT |
1009 | /* Support for hardware single step. */ |
1010 | ||
1011 | static int | |
1012 | arm_supports_hardware_single_step (void) | |
1013 | { | |
1014 | return 0; | |
1015 | } | |
1016 | ||
79e7fd4f YQ |
1017 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
1018 | ||
1019 | static void | |
1020 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
1021 | { | |
1022 | if (arm_is_thumb_mode ()) | |
1023 | collect_register_by_name (regcache, "r7", sysno); | |
1024 | else | |
1025 | { | |
1026 | unsigned long pc; | |
1027 | unsigned long insn; | |
1028 | ||
1029 | collect_register_by_name (regcache, "pc", &pc); | |
1030 | ||
52405d85 | 1031 | if (the_target->read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
1032 | *sysno = UNKNOWN_SYSCALL; |
1033 | else | |
1034 | { | |
1035 | unsigned long svc_operand = (0x00ffffff & insn); | |
1036 | ||
1037 | if (svc_operand) | |
1038 | { | |
1039 | /* OABI */ | |
1040 | *sysno = svc_operand - 0x900000; | |
1041 | } | |
1042 | else | |
1043 | { | |
1044 | /* EABI */ | |
1045 | collect_register_by_name (regcache, "r7", sysno); | |
1046 | } | |
1047 | } | |
1048 | } | |
1049 | } | |
1050 | ||
bd9e6534 YQ |
1051 | /* Register sets without using PTRACE_GETREGSET. */ |
1052 | ||
3aee8918 | 1053 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
1054 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
1055 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 1056 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 1057 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 1058 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 1059 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 1060 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 1061 | NULL_REGSET |
fb1e4ffc DJ |
1062 | }; |
1063 | ||
3aee8918 PA |
1064 | static struct regsets_info arm_regsets_info = |
1065 | { | |
1066 | arm_regsets, /* regsets */ | |
1067 | 0, /* num_regsets */ | |
1068 | NULL, /* disabled_regsets */ | |
1069 | }; | |
1070 | ||
1071 | static struct usrregs_info arm_usrregs_info = | |
1072 | { | |
1073 | arm_num_regs, | |
1074 | arm_regmap, | |
1075 | }; | |
1076 | ||
bd9e6534 | 1077 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1078 | { |
1079 | NULL, /* regset_bitmap */ | |
1080 | &arm_usrregs_info, | |
1081 | &arm_regsets_info | |
1082 | }; | |
1083 | ||
aa8d21c9 TBA |
1084 | const regs_info * |
1085 | arm_target::get_regs_info () | |
3aee8918 | 1086 | { |
bd9e6534 YQ |
1087 | const struct target_desc *tdesc = current_process ()->tdesc; |
1088 | ||
1089 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1090 | && (is_aarch32_linux_description (tdesc) |
1091 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1092 | return ®s_info_aarch32; |
7cc17433 AH |
1093 | |
1094 | return ®s_info_arm; | |
3aee8918 PA |
1095 | } |
1096 | ||
dd373349 | 1097 | struct linux_target_ops the_low_target = { |
09b4ad9f UW |
1098 | arm_insert_point, |
1099 | arm_remove_point, | |
1100 | arm_stopped_by_watchpoint, | |
1101 | arm_stopped_data_address, | |
1102 | NULL, /* collect_ptrace_register */ | |
1103 | NULL, /* supply_ptrace_register */ | |
1104 | NULL, /* siginfo_fixup */ | |
1105 | arm_new_process, | |
04ec7890 | 1106 | arm_delete_process, |
09b4ad9f | 1107 | arm_new_thread, |
466eecee | 1108 | arm_delete_thread, |
3a8a0396 | 1109 | arm_new_fork, |
09b4ad9f | 1110 | arm_prepare_to_resume, |
769ef81f AT |
1111 | NULL, /* process_qsupported */ |
1112 | NULL, /* supports_tracepoints */ | |
1113 | NULL, /* get_thread_area */ | |
1114 | NULL, /* install_fast_tracepoint_jump_pad */ | |
1115 | NULL, /* emit_ops */ | |
1116 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
1117 | NULL, /* supports_range_stepping */ | |
79e7fd4f YQ |
1118 | arm_supports_hardware_single_step, |
1119 | arm_get_syscall_trapinfo, | |
2ec06d2e | 1120 | }; |
3aee8918 | 1121 | |
ef0478f6 TBA |
1122 | /* The linux target ops object. */ |
1123 | ||
1124 | linux_process_target *the_linux_target = &the_arm_target; | |
1125 | ||
3aee8918 PA |
1126 | void |
1127 | initialize_low_arch (void) | |
1128 | { | |
bd9e6534 | 1129 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1130 | initialize_regsets_info (&arm_regsets_info); |
1131 | } |