Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
aa8d21c9 TBA |
63 | const regs_info *get_regs_info () override; |
64 | ||
06250e4e TBA |
65 | int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; |
66 | ||
67 | int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; | |
68 | ||
3ca4edb6 TBA |
69 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
70 | ||
7582c77c TBA |
71 | bool supports_software_single_step () override; |
72 | ||
007c9b97 TBA |
73 | bool supports_z_point_type (char z_type) override; |
74 | ||
797bcff5 TBA |
75 | protected: |
76 | ||
77 | void low_arch_setup () override; | |
daca57a7 TBA |
78 | |
79 | bool low_cannot_fetch_register (int regno) override; | |
80 | ||
81 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
82 | |
83 | bool low_supports_breakpoints () override; | |
84 | ||
85 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
86 | ||
87 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
7582c77c TBA |
88 | |
89 | std::vector<CORE_ADDR> low_get_next_pcs (regcache *regcache) override; | |
d7146cda TBA |
90 | |
91 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
92 | |
93 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
94 | int size, raw_breakpoint *bp) override; | |
95 | ||
96 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
97 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
98 | |
99 | bool low_stopped_by_watchpoint () override; | |
100 | ||
101 | CORE_ADDR low_stopped_data_address () override; | |
fd000fb3 TBA |
102 | |
103 | arch_process_info *low_new_process () override; | |
104 | ||
105 | void low_delete_process (arch_process_info *info) override; | |
106 | ||
107 | void low_new_thread (lwp_info *) override; | |
108 | ||
109 | void low_delete_thread (arch_lwp_info *) override; | |
110 | ||
111 | void low_new_fork (process_info *parent, process_info *child) override; | |
d7599cc0 TBA |
112 | |
113 | void low_prepare_to_resume (lwp_info *lwp) override; | |
ef0478f6 TBA |
114 | }; |
115 | ||
116 | /* The singleton target ops object. */ | |
117 | ||
118 | static arm_target the_arm_target; | |
119 | ||
bf9ae9d8 TBA |
120 | bool |
121 | arm_target::low_supports_breakpoints () | |
122 | { | |
123 | return true; | |
124 | } | |
125 | ||
126 | CORE_ADDR | |
127 | arm_target::low_get_pc (regcache *regcache) | |
128 | { | |
129 | return linux_get_pc_32bit (regcache); | |
130 | } | |
131 | ||
132 | void | |
133 | arm_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
134 | { | |
135 | linux_set_pc_32bit (regcache, pc); | |
136 | } | |
137 | ||
06250e4e TBA |
138 | int |
139 | arm_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
140 | { | |
141 | return arm_breakpoint_kind_from_pc (pcptr); | |
142 | } | |
143 | ||
144 | int | |
145 | arm_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
146 | { | |
147 | return arm_breakpoint_kind_from_current_state (pcptr); | |
148 | } | |
149 | ||
3ca4edb6 TBA |
150 | const gdb_byte * |
151 | arm_target::sw_breakpoint_from_kind (int kind, int *size) | |
152 | { | |
153 | return arm_sw_breakpoint_from_kind (kind, size); | |
154 | } | |
155 | ||
d7146cda TBA |
156 | bool |
157 | arm_target::low_breakpoint_at (CORE_ADDR pc) | |
158 | { | |
159 | return arm_breakpoint_at (pc); | |
160 | } | |
161 | ||
09b4ad9f | 162 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 163 | static struct |
09b4ad9f UW |
164 | { |
165 | unsigned char arch; | |
166 | unsigned char max_wp_length; | |
167 | unsigned char wp_count; | |
168 | unsigned char bp_count; | |
71487fd7 | 169 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
170 | |
171 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
172 | typedef enum | |
173 | { | |
174 | arm_hwbp_break = 0, | |
175 | arm_hwbp_load = 1, | |
176 | arm_hwbp_store = 2, | |
177 | arm_hwbp_access = 3 | |
178 | } arm_hwbp_type; | |
179 | ||
180 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
181 | typedef unsigned int arm_hwbp_control_t; | |
182 | ||
183 | /* Structure used to keep track of hardware break-/watch-points. */ | |
184 | struct arm_linux_hw_breakpoint | |
185 | { | |
186 | /* Address to break on, or being watched. */ | |
187 | unsigned int address; | |
188 | /* Control register for break-/watch- point. */ | |
189 | arm_hwbp_control_t control; | |
190 | }; | |
191 | ||
192 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
193 | assume a maximum number of supported break-/watchpoints. */ | |
194 | #define MAX_BPTS 32 | |
195 | #define MAX_WPTS 32 | |
196 | ||
197 | /* Per-process arch-specific data we want to keep. */ | |
198 | struct arch_process_info | |
199 | { | |
200 | /* Hardware breakpoints for this process. */ | |
201 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
202 | /* Hardware watchpoints for this process. */ | |
203 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
204 | }; | |
205 | ||
206 | /* Per-thread arch-specific data we want to keep. */ | |
207 | struct arch_lwp_info | |
208 | { | |
209 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
210 | char bpts_changed[MAX_BPTS]; | |
211 | char wpts_changed[MAX_WPTS]; | |
212 | /* Cached stopped data address. */ | |
213 | CORE_ADDR stopped_data_address; | |
214 | }; | |
215 | ||
58d6951d DJ |
216 | /* These are in <asm/elf.h> in current kernels. */ |
217 | #define HWCAP_VFP 64 | |
218 | #define HWCAP_IWMMXT 512 | |
219 | #define HWCAP_NEON 4096 | |
220 | #define HWCAP_VFPv3 8192 | |
221 | #define HWCAP_VFPv3D16 16384 | |
222 | ||
0a30fbc4 DJ |
223 | #ifdef HAVE_SYS_REG_H |
224 | #include <sys/reg.h> | |
225 | #endif | |
226 | ||
23ce3b1c | 227 | #define arm_num_regs 26 |
0a30fbc4 | 228 | |
2ec06d2e | 229 | static int arm_regmap[] = { |
0a30fbc4 DJ |
230 | 0, 4, 8, 12, 16, 20, 24, 28, |
231 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
232 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
233 | 64 | |
0a30fbc4 DJ |
234 | }; |
235 | ||
d9311bfa AT |
236 | /* Forward declarations needed for get_next_pcs ops. */ |
237 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
238 | int len, | |
239 | int byte_order); | |
240 | ||
241 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
242 | CORE_ADDR val); | |
243 | ||
553cb527 | 244 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
245 | |
246 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
247 | ||
248 | /* get_next_pcs operations. */ | |
249 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
250 | get_next_pcs_read_memory_unsigned_integer, | |
251 | get_next_pcs_syscall_next_pc, | |
252 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
253 | get_next_pcs_is_thumb, |
254 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
255 | }; |
256 | ||
daca57a7 TBA |
257 | bool |
258 | arm_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 259 | { |
2ec06d2e | 260 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
261 | } |
262 | ||
daca57a7 TBA |
263 | bool |
264 | arm_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 265 | { |
2ec06d2e | 266 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
267 | } |
268 | ||
fb1e4ffc | 269 | static void |
442ea881 | 270 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 271 | { |
7cc17433 | 272 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
273 | return; |
274 | ||
166a82be | 275 | for (int i = 0; i < 16; i++) |
442ea881 | 276 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
277 | |
278 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 279 | for (int i = 0; i < 6; i++) |
442ea881 PA |
280 | collect_register (regcache, arm_num_regs + i + 16, |
281 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
282 | } |
283 | ||
284 | static void | |
442ea881 | 285 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 286 | { |
7cc17433 | 287 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
288 | return; |
289 | ||
166a82be | 290 | for (int i = 0; i < 16; i++) |
442ea881 | 291 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
292 | |
293 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 294 | for (int i = 0; i < 6; i++) |
442ea881 PA |
295 | supply_register (regcache, arm_num_regs + i + 16, |
296 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
297 | } |
298 | ||
58d6951d | 299 | static void |
442ea881 | 300 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 301 | { |
bd9e6534 | 302 | int num; |
58d6951d | 303 | |
7cc17433 | 304 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 305 | num = 32; |
89abb039 | 306 | else |
7cc17433 AH |
307 | { |
308 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
309 | ||
310 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
311 | num = 32; | |
312 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
313 | num = 16; | |
314 | else | |
315 | return; | |
316 | } | |
58d6951d | 317 | |
bd9e6534 | 318 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
319 | } |
320 | ||
d9311bfa AT |
321 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
322 | static CORE_ADDR | |
323 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
324 | { | |
325 | return UNMAKE_THUMB_ADDR (val); | |
326 | } | |
327 | ||
58d6951d | 328 | static void |
442ea881 | 329 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 330 | { |
bd9e6534 | 331 | int num; |
58d6951d | 332 | |
7cc17433 | 333 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 334 | num = 32; |
89abb039 | 335 | else |
7cc17433 AH |
336 | { |
337 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
338 | ||
339 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
340 | num = 32; | |
341 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
342 | num = 16; | |
343 | else | |
344 | return; | |
345 | } | |
58d6951d | 346 | |
bd9e6534 | 347 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 348 | } |
fb1e4ffc | 349 | |
d9311bfa AT |
350 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
351 | static int | |
352 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
353 | { | |
354 | return arm_is_thumb_mode (); | |
355 | } | |
356 | ||
30baf67b | 357 | /* Read memory from the inferior. |
d9311bfa AT |
358 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
359 | read_memory_unsigned_integer. */ | |
360 | static ULONGEST | |
361 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
362 | int len, | |
363 | int byte_order) | |
364 | { | |
365 | ULONGEST res; | |
366 | ||
9e784964 | 367 | res = 0; |
694b382c AT |
368 | target_read_memory (memaddr, (unsigned char *) &res, len); |
369 | ||
d9311bfa AT |
370 | return res; |
371 | } | |
372 | ||
9308fc88 DJ |
373 | /* Fetch the thread-local storage pointer for libthread_db. */ |
374 | ||
375 | ps_err_e | |
754653a7 | 376 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 377 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
378 | { |
379 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
380 | return PS_ERR; | |
381 | ||
382 | /* IDX is the bias from the thread pointer to the beginning of the | |
383 | thread descriptor. It has to be subtracted due to implementation | |
384 | quirks in libthread_db. */ | |
385 | *base = (void *) ((char *)*base - idx); | |
386 | ||
387 | return PS_OK; | |
388 | } | |
389 | ||
09b4ad9f | 390 | |
71487fd7 UW |
391 | /* Query Hardware Breakpoint information for the target we are attached to |
392 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
393 | static void | |
394 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 395 | { |
71487fd7 | 396 | unsigned int val; |
09b4ad9f | 397 | |
71487fd7 UW |
398 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
399 | return; | |
09b4ad9f | 400 | |
71487fd7 UW |
401 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
402 | if (arm_linux_hwbp_cap.arch == 0) | |
403 | return; | |
09b4ad9f | 404 | |
71487fd7 UW |
405 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
406 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
407 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 408 | |
71487fd7 UW |
409 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
410 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
411 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
412 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
413 | } |
414 | ||
415 | /* How many hardware breakpoints are available? */ | |
416 | static int | |
417 | arm_linux_get_hw_breakpoint_count (void) | |
418 | { | |
71487fd7 | 419 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
420 | } |
421 | ||
422 | /* How many hardware watchpoints are available? */ | |
423 | static int | |
424 | arm_linux_get_hw_watchpoint_count (void) | |
425 | { | |
71487fd7 | 426 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
427 | } |
428 | ||
429 | /* Maximum length of area watched by hardware watchpoint. */ | |
430 | static int | |
431 | arm_linux_get_hw_watchpoint_max_length (void) | |
432 | { | |
71487fd7 | 433 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
434 | } |
435 | ||
436 | /* Initialize an ARM hardware break-/watch-point control register value. | |
437 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
438 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
439 | */ | |
440 | static arm_hwbp_control_t | |
441 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
442 | arm_hwbp_type hwbp_type, | |
443 | int enable) | |
444 | { | |
445 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
446 | gdb_assert (hwbp_type != arm_hwbp_break | |
447 | || ((byte_address_select & 0xfU) != 0)); | |
448 | ||
449 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
450 | } | |
451 | ||
452 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
453 | static int | |
454 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
455 | { | |
456 | return control & 0x1; | |
457 | } | |
458 | ||
459 | /* Is the breakpoint control value CONTROL initialized? */ | |
460 | static int | |
461 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
462 | { | |
463 | return control != 0; | |
464 | } | |
465 | ||
466 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
467 | static arm_hwbp_control_t | |
468 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
469 | { | |
470 | return control & ~0x1; | |
471 | } | |
472 | ||
473 | /* Are two break-/watch-points equal? */ | |
474 | static int | |
475 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
476 | const struct arm_linux_hw_breakpoint *p2) | |
477 | { | |
478 | return p1->address == p2->address && p1->control == p2->control; | |
479 | } | |
480 | ||
802e8e6d PA |
481 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
482 | ||
171de4b8 | 483 | static arm_hwbp_type |
802e8e6d PA |
484 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
485 | { | |
486 | switch (raw_type) | |
487 | { | |
488 | case raw_bkpt_type_hw: | |
489 | return arm_hwbp_break; | |
490 | case raw_bkpt_type_write_wp: | |
491 | return arm_hwbp_store; | |
492 | case raw_bkpt_type_read_wp: | |
493 | return arm_hwbp_load; | |
494 | case raw_bkpt_type_access_wp: | |
495 | return arm_hwbp_access; | |
496 | default: | |
497 | gdb_assert_not_reached ("unhandled raw type"); | |
498 | } | |
499 | } | |
500 | ||
09b4ad9f UW |
501 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
502 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
503 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
504 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
505 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 506 | static int |
802e8e6d PA |
507 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
508 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
509 | { |
510 | arm_hwbp_type hwbp_type; | |
511 | unsigned mask; | |
512 | ||
802e8e6d | 513 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
514 | |
515 | if (hwbp_type == arm_hwbp_break) | |
516 | { | |
517 | /* For breakpoints, the length field encodes the mode. */ | |
518 | switch (len) | |
519 | { | |
520 | case 2: /* 16-bit Thumb mode breakpoint */ | |
521 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
522 | mask = 0x3; |
523 | addr &= ~1; | |
09b4ad9f UW |
524 | break; |
525 | case 4: /* 32-bit ARM mode breakpoint */ | |
526 | mask = 0xf; | |
fcf303ab | 527 | addr &= ~3; |
09b4ad9f UW |
528 | break; |
529 | default: | |
530 | /* Unsupported. */ | |
b62e2b27 | 531 | return -2; |
09b4ad9f | 532 | } |
09b4ad9f UW |
533 | } |
534 | else | |
535 | { | |
536 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
537 | CORE_ADDR aligned_addr; | |
538 | ||
539 | /* Can not set watchpoints for zero or negative lengths. */ | |
540 | if (len <= 0) | |
b62e2b27 | 541 | return -2; |
09b4ad9f UW |
542 | /* The current ptrace interface can only handle watchpoints that are a |
543 | power of 2. */ | |
544 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 545 | return -2; |
09b4ad9f UW |
546 | |
547 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
548 | range covered by a watchpoint. */ | |
549 | aligned_addr = addr & ~(max_wp_length - 1); | |
550 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 551 | return -2; |
09b4ad9f UW |
552 | |
553 | mask = (1 << len) - 1; | |
554 | } | |
555 | ||
556 | p->address = (unsigned int) addr; | |
557 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
558 | ||
559 | return hwbp_type != arm_hwbp_break; | |
560 | } | |
561 | ||
562 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
563 | the current process. */ | |
564 | ||
00192f77 SM |
565 | static void |
566 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 567 | { |
d86d4aaf | 568 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 569 | |
00192f77 SM |
570 | /* The actual update is done later just before resuming the lwp, |
571 | we just mark that the registers need updating. */ | |
572 | if (watch) | |
573 | lwp->arch_private->wpts_changed[i] = 1; | |
574 | else | |
575 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 576 | |
00192f77 SM |
577 | /* If the lwp isn't stopped, force it to momentarily pause, so |
578 | we can update its breakpoint registers. */ | |
579 | if (!lwp->stopped) | |
580 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
581 | } |
582 | ||
007c9b97 TBA |
583 | bool |
584 | arm_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
585 | { |
586 | switch (z_type) | |
587 | { | |
abeead09 | 588 | case Z_PACKET_SW_BP: |
802e8e6d PA |
589 | case Z_PACKET_HW_BP: |
590 | case Z_PACKET_WRITE_WP: | |
591 | case Z_PACKET_READ_WP: | |
592 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 593 | return true; |
802e8e6d PA |
594 | default: |
595 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
007c9b97 | 596 | return false; |
802e8e6d PA |
597 | } |
598 | } | |
599 | ||
09b4ad9f | 600 | /* Insert hardware break-/watchpoint. */ |
9db9aa23 TBA |
601 | int |
602 | arm_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
603 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
604 | { |
605 | struct process_info *proc = current_process (); | |
606 | struct arm_linux_hw_breakpoint p, *pts; | |
607 | int watch, i, count; | |
608 | ||
609 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
610 | if (watch < 0) | |
611 | { | |
612 | /* Unsupported. */ | |
b62e2b27 | 613 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
614 | } |
615 | ||
616 | if (watch) | |
617 | { | |
618 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 619 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
620 | } |
621 | else | |
622 | { | |
623 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 624 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
625 | } |
626 | ||
627 | for (i = 0; i < count; i++) | |
628 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
629 | { | |
09b4ad9f | 630 | pts[i] = p; |
00192f77 SM |
631 | |
632 | /* Only update the threads of the current process. */ | |
633 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
634 | { | |
635 | update_registers_callback (thread, watch, i); | |
636 | }); | |
637 | ||
09b4ad9f UW |
638 | return 0; |
639 | } | |
640 | ||
641 | /* We're out of watchpoints. */ | |
642 | return -1; | |
643 | } | |
644 | ||
645 | /* Remove hardware break-/watchpoint. */ | |
9db9aa23 TBA |
646 | int |
647 | arm_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
648 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
649 | { |
650 | struct process_info *proc = current_process (); | |
651 | struct arm_linux_hw_breakpoint p, *pts; | |
652 | int watch, i, count; | |
653 | ||
654 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
655 | if (watch < 0) | |
656 | { | |
657 | /* Unsupported. */ | |
658 | return -1; | |
659 | } | |
660 | ||
661 | if (watch) | |
662 | { | |
663 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 664 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
665 | } |
666 | else | |
667 | { | |
668 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 669 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
670 | } |
671 | ||
672 | for (i = 0; i < count; i++) | |
673 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
674 | { | |
09b4ad9f | 675 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
676 | |
677 | /* Only update the threads of the current process. */ | |
678 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
679 | { | |
680 | update_registers_callback (thread, watch, i); | |
681 | }); | |
682 | ||
09b4ad9f UW |
683 | return 0; |
684 | } | |
685 | ||
686 | /* No watchpoint matched. */ | |
687 | return -1; | |
688 | } | |
689 | ||
690 | /* Return whether current thread is stopped due to a watchpoint. */ | |
ac1bbaca TBA |
691 | bool |
692 | arm_target::low_stopped_by_watchpoint () | |
09b4ad9f | 693 | { |
0bfdf32f | 694 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 695 | siginfo_t siginfo; |
09b4ad9f UW |
696 | |
697 | /* We must be able to set hardware watchpoints. */ | |
698 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
ac1bbaca | 699 | return false; |
09b4ad9f UW |
700 | |
701 | /* Retrieve siginfo. */ | |
702 | errno = 0; | |
0bfdf32f | 703 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f | 704 | if (errno != 0) |
ac1bbaca | 705 | return false; |
09b4ad9f UW |
706 | |
707 | /* This must be a hardware breakpoint. */ | |
708 | if (siginfo.si_signo != SIGTRAP | |
709 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
ac1bbaca | 710 | return false; |
09b4ad9f UW |
711 | |
712 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
713 | a watchpoint. */ | |
714 | if (siginfo.si_errno >= 0) | |
ac1bbaca | 715 | return false; |
09b4ad9f UW |
716 | |
717 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
718 | lwp->arch_private->stopped_data_address | |
719 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
720 | ||
ac1bbaca | 721 | return true; |
09b4ad9f UW |
722 | } |
723 | ||
724 | /* Return data address that triggered watchpoint. Called only if | |
ac1bbaca TBA |
725 | low_stopped_by_watchpoint returned true. */ |
726 | CORE_ADDR | |
727 | arm_target::low_stopped_data_address () | |
09b4ad9f | 728 | { |
0bfdf32f | 729 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
730 | return lwp->arch_private->stopped_data_address; |
731 | } | |
732 | ||
733 | /* Called when a new process is created. */ | |
fd000fb3 TBA |
734 | arch_process_info * |
735 | arm_target::low_new_process () | |
09b4ad9f | 736 | { |
8d749320 | 737 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
738 | return info; |
739 | } | |
740 | ||
04ec7890 SM |
741 | /* Called when a process is being deleted. */ |
742 | ||
fd000fb3 TBA |
743 | void |
744 | arm_target::low_delete_process (arch_process_info *info) | |
04ec7890 SM |
745 | { |
746 | xfree (info); | |
747 | } | |
748 | ||
09b4ad9f | 749 | /* Called when a new thread is detected. */ |
fd000fb3 TBA |
750 | void |
751 | arm_target::low_new_thread (lwp_info *lwp) | |
09b4ad9f | 752 | { |
8d749320 | 753 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
754 | int i; |
755 | ||
756 | for (i = 0; i < MAX_BPTS; i++) | |
757 | info->bpts_changed[i] = 1; | |
758 | for (i = 0; i < MAX_WPTS; i++) | |
759 | info->wpts_changed[i] = 1; | |
760 | ||
34c703da | 761 | lwp->arch_private = info; |
09b4ad9f UW |
762 | } |
763 | ||
466eecee SM |
764 | /* Function to call when a thread is being deleted. */ |
765 | ||
fd000fb3 TBA |
766 | void |
767 | arm_target::low_delete_thread (arch_lwp_info *arch_lwp) | |
466eecee SM |
768 | { |
769 | xfree (arch_lwp); | |
770 | } | |
771 | ||
fd000fb3 TBA |
772 | void |
773 | arm_target::low_new_fork (process_info *parent, process_info *child) | |
3a8a0396 | 774 | { |
69291610 HW |
775 | struct arch_process_info *parent_proc_info; |
776 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
777 | struct lwp_info *child_lwp; |
778 | struct arch_lwp_info *child_lwp_info; | |
779 | int i; | |
780 | ||
781 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
782 | gdb_assert (parent->priv != NULL |
783 | && parent->priv->arch_private != NULL); | |
784 | gdb_assert (child->priv != NULL | |
785 | && child->priv->arch_private != NULL); | |
3a8a0396 | 786 | |
69291610 HW |
787 | parent_proc_info = parent->priv->arch_private; |
788 | child_proc_info = child->priv->arch_private; | |
789 | ||
3a8a0396 DB |
790 | /* Linux kernel before 2.6.33 commit |
791 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
792 | will inherit hardware debug registers from parent | |
793 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
794 | zeroed debug registers. | |
795 | ||
796 | GDB core assumes the child inherits the watchpoints/hw | |
797 | breakpoints of the parent, and will remove them all from the | |
798 | forked off process. Copy the debug registers mirrors into the | |
799 | new process so that all breakpoints and watchpoints can be | |
800 | removed together. The debug registers mirror will become zeroed | |
801 | in the end before detaching the forked off process, thus making | |
802 | this compatible with older Linux kernels too. */ | |
803 | ||
804 | *child_proc_info = *parent_proc_info; | |
805 | ||
806 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
807 | make sure that the registers will be updated. */ | |
9179355e | 808 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
809 | child_lwp_info = child_lwp->arch_private; |
810 | for (i = 0; i < MAX_BPTS; i++) | |
811 | child_lwp_info->bpts_changed[i] = 1; | |
812 | for (i = 0; i < MAX_WPTS; i++) | |
813 | child_lwp_info->wpts_changed[i] = 1; | |
814 | } | |
815 | ||
09b4ad9f UW |
816 | /* Called when resuming a thread. |
817 | If the debug regs have changed, update the thread's copies. */ | |
d7599cc0 TBA |
818 | void |
819 | arm_target::low_prepare_to_resume (lwp_info *lwp) | |
09b4ad9f | 820 | { |
d86d4aaf DE |
821 | struct thread_info *thread = get_lwp_thread (lwp); |
822 | int pid = lwpid_of (thread); | |
823 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 824 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
825 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
826 | int i; | |
827 | ||
828 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
829 | if (lwp_info->bpts_changed[i]) | |
830 | { | |
831 | errno = 0; | |
832 | ||
833 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 834 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 835 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 836 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 837 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
838 | |
839 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 840 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 841 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 842 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 843 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
844 | |
845 | lwp_info->bpts_changed[i] = 0; | |
846 | } | |
847 | ||
848 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
849 | if (lwp_info->wpts_changed[i]) | |
850 | { | |
851 | errno = 0; | |
852 | ||
853 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 854 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 855 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 856 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 857 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
858 | |
859 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 860 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 861 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 862 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 863 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
864 | |
865 | lwp_info->wpts_changed[i] = 0; | |
866 | } | |
867 | } | |
868 | ||
f7a6a40d YQ |
869 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
870 | addition, set IS_THUMB depending on whether we will return to ARM | |
871 | or Thumb code. | |
d9311bfa AT |
872 | See arm-linux.h for stack layout details. */ |
873 | static CORE_ADDR | |
f7a6a40d YQ |
874 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
875 | int *is_thumb) | |
d9311bfa AT |
876 | { |
877 | unsigned long sp; | |
878 | unsigned long sp_data; | |
879 | /* Offset of PC register. */ | |
880 | int pc_offset = 0; | |
881 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 882 | uint32_t cpsr; |
d9311bfa AT |
883 | |
884 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
885 | ||
886 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 887 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
888 | |
889 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
890 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
891 | ||
52405d85 | 892 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 893 | |
f7a6a40d | 894 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 895 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
896 | *is_thumb = ((cpsr & CPSR_T) != 0); |
897 | ||
d9311bfa AT |
898 | return next_pc; |
899 | } | |
900 | ||
901 | /* When PC is at a syscall instruction, return the PC of the next | |
902 | instruction to be executed. */ | |
903 | static CORE_ADDR | |
553cb527 | 904 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
905 | { |
906 | CORE_ADDR next_pc = 0; | |
553cb527 | 907 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
908 | int is_thumb = arm_is_thumb_mode (); |
909 | ULONGEST svc_number = 0; | |
910 | struct regcache *regcache = self->regcache; | |
911 | ||
912 | if (is_thumb) | |
913 | { | |
914 | collect_register (regcache, 7, &svc_number); | |
915 | next_pc = pc + 2; | |
916 | } | |
917 | else | |
918 | { | |
919 | unsigned long this_instr; | |
920 | unsigned long svc_operand; | |
921 | ||
694b382c | 922 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
923 | svc_operand = (0x00ffffff & this_instr); |
924 | ||
925 | if (svc_operand) /* OABI. */ | |
926 | { | |
927 | svc_number = svc_operand - 0x900000; | |
928 | } | |
929 | else /* EABI. */ | |
930 | { | |
931 | collect_register (regcache, 7, &svc_number); | |
932 | } | |
933 | ||
934 | next_pc = pc + 4; | |
935 | } | |
936 | ||
937 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
938 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
939 | { | |
f7a6a40d YQ |
940 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
941 | update IS_THUMB. */ | |
942 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
943 | } |
944 | ||
945 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
946 | if (is_thumb) | |
947 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
948 | ||
949 | return next_pc; | |
950 | } | |
09b4ad9f | 951 | |
3aee8918 PA |
952 | static const struct target_desc * |
953 | arm_read_description (void) | |
58d6951d | 954 | { |
974c89e0 | 955 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 956 | |
58d6951d | 957 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 958 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
959 | |
960 | if (arm_hwcap & HWCAP_VFP) | |
961 | { | |
166a82be AH |
962 | /* Make sure that the kernel supports reading VFP registers. Support was |
963 | added in 2.6.30. */ | |
964 | int pid = lwpid_of (current_thread); | |
965 | errno = 0; | |
966 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
967 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 968 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
969 | |
970 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
971 | it with VFP. */ | |
972 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 973 | return aarch32_linux_read_description (); |
58d6951d | 974 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 975 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 976 | else |
7cc17433 | 977 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
978 | } |
979 | ||
980 | /* The default configuration uses legacy FPA registers, probably | |
981 | simulated. */ | |
7cc17433 | 982 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
983 | } |
984 | ||
797bcff5 TBA |
985 | void |
986 | arm_target::low_arch_setup () | |
3aee8918 | 987 | { |
bd9e6534 YQ |
988 | int tid = lwpid_of (current_thread); |
989 | int gpregs[18]; | |
990 | struct iovec iov; | |
991 | ||
166a82be AH |
992 | /* Query hardware watchpoint/breakpoint capabilities. */ |
993 | arm_linux_init_hwbp_cap (tid); | |
994 | ||
3aee8918 | 995 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
996 | |
997 | iov.iov_base = gpregs; | |
998 | iov.iov_len = sizeof (gpregs); | |
999 | ||
1000 | /* Check if PTRACE_GETREGSET works. */ | |
1001 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
1002 | have_ptrace_getregset = 1; | |
1003 | else | |
1004 | have_ptrace_getregset = 0; | |
3aee8918 PA |
1005 | } |
1006 | ||
7582c77c TBA |
1007 | bool |
1008 | arm_target::supports_software_single_step () | |
1009 | { | |
1010 | return true; | |
1011 | } | |
1012 | ||
d9311bfa AT |
1013 | /* Fetch the next possible PCs after the current instruction executes. */ |
1014 | ||
7582c77c TBA |
1015 | std::vector<CORE_ADDR> |
1016 | arm_target::low_get_next_pcs (regcache *regcache) | |
d9311bfa AT |
1017 | { |
1018 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
1019 | |
1020 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
1021 | &get_next_pcs_ops, | |
1022 | /* Byte order is ignored assumed as host. */ | |
1023 | 0, | |
1024 | 0, | |
1b451dda | 1025 | 1, |
d9311bfa AT |
1026 | regcache); |
1027 | ||
a0ff9e1a | 1028 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
1029 | } |
1030 | ||
7d00775e AT |
1031 | /* Support for hardware single step. */ |
1032 | ||
1033 | static int | |
1034 | arm_supports_hardware_single_step (void) | |
1035 | { | |
1036 | return 0; | |
1037 | } | |
1038 | ||
79e7fd4f YQ |
1039 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
1040 | ||
1041 | static void | |
1042 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
1043 | { | |
1044 | if (arm_is_thumb_mode ()) | |
1045 | collect_register_by_name (regcache, "r7", sysno); | |
1046 | else | |
1047 | { | |
1048 | unsigned long pc; | |
1049 | unsigned long insn; | |
1050 | ||
1051 | collect_register_by_name (regcache, "pc", &pc); | |
1052 | ||
52405d85 | 1053 | if (the_target->read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
1054 | *sysno = UNKNOWN_SYSCALL; |
1055 | else | |
1056 | { | |
1057 | unsigned long svc_operand = (0x00ffffff & insn); | |
1058 | ||
1059 | if (svc_operand) | |
1060 | { | |
1061 | /* OABI */ | |
1062 | *sysno = svc_operand - 0x900000; | |
1063 | } | |
1064 | else | |
1065 | { | |
1066 | /* EABI */ | |
1067 | collect_register_by_name (regcache, "r7", sysno); | |
1068 | } | |
1069 | } | |
1070 | } | |
1071 | } | |
1072 | ||
bd9e6534 YQ |
1073 | /* Register sets without using PTRACE_GETREGSET. */ |
1074 | ||
3aee8918 | 1075 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
1076 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
1077 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 1078 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 1079 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 1080 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 1081 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 1082 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 1083 | NULL_REGSET |
fb1e4ffc DJ |
1084 | }; |
1085 | ||
3aee8918 PA |
1086 | static struct regsets_info arm_regsets_info = |
1087 | { | |
1088 | arm_regsets, /* regsets */ | |
1089 | 0, /* num_regsets */ | |
1090 | NULL, /* disabled_regsets */ | |
1091 | }; | |
1092 | ||
1093 | static struct usrregs_info arm_usrregs_info = | |
1094 | { | |
1095 | arm_num_regs, | |
1096 | arm_regmap, | |
1097 | }; | |
1098 | ||
bd9e6534 | 1099 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1100 | { |
1101 | NULL, /* regset_bitmap */ | |
1102 | &arm_usrregs_info, | |
1103 | &arm_regsets_info | |
1104 | }; | |
1105 | ||
aa8d21c9 TBA |
1106 | const regs_info * |
1107 | arm_target::get_regs_info () | |
3aee8918 | 1108 | { |
bd9e6534 YQ |
1109 | const struct target_desc *tdesc = current_process ()->tdesc; |
1110 | ||
1111 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1112 | && (is_aarch32_linux_description (tdesc) |
1113 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1114 | return ®s_info_aarch32; |
7cc17433 AH |
1115 | |
1116 | return ®s_info_arm; | |
3aee8918 PA |
1117 | } |
1118 | ||
dd373349 | 1119 | struct linux_target_ops the_low_target = { |
79e7fd4f YQ |
1120 | arm_supports_hardware_single_step, |
1121 | arm_get_syscall_trapinfo, | |
2ec06d2e | 1122 | }; |
3aee8918 | 1123 | |
ef0478f6 TBA |
1124 | /* The linux target ops object. */ |
1125 | ||
1126 | linux_process_target *the_linux_target = &the_arm_target; | |
1127 | ||
3aee8918 PA |
1128 | void |
1129 | initialize_low_arch (void) | |
1130 | { | |
bd9e6534 | 1131 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1132 | initialize_regsets_info (&arm_regsets_info); |
1133 | } |