Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
aa8d21c9 TBA |
63 | const regs_info *get_regs_info () override; |
64 | ||
797bcff5 TBA |
65 | protected: |
66 | ||
67 | void low_arch_setup () override; | |
ef0478f6 TBA |
68 | }; |
69 | ||
70 | /* The singleton target ops object. */ | |
71 | ||
72 | static arm_target the_arm_target; | |
73 | ||
09b4ad9f | 74 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 75 | static struct |
09b4ad9f UW |
76 | { |
77 | unsigned char arch; | |
78 | unsigned char max_wp_length; | |
79 | unsigned char wp_count; | |
80 | unsigned char bp_count; | |
71487fd7 | 81 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
82 | |
83 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
84 | typedef enum | |
85 | { | |
86 | arm_hwbp_break = 0, | |
87 | arm_hwbp_load = 1, | |
88 | arm_hwbp_store = 2, | |
89 | arm_hwbp_access = 3 | |
90 | } arm_hwbp_type; | |
91 | ||
92 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
93 | typedef unsigned int arm_hwbp_control_t; | |
94 | ||
95 | /* Structure used to keep track of hardware break-/watch-points. */ | |
96 | struct arm_linux_hw_breakpoint | |
97 | { | |
98 | /* Address to break on, or being watched. */ | |
99 | unsigned int address; | |
100 | /* Control register for break-/watch- point. */ | |
101 | arm_hwbp_control_t control; | |
102 | }; | |
103 | ||
104 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
105 | assume a maximum number of supported break-/watchpoints. */ | |
106 | #define MAX_BPTS 32 | |
107 | #define MAX_WPTS 32 | |
108 | ||
109 | /* Per-process arch-specific data we want to keep. */ | |
110 | struct arch_process_info | |
111 | { | |
112 | /* Hardware breakpoints for this process. */ | |
113 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
114 | /* Hardware watchpoints for this process. */ | |
115 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
116 | }; | |
117 | ||
118 | /* Per-thread arch-specific data we want to keep. */ | |
119 | struct arch_lwp_info | |
120 | { | |
121 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
122 | char bpts_changed[MAX_BPTS]; | |
123 | char wpts_changed[MAX_WPTS]; | |
124 | /* Cached stopped data address. */ | |
125 | CORE_ADDR stopped_data_address; | |
126 | }; | |
127 | ||
58d6951d DJ |
128 | /* These are in <asm/elf.h> in current kernels. */ |
129 | #define HWCAP_VFP 64 | |
130 | #define HWCAP_IWMMXT 512 | |
131 | #define HWCAP_NEON 4096 | |
132 | #define HWCAP_VFPv3 8192 | |
133 | #define HWCAP_VFPv3D16 16384 | |
134 | ||
0a30fbc4 DJ |
135 | #ifdef HAVE_SYS_REG_H |
136 | #include <sys/reg.h> | |
137 | #endif | |
138 | ||
23ce3b1c | 139 | #define arm_num_regs 26 |
0a30fbc4 | 140 | |
2ec06d2e | 141 | static int arm_regmap[] = { |
0a30fbc4 DJ |
142 | 0, 4, 8, 12, 16, 20, 24, 28, |
143 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
144 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
145 | 64 | |
0a30fbc4 DJ |
146 | }; |
147 | ||
d9311bfa AT |
148 | /* Forward declarations needed for get_next_pcs ops. */ |
149 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
150 | int len, | |
151 | int byte_order); | |
152 | ||
153 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
154 | CORE_ADDR val); | |
155 | ||
553cb527 | 156 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
157 | |
158 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
159 | ||
160 | /* get_next_pcs operations. */ | |
161 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
162 | get_next_pcs_read_memory_unsigned_integer, | |
163 | get_next_pcs_syscall_next_pc, | |
164 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
165 | get_next_pcs_is_thumb, |
166 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
167 | }; |
168 | ||
2ec06d2e DJ |
169 | static int |
170 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 171 | { |
2ec06d2e | 172 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
173 | } |
174 | ||
2ec06d2e DJ |
175 | static int |
176 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 177 | { |
2ec06d2e | 178 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
179 | } |
180 | ||
fb1e4ffc | 181 | static void |
442ea881 | 182 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 183 | { |
7cc17433 | 184 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
185 | return; |
186 | ||
166a82be | 187 | for (int i = 0; i < 16; i++) |
442ea881 | 188 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
189 | |
190 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 191 | for (int i = 0; i < 6; i++) |
442ea881 PA |
192 | collect_register (regcache, arm_num_regs + i + 16, |
193 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
194 | } |
195 | ||
196 | static void | |
442ea881 | 197 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 198 | { |
7cc17433 | 199 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
200 | return; |
201 | ||
166a82be | 202 | for (int i = 0; i < 16; i++) |
442ea881 | 203 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
204 | |
205 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 206 | for (int i = 0; i < 6; i++) |
442ea881 PA |
207 | supply_register (regcache, arm_num_regs + i + 16, |
208 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
209 | } |
210 | ||
58d6951d | 211 | static void |
442ea881 | 212 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 213 | { |
bd9e6534 | 214 | int num; |
58d6951d | 215 | |
7cc17433 | 216 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 217 | num = 32; |
89abb039 | 218 | else |
7cc17433 AH |
219 | { |
220 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
221 | ||
222 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
223 | num = 32; | |
224 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
225 | num = 16; | |
226 | else | |
227 | return; | |
228 | } | |
58d6951d | 229 | |
bd9e6534 | 230 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
231 | } |
232 | ||
d9311bfa AT |
233 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
234 | static CORE_ADDR | |
235 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
236 | { | |
237 | return UNMAKE_THUMB_ADDR (val); | |
238 | } | |
239 | ||
58d6951d | 240 | static void |
442ea881 | 241 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 242 | { |
bd9e6534 | 243 | int num; |
58d6951d | 244 | |
7cc17433 | 245 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 246 | num = 32; |
89abb039 | 247 | else |
7cc17433 AH |
248 | { |
249 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
250 | ||
251 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
252 | num = 32; | |
253 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
254 | num = 16; | |
255 | else | |
256 | return; | |
257 | } | |
58d6951d | 258 | |
bd9e6534 | 259 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 260 | } |
fb1e4ffc | 261 | |
d9311bfa AT |
262 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
263 | static int | |
264 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
265 | { | |
266 | return arm_is_thumb_mode (); | |
267 | } | |
268 | ||
30baf67b | 269 | /* Read memory from the inferior. |
d9311bfa AT |
270 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
271 | read_memory_unsigned_integer. */ | |
272 | static ULONGEST | |
273 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
274 | int len, | |
275 | int byte_order) | |
276 | { | |
277 | ULONGEST res; | |
278 | ||
9e784964 | 279 | res = 0; |
694b382c AT |
280 | target_read_memory (memaddr, (unsigned char *) &res, len); |
281 | ||
d9311bfa AT |
282 | return res; |
283 | } | |
284 | ||
9308fc88 DJ |
285 | /* Fetch the thread-local storage pointer for libthread_db. */ |
286 | ||
287 | ps_err_e | |
754653a7 | 288 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 289 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
290 | { |
291 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
292 | return PS_ERR; | |
293 | ||
294 | /* IDX is the bias from the thread pointer to the beginning of the | |
295 | thread descriptor. It has to be subtracted due to implementation | |
296 | quirks in libthread_db. */ | |
297 | *base = (void *) ((char *)*base - idx); | |
298 | ||
299 | return PS_OK; | |
300 | } | |
301 | ||
09b4ad9f | 302 | |
71487fd7 UW |
303 | /* Query Hardware Breakpoint information for the target we are attached to |
304 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
305 | static void | |
306 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 307 | { |
71487fd7 | 308 | unsigned int val; |
09b4ad9f | 309 | |
71487fd7 UW |
310 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
311 | return; | |
09b4ad9f | 312 | |
71487fd7 UW |
313 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
314 | if (arm_linux_hwbp_cap.arch == 0) | |
315 | return; | |
09b4ad9f | 316 | |
71487fd7 UW |
317 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
318 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
319 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 320 | |
71487fd7 UW |
321 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
322 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
323 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
324 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
325 | } |
326 | ||
327 | /* How many hardware breakpoints are available? */ | |
328 | static int | |
329 | arm_linux_get_hw_breakpoint_count (void) | |
330 | { | |
71487fd7 | 331 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
332 | } |
333 | ||
334 | /* How many hardware watchpoints are available? */ | |
335 | static int | |
336 | arm_linux_get_hw_watchpoint_count (void) | |
337 | { | |
71487fd7 | 338 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
339 | } |
340 | ||
341 | /* Maximum length of area watched by hardware watchpoint. */ | |
342 | static int | |
343 | arm_linux_get_hw_watchpoint_max_length (void) | |
344 | { | |
71487fd7 | 345 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
346 | } |
347 | ||
348 | /* Initialize an ARM hardware break-/watch-point control register value. | |
349 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
350 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
351 | */ | |
352 | static arm_hwbp_control_t | |
353 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
354 | arm_hwbp_type hwbp_type, | |
355 | int enable) | |
356 | { | |
357 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
358 | gdb_assert (hwbp_type != arm_hwbp_break | |
359 | || ((byte_address_select & 0xfU) != 0)); | |
360 | ||
361 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
362 | } | |
363 | ||
364 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
365 | static int | |
366 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
367 | { | |
368 | return control & 0x1; | |
369 | } | |
370 | ||
371 | /* Is the breakpoint control value CONTROL initialized? */ | |
372 | static int | |
373 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
374 | { | |
375 | return control != 0; | |
376 | } | |
377 | ||
378 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
379 | static arm_hwbp_control_t | |
380 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
381 | { | |
382 | return control & ~0x1; | |
383 | } | |
384 | ||
385 | /* Are two break-/watch-points equal? */ | |
386 | static int | |
387 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
388 | const struct arm_linux_hw_breakpoint *p2) | |
389 | { | |
390 | return p1->address == p2->address && p1->control == p2->control; | |
391 | } | |
392 | ||
802e8e6d PA |
393 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
394 | ||
171de4b8 | 395 | static arm_hwbp_type |
802e8e6d PA |
396 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
397 | { | |
398 | switch (raw_type) | |
399 | { | |
400 | case raw_bkpt_type_hw: | |
401 | return arm_hwbp_break; | |
402 | case raw_bkpt_type_write_wp: | |
403 | return arm_hwbp_store; | |
404 | case raw_bkpt_type_read_wp: | |
405 | return arm_hwbp_load; | |
406 | case raw_bkpt_type_access_wp: | |
407 | return arm_hwbp_access; | |
408 | default: | |
409 | gdb_assert_not_reached ("unhandled raw type"); | |
410 | } | |
411 | } | |
412 | ||
09b4ad9f UW |
413 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
414 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
415 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
416 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
417 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 418 | static int |
802e8e6d PA |
419 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
420 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
421 | { |
422 | arm_hwbp_type hwbp_type; | |
423 | unsigned mask; | |
424 | ||
802e8e6d | 425 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
426 | |
427 | if (hwbp_type == arm_hwbp_break) | |
428 | { | |
429 | /* For breakpoints, the length field encodes the mode. */ | |
430 | switch (len) | |
431 | { | |
432 | case 2: /* 16-bit Thumb mode breakpoint */ | |
433 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
434 | mask = 0x3; |
435 | addr &= ~1; | |
09b4ad9f UW |
436 | break; |
437 | case 4: /* 32-bit ARM mode breakpoint */ | |
438 | mask = 0xf; | |
fcf303ab | 439 | addr &= ~3; |
09b4ad9f UW |
440 | break; |
441 | default: | |
442 | /* Unsupported. */ | |
b62e2b27 | 443 | return -2; |
09b4ad9f | 444 | } |
09b4ad9f UW |
445 | } |
446 | else | |
447 | { | |
448 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
449 | CORE_ADDR aligned_addr; | |
450 | ||
451 | /* Can not set watchpoints for zero or negative lengths. */ | |
452 | if (len <= 0) | |
b62e2b27 | 453 | return -2; |
09b4ad9f UW |
454 | /* The current ptrace interface can only handle watchpoints that are a |
455 | power of 2. */ | |
456 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 457 | return -2; |
09b4ad9f UW |
458 | |
459 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
460 | range covered by a watchpoint. */ | |
461 | aligned_addr = addr & ~(max_wp_length - 1); | |
462 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 463 | return -2; |
09b4ad9f UW |
464 | |
465 | mask = (1 << len) - 1; | |
466 | } | |
467 | ||
468 | p->address = (unsigned int) addr; | |
469 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
470 | ||
471 | return hwbp_type != arm_hwbp_break; | |
472 | } | |
473 | ||
474 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
475 | the current process. */ | |
476 | ||
00192f77 SM |
477 | static void |
478 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 479 | { |
d86d4aaf | 480 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 481 | |
00192f77 SM |
482 | /* The actual update is done later just before resuming the lwp, |
483 | we just mark that the registers need updating. */ | |
484 | if (watch) | |
485 | lwp->arch_private->wpts_changed[i] = 1; | |
486 | else | |
487 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 488 | |
00192f77 SM |
489 | /* If the lwp isn't stopped, force it to momentarily pause, so |
490 | we can update its breakpoint registers. */ | |
491 | if (!lwp->stopped) | |
492 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
493 | } |
494 | ||
802e8e6d PA |
495 | static int |
496 | arm_supports_z_point_type (char z_type) | |
497 | { | |
498 | switch (z_type) | |
499 | { | |
abeead09 | 500 | case Z_PACKET_SW_BP: |
802e8e6d PA |
501 | case Z_PACKET_HW_BP: |
502 | case Z_PACKET_WRITE_WP: | |
503 | case Z_PACKET_READ_WP: | |
504 | case Z_PACKET_ACCESS_WP: | |
505 | return 1; | |
506 | default: | |
507 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
508 | return 0; | |
509 | } | |
510 | } | |
511 | ||
09b4ad9f UW |
512 | /* Insert hardware break-/watchpoint. */ |
513 | static int | |
802e8e6d PA |
514 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
515 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
516 | { |
517 | struct process_info *proc = current_process (); | |
518 | struct arm_linux_hw_breakpoint p, *pts; | |
519 | int watch, i, count; | |
520 | ||
521 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
522 | if (watch < 0) | |
523 | { | |
524 | /* Unsupported. */ | |
b62e2b27 | 525 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
526 | } |
527 | ||
528 | if (watch) | |
529 | { | |
530 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 531 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
532 | } |
533 | else | |
534 | { | |
535 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 536 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
537 | } |
538 | ||
539 | for (i = 0; i < count; i++) | |
540 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
541 | { | |
09b4ad9f | 542 | pts[i] = p; |
00192f77 SM |
543 | |
544 | /* Only update the threads of the current process. */ | |
545 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
546 | { | |
547 | update_registers_callback (thread, watch, i); | |
548 | }); | |
549 | ||
09b4ad9f UW |
550 | return 0; |
551 | } | |
552 | ||
553 | /* We're out of watchpoints. */ | |
554 | return -1; | |
555 | } | |
556 | ||
557 | /* Remove hardware break-/watchpoint. */ | |
558 | static int | |
802e8e6d PA |
559 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
560 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
561 | { |
562 | struct process_info *proc = current_process (); | |
563 | struct arm_linux_hw_breakpoint p, *pts; | |
564 | int watch, i, count; | |
565 | ||
566 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
567 | if (watch < 0) | |
568 | { | |
569 | /* Unsupported. */ | |
570 | return -1; | |
571 | } | |
572 | ||
573 | if (watch) | |
574 | { | |
575 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 576 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
577 | } |
578 | else | |
579 | { | |
580 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 581 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
582 | } |
583 | ||
584 | for (i = 0; i < count; i++) | |
585 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
586 | { | |
09b4ad9f | 587 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
588 | |
589 | /* Only update the threads of the current process. */ | |
590 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
591 | { | |
592 | update_registers_callback (thread, watch, i); | |
593 | }); | |
594 | ||
09b4ad9f UW |
595 | return 0; |
596 | } | |
597 | ||
598 | /* No watchpoint matched. */ | |
599 | return -1; | |
600 | } | |
601 | ||
602 | /* Return whether current thread is stopped due to a watchpoint. */ | |
603 | static int | |
604 | arm_stopped_by_watchpoint (void) | |
605 | { | |
0bfdf32f | 606 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 607 | siginfo_t siginfo; |
09b4ad9f UW |
608 | |
609 | /* We must be able to set hardware watchpoints. */ | |
610 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
611 | return 0; | |
612 | ||
613 | /* Retrieve siginfo. */ | |
614 | errno = 0; | |
0bfdf32f | 615 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
616 | if (errno != 0) |
617 | return 0; | |
618 | ||
619 | /* This must be a hardware breakpoint. */ | |
620 | if (siginfo.si_signo != SIGTRAP | |
621 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
622 | return 0; | |
623 | ||
624 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
625 | a watchpoint. */ | |
626 | if (siginfo.si_errno >= 0) | |
627 | return 0; | |
628 | ||
629 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
630 | lwp->arch_private->stopped_data_address | |
631 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
632 | ||
633 | return 1; | |
634 | } | |
635 | ||
636 | /* Return data address that triggered watchpoint. Called only if | |
637 | arm_stopped_by_watchpoint returned true. */ | |
638 | static CORE_ADDR | |
639 | arm_stopped_data_address (void) | |
640 | { | |
0bfdf32f | 641 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
642 | return lwp->arch_private->stopped_data_address; |
643 | } | |
644 | ||
645 | /* Called when a new process is created. */ | |
646 | static struct arch_process_info * | |
647 | arm_new_process (void) | |
648 | { | |
8d749320 | 649 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
650 | return info; |
651 | } | |
652 | ||
04ec7890 SM |
653 | /* Called when a process is being deleted. */ |
654 | ||
655 | static void | |
656 | arm_delete_process (struct arch_process_info *info) | |
657 | { | |
658 | xfree (info); | |
659 | } | |
660 | ||
09b4ad9f | 661 | /* Called when a new thread is detected. */ |
34c703da GB |
662 | static void |
663 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 664 | { |
8d749320 | 665 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
666 | int i; |
667 | ||
668 | for (i = 0; i < MAX_BPTS; i++) | |
669 | info->bpts_changed[i] = 1; | |
670 | for (i = 0; i < MAX_WPTS; i++) | |
671 | info->wpts_changed[i] = 1; | |
672 | ||
34c703da | 673 | lwp->arch_private = info; |
09b4ad9f UW |
674 | } |
675 | ||
466eecee SM |
676 | /* Function to call when a thread is being deleted. */ |
677 | ||
678 | static void | |
679 | arm_delete_thread (struct arch_lwp_info *arch_lwp) | |
680 | { | |
681 | xfree (arch_lwp); | |
682 | } | |
683 | ||
3a8a0396 DB |
684 | static void |
685 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
686 | { | |
69291610 HW |
687 | struct arch_process_info *parent_proc_info; |
688 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
689 | struct lwp_info *child_lwp; |
690 | struct arch_lwp_info *child_lwp_info; | |
691 | int i; | |
692 | ||
693 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
694 | gdb_assert (parent->priv != NULL |
695 | && parent->priv->arch_private != NULL); | |
696 | gdb_assert (child->priv != NULL | |
697 | && child->priv->arch_private != NULL); | |
3a8a0396 | 698 | |
69291610 HW |
699 | parent_proc_info = parent->priv->arch_private; |
700 | child_proc_info = child->priv->arch_private; | |
701 | ||
3a8a0396 DB |
702 | /* Linux kernel before 2.6.33 commit |
703 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
704 | will inherit hardware debug registers from parent | |
705 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
706 | zeroed debug registers. | |
707 | ||
708 | GDB core assumes the child inherits the watchpoints/hw | |
709 | breakpoints of the parent, and will remove them all from the | |
710 | forked off process. Copy the debug registers mirrors into the | |
711 | new process so that all breakpoints and watchpoints can be | |
712 | removed together. The debug registers mirror will become zeroed | |
713 | in the end before detaching the forked off process, thus making | |
714 | this compatible with older Linux kernels too. */ | |
715 | ||
716 | *child_proc_info = *parent_proc_info; | |
717 | ||
718 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
719 | make sure that the registers will be updated. */ | |
9179355e | 720 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
721 | child_lwp_info = child_lwp->arch_private; |
722 | for (i = 0; i < MAX_BPTS; i++) | |
723 | child_lwp_info->bpts_changed[i] = 1; | |
724 | for (i = 0; i < MAX_WPTS; i++) | |
725 | child_lwp_info->wpts_changed[i] = 1; | |
726 | } | |
727 | ||
09b4ad9f UW |
728 | /* Called when resuming a thread. |
729 | If the debug regs have changed, update the thread's copies. */ | |
730 | static void | |
731 | arm_prepare_to_resume (struct lwp_info *lwp) | |
732 | { | |
d86d4aaf DE |
733 | struct thread_info *thread = get_lwp_thread (lwp); |
734 | int pid = lwpid_of (thread); | |
735 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 736 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
737 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
738 | int i; | |
739 | ||
740 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
741 | if (lwp_info->bpts_changed[i]) | |
742 | { | |
743 | errno = 0; | |
744 | ||
745 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 746 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 747 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 748 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 749 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
750 | |
751 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 752 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 753 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 754 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 755 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
756 | |
757 | lwp_info->bpts_changed[i] = 0; | |
758 | } | |
759 | ||
760 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
761 | if (lwp_info->wpts_changed[i]) | |
762 | { | |
763 | errno = 0; | |
764 | ||
765 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 766 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 767 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 768 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 769 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
770 | |
771 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 772 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 773 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 774 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 775 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
776 | |
777 | lwp_info->wpts_changed[i] = 0; | |
778 | } | |
779 | } | |
780 | ||
f7a6a40d YQ |
781 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
782 | addition, set IS_THUMB depending on whether we will return to ARM | |
783 | or Thumb code. | |
d9311bfa AT |
784 | See arm-linux.h for stack layout details. */ |
785 | static CORE_ADDR | |
f7a6a40d YQ |
786 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
787 | int *is_thumb) | |
d9311bfa AT |
788 | { |
789 | unsigned long sp; | |
790 | unsigned long sp_data; | |
791 | /* Offset of PC register. */ | |
792 | int pc_offset = 0; | |
793 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 794 | uint32_t cpsr; |
d9311bfa AT |
795 | |
796 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
797 | ||
798 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 799 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
800 | |
801 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
802 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
803 | ||
52405d85 | 804 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 805 | |
f7a6a40d | 806 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 807 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
808 | *is_thumb = ((cpsr & CPSR_T) != 0); |
809 | ||
d9311bfa AT |
810 | return next_pc; |
811 | } | |
812 | ||
813 | /* When PC is at a syscall instruction, return the PC of the next | |
814 | instruction to be executed. */ | |
815 | static CORE_ADDR | |
553cb527 | 816 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
817 | { |
818 | CORE_ADDR next_pc = 0; | |
553cb527 | 819 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
820 | int is_thumb = arm_is_thumb_mode (); |
821 | ULONGEST svc_number = 0; | |
822 | struct regcache *regcache = self->regcache; | |
823 | ||
824 | if (is_thumb) | |
825 | { | |
826 | collect_register (regcache, 7, &svc_number); | |
827 | next_pc = pc + 2; | |
828 | } | |
829 | else | |
830 | { | |
831 | unsigned long this_instr; | |
832 | unsigned long svc_operand; | |
833 | ||
694b382c | 834 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
835 | svc_operand = (0x00ffffff & this_instr); |
836 | ||
837 | if (svc_operand) /* OABI. */ | |
838 | { | |
839 | svc_number = svc_operand - 0x900000; | |
840 | } | |
841 | else /* EABI. */ | |
842 | { | |
843 | collect_register (regcache, 7, &svc_number); | |
844 | } | |
845 | ||
846 | next_pc = pc + 4; | |
847 | } | |
848 | ||
849 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
850 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
851 | { | |
f7a6a40d YQ |
852 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
853 | update IS_THUMB. */ | |
854 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
855 | } |
856 | ||
857 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
858 | if (is_thumb) | |
859 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
860 | ||
861 | return next_pc; | |
862 | } | |
09b4ad9f | 863 | |
3aee8918 PA |
864 | static const struct target_desc * |
865 | arm_read_description (void) | |
58d6951d | 866 | { |
974c89e0 | 867 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 868 | |
58d6951d | 869 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 870 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
871 | |
872 | if (arm_hwcap & HWCAP_VFP) | |
873 | { | |
166a82be AH |
874 | /* Make sure that the kernel supports reading VFP registers. Support was |
875 | added in 2.6.30. */ | |
876 | int pid = lwpid_of (current_thread); | |
877 | errno = 0; | |
878 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
879 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 880 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
881 | |
882 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
883 | it with VFP. */ | |
884 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 885 | return aarch32_linux_read_description (); |
58d6951d | 886 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 887 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 888 | else |
7cc17433 | 889 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
890 | } |
891 | ||
892 | /* The default configuration uses legacy FPA registers, probably | |
893 | simulated. */ | |
7cc17433 | 894 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
895 | } |
896 | ||
797bcff5 TBA |
897 | void |
898 | arm_target::low_arch_setup () | |
3aee8918 | 899 | { |
bd9e6534 YQ |
900 | int tid = lwpid_of (current_thread); |
901 | int gpregs[18]; | |
902 | struct iovec iov; | |
903 | ||
166a82be AH |
904 | /* Query hardware watchpoint/breakpoint capabilities. */ |
905 | arm_linux_init_hwbp_cap (tid); | |
906 | ||
3aee8918 | 907 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
908 | |
909 | iov.iov_base = gpregs; | |
910 | iov.iov_len = sizeof (gpregs); | |
911 | ||
912 | /* Check if PTRACE_GETREGSET works. */ | |
913 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
914 | have_ptrace_getregset = 1; | |
915 | else | |
916 | have_ptrace_getregset = 0; | |
3aee8918 PA |
917 | } |
918 | ||
d9311bfa AT |
919 | /* Fetch the next possible PCs after the current instruction executes. */ |
920 | ||
a0ff9e1a | 921 | static std::vector<CORE_ADDR> |
4d18591b | 922 | arm_gdbserver_get_next_pcs (struct regcache *regcache) |
d9311bfa AT |
923 | { |
924 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
925 | |
926 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
927 | &get_next_pcs_ops, | |
928 | /* Byte order is ignored assumed as host. */ | |
929 | 0, | |
930 | 0, | |
1b451dda | 931 | 1, |
d9311bfa AT |
932 | regcache); |
933 | ||
a0ff9e1a | 934 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
935 | } |
936 | ||
7d00775e AT |
937 | /* Support for hardware single step. */ |
938 | ||
939 | static int | |
940 | arm_supports_hardware_single_step (void) | |
941 | { | |
942 | return 0; | |
943 | } | |
944 | ||
79e7fd4f YQ |
945 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
946 | ||
947 | static void | |
948 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
949 | { | |
950 | if (arm_is_thumb_mode ()) | |
951 | collect_register_by_name (regcache, "r7", sysno); | |
952 | else | |
953 | { | |
954 | unsigned long pc; | |
955 | unsigned long insn; | |
956 | ||
957 | collect_register_by_name (regcache, "pc", &pc); | |
958 | ||
52405d85 | 959 | if (the_target->read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
960 | *sysno = UNKNOWN_SYSCALL; |
961 | else | |
962 | { | |
963 | unsigned long svc_operand = (0x00ffffff & insn); | |
964 | ||
965 | if (svc_operand) | |
966 | { | |
967 | /* OABI */ | |
968 | *sysno = svc_operand - 0x900000; | |
969 | } | |
970 | else | |
971 | { | |
972 | /* EABI */ | |
973 | collect_register_by_name (regcache, "r7", sysno); | |
974 | } | |
975 | } | |
976 | } | |
977 | } | |
978 | ||
bd9e6534 YQ |
979 | /* Register sets without using PTRACE_GETREGSET. */ |
980 | ||
3aee8918 | 981 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
982 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
983 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 984 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 985 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 986 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 987 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 988 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 989 | NULL_REGSET |
fb1e4ffc DJ |
990 | }; |
991 | ||
3aee8918 PA |
992 | static struct regsets_info arm_regsets_info = |
993 | { | |
994 | arm_regsets, /* regsets */ | |
995 | 0, /* num_regsets */ | |
996 | NULL, /* disabled_regsets */ | |
997 | }; | |
998 | ||
999 | static struct usrregs_info arm_usrregs_info = | |
1000 | { | |
1001 | arm_num_regs, | |
1002 | arm_regmap, | |
1003 | }; | |
1004 | ||
bd9e6534 | 1005 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1006 | { |
1007 | NULL, /* regset_bitmap */ | |
1008 | &arm_usrregs_info, | |
1009 | &arm_regsets_info | |
1010 | }; | |
1011 | ||
aa8d21c9 TBA |
1012 | const regs_info * |
1013 | arm_target::get_regs_info () | |
3aee8918 | 1014 | { |
bd9e6534 YQ |
1015 | const struct target_desc *tdesc = current_process ()->tdesc; |
1016 | ||
1017 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1018 | && (is_aarch32_linux_description (tdesc) |
1019 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1020 | return ®s_info_aarch32; |
7cc17433 AH |
1021 | |
1022 | return ®s_info_arm; | |
3aee8918 PA |
1023 | } |
1024 | ||
dd373349 | 1025 | struct linux_target_ops the_low_target = { |
dd373349 AT |
1026 | arm_cannot_fetch_register, |
1027 | arm_cannot_store_register, | |
1028 | NULL, /* fetch_register */ | |
276d4552 YQ |
1029 | linux_get_pc_32bit, |
1030 | linux_set_pc_32bit, | |
8689682c | 1031 | arm_breakpoint_kind_from_pc, |
dd373349 | 1032 | arm_sw_breakpoint_from_kind, |
d9311bfa | 1033 | arm_gdbserver_get_next_pcs, |
0d62e5e8 DJ |
1034 | 0, |
1035 | arm_breakpoint_at, | |
802e8e6d | 1036 | arm_supports_z_point_type, |
09b4ad9f UW |
1037 | arm_insert_point, |
1038 | arm_remove_point, | |
1039 | arm_stopped_by_watchpoint, | |
1040 | arm_stopped_data_address, | |
1041 | NULL, /* collect_ptrace_register */ | |
1042 | NULL, /* supply_ptrace_register */ | |
1043 | NULL, /* siginfo_fixup */ | |
1044 | arm_new_process, | |
04ec7890 | 1045 | arm_delete_process, |
09b4ad9f | 1046 | arm_new_thread, |
466eecee | 1047 | arm_delete_thread, |
3a8a0396 | 1048 | arm_new_fork, |
09b4ad9f | 1049 | arm_prepare_to_resume, |
769ef81f AT |
1050 | NULL, /* process_qsupported */ |
1051 | NULL, /* supports_tracepoints */ | |
1052 | NULL, /* get_thread_area */ | |
1053 | NULL, /* install_fast_tracepoint_jump_pad */ | |
1054 | NULL, /* emit_ops */ | |
1055 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
1056 | NULL, /* supports_range_stepping */ | |
7d00775e | 1057 | arm_breakpoint_kind_from_current_state, |
79e7fd4f YQ |
1058 | arm_supports_hardware_single_step, |
1059 | arm_get_syscall_trapinfo, | |
2ec06d2e | 1060 | }; |
3aee8918 | 1061 | |
ef0478f6 TBA |
1062 | /* The linux target ops object. */ |
1063 | ||
1064 | linux_process_target *the_linux_target = &the_arm_target; | |
1065 | ||
3aee8918 PA |
1066 | void |
1067 | initialize_low_arch (void) | |
1068 | { | |
bd9e6534 | 1069 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1070 | initialize_regsets_info (&arm_regsets_info); |
1071 | } |