Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
aa8d21c9 TBA |
63 | const regs_info *get_regs_info () override; |
64 | ||
06250e4e TBA |
65 | int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; |
66 | ||
67 | int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; | |
68 | ||
3ca4edb6 TBA |
69 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
70 | ||
7582c77c TBA |
71 | bool supports_software_single_step () override; |
72 | ||
007c9b97 TBA |
73 | bool supports_z_point_type (char z_type) override; |
74 | ||
b31cdfa6 TBA |
75 | bool supports_hardware_single_step () override; |
76 | ||
797bcff5 TBA |
77 | protected: |
78 | ||
79 | void low_arch_setup () override; | |
daca57a7 TBA |
80 | |
81 | bool low_cannot_fetch_register (int regno) override; | |
82 | ||
83 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
84 | |
85 | bool low_supports_breakpoints () override; | |
86 | ||
87 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
88 | ||
89 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
7582c77c TBA |
90 | |
91 | std::vector<CORE_ADDR> low_get_next_pcs (regcache *regcache) override; | |
d7146cda TBA |
92 | |
93 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
94 | |
95 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
96 | int size, raw_breakpoint *bp) override; | |
97 | ||
98 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
99 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
100 | |
101 | bool low_stopped_by_watchpoint () override; | |
102 | ||
103 | CORE_ADDR low_stopped_data_address () override; | |
fd000fb3 TBA |
104 | |
105 | arch_process_info *low_new_process () override; | |
106 | ||
107 | void low_delete_process (arch_process_info *info) override; | |
108 | ||
109 | void low_new_thread (lwp_info *) override; | |
110 | ||
111 | void low_delete_thread (arch_lwp_info *) override; | |
112 | ||
113 | void low_new_fork (process_info *parent, process_info *child) override; | |
d7599cc0 TBA |
114 | |
115 | void low_prepare_to_resume (lwp_info *lwp) override; | |
ef0478f6 TBA |
116 | }; |
117 | ||
118 | /* The singleton target ops object. */ | |
119 | ||
120 | static arm_target the_arm_target; | |
121 | ||
bf9ae9d8 TBA |
122 | bool |
123 | arm_target::low_supports_breakpoints () | |
124 | { | |
125 | return true; | |
126 | } | |
127 | ||
128 | CORE_ADDR | |
129 | arm_target::low_get_pc (regcache *regcache) | |
130 | { | |
131 | return linux_get_pc_32bit (regcache); | |
132 | } | |
133 | ||
134 | void | |
135 | arm_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
136 | { | |
137 | linux_set_pc_32bit (regcache, pc); | |
138 | } | |
139 | ||
06250e4e TBA |
140 | int |
141 | arm_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
142 | { | |
143 | return arm_breakpoint_kind_from_pc (pcptr); | |
144 | } | |
145 | ||
146 | int | |
147 | arm_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
148 | { | |
149 | return arm_breakpoint_kind_from_current_state (pcptr); | |
150 | } | |
151 | ||
3ca4edb6 TBA |
152 | const gdb_byte * |
153 | arm_target::sw_breakpoint_from_kind (int kind, int *size) | |
154 | { | |
155 | return arm_sw_breakpoint_from_kind (kind, size); | |
156 | } | |
157 | ||
d7146cda TBA |
158 | bool |
159 | arm_target::low_breakpoint_at (CORE_ADDR pc) | |
160 | { | |
161 | return arm_breakpoint_at (pc); | |
162 | } | |
163 | ||
09b4ad9f | 164 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 165 | static struct |
09b4ad9f UW |
166 | { |
167 | unsigned char arch; | |
168 | unsigned char max_wp_length; | |
169 | unsigned char wp_count; | |
170 | unsigned char bp_count; | |
71487fd7 | 171 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
172 | |
173 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
174 | typedef enum | |
175 | { | |
176 | arm_hwbp_break = 0, | |
177 | arm_hwbp_load = 1, | |
178 | arm_hwbp_store = 2, | |
179 | arm_hwbp_access = 3 | |
180 | } arm_hwbp_type; | |
181 | ||
182 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
183 | typedef unsigned int arm_hwbp_control_t; | |
184 | ||
185 | /* Structure used to keep track of hardware break-/watch-points. */ | |
186 | struct arm_linux_hw_breakpoint | |
187 | { | |
188 | /* Address to break on, or being watched. */ | |
189 | unsigned int address; | |
190 | /* Control register for break-/watch- point. */ | |
191 | arm_hwbp_control_t control; | |
192 | }; | |
193 | ||
194 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
195 | assume a maximum number of supported break-/watchpoints. */ | |
196 | #define MAX_BPTS 32 | |
197 | #define MAX_WPTS 32 | |
198 | ||
199 | /* Per-process arch-specific data we want to keep. */ | |
200 | struct arch_process_info | |
201 | { | |
202 | /* Hardware breakpoints for this process. */ | |
203 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
204 | /* Hardware watchpoints for this process. */ | |
205 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
206 | }; | |
207 | ||
208 | /* Per-thread arch-specific data we want to keep. */ | |
209 | struct arch_lwp_info | |
210 | { | |
211 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
212 | char bpts_changed[MAX_BPTS]; | |
213 | char wpts_changed[MAX_WPTS]; | |
214 | /* Cached stopped data address. */ | |
215 | CORE_ADDR stopped_data_address; | |
216 | }; | |
217 | ||
58d6951d DJ |
218 | /* These are in <asm/elf.h> in current kernels. */ |
219 | #define HWCAP_VFP 64 | |
220 | #define HWCAP_IWMMXT 512 | |
221 | #define HWCAP_NEON 4096 | |
222 | #define HWCAP_VFPv3 8192 | |
223 | #define HWCAP_VFPv3D16 16384 | |
224 | ||
0a30fbc4 DJ |
225 | #ifdef HAVE_SYS_REG_H |
226 | #include <sys/reg.h> | |
227 | #endif | |
228 | ||
23ce3b1c | 229 | #define arm_num_regs 26 |
0a30fbc4 | 230 | |
2ec06d2e | 231 | static int arm_regmap[] = { |
0a30fbc4 DJ |
232 | 0, 4, 8, 12, 16, 20, 24, 28, |
233 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
234 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
235 | 64 | |
0a30fbc4 DJ |
236 | }; |
237 | ||
d9311bfa AT |
238 | /* Forward declarations needed for get_next_pcs ops. */ |
239 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
240 | int len, | |
241 | int byte_order); | |
242 | ||
243 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
244 | CORE_ADDR val); | |
245 | ||
553cb527 | 246 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
247 | |
248 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
249 | ||
250 | /* get_next_pcs operations. */ | |
251 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
252 | get_next_pcs_read_memory_unsigned_integer, | |
253 | get_next_pcs_syscall_next_pc, | |
254 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
255 | get_next_pcs_is_thumb, |
256 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
257 | }; |
258 | ||
daca57a7 TBA |
259 | bool |
260 | arm_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 261 | { |
2ec06d2e | 262 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
263 | } |
264 | ||
daca57a7 TBA |
265 | bool |
266 | arm_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 267 | { |
2ec06d2e | 268 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
269 | } |
270 | ||
fb1e4ffc | 271 | static void |
442ea881 | 272 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 273 | { |
7cc17433 | 274 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
275 | return; |
276 | ||
166a82be | 277 | for (int i = 0; i < 16; i++) |
442ea881 | 278 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
279 | |
280 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 281 | for (int i = 0; i < 6; i++) |
442ea881 PA |
282 | collect_register (regcache, arm_num_regs + i + 16, |
283 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
284 | } |
285 | ||
286 | static void | |
442ea881 | 287 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 288 | { |
7cc17433 | 289 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
290 | return; |
291 | ||
166a82be | 292 | for (int i = 0; i < 16; i++) |
442ea881 | 293 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
294 | |
295 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 296 | for (int i = 0; i < 6; i++) |
442ea881 PA |
297 | supply_register (regcache, arm_num_regs + i + 16, |
298 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
299 | } |
300 | ||
58d6951d | 301 | static void |
442ea881 | 302 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 303 | { |
bd9e6534 | 304 | int num; |
58d6951d | 305 | |
7cc17433 | 306 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 307 | num = 32; |
89abb039 | 308 | else |
7cc17433 AH |
309 | { |
310 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
311 | ||
312 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
313 | num = 32; | |
314 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
315 | num = 16; | |
316 | else | |
317 | return; | |
318 | } | |
58d6951d | 319 | |
bd9e6534 | 320 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
321 | } |
322 | ||
d9311bfa AT |
323 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
324 | static CORE_ADDR | |
325 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
326 | { | |
327 | return UNMAKE_THUMB_ADDR (val); | |
328 | } | |
329 | ||
58d6951d | 330 | static void |
442ea881 | 331 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 332 | { |
bd9e6534 | 333 | int num; |
58d6951d | 334 | |
7cc17433 | 335 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 336 | num = 32; |
89abb039 | 337 | else |
7cc17433 AH |
338 | { |
339 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
340 | ||
341 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
342 | num = 32; | |
343 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
344 | num = 16; | |
345 | else | |
346 | return; | |
347 | } | |
58d6951d | 348 | |
bd9e6534 | 349 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 350 | } |
fb1e4ffc | 351 | |
d9311bfa AT |
352 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
353 | static int | |
354 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
355 | { | |
356 | return arm_is_thumb_mode (); | |
357 | } | |
358 | ||
30baf67b | 359 | /* Read memory from the inferior. |
d9311bfa AT |
360 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
361 | read_memory_unsigned_integer. */ | |
362 | static ULONGEST | |
363 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
364 | int len, | |
365 | int byte_order) | |
366 | { | |
367 | ULONGEST res; | |
368 | ||
9e784964 | 369 | res = 0; |
694b382c AT |
370 | target_read_memory (memaddr, (unsigned char *) &res, len); |
371 | ||
d9311bfa AT |
372 | return res; |
373 | } | |
374 | ||
9308fc88 DJ |
375 | /* Fetch the thread-local storage pointer for libthread_db. */ |
376 | ||
377 | ps_err_e | |
754653a7 | 378 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 379 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
380 | { |
381 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
382 | return PS_ERR; | |
383 | ||
384 | /* IDX is the bias from the thread pointer to the beginning of the | |
385 | thread descriptor. It has to be subtracted due to implementation | |
386 | quirks in libthread_db. */ | |
387 | *base = (void *) ((char *)*base - idx); | |
388 | ||
389 | return PS_OK; | |
390 | } | |
391 | ||
09b4ad9f | 392 | |
71487fd7 UW |
393 | /* Query Hardware Breakpoint information for the target we are attached to |
394 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
395 | static void | |
396 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 397 | { |
71487fd7 | 398 | unsigned int val; |
09b4ad9f | 399 | |
71487fd7 UW |
400 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
401 | return; | |
09b4ad9f | 402 | |
71487fd7 UW |
403 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
404 | if (arm_linux_hwbp_cap.arch == 0) | |
405 | return; | |
09b4ad9f | 406 | |
71487fd7 UW |
407 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
408 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
409 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 410 | |
71487fd7 UW |
411 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
412 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
413 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
414 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
415 | } |
416 | ||
417 | /* How many hardware breakpoints are available? */ | |
418 | static int | |
419 | arm_linux_get_hw_breakpoint_count (void) | |
420 | { | |
71487fd7 | 421 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
422 | } |
423 | ||
424 | /* How many hardware watchpoints are available? */ | |
425 | static int | |
426 | arm_linux_get_hw_watchpoint_count (void) | |
427 | { | |
71487fd7 | 428 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
429 | } |
430 | ||
431 | /* Maximum length of area watched by hardware watchpoint. */ | |
432 | static int | |
433 | arm_linux_get_hw_watchpoint_max_length (void) | |
434 | { | |
71487fd7 | 435 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
436 | } |
437 | ||
438 | /* Initialize an ARM hardware break-/watch-point control register value. | |
439 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
440 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
441 | */ | |
442 | static arm_hwbp_control_t | |
443 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
444 | arm_hwbp_type hwbp_type, | |
445 | int enable) | |
446 | { | |
447 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
448 | gdb_assert (hwbp_type != arm_hwbp_break | |
449 | || ((byte_address_select & 0xfU) != 0)); | |
450 | ||
451 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
452 | } | |
453 | ||
454 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
455 | static int | |
456 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
457 | { | |
458 | return control & 0x1; | |
459 | } | |
460 | ||
461 | /* Is the breakpoint control value CONTROL initialized? */ | |
462 | static int | |
463 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
464 | { | |
465 | return control != 0; | |
466 | } | |
467 | ||
468 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
469 | static arm_hwbp_control_t | |
470 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
471 | { | |
472 | return control & ~0x1; | |
473 | } | |
474 | ||
475 | /* Are two break-/watch-points equal? */ | |
476 | static int | |
477 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
478 | const struct arm_linux_hw_breakpoint *p2) | |
479 | { | |
480 | return p1->address == p2->address && p1->control == p2->control; | |
481 | } | |
482 | ||
802e8e6d PA |
483 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
484 | ||
171de4b8 | 485 | static arm_hwbp_type |
802e8e6d PA |
486 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
487 | { | |
488 | switch (raw_type) | |
489 | { | |
490 | case raw_bkpt_type_hw: | |
491 | return arm_hwbp_break; | |
492 | case raw_bkpt_type_write_wp: | |
493 | return arm_hwbp_store; | |
494 | case raw_bkpt_type_read_wp: | |
495 | return arm_hwbp_load; | |
496 | case raw_bkpt_type_access_wp: | |
497 | return arm_hwbp_access; | |
498 | default: | |
499 | gdb_assert_not_reached ("unhandled raw type"); | |
500 | } | |
501 | } | |
502 | ||
09b4ad9f UW |
503 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
504 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
505 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
506 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
507 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 508 | static int |
802e8e6d PA |
509 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
510 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
511 | { |
512 | arm_hwbp_type hwbp_type; | |
513 | unsigned mask; | |
514 | ||
802e8e6d | 515 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
516 | |
517 | if (hwbp_type == arm_hwbp_break) | |
518 | { | |
519 | /* For breakpoints, the length field encodes the mode. */ | |
520 | switch (len) | |
521 | { | |
522 | case 2: /* 16-bit Thumb mode breakpoint */ | |
523 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
524 | mask = 0x3; |
525 | addr &= ~1; | |
09b4ad9f UW |
526 | break; |
527 | case 4: /* 32-bit ARM mode breakpoint */ | |
528 | mask = 0xf; | |
fcf303ab | 529 | addr &= ~3; |
09b4ad9f UW |
530 | break; |
531 | default: | |
532 | /* Unsupported. */ | |
b62e2b27 | 533 | return -2; |
09b4ad9f | 534 | } |
09b4ad9f UW |
535 | } |
536 | else | |
537 | { | |
538 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
539 | CORE_ADDR aligned_addr; | |
540 | ||
541 | /* Can not set watchpoints for zero or negative lengths. */ | |
542 | if (len <= 0) | |
b62e2b27 | 543 | return -2; |
09b4ad9f UW |
544 | /* The current ptrace interface can only handle watchpoints that are a |
545 | power of 2. */ | |
546 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 547 | return -2; |
09b4ad9f UW |
548 | |
549 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
550 | range covered by a watchpoint. */ | |
551 | aligned_addr = addr & ~(max_wp_length - 1); | |
552 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 553 | return -2; |
09b4ad9f UW |
554 | |
555 | mask = (1 << len) - 1; | |
556 | } | |
557 | ||
558 | p->address = (unsigned int) addr; | |
559 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
560 | ||
561 | return hwbp_type != arm_hwbp_break; | |
562 | } | |
563 | ||
564 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
565 | the current process. */ | |
566 | ||
00192f77 SM |
567 | static void |
568 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 569 | { |
d86d4aaf | 570 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 571 | |
00192f77 SM |
572 | /* The actual update is done later just before resuming the lwp, |
573 | we just mark that the registers need updating. */ | |
574 | if (watch) | |
575 | lwp->arch_private->wpts_changed[i] = 1; | |
576 | else | |
577 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 578 | |
00192f77 SM |
579 | /* If the lwp isn't stopped, force it to momentarily pause, so |
580 | we can update its breakpoint registers. */ | |
581 | if (!lwp->stopped) | |
582 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
583 | } |
584 | ||
007c9b97 TBA |
585 | bool |
586 | arm_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
587 | { |
588 | switch (z_type) | |
589 | { | |
abeead09 | 590 | case Z_PACKET_SW_BP: |
802e8e6d PA |
591 | case Z_PACKET_HW_BP: |
592 | case Z_PACKET_WRITE_WP: | |
593 | case Z_PACKET_READ_WP: | |
594 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 595 | return true; |
802e8e6d PA |
596 | default: |
597 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
007c9b97 | 598 | return false; |
802e8e6d PA |
599 | } |
600 | } | |
601 | ||
09b4ad9f | 602 | /* Insert hardware break-/watchpoint. */ |
9db9aa23 TBA |
603 | int |
604 | arm_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
605 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
606 | { |
607 | struct process_info *proc = current_process (); | |
608 | struct arm_linux_hw_breakpoint p, *pts; | |
609 | int watch, i, count; | |
610 | ||
611 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
612 | if (watch < 0) | |
613 | { | |
614 | /* Unsupported. */ | |
b62e2b27 | 615 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
616 | } |
617 | ||
618 | if (watch) | |
619 | { | |
620 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 621 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
622 | } |
623 | else | |
624 | { | |
625 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 626 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
627 | } |
628 | ||
629 | for (i = 0; i < count; i++) | |
630 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
631 | { | |
09b4ad9f | 632 | pts[i] = p; |
00192f77 SM |
633 | |
634 | /* Only update the threads of the current process. */ | |
635 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
636 | { | |
637 | update_registers_callback (thread, watch, i); | |
638 | }); | |
639 | ||
09b4ad9f UW |
640 | return 0; |
641 | } | |
642 | ||
643 | /* We're out of watchpoints. */ | |
644 | return -1; | |
645 | } | |
646 | ||
647 | /* Remove hardware break-/watchpoint. */ | |
9db9aa23 TBA |
648 | int |
649 | arm_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
650 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
651 | { |
652 | struct process_info *proc = current_process (); | |
653 | struct arm_linux_hw_breakpoint p, *pts; | |
654 | int watch, i, count; | |
655 | ||
656 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
657 | if (watch < 0) | |
658 | { | |
659 | /* Unsupported. */ | |
660 | return -1; | |
661 | } | |
662 | ||
663 | if (watch) | |
664 | { | |
665 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 666 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
667 | } |
668 | else | |
669 | { | |
670 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 671 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
672 | } |
673 | ||
674 | for (i = 0; i < count; i++) | |
675 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
676 | { | |
09b4ad9f | 677 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
678 | |
679 | /* Only update the threads of the current process. */ | |
680 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
681 | { | |
682 | update_registers_callback (thread, watch, i); | |
683 | }); | |
684 | ||
09b4ad9f UW |
685 | return 0; |
686 | } | |
687 | ||
688 | /* No watchpoint matched. */ | |
689 | return -1; | |
690 | } | |
691 | ||
692 | /* Return whether current thread is stopped due to a watchpoint. */ | |
ac1bbaca TBA |
693 | bool |
694 | arm_target::low_stopped_by_watchpoint () | |
09b4ad9f | 695 | { |
0bfdf32f | 696 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 697 | siginfo_t siginfo; |
09b4ad9f UW |
698 | |
699 | /* We must be able to set hardware watchpoints. */ | |
700 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
ac1bbaca | 701 | return false; |
09b4ad9f UW |
702 | |
703 | /* Retrieve siginfo. */ | |
704 | errno = 0; | |
0bfdf32f | 705 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f | 706 | if (errno != 0) |
ac1bbaca | 707 | return false; |
09b4ad9f UW |
708 | |
709 | /* This must be a hardware breakpoint. */ | |
710 | if (siginfo.si_signo != SIGTRAP | |
711 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
ac1bbaca | 712 | return false; |
09b4ad9f UW |
713 | |
714 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
715 | a watchpoint. */ | |
716 | if (siginfo.si_errno >= 0) | |
ac1bbaca | 717 | return false; |
09b4ad9f UW |
718 | |
719 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
720 | lwp->arch_private->stopped_data_address | |
721 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
722 | ||
ac1bbaca | 723 | return true; |
09b4ad9f UW |
724 | } |
725 | ||
726 | /* Return data address that triggered watchpoint. Called only if | |
ac1bbaca TBA |
727 | low_stopped_by_watchpoint returned true. */ |
728 | CORE_ADDR | |
729 | arm_target::low_stopped_data_address () | |
09b4ad9f | 730 | { |
0bfdf32f | 731 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
732 | return lwp->arch_private->stopped_data_address; |
733 | } | |
734 | ||
735 | /* Called when a new process is created. */ | |
fd000fb3 TBA |
736 | arch_process_info * |
737 | arm_target::low_new_process () | |
09b4ad9f | 738 | { |
8d749320 | 739 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
740 | return info; |
741 | } | |
742 | ||
04ec7890 SM |
743 | /* Called when a process is being deleted. */ |
744 | ||
fd000fb3 TBA |
745 | void |
746 | arm_target::low_delete_process (arch_process_info *info) | |
04ec7890 SM |
747 | { |
748 | xfree (info); | |
749 | } | |
750 | ||
09b4ad9f | 751 | /* Called when a new thread is detected. */ |
fd000fb3 TBA |
752 | void |
753 | arm_target::low_new_thread (lwp_info *lwp) | |
09b4ad9f | 754 | { |
8d749320 | 755 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
756 | int i; |
757 | ||
758 | for (i = 0; i < MAX_BPTS; i++) | |
759 | info->bpts_changed[i] = 1; | |
760 | for (i = 0; i < MAX_WPTS; i++) | |
761 | info->wpts_changed[i] = 1; | |
762 | ||
34c703da | 763 | lwp->arch_private = info; |
09b4ad9f UW |
764 | } |
765 | ||
466eecee SM |
766 | /* Function to call when a thread is being deleted. */ |
767 | ||
fd000fb3 TBA |
768 | void |
769 | arm_target::low_delete_thread (arch_lwp_info *arch_lwp) | |
466eecee SM |
770 | { |
771 | xfree (arch_lwp); | |
772 | } | |
773 | ||
fd000fb3 TBA |
774 | void |
775 | arm_target::low_new_fork (process_info *parent, process_info *child) | |
3a8a0396 | 776 | { |
69291610 HW |
777 | struct arch_process_info *parent_proc_info; |
778 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
779 | struct lwp_info *child_lwp; |
780 | struct arch_lwp_info *child_lwp_info; | |
781 | int i; | |
782 | ||
783 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
784 | gdb_assert (parent->priv != NULL |
785 | && parent->priv->arch_private != NULL); | |
786 | gdb_assert (child->priv != NULL | |
787 | && child->priv->arch_private != NULL); | |
3a8a0396 | 788 | |
69291610 HW |
789 | parent_proc_info = parent->priv->arch_private; |
790 | child_proc_info = child->priv->arch_private; | |
791 | ||
3a8a0396 DB |
792 | /* Linux kernel before 2.6.33 commit |
793 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
794 | will inherit hardware debug registers from parent | |
795 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
796 | zeroed debug registers. | |
797 | ||
798 | GDB core assumes the child inherits the watchpoints/hw | |
799 | breakpoints of the parent, and will remove them all from the | |
800 | forked off process. Copy the debug registers mirrors into the | |
801 | new process so that all breakpoints and watchpoints can be | |
802 | removed together. The debug registers mirror will become zeroed | |
803 | in the end before detaching the forked off process, thus making | |
804 | this compatible with older Linux kernels too. */ | |
805 | ||
806 | *child_proc_info = *parent_proc_info; | |
807 | ||
808 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
809 | make sure that the registers will be updated. */ | |
9179355e | 810 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
811 | child_lwp_info = child_lwp->arch_private; |
812 | for (i = 0; i < MAX_BPTS; i++) | |
813 | child_lwp_info->bpts_changed[i] = 1; | |
814 | for (i = 0; i < MAX_WPTS; i++) | |
815 | child_lwp_info->wpts_changed[i] = 1; | |
816 | } | |
817 | ||
09b4ad9f UW |
818 | /* Called when resuming a thread. |
819 | If the debug regs have changed, update the thread's copies. */ | |
d7599cc0 TBA |
820 | void |
821 | arm_target::low_prepare_to_resume (lwp_info *lwp) | |
09b4ad9f | 822 | { |
d86d4aaf DE |
823 | struct thread_info *thread = get_lwp_thread (lwp); |
824 | int pid = lwpid_of (thread); | |
825 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 826 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
827 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
828 | int i; | |
829 | ||
830 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
831 | if (lwp_info->bpts_changed[i]) | |
832 | { | |
833 | errno = 0; | |
834 | ||
835 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 836 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 837 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 838 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 839 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
840 | |
841 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 842 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 843 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 844 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 845 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
846 | |
847 | lwp_info->bpts_changed[i] = 0; | |
848 | } | |
849 | ||
850 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
851 | if (lwp_info->wpts_changed[i]) | |
852 | { | |
853 | errno = 0; | |
854 | ||
855 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 856 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 857 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 858 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 859 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
860 | |
861 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 862 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 863 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 864 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 865 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
866 | |
867 | lwp_info->wpts_changed[i] = 0; | |
868 | } | |
869 | } | |
870 | ||
f7a6a40d YQ |
871 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
872 | addition, set IS_THUMB depending on whether we will return to ARM | |
873 | or Thumb code. | |
d9311bfa AT |
874 | See arm-linux.h for stack layout details. */ |
875 | static CORE_ADDR | |
f7a6a40d YQ |
876 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
877 | int *is_thumb) | |
d9311bfa AT |
878 | { |
879 | unsigned long sp; | |
880 | unsigned long sp_data; | |
881 | /* Offset of PC register. */ | |
882 | int pc_offset = 0; | |
883 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 884 | uint32_t cpsr; |
d9311bfa AT |
885 | |
886 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
887 | ||
888 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 889 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
890 | |
891 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
892 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
893 | ||
52405d85 | 894 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 895 | |
f7a6a40d | 896 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 897 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
898 | *is_thumb = ((cpsr & CPSR_T) != 0); |
899 | ||
d9311bfa AT |
900 | return next_pc; |
901 | } | |
902 | ||
903 | /* When PC is at a syscall instruction, return the PC of the next | |
904 | instruction to be executed. */ | |
905 | static CORE_ADDR | |
553cb527 | 906 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
907 | { |
908 | CORE_ADDR next_pc = 0; | |
553cb527 | 909 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
910 | int is_thumb = arm_is_thumb_mode (); |
911 | ULONGEST svc_number = 0; | |
912 | struct regcache *regcache = self->regcache; | |
913 | ||
914 | if (is_thumb) | |
915 | { | |
916 | collect_register (regcache, 7, &svc_number); | |
917 | next_pc = pc + 2; | |
918 | } | |
919 | else | |
920 | { | |
921 | unsigned long this_instr; | |
922 | unsigned long svc_operand; | |
923 | ||
694b382c | 924 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
925 | svc_operand = (0x00ffffff & this_instr); |
926 | ||
927 | if (svc_operand) /* OABI. */ | |
928 | { | |
929 | svc_number = svc_operand - 0x900000; | |
930 | } | |
931 | else /* EABI. */ | |
932 | { | |
933 | collect_register (regcache, 7, &svc_number); | |
934 | } | |
935 | ||
936 | next_pc = pc + 4; | |
937 | } | |
938 | ||
939 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
940 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
941 | { | |
f7a6a40d YQ |
942 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
943 | update IS_THUMB. */ | |
944 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
945 | } |
946 | ||
947 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
948 | if (is_thumb) | |
949 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
950 | ||
951 | return next_pc; | |
952 | } | |
09b4ad9f | 953 | |
3aee8918 PA |
954 | static const struct target_desc * |
955 | arm_read_description (void) | |
58d6951d | 956 | { |
974c89e0 | 957 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 958 | |
58d6951d | 959 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 960 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
961 | |
962 | if (arm_hwcap & HWCAP_VFP) | |
963 | { | |
166a82be AH |
964 | /* Make sure that the kernel supports reading VFP registers. Support was |
965 | added in 2.6.30. */ | |
966 | int pid = lwpid_of (current_thread); | |
967 | errno = 0; | |
968 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
969 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 970 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
971 | |
972 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
973 | it with VFP. */ | |
974 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 975 | return aarch32_linux_read_description (); |
58d6951d | 976 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 977 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 978 | else |
7cc17433 | 979 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
980 | } |
981 | ||
982 | /* The default configuration uses legacy FPA registers, probably | |
983 | simulated. */ | |
7cc17433 | 984 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
985 | } |
986 | ||
797bcff5 TBA |
987 | void |
988 | arm_target::low_arch_setup () | |
3aee8918 | 989 | { |
bd9e6534 YQ |
990 | int tid = lwpid_of (current_thread); |
991 | int gpregs[18]; | |
992 | struct iovec iov; | |
993 | ||
166a82be AH |
994 | /* Query hardware watchpoint/breakpoint capabilities. */ |
995 | arm_linux_init_hwbp_cap (tid); | |
996 | ||
3aee8918 | 997 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
998 | |
999 | iov.iov_base = gpregs; | |
1000 | iov.iov_len = sizeof (gpregs); | |
1001 | ||
1002 | /* Check if PTRACE_GETREGSET works. */ | |
1003 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
1004 | have_ptrace_getregset = 1; | |
1005 | else | |
1006 | have_ptrace_getregset = 0; | |
3aee8918 PA |
1007 | } |
1008 | ||
7582c77c TBA |
1009 | bool |
1010 | arm_target::supports_software_single_step () | |
1011 | { | |
1012 | return true; | |
1013 | } | |
1014 | ||
d9311bfa AT |
1015 | /* Fetch the next possible PCs after the current instruction executes. */ |
1016 | ||
7582c77c TBA |
1017 | std::vector<CORE_ADDR> |
1018 | arm_target::low_get_next_pcs (regcache *regcache) | |
d9311bfa AT |
1019 | { |
1020 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
1021 | |
1022 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
1023 | &get_next_pcs_ops, | |
1024 | /* Byte order is ignored assumed as host. */ | |
1025 | 0, | |
1026 | 0, | |
1b451dda | 1027 | 1, |
d9311bfa AT |
1028 | regcache); |
1029 | ||
a0ff9e1a | 1030 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
1031 | } |
1032 | ||
7d00775e AT |
1033 | /* Support for hardware single step. */ |
1034 | ||
b31cdfa6 TBA |
1035 | bool |
1036 | arm_target::supports_hardware_single_step () | |
7d00775e | 1037 | { |
b31cdfa6 | 1038 | return false; |
7d00775e AT |
1039 | } |
1040 | ||
79e7fd4f YQ |
1041 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
1042 | ||
1043 | static void | |
1044 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
1045 | { | |
1046 | if (arm_is_thumb_mode ()) | |
1047 | collect_register_by_name (regcache, "r7", sysno); | |
1048 | else | |
1049 | { | |
1050 | unsigned long pc; | |
1051 | unsigned long insn; | |
1052 | ||
1053 | collect_register_by_name (regcache, "pc", &pc); | |
1054 | ||
52405d85 | 1055 | if (the_target->read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
1056 | *sysno = UNKNOWN_SYSCALL; |
1057 | else | |
1058 | { | |
1059 | unsigned long svc_operand = (0x00ffffff & insn); | |
1060 | ||
1061 | if (svc_operand) | |
1062 | { | |
1063 | /* OABI */ | |
1064 | *sysno = svc_operand - 0x900000; | |
1065 | } | |
1066 | else | |
1067 | { | |
1068 | /* EABI */ | |
1069 | collect_register_by_name (regcache, "r7", sysno); | |
1070 | } | |
1071 | } | |
1072 | } | |
1073 | } | |
1074 | ||
bd9e6534 YQ |
1075 | /* Register sets without using PTRACE_GETREGSET. */ |
1076 | ||
3aee8918 | 1077 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
1078 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
1079 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 1080 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 1081 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 1082 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 1083 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 1084 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 1085 | NULL_REGSET |
fb1e4ffc DJ |
1086 | }; |
1087 | ||
3aee8918 PA |
1088 | static struct regsets_info arm_regsets_info = |
1089 | { | |
1090 | arm_regsets, /* regsets */ | |
1091 | 0, /* num_regsets */ | |
1092 | NULL, /* disabled_regsets */ | |
1093 | }; | |
1094 | ||
1095 | static struct usrregs_info arm_usrregs_info = | |
1096 | { | |
1097 | arm_num_regs, | |
1098 | arm_regmap, | |
1099 | }; | |
1100 | ||
bd9e6534 | 1101 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1102 | { |
1103 | NULL, /* regset_bitmap */ | |
1104 | &arm_usrregs_info, | |
1105 | &arm_regsets_info | |
1106 | }; | |
1107 | ||
aa8d21c9 TBA |
1108 | const regs_info * |
1109 | arm_target::get_regs_info () | |
3aee8918 | 1110 | { |
bd9e6534 YQ |
1111 | const struct target_desc *tdesc = current_process ()->tdesc; |
1112 | ||
1113 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1114 | && (is_aarch32_linux_description (tdesc) |
1115 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1116 | return ®s_info_aarch32; |
7cc17433 AH |
1117 | |
1118 | return ®s_info_arm; | |
3aee8918 PA |
1119 | } |
1120 | ||
dd373349 | 1121 | struct linux_target_ops the_low_target = { |
79e7fd4f | 1122 | arm_get_syscall_trapinfo, |
2ec06d2e | 1123 | }; |
3aee8918 | 1124 | |
ef0478f6 TBA |
1125 | /* The linux target ops object. */ |
1126 | ||
1127 | linux_process_target *the_linux_target = &the_arm_target; | |
1128 | ||
3aee8918 PA |
1129 | void |
1130 | initialize_low_arch (void) | |
1131 | { | |
bd9e6534 | 1132 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1133 | initialize_regsets_info (&arm_regsets_info); |
1134 | } |