Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
007c9b97 TBA |
38 | bool supports_z_point_type (char z_type) override; |
39 | ||
797bcff5 TBA |
40 | protected: |
41 | ||
42 | void low_arch_setup () override; | |
daca57a7 TBA |
43 | |
44 | bool low_cannot_fetch_register (int regno) override; | |
45 | ||
46 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
47 | |
48 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
49 | |
50 | bool low_supports_breakpoints () override; | |
51 | ||
52 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
53 | ||
54 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
55 | |
56 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
ef0478f6 TBA |
57 | }; |
58 | ||
59 | /* The singleton target ops object. */ | |
60 | ||
61 | static mips_target the_mips_target; | |
62 | ||
d05b4ac3 UW |
63 | /* Defined in auto-generated file mips-linux.c. */ |
64 | void init_registers_mips_linux (void); | |
3aee8918 PA |
65 | extern const struct target_desc *tdesc_mips_linux; |
66 | ||
1faeff08 MR |
67 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
68 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
69 | extern const struct target_desc *tdesc_mips_dsp_linux; |
70 | ||
d05b4ac3 UW |
71 | /* Defined in auto-generated file mips64-linux.c. */ |
72 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
73 | extern const struct target_desc *tdesc_mips64_linux; |
74 | ||
1faeff08 MR |
75 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
76 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 77 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
78 | |
79 | #ifdef __mips64 | |
3aee8918 PA |
80 | #define tdesc_mips_linux tdesc_mips64_linux |
81 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 82 | #endif |
d05b4ac3 | 83 | |
21b0f40c DJ |
84 | #ifndef PTRACE_GET_THREAD_AREA |
85 | #define PTRACE_GET_THREAD_AREA 25 | |
86 | #endif | |
87 | ||
0a30fbc4 DJ |
88 | #ifdef HAVE_SYS_REG_H |
89 | #include <sys/reg.h> | |
90 | #endif | |
91 | ||
117ce543 | 92 | #define mips_num_regs 73 |
1faeff08 | 93 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
94 | |
95 | #include <asm/ptrace.h> | |
96 | ||
1faeff08 MR |
97 | #ifndef DSP_BASE |
98 | #define DSP_BASE 71 | |
99 | #define DSP_CONTROL 77 | |
100 | #endif | |
101 | ||
186947f7 DJ |
102 | union mips_register |
103 | { | |
104 | unsigned char buf[8]; | |
105 | ||
106 | /* Deliberately signed, for proper sign extension. */ | |
107 | int reg32; | |
108 | long long reg64; | |
109 | }; | |
110 | ||
0a30fbc4 DJ |
111 | /* Return the ptrace ``address'' of register REGNO. */ |
112 | ||
1faeff08 MR |
113 | #define mips_base_regs \ |
114 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
115 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
116 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
117 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
118 | \ | |
119 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
120 | \ | |
121 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
122 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
123 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
124 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
125 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
126 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
127 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
128 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
129 | FPC_CSR, FPC_EIR | |
130 | ||
131 | #define mips_dsp_regs \ | |
132 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
133 | DSP_BASE + 4, DSP_BASE + 5, \ | |
134 | DSP_CONTROL | |
135 | ||
136 | static int mips_regmap[mips_num_regs] = { | |
137 | mips_base_regs, | |
138 | 0 | |
139 | }; | |
0a30fbc4 | 140 | |
1faeff08 MR |
141 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
142 | mips_base_regs, | |
143 | mips_dsp_regs, | |
144 | 0 | |
145 | }; | |
0a30fbc4 | 146 | |
1faeff08 MR |
147 | /* DSP registers are not in any regset and can only be accessed |
148 | individually. */ | |
0a30fbc4 | 149 | |
1faeff08 MR |
150 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
151 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
152 | }; |
153 | ||
3aee8918 PA |
154 | static int have_dsp = -1; |
155 | ||
1faeff08 MR |
156 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
157 | user register set accordingly. */ | |
158 | ||
3aee8918 PA |
159 | static const struct target_desc * |
160 | mips_read_description (void) | |
1faeff08 | 161 | { |
3aee8918 | 162 | if (have_dsp < 0) |
1faeff08 | 163 | { |
0bfdf32f | 164 | int pid = lwpid_of (current_thread); |
1faeff08 | 165 | |
ac740bc7 | 166 | errno = 0; |
1faeff08 MR |
167 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
168 | switch (errno) | |
169 | { | |
170 | case 0: | |
3aee8918 | 171 | have_dsp = 1; |
1faeff08 MR |
172 | break; |
173 | case EIO: | |
3aee8918 | 174 | have_dsp = 0; |
1faeff08 MR |
175 | break; |
176 | default: | |
177 | perror_with_name ("ptrace"); | |
178 | break; | |
179 | } | |
180 | } | |
3aee8918 PA |
181 | |
182 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
183 | } | |
184 | ||
797bcff5 TBA |
185 | void |
186 | mips_target::low_arch_setup () | |
3aee8918 PA |
187 | { |
188 | current_process ()->tdesc = mips_read_description (); | |
189 | } | |
190 | ||
7a60ad40 YQ |
191 | /* Per-process arch-specific data we want to keep. */ |
192 | ||
193 | struct arch_process_info | |
194 | { | |
195 | /* -1 if the kernel and/or CPU do not support watch registers. | |
196 | 1 if watch_readback is valid and we can read style, num_valid | |
197 | and the masks. | |
198 | 0 if we need to read the watch_readback. */ | |
199 | ||
200 | int watch_readback_valid; | |
201 | ||
202 | /* Cached watch register read values. */ | |
203 | ||
204 | struct pt_watch_regs watch_readback; | |
205 | ||
206 | /* Current watchpoint requests for this process. */ | |
207 | ||
208 | struct mips_watchpoint *current_watches; | |
209 | ||
210 | /* The current set of watch register values for writing the | |
211 | registers. */ | |
212 | ||
213 | struct pt_watch_regs watch_mirror; | |
214 | }; | |
215 | ||
216 | /* Per-thread arch-specific data we want to keep. */ | |
217 | ||
218 | struct arch_lwp_info | |
219 | { | |
220 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
221 | int watch_registers_changed; | |
222 | }; | |
223 | ||
0a30fbc4 DJ |
224 | /* From mips-linux-nat.c. */ |
225 | ||
226 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
227 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
228 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
229 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 230 | |
daca57a7 TBA |
231 | bool |
232 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 233 | { |
3aee8918 PA |
234 | const struct target_desc *tdesc; |
235 | ||
daca57a7 TBA |
236 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
237 | return true; | |
0a30fbc4 | 238 | |
3aee8918 PA |
239 | tdesc = current_process ()->tdesc; |
240 | ||
75d74cca MR |
241 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
242 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 243 | return true; |
75d74cca | 244 | |
3aee8918 | 245 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 246 | return true; |
0a30fbc4 | 247 | |
daca57a7 | 248 | return false; |
0a30fbc4 DJ |
249 | } |
250 | ||
daca57a7 TBA |
251 | bool |
252 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 253 | { |
3aee8918 PA |
254 | const struct target_desc *tdesc; |
255 | ||
daca57a7 TBA |
256 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
257 | return true; | |
0a30fbc4 | 258 | |
3aee8918 PA |
259 | tdesc = current_process ()->tdesc; |
260 | ||
75d74cca MR |
261 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
262 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 263 | return true; |
75d74cca | 264 | |
3aee8918 | 265 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 266 | return true; |
0a30fbc4 | 267 | |
3aee8918 | 268 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 269 | return true; |
0a30fbc4 | 270 | |
3aee8918 | 271 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 272 | return true; |
0a30fbc4 | 273 | |
3aee8918 | 274 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 275 | return true; |
0a30fbc4 | 276 | |
daca57a7 | 277 | return false; |
0a30fbc4 | 278 | } |
2ec06d2e | 279 | |
bd70b1f2 TBA |
280 | bool |
281 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
282 | { |
283 | const struct target_desc *tdesc = current_process ()->tdesc; | |
284 | ||
285 | if (find_regno (tdesc, "r0") == regno) | |
286 | { | |
287 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 288 | return true; |
e4439e43 MR |
289 | } |
290 | ||
bd70b1f2 | 291 | return false; |
e4439e43 MR |
292 | } |
293 | ||
bf9ae9d8 TBA |
294 | bool |
295 | mips_target::low_supports_breakpoints () | |
296 | { | |
297 | return true; | |
298 | } | |
299 | ||
300 | CORE_ADDR | |
301 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 302 | { |
186947f7 | 303 | union mips_register pc; |
442ea881 | 304 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 305 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
306 | } |
307 | ||
bf9ae9d8 TBA |
308 | void |
309 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 310 | { |
186947f7 | 311 | union mips_register newpc; |
3aee8918 | 312 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
313 | newpc.reg32 = pc; |
314 | else | |
315 | newpc.reg64 = pc; | |
316 | ||
442ea881 | 317 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
318 | } |
319 | ||
320 | /* Correct in either endianness. */ | |
186947f7 | 321 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
322 | #define mips_breakpoint_len 4 |
323 | ||
3ca4edb6 | 324 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 325 | |
3ca4edb6 TBA |
326 | const gdb_byte * |
327 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
328 | { |
329 | *size = mips_breakpoint_len; | |
330 | return (const gdb_byte *) &mips_breakpoint; | |
331 | } | |
332 | ||
d7146cda TBA |
333 | bool |
334 | mips_target::low_breakpoint_at (CORE_ADDR where) | |
0d62e5e8 | 335 | { |
186947f7 | 336 | unsigned int insn; |
0d62e5e8 | 337 | |
d7146cda | 338 | read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 | 339 | if (insn == mips_breakpoint) |
d7146cda | 340 | return true; |
0d62e5e8 DJ |
341 | |
342 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
343 | one. */ | |
d7146cda | 344 | return false; |
0d62e5e8 DJ |
345 | } |
346 | ||
da25033c | 347 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 348 | |
da25033c SM |
349 | static void |
350 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 351 | { |
d86d4aaf | 352 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 353 | |
da25033c SM |
354 | /* The actual update is done later just before resuming the lwp, |
355 | we just mark that the registers need updating. */ | |
356 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 357 | |
da25033c SM |
358 | /* If the lwp isn't stopped, force it to momentarily pause, so |
359 | we can update its watch registers. */ | |
360 | if (!lwp->stopped) | |
361 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
362 | } |
363 | ||
364 | /* This is the implementation of linux_target_ops method | |
365 | new_process. */ | |
366 | ||
367 | static struct arch_process_info * | |
368 | mips_linux_new_process (void) | |
369 | { | |
8d749320 | 370 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
371 | |
372 | return info; | |
373 | } | |
374 | ||
04ec7890 SM |
375 | /* This is the implementation of linux_target_ops method |
376 | delete_process. */ | |
377 | ||
378 | static void | |
379 | mips_linux_delete_process (struct arch_process_info *info) | |
380 | { | |
381 | xfree (info); | |
382 | } | |
383 | ||
7a60ad40 YQ |
384 | /* This is the implementation of linux_target_ops method new_thread. |
385 | Mark the watch registers as changed, so the threads' copies will | |
386 | be updated. */ | |
387 | ||
34c703da GB |
388 | static void |
389 | mips_linux_new_thread (struct lwp_info *lwp) | |
7a60ad40 | 390 | { |
8d749320 | 391 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
392 | |
393 | info->watch_registers_changed = 1; | |
394 | ||
34c703da | 395 | lwp->arch_private = info; |
7a60ad40 YQ |
396 | } |
397 | ||
466eecee SM |
398 | /* Function to call when a thread is being deleted. */ |
399 | ||
400 | static void | |
401 | mips_linux_delete_thread (struct arch_lwp_info *arch_lwp) | |
402 | { | |
403 | xfree (arch_lwp); | |
404 | } | |
405 | ||
3a8a0396 DB |
406 | /* Create a new mips_watchpoint and add it to the list. */ |
407 | ||
408 | static void | |
cbec665b | 409 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 410 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
411 | { |
412 | struct mips_watchpoint *new_watch; | |
413 | struct mips_watchpoint **pw; | |
414 | ||
8d749320 | 415 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
416 | new_watch->addr = addr; |
417 | new_watch->len = len; | |
418 | new_watch->type = watch_type; | |
419 | new_watch->next = NULL; | |
420 | ||
cbec665b | 421 | pw = &priv->current_watches; |
3a8a0396 DB |
422 | while (*pw != NULL) |
423 | pw = &(*pw)->next; | |
424 | *pw = new_watch; | |
425 | } | |
426 | ||
427 | /* Hook to call when a new fork is attached. */ | |
428 | ||
429 | static void | |
430 | mips_linux_new_fork (struct process_info *parent, | |
431 | struct process_info *child) | |
432 | { | |
433 | struct arch_process_info *parent_private; | |
434 | struct arch_process_info *child_private; | |
435 | struct mips_watchpoint *wp; | |
436 | ||
437 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
438 | gdb_assert (parent->priv != NULL |
439 | && parent->priv->arch_private != NULL); | |
440 | gdb_assert (child->priv != NULL | |
441 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
442 | |
443 | /* Linux kernel before 2.6.33 commit | |
444 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
445 | will inherit hardware debug registers from parent | |
446 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
447 | zeroed debug registers. | |
448 | ||
449 | GDB core assumes the child inherits the watchpoints/hw | |
450 | breakpoints of the parent, and will remove them all from the | |
451 | forked off process. Copy the debug registers mirrors into the | |
452 | new process so that all breakpoints and watchpoints can be | |
453 | removed together. The debug registers mirror will become zeroed | |
454 | in the end before detaching the forked off process, thus making | |
455 | this compatible with older Linux kernels too. */ | |
456 | ||
61a7418c DB |
457 | parent_private = parent->priv->arch_private; |
458 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
459 | |
460 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
461 | child_private->watch_readback = parent_private->watch_readback; | |
462 | ||
463 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
464 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
465 | ||
466 | child_private->watch_mirror = parent_private->watch_mirror; | |
467 | } | |
7a60ad40 YQ |
468 | /* This is the implementation of linux_target_ops method |
469 | prepare_to_resume. If the watch regs have changed, update the | |
470 | thread's copies. */ | |
471 | ||
472 | static void | |
473 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
474 | { | |
d86d4aaf | 475 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 476 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 477 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
478 | |
479 | if (lwp->arch_private->watch_registers_changed) | |
480 | { | |
481 | /* Only update the watch registers if we have set or unset a | |
482 | watchpoint already. */ | |
fe978cb0 | 483 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
484 | { |
485 | /* Write the mirrored watch register values. */ | |
e38504b3 | 486 | int tid = ptid.lwp (); |
7a60ad40 YQ |
487 | |
488 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 489 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
490 | perror_with_name ("Couldn't write watch register"); |
491 | } | |
492 | ||
493 | lwp->arch_private->watch_registers_changed = 0; | |
494 | } | |
495 | } | |
496 | ||
007c9b97 TBA |
497 | bool |
498 | mips_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
499 | { |
500 | switch (z_type) | |
501 | { | |
502 | case Z_PACKET_WRITE_WP: | |
503 | case Z_PACKET_READ_WP: | |
504 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 505 | return true; |
802e8e6d | 506 | default: |
007c9b97 | 507 | return false; |
802e8e6d PA |
508 | } |
509 | } | |
510 | ||
7a60ad40 YQ |
511 | /* This is the implementation of linux_target_ops method |
512 | insert_point. */ | |
513 | ||
514 | static int | |
802e8e6d PA |
515 | mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
516 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
517 | { |
518 | struct process_info *proc = current_process (); | |
fe978cb0 | 519 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 520 | struct pt_watch_regs regs; |
7a60ad40 YQ |
521 | long lwpid; |
522 | enum target_hw_bp_type watch_type; | |
523 | uint32_t irw; | |
524 | ||
0bfdf32f | 525 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 526 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
527 | &priv->watch_readback, |
528 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
529 | 0)) |
530 | return -1; | |
531 | ||
532 | if (len <= 0) | |
533 | return -1; | |
534 | ||
fe978cb0 | 535 | regs = priv->watch_readback; |
7a60ad40 | 536 | /* Add the current watches. */ |
fe978cb0 | 537 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
538 | |
539 | /* Now try to add the new watch. */ | |
802e8e6d | 540 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
541 | irw = mips_linux_watch_type_to_irw (watch_type); |
542 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
543 | return -1; | |
544 | ||
545 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 546 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 547 | |
fe978cb0 | 548 | priv->watch_mirror = regs; |
7a60ad40 YQ |
549 | |
550 | /* Only update the threads of this process. */ | |
da25033c | 551 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
552 | |
553 | return 0; | |
554 | } | |
555 | ||
556 | /* This is the implementation of linux_target_ops method | |
557 | remove_point. */ | |
558 | ||
559 | static int | |
802e8e6d PA |
560 | mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
561 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
562 | { |
563 | struct process_info *proc = current_process (); | |
fe978cb0 | 564 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
565 | |
566 | int deleted_one; | |
7a60ad40 YQ |
567 | enum target_hw_bp_type watch_type; |
568 | ||
569 | struct mips_watchpoint **pw; | |
570 | struct mips_watchpoint *w; | |
571 | ||
7a60ad40 | 572 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 573 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 574 | deleted_one = 0; |
fe978cb0 | 575 | pw = &priv->current_watches; |
7a60ad40 YQ |
576 | while ((w = *pw)) |
577 | { | |
578 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
579 | { | |
580 | *pw = w->next; | |
581 | free (w); | |
582 | deleted_one = 1; | |
583 | break; | |
584 | } | |
585 | pw = &(w->next); | |
586 | } | |
587 | ||
588 | if (!deleted_one) | |
589 | return -1; /* We don't know about it, fail doing nothing. */ | |
590 | ||
591 | /* At this point watch_readback is known to be valid because we | |
592 | could not have added the watch without reading it. */ | |
fe978cb0 | 593 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 594 | |
fe978cb0 PA |
595 | priv->watch_mirror = priv->watch_readback; |
596 | mips_linux_watch_populate_regs (priv->current_watches, | |
597 | &priv->watch_mirror); | |
7a60ad40 YQ |
598 | |
599 | /* Only update the threads of this process. */ | |
da25033c SM |
600 | for_each_thread (proc->pid, update_watch_registers_callback); |
601 | ||
7a60ad40 YQ |
602 | return 0; |
603 | } | |
604 | ||
605 | /* This is the implementation of linux_target_ops method | |
606 | stopped_by_watchpoint. The watchhi R and W bits indicate | |
607 | the watch register triggered. */ | |
608 | ||
609 | static int | |
610 | mips_stopped_by_watchpoint (void) | |
611 | { | |
612 | struct process_info *proc = current_process (); | |
fe978cb0 | 613 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
614 | int n; |
615 | int num_valid; | |
0bfdf32f | 616 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
617 | |
618 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
619 | &priv->watch_readback, |
620 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
621 | 1)) |
622 | return 0; | |
623 | ||
fe978cb0 | 624 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
625 | |
626 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 627 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
628 | & (R_MASK | W_MASK)) |
629 | return 1; | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
634 | /* This is the implementation of linux_target_ops method | |
635 | stopped_data_address. */ | |
636 | ||
637 | static CORE_ADDR | |
638 | mips_stopped_data_address (void) | |
639 | { | |
640 | struct process_info *proc = current_process (); | |
fe978cb0 | 641 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
642 | int n; |
643 | int num_valid; | |
0bfdf32f | 644 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
645 | |
646 | /* On MIPS we don't know the low order 3 bits of the data address. | |
647 | GDB does not support remote targets that can't report the | |
648 | watchpoint address. So, make our best guess; return the starting | |
649 | address of a watchpoint request which overlaps the one that | |
650 | triggered. */ | |
651 | ||
652 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
653 | &priv->watch_readback, |
654 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
655 | 0)) |
656 | return 0; | |
657 | ||
fe978cb0 | 658 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
659 | |
660 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 661 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
662 | & (R_MASK | W_MASK)) |
663 | { | |
664 | CORE_ADDR t_low, t_hi; | |
665 | int t_irw; | |
666 | struct mips_watchpoint *watch; | |
667 | ||
fe978cb0 | 668 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 669 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 670 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
671 | | IRW_MASK); |
672 | t_low &= ~(CORE_ADDR)t_hi; | |
673 | ||
fe978cb0 | 674 | for (watch = priv->current_watches; |
7a60ad40 YQ |
675 | watch != NULL; |
676 | watch = watch->next) | |
677 | { | |
678 | CORE_ADDR addr = watch->addr; | |
679 | CORE_ADDR last_byte = addr + watch->len - 1; | |
680 | ||
681 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
682 | { | |
683 | /* Different type. */ | |
684 | continue; | |
685 | } | |
686 | /* Check for overlap of even a single byte. */ | |
687 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
688 | return addr; | |
689 | } | |
690 | } | |
691 | ||
692 | /* Shouldn't happen. */ | |
693 | return 0; | |
694 | } | |
695 | ||
21b0f40c DJ |
696 | /* Fetch the thread-local storage pointer for libthread_db. */ |
697 | ||
698 | ps_err_e | |
754653a7 | 699 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 700 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
701 | { |
702 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
703 | return PS_ERR; | |
704 | ||
705 | /* IDX is the bias from the thread pointer to the beginning of the | |
706 | thread descriptor. It has to be subtracted due to implementation | |
707 | quirks in libthread_db. */ | |
708 | *base = (void *) ((char *)*base - idx); | |
709 | ||
710 | return PS_OK; | |
711 | } | |
712 | ||
186947f7 | 713 | static void |
442ea881 PA |
714 | mips_collect_register (struct regcache *regcache, |
715 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
716 | { |
717 | union mips_register tmp_reg; | |
718 | ||
719 | if (use_64bit) | |
720 | { | |
442ea881 | 721 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
722 | *reg = tmp_reg; |
723 | } | |
724 | else | |
725 | { | |
442ea881 | 726 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
727 | reg->reg64 = tmp_reg.reg32; |
728 | } | |
729 | } | |
730 | ||
731 | static void | |
442ea881 PA |
732 | mips_supply_register (struct regcache *regcache, |
733 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
734 | { |
735 | int offset = 0; | |
736 | ||
737 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
738 | eight-byte slot. */ | |
739 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
740 | offset = 4; | |
741 | ||
442ea881 | 742 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
743 | } |
744 | ||
7e947ad3 MR |
745 | #ifdef HAVE_PTRACE_GETREGS |
746 | ||
186947f7 | 747 | static void |
442ea881 PA |
748 | mips_collect_register_32bit (struct regcache *regcache, |
749 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
750 | { |
751 | union mips_register tmp_reg; | |
752 | int reg32; | |
753 | ||
442ea881 | 754 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
755 | reg32 = tmp_reg.reg64; |
756 | memcpy (buf, ®32, 4); | |
757 | } | |
758 | ||
759 | static void | |
442ea881 PA |
760 | mips_supply_register_32bit (struct regcache *regcache, |
761 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
762 | { |
763 | union mips_register tmp_reg; | |
764 | int reg32; | |
765 | ||
766 | memcpy (®32, buf, 4); | |
767 | tmp_reg.reg64 = reg32; | |
442ea881 | 768 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
769 | } |
770 | ||
771 | static void | |
442ea881 | 772 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 773 | { |
1996e237 | 774 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 775 | int i, use_64bit; |
3aee8918 | 776 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 777 | |
3aee8918 | 778 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 779 | |
117ce543 | 780 | for (i = 1; i < 32; i++) |
442ea881 PA |
781 | mips_collect_register (regcache, use_64bit, i, regset + i); |
782 | ||
783 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 784 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 785 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 786 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 787 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 788 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 789 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 790 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 791 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 792 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 793 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 794 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
795 | |
796 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 797 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
798 | } |
799 | ||
800 | static void | |
442ea881 | 801 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 802 | { |
1996e237 | 803 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
804 | int i, use_64bit; |
805 | ||
3aee8918 | 806 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 807 | |
e4439e43 MR |
808 | supply_register_by_name_zeroed (regcache, "r0"); |
809 | ||
810 | for (i = 1; i < 32; i++) | |
442ea881 PA |
811 | mips_supply_register (regcache, use_64bit, i, regset + i); |
812 | ||
442ea881 | 813 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
814 | find_regno (regcache->tdesc, "lo"), regset + 32); |
815 | mips_supply_register (regcache, use_64bit, | |
816 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 817 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 818 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 819 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
820 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
821 | mips_supply_register (regcache, use_64bit, | |
822 | find_regno (regcache->tdesc, "status"), regset + 36); | |
823 | mips_supply_register (regcache, use_64bit, | |
824 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
825 | |
826 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 827 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
828 | } |
829 | ||
830 | static void | |
442ea881 | 831 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 832 | { |
1996e237 | 833 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
834 | int i, use_64bit, first_fp, big_endian; |
835 | ||
3aee8918 PA |
836 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
837 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
838 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
839 | ||
840 | /* See GDB for a discussion of this peculiar layout. */ | |
841 | for (i = 0; i < 32; i++) | |
842 | if (use_64bit) | |
442ea881 | 843 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 844 | else |
442ea881 | 845 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
846 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
847 | ||
442ea881 | 848 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
849 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
850 | mips_collect_register_32bit (regcache, use_64bit, | |
851 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
852 | regset[32].buf + 4); |
853 | } | |
854 | ||
855 | static void | |
442ea881 | 856 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 857 | { |
1996e237 | 858 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
859 | int i, use_64bit, first_fp, big_endian; |
860 | ||
3aee8918 PA |
861 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
862 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
863 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
864 | ||
865 | /* See GDB for a discussion of this peculiar layout. */ | |
866 | for (i = 0; i < 32; i++) | |
867 | if (use_64bit) | |
442ea881 | 868 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 869 | else |
442ea881 | 870 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
871 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
872 | ||
442ea881 | 873 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
874 | find_regno (regcache->tdesc, "fcsr"), |
875 | regset[32].buf); | |
876 | mips_supply_register_32bit (regcache, use_64bit, | |
877 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
878 | regset[32].buf + 4); |
879 | } | |
880 | #endif /* HAVE_PTRACE_GETREGS */ | |
881 | ||
7e947ad3 MR |
882 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
883 | ||
884 | static void | |
885 | mips_collect_ptrace_register (struct regcache *regcache, | |
886 | int regno, char *buf) | |
887 | { | |
7e947ad3 MR |
888 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
889 | ||
890 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
891 | { | |
892 | union mips_register reg; | |
893 | ||
894 | mips_collect_register (regcache, 0, regno, ®); | |
895 | memcpy (buf, ®, sizeof (reg)); | |
896 | } | |
897 | else | |
898 | collect_register (regcache, regno, buf); | |
899 | } | |
900 | ||
901 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
902 | ||
903 | static void | |
904 | mips_supply_ptrace_register (struct regcache *regcache, | |
905 | int regno, const char *buf) | |
906 | { | |
7e947ad3 MR |
907 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
908 | ||
909 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
910 | { | |
911 | union mips_register reg; | |
912 | ||
913 | memcpy (®, buf, sizeof (reg)); | |
914 | mips_supply_register (regcache, 0, regno, ®); | |
915 | } | |
916 | else | |
917 | supply_register (regcache, regno, buf); | |
918 | } | |
919 | ||
3aee8918 | 920 | static struct regset_info mips_regsets[] = { |
186947f7 | 921 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 922 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 923 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 924 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
925 | mips_fill_fpregset, mips_store_fpregset }, |
926 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 927 | NULL_REGSET |
186947f7 DJ |
928 | }; |
929 | ||
3aee8918 PA |
930 | static struct regsets_info mips_regsets_info = |
931 | { | |
932 | mips_regsets, /* regsets */ | |
933 | 0, /* num_regsets */ | |
934 | NULL, /* disabled_regsets */ | |
935 | }; | |
936 | ||
937 | static struct usrregs_info mips_dsp_usrregs_info = | |
938 | { | |
939 | mips_dsp_num_regs, | |
940 | mips_dsp_regmap, | |
941 | }; | |
942 | ||
943 | static struct usrregs_info mips_usrregs_info = | |
944 | { | |
945 | mips_num_regs, | |
946 | mips_regmap, | |
947 | }; | |
948 | ||
949 | static struct regs_info dsp_regs_info = | |
950 | { | |
951 | mips_dsp_regset_bitmap, | |
952 | &mips_dsp_usrregs_info, | |
953 | &mips_regsets_info | |
954 | }; | |
955 | ||
aa8d21c9 | 956 | static struct regs_info myregs_info = |
3aee8918 PA |
957 | { |
958 | NULL, /* regset_bitmap */ | |
959 | &mips_usrregs_info, | |
960 | &mips_regsets_info | |
961 | }; | |
962 | ||
aa8d21c9 TBA |
963 | const regs_info * |
964 | mips_target::get_regs_info () | |
3aee8918 PA |
965 | { |
966 | if (have_dsp) | |
967 | return &dsp_regs_info; | |
968 | else | |
aa8d21c9 | 969 | return &myregs_info; |
3aee8918 PA |
970 | } |
971 | ||
2ec06d2e | 972 | struct linux_target_ops the_low_target = { |
7a60ad40 YQ |
973 | mips_insert_point, |
974 | mips_remove_point, | |
975 | mips_stopped_by_watchpoint, | |
976 | mips_stopped_data_address, | |
7e947ad3 MR |
977 | mips_collect_ptrace_register, |
978 | mips_supply_ptrace_register, | |
7a60ad40 YQ |
979 | NULL, /* siginfo_fixup */ |
980 | mips_linux_new_process, | |
04ec7890 | 981 | mips_linux_delete_process, |
7a60ad40 | 982 | mips_linux_new_thread, |
466eecee | 983 | mips_linux_delete_thread, |
3a8a0396 | 984 | mips_linux_new_fork, |
7a60ad40 | 985 | mips_linux_prepare_to_resume |
2ec06d2e | 986 | }; |
3aee8918 | 987 | |
ef0478f6 TBA |
988 | /* The linux target ops object. */ |
989 | ||
990 | linux_process_target *the_linux_target = &the_mips_target; | |
991 | ||
3aee8918 PA |
992 | void |
993 | initialize_low_arch (void) | |
994 | { | |
995 | /* Initialize the Linux target descriptions. */ | |
996 | init_registers_mips_linux (); | |
997 | init_registers_mips_dsp_linux (); | |
998 | init_registers_mips64_linux (); | |
999 | init_registers_mips64_dsp_linux (); | |
1000 | ||
1001 | initialize_regsets_info (&mips_regsets_info); | |
1002 | } |