Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
007c9b97 TBA |
38 | bool supports_z_point_type (char z_type) override; |
39 | ||
797bcff5 TBA |
40 | protected: |
41 | ||
42 | void low_arch_setup () override; | |
daca57a7 TBA |
43 | |
44 | bool low_cannot_fetch_register (int regno) override; | |
45 | ||
46 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
47 | |
48 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
49 | |
50 | bool low_supports_breakpoints () override; | |
51 | ||
52 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
53 | ||
54 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
55 | |
56 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
57 | |
58 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
59 | int size, raw_breakpoint *bp) override; | |
60 | ||
61 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
62 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
63 | |
64 | bool low_stopped_by_watchpoint () override; | |
65 | ||
66 | CORE_ADDR low_stopped_data_address () override; | |
b35db733 TBA |
67 | |
68 | void low_collect_ptrace_register (regcache *regcache, int regno, | |
69 | char *buf) override; | |
70 | ||
71 | void low_supply_ptrace_register (regcache *regcache, int regno, | |
72 | const char *buf) override; | |
fd000fb3 TBA |
73 | |
74 | arch_process_info *low_new_process () override; | |
75 | ||
76 | void low_delete_process (arch_process_info *info) override; | |
77 | ||
78 | void low_new_thread (lwp_info *) override; | |
79 | ||
80 | void low_delete_thread (arch_lwp_info *) override; | |
81 | ||
82 | void low_new_fork (process_info *parent, process_info *child) override; | |
ef0478f6 TBA |
83 | }; |
84 | ||
85 | /* The singleton target ops object. */ | |
86 | ||
87 | static mips_target the_mips_target; | |
88 | ||
d05b4ac3 UW |
89 | /* Defined in auto-generated file mips-linux.c. */ |
90 | void init_registers_mips_linux (void); | |
3aee8918 PA |
91 | extern const struct target_desc *tdesc_mips_linux; |
92 | ||
1faeff08 MR |
93 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
94 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
95 | extern const struct target_desc *tdesc_mips_dsp_linux; |
96 | ||
d05b4ac3 UW |
97 | /* Defined in auto-generated file mips64-linux.c. */ |
98 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
99 | extern const struct target_desc *tdesc_mips64_linux; |
100 | ||
1faeff08 MR |
101 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
102 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 103 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
104 | |
105 | #ifdef __mips64 | |
3aee8918 PA |
106 | #define tdesc_mips_linux tdesc_mips64_linux |
107 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 108 | #endif |
d05b4ac3 | 109 | |
21b0f40c DJ |
110 | #ifndef PTRACE_GET_THREAD_AREA |
111 | #define PTRACE_GET_THREAD_AREA 25 | |
112 | #endif | |
113 | ||
0a30fbc4 DJ |
114 | #ifdef HAVE_SYS_REG_H |
115 | #include <sys/reg.h> | |
116 | #endif | |
117 | ||
117ce543 | 118 | #define mips_num_regs 73 |
1faeff08 | 119 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
120 | |
121 | #include <asm/ptrace.h> | |
122 | ||
1faeff08 MR |
123 | #ifndef DSP_BASE |
124 | #define DSP_BASE 71 | |
125 | #define DSP_CONTROL 77 | |
126 | #endif | |
127 | ||
186947f7 DJ |
128 | union mips_register |
129 | { | |
130 | unsigned char buf[8]; | |
131 | ||
132 | /* Deliberately signed, for proper sign extension. */ | |
133 | int reg32; | |
134 | long long reg64; | |
135 | }; | |
136 | ||
0a30fbc4 DJ |
137 | /* Return the ptrace ``address'' of register REGNO. */ |
138 | ||
1faeff08 MR |
139 | #define mips_base_regs \ |
140 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
141 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
142 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
143 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
144 | \ | |
145 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
146 | \ | |
147 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
148 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
149 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
150 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
151 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
152 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
153 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
154 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
155 | FPC_CSR, FPC_EIR | |
156 | ||
157 | #define mips_dsp_regs \ | |
158 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
159 | DSP_BASE + 4, DSP_BASE + 5, \ | |
160 | DSP_CONTROL | |
161 | ||
162 | static int mips_regmap[mips_num_regs] = { | |
163 | mips_base_regs, | |
164 | 0 | |
165 | }; | |
0a30fbc4 | 166 | |
1faeff08 MR |
167 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
168 | mips_base_regs, | |
169 | mips_dsp_regs, | |
170 | 0 | |
171 | }; | |
0a30fbc4 | 172 | |
1faeff08 MR |
173 | /* DSP registers are not in any regset and can only be accessed |
174 | individually. */ | |
0a30fbc4 | 175 | |
1faeff08 MR |
176 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
177 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
178 | }; |
179 | ||
3aee8918 PA |
180 | static int have_dsp = -1; |
181 | ||
1faeff08 MR |
182 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
183 | user register set accordingly. */ | |
184 | ||
3aee8918 PA |
185 | static const struct target_desc * |
186 | mips_read_description (void) | |
1faeff08 | 187 | { |
3aee8918 | 188 | if (have_dsp < 0) |
1faeff08 | 189 | { |
0bfdf32f | 190 | int pid = lwpid_of (current_thread); |
1faeff08 | 191 | |
ac740bc7 | 192 | errno = 0; |
1faeff08 MR |
193 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
194 | switch (errno) | |
195 | { | |
196 | case 0: | |
3aee8918 | 197 | have_dsp = 1; |
1faeff08 MR |
198 | break; |
199 | case EIO: | |
3aee8918 | 200 | have_dsp = 0; |
1faeff08 MR |
201 | break; |
202 | default: | |
203 | perror_with_name ("ptrace"); | |
204 | break; | |
205 | } | |
206 | } | |
3aee8918 PA |
207 | |
208 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
209 | } | |
210 | ||
797bcff5 TBA |
211 | void |
212 | mips_target::low_arch_setup () | |
3aee8918 PA |
213 | { |
214 | current_process ()->tdesc = mips_read_description (); | |
215 | } | |
216 | ||
7a60ad40 YQ |
217 | /* Per-process arch-specific data we want to keep. */ |
218 | ||
219 | struct arch_process_info | |
220 | { | |
221 | /* -1 if the kernel and/or CPU do not support watch registers. | |
222 | 1 if watch_readback is valid and we can read style, num_valid | |
223 | and the masks. | |
224 | 0 if we need to read the watch_readback. */ | |
225 | ||
226 | int watch_readback_valid; | |
227 | ||
228 | /* Cached watch register read values. */ | |
229 | ||
230 | struct pt_watch_regs watch_readback; | |
231 | ||
232 | /* Current watchpoint requests for this process. */ | |
233 | ||
234 | struct mips_watchpoint *current_watches; | |
235 | ||
236 | /* The current set of watch register values for writing the | |
237 | registers. */ | |
238 | ||
239 | struct pt_watch_regs watch_mirror; | |
240 | }; | |
241 | ||
242 | /* Per-thread arch-specific data we want to keep. */ | |
243 | ||
244 | struct arch_lwp_info | |
245 | { | |
246 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
247 | int watch_registers_changed; | |
248 | }; | |
249 | ||
0a30fbc4 DJ |
250 | /* From mips-linux-nat.c. */ |
251 | ||
252 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
253 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
254 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
255 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 256 | |
daca57a7 TBA |
257 | bool |
258 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 259 | { |
3aee8918 PA |
260 | const struct target_desc *tdesc; |
261 | ||
daca57a7 TBA |
262 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
263 | return true; | |
0a30fbc4 | 264 | |
3aee8918 PA |
265 | tdesc = current_process ()->tdesc; |
266 | ||
75d74cca MR |
267 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
268 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 269 | return true; |
75d74cca | 270 | |
3aee8918 | 271 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 272 | return true; |
0a30fbc4 | 273 | |
daca57a7 | 274 | return false; |
0a30fbc4 DJ |
275 | } |
276 | ||
daca57a7 TBA |
277 | bool |
278 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 279 | { |
3aee8918 PA |
280 | const struct target_desc *tdesc; |
281 | ||
daca57a7 TBA |
282 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
283 | return true; | |
0a30fbc4 | 284 | |
3aee8918 PA |
285 | tdesc = current_process ()->tdesc; |
286 | ||
75d74cca MR |
287 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
288 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 289 | return true; |
75d74cca | 290 | |
3aee8918 | 291 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 292 | return true; |
0a30fbc4 | 293 | |
3aee8918 | 294 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 295 | return true; |
0a30fbc4 | 296 | |
3aee8918 | 297 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 298 | return true; |
0a30fbc4 | 299 | |
3aee8918 | 300 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 301 | return true; |
0a30fbc4 | 302 | |
daca57a7 | 303 | return false; |
0a30fbc4 | 304 | } |
2ec06d2e | 305 | |
bd70b1f2 TBA |
306 | bool |
307 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
308 | { |
309 | const struct target_desc *tdesc = current_process ()->tdesc; | |
310 | ||
311 | if (find_regno (tdesc, "r0") == regno) | |
312 | { | |
313 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 314 | return true; |
e4439e43 MR |
315 | } |
316 | ||
bd70b1f2 | 317 | return false; |
e4439e43 MR |
318 | } |
319 | ||
bf9ae9d8 TBA |
320 | bool |
321 | mips_target::low_supports_breakpoints () | |
322 | { | |
323 | return true; | |
324 | } | |
325 | ||
326 | CORE_ADDR | |
327 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 328 | { |
186947f7 | 329 | union mips_register pc; |
442ea881 | 330 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 331 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
332 | } |
333 | ||
bf9ae9d8 TBA |
334 | void |
335 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 336 | { |
186947f7 | 337 | union mips_register newpc; |
3aee8918 | 338 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
339 | newpc.reg32 = pc; |
340 | else | |
341 | newpc.reg64 = pc; | |
342 | ||
442ea881 | 343 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
344 | } |
345 | ||
346 | /* Correct in either endianness. */ | |
186947f7 | 347 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
348 | #define mips_breakpoint_len 4 |
349 | ||
3ca4edb6 | 350 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 351 | |
3ca4edb6 TBA |
352 | const gdb_byte * |
353 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
354 | { |
355 | *size = mips_breakpoint_len; | |
356 | return (const gdb_byte *) &mips_breakpoint; | |
357 | } | |
358 | ||
d7146cda TBA |
359 | bool |
360 | mips_target::low_breakpoint_at (CORE_ADDR where) | |
0d62e5e8 | 361 | { |
186947f7 | 362 | unsigned int insn; |
0d62e5e8 | 363 | |
d7146cda | 364 | read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 | 365 | if (insn == mips_breakpoint) |
d7146cda | 366 | return true; |
0d62e5e8 DJ |
367 | |
368 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
369 | one. */ | |
d7146cda | 370 | return false; |
0d62e5e8 DJ |
371 | } |
372 | ||
da25033c | 373 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 374 | |
da25033c SM |
375 | static void |
376 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 377 | { |
d86d4aaf | 378 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 379 | |
da25033c SM |
380 | /* The actual update is done later just before resuming the lwp, |
381 | we just mark that the registers need updating. */ | |
382 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 383 | |
da25033c SM |
384 | /* If the lwp isn't stopped, force it to momentarily pause, so |
385 | we can update its watch registers. */ | |
386 | if (!lwp->stopped) | |
387 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
388 | } |
389 | ||
fd000fb3 TBA |
390 | /* This is the implementation of linux target ops method |
391 | low_new_process. */ | |
7a60ad40 | 392 | |
fd000fb3 TBA |
393 | arch_process_info * |
394 | mips_target::low_new_process () | |
7a60ad40 | 395 | { |
8d749320 | 396 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
397 | |
398 | return info; | |
399 | } | |
400 | ||
fd000fb3 TBA |
401 | /* This is the implementation of linux target ops method |
402 | low_delete_process. */ | |
04ec7890 | 403 | |
fd000fb3 TBA |
404 | void |
405 | mips_target::low_delete_process (arch_process_info *info) | |
04ec7890 SM |
406 | { |
407 | xfree (info); | |
408 | } | |
409 | ||
fd000fb3 | 410 | /* This is the implementation of linux target ops method low_new_thread. |
7a60ad40 YQ |
411 | Mark the watch registers as changed, so the threads' copies will |
412 | be updated. */ | |
413 | ||
fd000fb3 TBA |
414 | void |
415 | mips_target::low_new_thread (lwp_info *lwp) | |
7a60ad40 | 416 | { |
8d749320 | 417 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
418 | |
419 | info->watch_registers_changed = 1; | |
420 | ||
34c703da | 421 | lwp->arch_private = info; |
7a60ad40 YQ |
422 | } |
423 | ||
466eecee SM |
424 | /* Function to call when a thread is being deleted. */ |
425 | ||
fd000fb3 TBA |
426 | void |
427 | mips_target::low_delete_thread (arch_lwp_info *arch_lwp) | |
466eecee SM |
428 | { |
429 | xfree (arch_lwp); | |
430 | } | |
431 | ||
3a8a0396 DB |
432 | /* Create a new mips_watchpoint and add it to the list. */ |
433 | ||
434 | static void | |
cbec665b | 435 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 436 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
437 | { |
438 | struct mips_watchpoint *new_watch; | |
439 | struct mips_watchpoint **pw; | |
440 | ||
8d749320 | 441 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
442 | new_watch->addr = addr; |
443 | new_watch->len = len; | |
444 | new_watch->type = watch_type; | |
445 | new_watch->next = NULL; | |
446 | ||
cbec665b | 447 | pw = &priv->current_watches; |
3a8a0396 DB |
448 | while (*pw != NULL) |
449 | pw = &(*pw)->next; | |
450 | *pw = new_watch; | |
451 | } | |
452 | ||
453 | /* Hook to call when a new fork is attached. */ | |
454 | ||
fd000fb3 TBA |
455 | void |
456 | mips_target::low_new_fork (process_info *parent, | |
457 | process_info *child) | |
3a8a0396 DB |
458 | { |
459 | struct arch_process_info *parent_private; | |
460 | struct arch_process_info *child_private; | |
461 | struct mips_watchpoint *wp; | |
462 | ||
463 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
464 | gdb_assert (parent->priv != NULL |
465 | && parent->priv->arch_private != NULL); | |
466 | gdb_assert (child->priv != NULL | |
467 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
468 | |
469 | /* Linux kernel before 2.6.33 commit | |
470 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
471 | will inherit hardware debug registers from parent | |
472 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
473 | zeroed debug registers. | |
474 | ||
475 | GDB core assumes the child inherits the watchpoints/hw | |
476 | breakpoints of the parent, and will remove them all from the | |
477 | forked off process. Copy the debug registers mirrors into the | |
478 | new process so that all breakpoints and watchpoints can be | |
479 | removed together. The debug registers mirror will become zeroed | |
480 | in the end before detaching the forked off process, thus making | |
481 | this compatible with older Linux kernels too. */ | |
482 | ||
61a7418c DB |
483 | parent_private = parent->priv->arch_private; |
484 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
485 | |
486 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
487 | child_private->watch_readback = parent_private->watch_readback; | |
488 | ||
489 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
490 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
491 | ||
492 | child_private->watch_mirror = parent_private->watch_mirror; | |
493 | } | |
7a60ad40 YQ |
494 | /* This is the implementation of linux_target_ops method |
495 | prepare_to_resume. If the watch regs have changed, update the | |
496 | thread's copies. */ | |
497 | ||
498 | static void | |
499 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
500 | { | |
d86d4aaf | 501 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 502 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 503 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
504 | |
505 | if (lwp->arch_private->watch_registers_changed) | |
506 | { | |
507 | /* Only update the watch registers if we have set or unset a | |
508 | watchpoint already. */ | |
fe978cb0 | 509 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
510 | { |
511 | /* Write the mirrored watch register values. */ | |
e38504b3 | 512 | int tid = ptid.lwp (); |
7a60ad40 YQ |
513 | |
514 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 515 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
516 | perror_with_name ("Couldn't write watch register"); |
517 | } | |
518 | ||
519 | lwp->arch_private->watch_registers_changed = 0; | |
520 | } | |
521 | } | |
522 | ||
007c9b97 TBA |
523 | bool |
524 | mips_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
525 | { |
526 | switch (z_type) | |
527 | { | |
528 | case Z_PACKET_WRITE_WP: | |
529 | case Z_PACKET_READ_WP: | |
530 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 531 | return true; |
802e8e6d | 532 | default: |
007c9b97 | 533 | return false; |
802e8e6d PA |
534 | } |
535 | } | |
536 | ||
9db9aa23 TBA |
537 | /* This is the implementation of linux target ops method |
538 | low_insert_point. */ | |
7a60ad40 | 539 | |
9db9aa23 TBA |
540 | int |
541 | mips_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
542 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
543 | { |
544 | struct process_info *proc = current_process (); | |
fe978cb0 | 545 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 546 | struct pt_watch_regs regs; |
7a60ad40 YQ |
547 | long lwpid; |
548 | enum target_hw_bp_type watch_type; | |
549 | uint32_t irw; | |
550 | ||
0bfdf32f | 551 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 552 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
553 | &priv->watch_readback, |
554 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
555 | 0)) |
556 | return -1; | |
557 | ||
558 | if (len <= 0) | |
559 | return -1; | |
560 | ||
fe978cb0 | 561 | regs = priv->watch_readback; |
7a60ad40 | 562 | /* Add the current watches. */ |
fe978cb0 | 563 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
564 | |
565 | /* Now try to add the new watch. */ | |
802e8e6d | 566 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
567 | irw = mips_linux_watch_type_to_irw (watch_type); |
568 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
569 | return -1; | |
570 | ||
571 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 572 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 573 | |
fe978cb0 | 574 | priv->watch_mirror = regs; |
7a60ad40 YQ |
575 | |
576 | /* Only update the threads of this process. */ | |
da25033c | 577 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
578 | |
579 | return 0; | |
580 | } | |
581 | ||
9db9aa23 TBA |
582 | /* This is the implementation of linux target ops method |
583 | low_remove_point. */ | |
7a60ad40 | 584 | |
9db9aa23 TBA |
585 | int |
586 | mips_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
587 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
588 | { |
589 | struct process_info *proc = current_process (); | |
fe978cb0 | 590 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
591 | |
592 | int deleted_one; | |
7a60ad40 YQ |
593 | enum target_hw_bp_type watch_type; |
594 | ||
595 | struct mips_watchpoint **pw; | |
596 | struct mips_watchpoint *w; | |
597 | ||
7a60ad40 | 598 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 599 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 600 | deleted_one = 0; |
fe978cb0 | 601 | pw = &priv->current_watches; |
7a60ad40 YQ |
602 | while ((w = *pw)) |
603 | { | |
604 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
605 | { | |
606 | *pw = w->next; | |
607 | free (w); | |
608 | deleted_one = 1; | |
609 | break; | |
610 | } | |
611 | pw = &(w->next); | |
612 | } | |
613 | ||
614 | if (!deleted_one) | |
615 | return -1; /* We don't know about it, fail doing nothing. */ | |
616 | ||
617 | /* At this point watch_readback is known to be valid because we | |
618 | could not have added the watch without reading it. */ | |
fe978cb0 | 619 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 620 | |
fe978cb0 PA |
621 | priv->watch_mirror = priv->watch_readback; |
622 | mips_linux_watch_populate_regs (priv->current_watches, | |
623 | &priv->watch_mirror); | |
7a60ad40 YQ |
624 | |
625 | /* Only update the threads of this process. */ | |
da25033c SM |
626 | for_each_thread (proc->pid, update_watch_registers_callback); |
627 | ||
7a60ad40 YQ |
628 | return 0; |
629 | } | |
630 | ||
ac1bbaca TBA |
631 | /* This is the implementation of linux target ops method |
632 | low_stopped_by_watchpoint. The watchhi R and W bits indicate | |
7a60ad40 YQ |
633 | the watch register triggered. */ |
634 | ||
ac1bbaca TBA |
635 | bool |
636 | mips_target::low_stopped_by_watchpoint () | |
7a60ad40 YQ |
637 | { |
638 | struct process_info *proc = current_process (); | |
fe978cb0 | 639 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
640 | int n; |
641 | int num_valid; | |
0bfdf32f | 642 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
643 | |
644 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
645 | &priv->watch_readback, |
646 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
647 | 1)) |
648 | return 0; | |
649 | ||
fe978cb0 | 650 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
651 | |
652 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 653 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 | 654 | & (R_MASK | W_MASK)) |
ac1bbaca | 655 | return true; |
7a60ad40 | 656 | |
ac1bbaca | 657 | return false; |
7a60ad40 YQ |
658 | } |
659 | ||
ac1bbaca TBA |
660 | /* This is the implementation of linux target ops method |
661 | low_stopped_data_address. */ | |
7a60ad40 | 662 | |
ac1bbaca TBA |
663 | CORE_ADDR |
664 | mips_target::low_stopped_data_address () | |
7a60ad40 YQ |
665 | { |
666 | struct process_info *proc = current_process (); | |
fe978cb0 | 667 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
668 | int n; |
669 | int num_valid; | |
0bfdf32f | 670 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
671 | |
672 | /* On MIPS we don't know the low order 3 bits of the data address. | |
673 | GDB does not support remote targets that can't report the | |
674 | watchpoint address. So, make our best guess; return the starting | |
675 | address of a watchpoint request which overlaps the one that | |
676 | triggered. */ | |
677 | ||
678 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
679 | &priv->watch_readback, |
680 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
681 | 0)) |
682 | return 0; | |
683 | ||
fe978cb0 | 684 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
685 | |
686 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 687 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
688 | & (R_MASK | W_MASK)) |
689 | { | |
690 | CORE_ADDR t_low, t_hi; | |
691 | int t_irw; | |
692 | struct mips_watchpoint *watch; | |
693 | ||
fe978cb0 | 694 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 695 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 696 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
697 | | IRW_MASK); |
698 | t_low &= ~(CORE_ADDR)t_hi; | |
699 | ||
fe978cb0 | 700 | for (watch = priv->current_watches; |
7a60ad40 YQ |
701 | watch != NULL; |
702 | watch = watch->next) | |
703 | { | |
704 | CORE_ADDR addr = watch->addr; | |
705 | CORE_ADDR last_byte = addr + watch->len - 1; | |
706 | ||
707 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
708 | { | |
709 | /* Different type. */ | |
710 | continue; | |
711 | } | |
712 | /* Check for overlap of even a single byte. */ | |
713 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
714 | return addr; | |
715 | } | |
716 | } | |
717 | ||
718 | /* Shouldn't happen. */ | |
719 | return 0; | |
720 | } | |
721 | ||
21b0f40c DJ |
722 | /* Fetch the thread-local storage pointer for libthread_db. */ |
723 | ||
724 | ps_err_e | |
754653a7 | 725 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 726 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
727 | { |
728 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
729 | return PS_ERR; | |
730 | ||
731 | /* IDX is the bias from the thread pointer to the beginning of the | |
732 | thread descriptor. It has to be subtracted due to implementation | |
733 | quirks in libthread_db. */ | |
734 | *base = (void *) ((char *)*base - idx); | |
735 | ||
736 | return PS_OK; | |
737 | } | |
738 | ||
186947f7 | 739 | static void |
442ea881 PA |
740 | mips_collect_register (struct regcache *regcache, |
741 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
742 | { |
743 | union mips_register tmp_reg; | |
744 | ||
745 | if (use_64bit) | |
746 | { | |
442ea881 | 747 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
748 | *reg = tmp_reg; |
749 | } | |
750 | else | |
751 | { | |
442ea881 | 752 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
753 | reg->reg64 = tmp_reg.reg32; |
754 | } | |
755 | } | |
756 | ||
757 | static void | |
442ea881 PA |
758 | mips_supply_register (struct regcache *regcache, |
759 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
760 | { |
761 | int offset = 0; | |
762 | ||
763 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
764 | eight-byte slot. */ | |
765 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
766 | offset = 4; | |
767 | ||
442ea881 | 768 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
769 | } |
770 | ||
7e947ad3 MR |
771 | #ifdef HAVE_PTRACE_GETREGS |
772 | ||
186947f7 | 773 | static void |
442ea881 PA |
774 | mips_collect_register_32bit (struct regcache *regcache, |
775 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
776 | { |
777 | union mips_register tmp_reg; | |
778 | int reg32; | |
779 | ||
442ea881 | 780 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
781 | reg32 = tmp_reg.reg64; |
782 | memcpy (buf, ®32, 4); | |
783 | } | |
784 | ||
785 | static void | |
442ea881 PA |
786 | mips_supply_register_32bit (struct regcache *regcache, |
787 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
788 | { |
789 | union mips_register tmp_reg; | |
790 | int reg32; | |
791 | ||
792 | memcpy (®32, buf, 4); | |
793 | tmp_reg.reg64 = reg32; | |
442ea881 | 794 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
795 | } |
796 | ||
797 | static void | |
442ea881 | 798 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 799 | { |
1996e237 | 800 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 801 | int i, use_64bit; |
3aee8918 | 802 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 803 | |
3aee8918 | 804 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 805 | |
117ce543 | 806 | for (i = 1; i < 32; i++) |
442ea881 PA |
807 | mips_collect_register (regcache, use_64bit, i, regset + i); |
808 | ||
809 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 810 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 811 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 812 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 813 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 814 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 815 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 816 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 817 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 818 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 819 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 820 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
821 | |
822 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 823 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
824 | } |
825 | ||
826 | static void | |
442ea881 | 827 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 828 | { |
1996e237 | 829 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
830 | int i, use_64bit; |
831 | ||
3aee8918 | 832 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 833 | |
e4439e43 MR |
834 | supply_register_by_name_zeroed (regcache, "r0"); |
835 | ||
836 | for (i = 1; i < 32; i++) | |
442ea881 PA |
837 | mips_supply_register (regcache, use_64bit, i, regset + i); |
838 | ||
442ea881 | 839 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
840 | find_regno (regcache->tdesc, "lo"), regset + 32); |
841 | mips_supply_register (regcache, use_64bit, | |
842 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 843 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 844 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 845 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
846 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
847 | mips_supply_register (regcache, use_64bit, | |
848 | find_regno (regcache->tdesc, "status"), regset + 36); | |
849 | mips_supply_register (regcache, use_64bit, | |
850 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
851 | |
852 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 853 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
854 | } |
855 | ||
856 | static void | |
442ea881 | 857 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 858 | { |
1996e237 | 859 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
860 | int i, use_64bit, first_fp, big_endian; |
861 | ||
3aee8918 PA |
862 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
863 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
864 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
865 | ||
866 | /* See GDB for a discussion of this peculiar layout. */ | |
867 | for (i = 0; i < 32; i++) | |
868 | if (use_64bit) | |
442ea881 | 869 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 870 | else |
442ea881 | 871 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
872 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
873 | ||
442ea881 | 874 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
875 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
876 | mips_collect_register_32bit (regcache, use_64bit, | |
877 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
878 | regset[32].buf + 4); |
879 | } | |
880 | ||
881 | static void | |
442ea881 | 882 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 883 | { |
1996e237 | 884 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
885 | int i, use_64bit, first_fp, big_endian; |
886 | ||
3aee8918 PA |
887 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
888 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
889 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
890 | ||
891 | /* See GDB for a discussion of this peculiar layout. */ | |
892 | for (i = 0; i < 32; i++) | |
893 | if (use_64bit) | |
442ea881 | 894 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 895 | else |
442ea881 | 896 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
897 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
898 | ||
442ea881 | 899 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
900 | find_regno (regcache->tdesc, "fcsr"), |
901 | regset[32].buf); | |
902 | mips_supply_register_32bit (regcache, use_64bit, | |
903 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
904 | regset[32].buf + 4); |
905 | } | |
906 | #endif /* HAVE_PTRACE_GETREGS */ | |
907 | ||
7e947ad3 MR |
908 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
909 | ||
b35db733 TBA |
910 | void |
911 | mips_target::low_collect_ptrace_register (regcache *regcache, int regno, | |
912 | char *buf) | |
7e947ad3 | 913 | { |
7e947ad3 MR |
914 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
915 | ||
916 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
917 | { | |
918 | union mips_register reg; | |
919 | ||
920 | mips_collect_register (regcache, 0, regno, ®); | |
921 | memcpy (buf, ®, sizeof (reg)); | |
922 | } | |
923 | else | |
924 | collect_register (regcache, regno, buf); | |
925 | } | |
926 | ||
927 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
928 | ||
b35db733 TBA |
929 | void |
930 | mips_target::low_supply_ptrace_register (regcache *regcache, int regno, | |
931 | const char *buf) | |
7e947ad3 | 932 | { |
7e947ad3 MR |
933 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
934 | ||
935 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
936 | { | |
937 | union mips_register reg; | |
938 | ||
939 | memcpy (®, buf, sizeof (reg)); | |
940 | mips_supply_register (regcache, 0, regno, ®); | |
941 | } | |
942 | else | |
943 | supply_register (regcache, regno, buf); | |
944 | } | |
945 | ||
3aee8918 | 946 | static struct regset_info mips_regsets[] = { |
186947f7 | 947 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 948 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 949 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 950 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
951 | mips_fill_fpregset, mips_store_fpregset }, |
952 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 953 | NULL_REGSET |
186947f7 DJ |
954 | }; |
955 | ||
3aee8918 PA |
956 | static struct regsets_info mips_regsets_info = |
957 | { | |
958 | mips_regsets, /* regsets */ | |
959 | 0, /* num_regsets */ | |
960 | NULL, /* disabled_regsets */ | |
961 | }; | |
962 | ||
963 | static struct usrregs_info mips_dsp_usrregs_info = | |
964 | { | |
965 | mips_dsp_num_regs, | |
966 | mips_dsp_regmap, | |
967 | }; | |
968 | ||
969 | static struct usrregs_info mips_usrregs_info = | |
970 | { | |
971 | mips_num_regs, | |
972 | mips_regmap, | |
973 | }; | |
974 | ||
975 | static struct regs_info dsp_regs_info = | |
976 | { | |
977 | mips_dsp_regset_bitmap, | |
978 | &mips_dsp_usrregs_info, | |
979 | &mips_regsets_info | |
980 | }; | |
981 | ||
aa8d21c9 | 982 | static struct regs_info myregs_info = |
3aee8918 PA |
983 | { |
984 | NULL, /* regset_bitmap */ | |
985 | &mips_usrregs_info, | |
986 | &mips_regsets_info | |
987 | }; | |
988 | ||
aa8d21c9 TBA |
989 | const regs_info * |
990 | mips_target::get_regs_info () | |
3aee8918 PA |
991 | { |
992 | if (have_dsp) | |
993 | return &dsp_regs_info; | |
994 | else | |
aa8d21c9 | 995 | return &myregs_info; |
3aee8918 PA |
996 | } |
997 | ||
2ec06d2e | 998 | struct linux_target_ops the_low_target = { |
7a60ad40 | 999 | mips_linux_prepare_to_resume |
2ec06d2e | 1000 | }; |
3aee8918 | 1001 | |
ef0478f6 TBA |
1002 | /* The linux target ops object. */ |
1003 | ||
1004 | linux_process_target *the_linux_target = &the_mips_target; | |
1005 | ||
3aee8918 PA |
1006 | void |
1007 | initialize_low_arch (void) | |
1008 | { | |
1009 | /* Initialize the Linux target descriptions. */ | |
1010 | init_registers_mips_linux (); | |
1011 | init_registers_mips_dsp_linux (); | |
1012 | init_registers_mips64_linux (); | |
1013 | init_registers_mips64_dsp_linux (); | |
1014 | ||
1015 | initialize_regsets_info (&mips_regsets_info); | |
1016 | } |