Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
007c9b97 TBA |
38 | bool supports_z_point_type (char z_type) override; |
39 | ||
797bcff5 TBA |
40 | protected: |
41 | ||
42 | void low_arch_setup () override; | |
daca57a7 TBA |
43 | |
44 | bool low_cannot_fetch_register (int regno) override; | |
45 | ||
46 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
47 | |
48 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
49 | |
50 | bool low_supports_breakpoints () override; | |
51 | ||
52 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
53 | ||
54 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
55 | |
56 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
57 | |
58 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
59 | int size, raw_breakpoint *bp) override; | |
60 | ||
61 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
62 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
63 | |
64 | bool low_stopped_by_watchpoint () override; | |
65 | ||
66 | CORE_ADDR low_stopped_data_address () override; | |
b35db733 TBA |
67 | |
68 | void low_collect_ptrace_register (regcache *regcache, int regno, | |
69 | char *buf) override; | |
70 | ||
71 | void low_supply_ptrace_register (regcache *regcache, int regno, | |
72 | const char *buf) override; | |
ef0478f6 TBA |
73 | }; |
74 | ||
75 | /* The singleton target ops object. */ | |
76 | ||
77 | static mips_target the_mips_target; | |
78 | ||
d05b4ac3 UW |
79 | /* Defined in auto-generated file mips-linux.c. */ |
80 | void init_registers_mips_linux (void); | |
3aee8918 PA |
81 | extern const struct target_desc *tdesc_mips_linux; |
82 | ||
1faeff08 MR |
83 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
84 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
85 | extern const struct target_desc *tdesc_mips_dsp_linux; |
86 | ||
d05b4ac3 UW |
87 | /* Defined in auto-generated file mips64-linux.c. */ |
88 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
89 | extern const struct target_desc *tdesc_mips64_linux; |
90 | ||
1faeff08 MR |
91 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
92 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 93 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
94 | |
95 | #ifdef __mips64 | |
3aee8918 PA |
96 | #define tdesc_mips_linux tdesc_mips64_linux |
97 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 98 | #endif |
d05b4ac3 | 99 | |
21b0f40c DJ |
100 | #ifndef PTRACE_GET_THREAD_AREA |
101 | #define PTRACE_GET_THREAD_AREA 25 | |
102 | #endif | |
103 | ||
0a30fbc4 DJ |
104 | #ifdef HAVE_SYS_REG_H |
105 | #include <sys/reg.h> | |
106 | #endif | |
107 | ||
117ce543 | 108 | #define mips_num_regs 73 |
1faeff08 | 109 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
110 | |
111 | #include <asm/ptrace.h> | |
112 | ||
1faeff08 MR |
113 | #ifndef DSP_BASE |
114 | #define DSP_BASE 71 | |
115 | #define DSP_CONTROL 77 | |
116 | #endif | |
117 | ||
186947f7 DJ |
118 | union mips_register |
119 | { | |
120 | unsigned char buf[8]; | |
121 | ||
122 | /* Deliberately signed, for proper sign extension. */ | |
123 | int reg32; | |
124 | long long reg64; | |
125 | }; | |
126 | ||
0a30fbc4 DJ |
127 | /* Return the ptrace ``address'' of register REGNO. */ |
128 | ||
1faeff08 MR |
129 | #define mips_base_regs \ |
130 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
131 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
132 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
133 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
134 | \ | |
135 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
136 | \ | |
137 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
138 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
139 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
140 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
141 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
142 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
143 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
144 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
145 | FPC_CSR, FPC_EIR | |
146 | ||
147 | #define mips_dsp_regs \ | |
148 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
149 | DSP_BASE + 4, DSP_BASE + 5, \ | |
150 | DSP_CONTROL | |
151 | ||
152 | static int mips_regmap[mips_num_regs] = { | |
153 | mips_base_regs, | |
154 | 0 | |
155 | }; | |
0a30fbc4 | 156 | |
1faeff08 MR |
157 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
158 | mips_base_regs, | |
159 | mips_dsp_regs, | |
160 | 0 | |
161 | }; | |
0a30fbc4 | 162 | |
1faeff08 MR |
163 | /* DSP registers are not in any regset and can only be accessed |
164 | individually. */ | |
0a30fbc4 | 165 | |
1faeff08 MR |
166 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
167 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
168 | }; |
169 | ||
3aee8918 PA |
170 | static int have_dsp = -1; |
171 | ||
1faeff08 MR |
172 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
173 | user register set accordingly. */ | |
174 | ||
3aee8918 PA |
175 | static const struct target_desc * |
176 | mips_read_description (void) | |
1faeff08 | 177 | { |
3aee8918 | 178 | if (have_dsp < 0) |
1faeff08 | 179 | { |
0bfdf32f | 180 | int pid = lwpid_of (current_thread); |
1faeff08 | 181 | |
ac740bc7 | 182 | errno = 0; |
1faeff08 MR |
183 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
184 | switch (errno) | |
185 | { | |
186 | case 0: | |
3aee8918 | 187 | have_dsp = 1; |
1faeff08 MR |
188 | break; |
189 | case EIO: | |
3aee8918 | 190 | have_dsp = 0; |
1faeff08 MR |
191 | break; |
192 | default: | |
193 | perror_with_name ("ptrace"); | |
194 | break; | |
195 | } | |
196 | } | |
3aee8918 PA |
197 | |
198 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
199 | } | |
200 | ||
797bcff5 TBA |
201 | void |
202 | mips_target::low_arch_setup () | |
3aee8918 PA |
203 | { |
204 | current_process ()->tdesc = mips_read_description (); | |
205 | } | |
206 | ||
7a60ad40 YQ |
207 | /* Per-process arch-specific data we want to keep. */ |
208 | ||
209 | struct arch_process_info | |
210 | { | |
211 | /* -1 if the kernel and/or CPU do not support watch registers. | |
212 | 1 if watch_readback is valid and we can read style, num_valid | |
213 | and the masks. | |
214 | 0 if we need to read the watch_readback. */ | |
215 | ||
216 | int watch_readback_valid; | |
217 | ||
218 | /* Cached watch register read values. */ | |
219 | ||
220 | struct pt_watch_regs watch_readback; | |
221 | ||
222 | /* Current watchpoint requests for this process. */ | |
223 | ||
224 | struct mips_watchpoint *current_watches; | |
225 | ||
226 | /* The current set of watch register values for writing the | |
227 | registers. */ | |
228 | ||
229 | struct pt_watch_regs watch_mirror; | |
230 | }; | |
231 | ||
232 | /* Per-thread arch-specific data we want to keep. */ | |
233 | ||
234 | struct arch_lwp_info | |
235 | { | |
236 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
237 | int watch_registers_changed; | |
238 | }; | |
239 | ||
0a30fbc4 DJ |
240 | /* From mips-linux-nat.c. */ |
241 | ||
242 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
243 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
244 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
245 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 246 | |
daca57a7 TBA |
247 | bool |
248 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 249 | { |
3aee8918 PA |
250 | const struct target_desc *tdesc; |
251 | ||
daca57a7 TBA |
252 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
253 | return true; | |
0a30fbc4 | 254 | |
3aee8918 PA |
255 | tdesc = current_process ()->tdesc; |
256 | ||
75d74cca MR |
257 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
258 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 259 | return true; |
75d74cca | 260 | |
3aee8918 | 261 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 262 | return true; |
0a30fbc4 | 263 | |
daca57a7 | 264 | return false; |
0a30fbc4 DJ |
265 | } |
266 | ||
daca57a7 TBA |
267 | bool |
268 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 269 | { |
3aee8918 PA |
270 | const struct target_desc *tdesc; |
271 | ||
daca57a7 TBA |
272 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
273 | return true; | |
0a30fbc4 | 274 | |
3aee8918 PA |
275 | tdesc = current_process ()->tdesc; |
276 | ||
75d74cca MR |
277 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
278 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 279 | return true; |
75d74cca | 280 | |
3aee8918 | 281 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 282 | return true; |
0a30fbc4 | 283 | |
3aee8918 | 284 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 285 | return true; |
0a30fbc4 | 286 | |
3aee8918 | 287 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 288 | return true; |
0a30fbc4 | 289 | |
3aee8918 | 290 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 291 | return true; |
0a30fbc4 | 292 | |
daca57a7 | 293 | return false; |
0a30fbc4 | 294 | } |
2ec06d2e | 295 | |
bd70b1f2 TBA |
296 | bool |
297 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
298 | { |
299 | const struct target_desc *tdesc = current_process ()->tdesc; | |
300 | ||
301 | if (find_regno (tdesc, "r0") == regno) | |
302 | { | |
303 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 304 | return true; |
e4439e43 MR |
305 | } |
306 | ||
bd70b1f2 | 307 | return false; |
e4439e43 MR |
308 | } |
309 | ||
bf9ae9d8 TBA |
310 | bool |
311 | mips_target::low_supports_breakpoints () | |
312 | { | |
313 | return true; | |
314 | } | |
315 | ||
316 | CORE_ADDR | |
317 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 318 | { |
186947f7 | 319 | union mips_register pc; |
442ea881 | 320 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 321 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
322 | } |
323 | ||
bf9ae9d8 TBA |
324 | void |
325 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 326 | { |
186947f7 | 327 | union mips_register newpc; |
3aee8918 | 328 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
329 | newpc.reg32 = pc; |
330 | else | |
331 | newpc.reg64 = pc; | |
332 | ||
442ea881 | 333 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
334 | } |
335 | ||
336 | /* Correct in either endianness. */ | |
186947f7 | 337 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
338 | #define mips_breakpoint_len 4 |
339 | ||
3ca4edb6 | 340 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 341 | |
3ca4edb6 TBA |
342 | const gdb_byte * |
343 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
344 | { |
345 | *size = mips_breakpoint_len; | |
346 | return (const gdb_byte *) &mips_breakpoint; | |
347 | } | |
348 | ||
d7146cda TBA |
349 | bool |
350 | mips_target::low_breakpoint_at (CORE_ADDR where) | |
0d62e5e8 | 351 | { |
186947f7 | 352 | unsigned int insn; |
0d62e5e8 | 353 | |
d7146cda | 354 | read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 | 355 | if (insn == mips_breakpoint) |
d7146cda | 356 | return true; |
0d62e5e8 DJ |
357 | |
358 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
359 | one. */ | |
d7146cda | 360 | return false; |
0d62e5e8 DJ |
361 | } |
362 | ||
da25033c | 363 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 364 | |
da25033c SM |
365 | static void |
366 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 367 | { |
d86d4aaf | 368 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 369 | |
da25033c SM |
370 | /* The actual update is done later just before resuming the lwp, |
371 | we just mark that the registers need updating. */ | |
372 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 373 | |
da25033c SM |
374 | /* If the lwp isn't stopped, force it to momentarily pause, so |
375 | we can update its watch registers. */ | |
376 | if (!lwp->stopped) | |
377 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
378 | } |
379 | ||
380 | /* This is the implementation of linux_target_ops method | |
381 | new_process. */ | |
382 | ||
383 | static struct arch_process_info * | |
384 | mips_linux_new_process (void) | |
385 | { | |
8d749320 | 386 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
387 | |
388 | return info; | |
389 | } | |
390 | ||
04ec7890 SM |
391 | /* This is the implementation of linux_target_ops method |
392 | delete_process. */ | |
393 | ||
394 | static void | |
395 | mips_linux_delete_process (struct arch_process_info *info) | |
396 | { | |
397 | xfree (info); | |
398 | } | |
399 | ||
7a60ad40 YQ |
400 | /* This is the implementation of linux_target_ops method new_thread. |
401 | Mark the watch registers as changed, so the threads' copies will | |
402 | be updated. */ | |
403 | ||
34c703da GB |
404 | static void |
405 | mips_linux_new_thread (struct lwp_info *lwp) | |
7a60ad40 | 406 | { |
8d749320 | 407 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
408 | |
409 | info->watch_registers_changed = 1; | |
410 | ||
34c703da | 411 | lwp->arch_private = info; |
7a60ad40 YQ |
412 | } |
413 | ||
466eecee SM |
414 | /* Function to call when a thread is being deleted. */ |
415 | ||
416 | static void | |
417 | mips_linux_delete_thread (struct arch_lwp_info *arch_lwp) | |
418 | { | |
419 | xfree (arch_lwp); | |
420 | } | |
421 | ||
3a8a0396 DB |
422 | /* Create a new mips_watchpoint and add it to the list. */ |
423 | ||
424 | static void | |
cbec665b | 425 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 426 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
427 | { |
428 | struct mips_watchpoint *new_watch; | |
429 | struct mips_watchpoint **pw; | |
430 | ||
8d749320 | 431 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
432 | new_watch->addr = addr; |
433 | new_watch->len = len; | |
434 | new_watch->type = watch_type; | |
435 | new_watch->next = NULL; | |
436 | ||
cbec665b | 437 | pw = &priv->current_watches; |
3a8a0396 DB |
438 | while (*pw != NULL) |
439 | pw = &(*pw)->next; | |
440 | *pw = new_watch; | |
441 | } | |
442 | ||
443 | /* Hook to call when a new fork is attached. */ | |
444 | ||
445 | static void | |
446 | mips_linux_new_fork (struct process_info *parent, | |
447 | struct process_info *child) | |
448 | { | |
449 | struct arch_process_info *parent_private; | |
450 | struct arch_process_info *child_private; | |
451 | struct mips_watchpoint *wp; | |
452 | ||
453 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
454 | gdb_assert (parent->priv != NULL |
455 | && parent->priv->arch_private != NULL); | |
456 | gdb_assert (child->priv != NULL | |
457 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
458 | |
459 | /* Linux kernel before 2.6.33 commit | |
460 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
461 | will inherit hardware debug registers from parent | |
462 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
463 | zeroed debug registers. | |
464 | ||
465 | GDB core assumes the child inherits the watchpoints/hw | |
466 | breakpoints of the parent, and will remove them all from the | |
467 | forked off process. Copy the debug registers mirrors into the | |
468 | new process so that all breakpoints and watchpoints can be | |
469 | removed together. The debug registers mirror will become zeroed | |
470 | in the end before detaching the forked off process, thus making | |
471 | this compatible with older Linux kernels too. */ | |
472 | ||
61a7418c DB |
473 | parent_private = parent->priv->arch_private; |
474 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
475 | |
476 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
477 | child_private->watch_readback = parent_private->watch_readback; | |
478 | ||
479 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
480 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
481 | ||
482 | child_private->watch_mirror = parent_private->watch_mirror; | |
483 | } | |
7a60ad40 YQ |
484 | /* This is the implementation of linux_target_ops method |
485 | prepare_to_resume. If the watch regs have changed, update the | |
486 | thread's copies. */ | |
487 | ||
488 | static void | |
489 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
490 | { | |
d86d4aaf | 491 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 492 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 493 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
494 | |
495 | if (lwp->arch_private->watch_registers_changed) | |
496 | { | |
497 | /* Only update the watch registers if we have set or unset a | |
498 | watchpoint already. */ | |
fe978cb0 | 499 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
500 | { |
501 | /* Write the mirrored watch register values. */ | |
e38504b3 | 502 | int tid = ptid.lwp (); |
7a60ad40 YQ |
503 | |
504 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 505 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
506 | perror_with_name ("Couldn't write watch register"); |
507 | } | |
508 | ||
509 | lwp->arch_private->watch_registers_changed = 0; | |
510 | } | |
511 | } | |
512 | ||
007c9b97 TBA |
513 | bool |
514 | mips_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
515 | { |
516 | switch (z_type) | |
517 | { | |
518 | case Z_PACKET_WRITE_WP: | |
519 | case Z_PACKET_READ_WP: | |
520 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 521 | return true; |
802e8e6d | 522 | default: |
007c9b97 | 523 | return false; |
802e8e6d PA |
524 | } |
525 | } | |
526 | ||
9db9aa23 TBA |
527 | /* This is the implementation of linux target ops method |
528 | low_insert_point. */ | |
7a60ad40 | 529 | |
9db9aa23 TBA |
530 | int |
531 | mips_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
532 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
533 | { |
534 | struct process_info *proc = current_process (); | |
fe978cb0 | 535 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 536 | struct pt_watch_regs regs; |
7a60ad40 YQ |
537 | long lwpid; |
538 | enum target_hw_bp_type watch_type; | |
539 | uint32_t irw; | |
540 | ||
0bfdf32f | 541 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 542 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
543 | &priv->watch_readback, |
544 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
545 | 0)) |
546 | return -1; | |
547 | ||
548 | if (len <= 0) | |
549 | return -1; | |
550 | ||
fe978cb0 | 551 | regs = priv->watch_readback; |
7a60ad40 | 552 | /* Add the current watches. */ |
fe978cb0 | 553 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
554 | |
555 | /* Now try to add the new watch. */ | |
802e8e6d | 556 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
557 | irw = mips_linux_watch_type_to_irw (watch_type); |
558 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
559 | return -1; | |
560 | ||
561 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 562 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 563 | |
fe978cb0 | 564 | priv->watch_mirror = regs; |
7a60ad40 YQ |
565 | |
566 | /* Only update the threads of this process. */ | |
da25033c | 567 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
9db9aa23 TBA |
572 | /* This is the implementation of linux target ops method |
573 | low_remove_point. */ | |
7a60ad40 | 574 | |
9db9aa23 TBA |
575 | int |
576 | mips_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
577 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
578 | { |
579 | struct process_info *proc = current_process (); | |
fe978cb0 | 580 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
581 | |
582 | int deleted_one; | |
7a60ad40 YQ |
583 | enum target_hw_bp_type watch_type; |
584 | ||
585 | struct mips_watchpoint **pw; | |
586 | struct mips_watchpoint *w; | |
587 | ||
7a60ad40 | 588 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 589 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 590 | deleted_one = 0; |
fe978cb0 | 591 | pw = &priv->current_watches; |
7a60ad40 YQ |
592 | while ((w = *pw)) |
593 | { | |
594 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
595 | { | |
596 | *pw = w->next; | |
597 | free (w); | |
598 | deleted_one = 1; | |
599 | break; | |
600 | } | |
601 | pw = &(w->next); | |
602 | } | |
603 | ||
604 | if (!deleted_one) | |
605 | return -1; /* We don't know about it, fail doing nothing. */ | |
606 | ||
607 | /* At this point watch_readback is known to be valid because we | |
608 | could not have added the watch without reading it. */ | |
fe978cb0 | 609 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 610 | |
fe978cb0 PA |
611 | priv->watch_mirror = priv->watch_readback; |
612 | mips_linux_watch_populate_regs (priv->current_watches, | |
613 | &priv->watch_mirror); | |
7a60ad40 YQ |
614 | |
615 | /* Only update the threads of this process. */ | |
da25033c SM |
616 | for_each_thread (proc->pid, update_watch_registers_callback); |
617 | ||
7a60ad40 YQ |
618 | return 0; |
619 | } | |
620 | ||
ac1bbaca TBA |
621 | /* This is the implementation of linux target ops method |
622 | low_stopped_by_watchpoint. The watchhi R and W bits indicate | |
7a60ad40 YQ |
623 | the watch register triggered. */ |
624 | ||
ac1bbaca TBA |
625 | bool |
626 | mips_target::low_stopped_by_watchpoint () | |
7a60ad40 YQ |
627 | { |
628 | struct process_info *proc = current_process (); | |
fe978cb0 | 629 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
630 | int n; |
631 | int num_valid; | |
0bfdf32f | 632 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
633 | |
634 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
635 | &priv->watch_readback, |
636 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
637 | 1)) |
638 | return 0; | |
639 | ||
fe978cb0 | 640 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
641 | |
642 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 643 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 | 644 | & (R_MASK | W_MASK)) |
ac1bbaca | 645 | return true; |
7a60ad40 | 646 | |
ac1bbaca | 647 | return false; |
7a60ad40 YQ |
648 | } |
649 | ||
ac1bbaca TBA |
650 | /* This is the implementation of linux target ops method |
651 | low_stopped_data_address. */ | |
7a60ad40 | 652 | |
ac1bbaca TBA |
653 | CORE_ADDR |
654 | mips_target::low_stopped_data_address () | |
7a60ad40 YQ |
655 | { |
656 | struct process_info *proc = current_process (); | |
fe978cb0 | 657 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
658 | int n; |
659 | int num_valid; | |
0bfdf32f | 660 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
661 | |
662 | /* On MIPS we don't know the low order 3 bits of the data address. | |
663 | GDB does not support remote targets that can't report the | |
664 | watchpoint address. So, make our best guess; return the starting | |
665 | address of a watchpoint request which overlaps the one that | |
666 | triggered. */ | |
667 | ||
668 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
669 | &priv->watch_readback, |
670 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
671 | 0)) |
672 | return 0; | |
673 | ||
fe978cb0 | 674 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
675 | |
676 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 677 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
678 | & (R_MASK | W_MASK)) |
679 | { | |
680 | CORE_ADDR t_low, t_hi; | |
681 | int t_irw; | |
682 | struct mips_watchpoint *watch; | |
683 | ||
fe978cb0 | 684 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 685 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 686 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
687 | | IRW_MASK); |
688 | t_low &= ~(CORE_ADDR)t_hi; | |
689 | ||
fe978cb0 | 690 | for (watch = priv->current_watches; |
7a60ad40 YQ |
691 | watch != NULL; |
692 | watch = watch->next) | |
693 | { | |
694 | CORE_ADDR addr = watch->addr; | |
695 | CORE_ADDR last_byte = addr + watch->len - 1; | |
696 | ||
697 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
698 | { | |
699 | /* Different type. */ | |
700 | continue; | |
701 | } | |
702 | /* Check for overlap of even a single byte. */ | |
703 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
704 | return addr; | |
705 | } | |
706 | } | |
707 | ||
708 | /* Shouldn't happen. */ | |
709 | return 0; | |
710 | } | |
711 | ||
21b0f40c DJ |
712 | /* Fetch the thread-local storage pointer for libthread_db. */ |
713 | ||
714 | ps_err_e | |
754653a7 | 715 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 716 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
717 | { |
718 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
719 | return PS_ERR; | |
720 | ||
721 | /* IDX is the bias from the thread pointer to the beginning of the | |
722 | thread descriptor. It has to be subtracted due to implementation | |
723 | quirks in libthread_db. */ | |
724 | *base = (void *) ((char *)*base - idx); | |
725 | ||
726 | return PS_OK; | |
727 | } | |
728 | ||
186947f7 | 729 | static void |
442ea881 PA |
730 | mips_collect_register (struct regcache *regcache, |
731 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
732 | { |
733 | union mips_register tmp_reg; | |
734 | ||
735 | if (use_64bit) | |
736 | { | |
442ea881 | 737 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
738 | *reg = tmp_reg; |
739 | } | |
740 | else | |
741 | { | |
442ea881 | 742 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
743 | reg->reg64 = tmp_reg.reg32; |
744 | } | |
745 | } | |
746 | ||
747 | static void | |
442ea881 PA |
748 | mips_supply_register (struct regcache *regcache, |
749 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
750 | { |
751 | int offset = 0; | |
752 | ||
753 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
754 | eight-byte slot. */ | |
755 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
756 | offset = 4; | |
757 | ||
442ea881 | 758 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
759 | } |
760 | ||
7e947ad3 MR |
761 | #ifdef HAVE_PTRACE_GETREGS |
762 | ||
186947f7 | 763 | static void |
442ea881 PA |
764 | mips_collect_register_32bit (struct regcache *regcache, |
765 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
766 | { |
767 | union mips_register tmp_reg; | |
768 | int reg32; | |
769 | ||
442ea881 | 770 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
771 | reg32 = tmp_reg.reg64; |
772 | memcpy (buf, ®32, 4); | |
773 | } | |
774 | ||
775 | static void | |
442ea881 PA |
776 | mips_supply_register_32bit (struct regcache *regcache, |
777 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
778 | { |
779 | union mips_register tmp_reg; | |
780 | int reg32; | |
781 | ||
782 | memcpy (®32, buf, 4); | |
783 | tmp_reg.reg64 = reg32; | |
442ea881 | 784 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
785 | } |
786 | ||
787 | static void | |
442ea881 | 788 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 789 | { |
1996e237 | 790 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 791 | int i, use_64bit; |
3aee8918 | 792 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 793 | |
3aee8918 | 794 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 795 | |
117ce543 | 796 | for (i = 1; i < 32; i++) |
442ea881 PA |
797 | mips_collect_register (regcache, use_64bit, i, regset + i); |
798 | ||
799 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 800 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 801 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 802 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 803 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 804 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 805 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 806 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 807 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 808 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 809 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 810 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
811 | |
812 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 813 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
814 | } |
815 | ||
816 | static void | |
442ea881 | 817 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 818 | { |
1996e237 | 819 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
820 | int i, use_64bit; |
821 | ||
3aee8918 | 822 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 823 | |
e4439e43 MR |
824 | supply_register_by_name_zeroed (regcache, "r0"); |
825 | ||
826 | for (i = 1; i < 32; i++) | |
442ea881 PA |
827 | mips_supply_register (regcache, use_64bit, i, regset + i); |
828 | ||
442ea881 | 829 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
830 | find_regno (regcache->tdesc, "lo"), regset + 32); |
831 | mips_supply_register (regcache, use_64bit, | |
832 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 833 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 834 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 835 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
836 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
837 | mips_supply_register (regcache, use_64bit, | |
838 | find_regno (regcache->tdesc, "status"), regset + 36); | |
839 | mips_supply_register (regcache, use_64bit, | |
840 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
841 | |
842 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 843 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
844 | } |
845 | ||
846 | static void | |
442ea881 | 847 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 848 | { |
1996e237 | 849 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
850 | int i, use_64bit, first_fp, big_endian; |
851 | ||
3aee8918 PA |
852 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
853 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
854 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
855 | ||
856 | /* See GDB for a discussion of this peculiar layout. */ | |
857 | for (i = 0; i < 32; i++) | |
858 | if (use_64bit) | |
442ea881 | 859 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 860 | else |
442ea881 | 861 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
862 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
863 | ||
442ea881 | 864 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
865 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
866 | mips_collect_register_32bit (regcache, use_64bit, | |
867 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
868 | regset[32].buf + 4); |
869 | } | |
870 | ||
871 | static void | |
442ea881 | 872 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 873 | { |
1996e237 | 874 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
875 | int i, use_64bit, first_fp, big_endian; |
876 | ||
3aee8918 PA |
877 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
878 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
879 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
880 | ||
881 | /* See GDB for a discussion of this peculiar layout. */ | |
882 | for (i = 0; i < 32; i++) | |
883 | if (use_64bit) | |
442ea881 | 884 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 885 | else |
442ea881 | 886 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
887 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
888 | ||
442ea881 | 889 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
890 | find_regno (regcache->tdesc, "fcsr"), |
891 | regset[32].buf); | |
892 | mips_supply_register_32bit (regcache, use_64bit, | |
893 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
894 | regset[32].buf + 4); |
895 | } | |
896 | #endif /* HAVE_PTRACE_GETREGS */ | |
897 | ||
7e947ad3 MR |
898 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
899 | ||
b35db733 TBA |
900 | void |
901 | mips_target::low_collect_ptrace_register (regcache *regcache, int regno, | |
902 | char *buf) | |
7e947ad3 | 903 | { |
7e947ad3 MR |
904 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
905 | ||
906 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
907 | { | |
908 | union mips_register reg; | |
909 | ||
910 | mips_collect_register (regcache, 0, regno, ®); | |
911 | memcpy (buf, ®, sizeof (reg)); | |
912 | } | |
913 | else | |
914 | collect_register (regcache, regno, buf); | |
915 | } | |
916 | ||
917 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
918 | ||
b35db733 TBA |
919 | void |
920 | mips_target::low_supply_ptrace_register (regcache *regcache, int regno, | |
921 | const char *buf) | |
7e947ad3 | 922 | { |
7e947ad3 MR |
923 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
924 | ||
925 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
926 | { | |
927 | union mips_register reg; | |
928 | ||
929 | memcpy (®, buf, sizeof (reg)); | |
930 | mips_supply_register (regcache, 0, regno, ®); | |
931 | } | |
932 | else | |
933 | supply_register (regcache, regno, buf); | |
934 | } | |
935 | ||
3aee8918 | 936 | static struct regset_info mips_regsets[] = { |
186947f7 | 937 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 938 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 939 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 940 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
941 | mips_fill_fpregset, mips_store_fpregset }, |
942 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 943 | NULL_REGSET |
186947f7 DJ |
944 | }; |
945 | ||
3aee8918 PA |
946 | static struct regsets_info mips_regsets_info = |
947 | { | |
948 | mips_regsets, /* regsets */ | |
949 | 0, /* num_regsets */ | |
950 | NULL, /* disabled_regsets */ | |
951 | }; | |
952 | ||
953 | static struct usrregs_info mips_dsp_usrregs_info = | |
954 | { | |
955 | mips_dsp_num_regs, | |
956 | mips_dsp_regmap, | |
957 | }; | |
958 | ||
959 | static struct usrregs_info mips_usrregs_info = | |
960 | { | |
961 | mips_num_regs, | |
962 | mips_regmap, | |
963 | }; | |
964 | ||
965 | static struct regs_info dsp_regs_info = | |
966 | { | |
967 | mips_dsp_regset_bitmap, | |
968 | &mips_dsp_usrregs_info, | |
969 | &mips_regsets_info | |
970 | }; | |
971 | ||
aa8d21c9 | 972 | static struct regs_info myregs_info = |
3aee8918 PA |
973 | { |
974 | NULL, /* regset_bitmap */ | |
975 | &mips_usrregs_info, | |
976 | &mips_regsets_info | |
977 | }; | |
978 | ||
aa8d21c9 TBA |
979 | const regs_info * |
980 | mips_target::get_regs_info () | |
3aee8918 PA |
981 | { |
982 | if (have_dsp) | |
983 | return &dsp_regs_info; | |
984 | else | |
aa8d21c9 | 985 | return &myregs_info; |
3aee8918 PA |
986 | } |
987 | ||
2ec06d2e | 988 | struct linux_target_ops the_low_target = { |
7a60ad40 YQ |
989 | NULL, /* siginfo_fixup */ |
990 | mips_linux_new_process, | |
04ec7890 | 991 | mips_linux_delete_process, |
7a60ad40 | 992 | mips_linux_new_thread, |
466eecee | 993 | mips_linux_delete_thread, |
3a8a0396 | 994 | mips_linux_new_fork, |
7a60ad40 | 995 | mips_linux_prepare_to_resume |
2ec06d2e | 996 | }; |
3aee8918 | 997 | |
ef0478f6 TBA |
998 | /* The linux target ops object. */ |
999 | ||
1000 | linux_process_target *the_linux_target = &the_mips_target; | |
1001 | ||
3aee8918 PA |
1002 | void |
1003 | initialize_low_arch (void) | |
1004 | { | |
1005 | /* Initialize the Linux target descriptions. */ | |
1006 | init_registers_mips_linux (); | |
1007 | init_registers_mips_dsp_linux (); | |
1008 | init_registers_mips64_linux (); | |
1009 | init_registers_mips64_dsp_linux (); | |
1010 | ||
1011 | initialize_regsets_info (&mips_regsets_info); | |
1012 | } |