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gdbserver/linux-low: turn 'supports_tracepoints' into a method
[deliverable/binutils-gdb.git] / gdbserver / linux-ppc-low.cc
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
b811d2c2 3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
64f57f3d 31#include "nat/linux-ptrace.h"
bd64614e 32#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 33#include "ax.h"
34#include "tracepoint.h"
35
36#define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38#define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 46
ef0478f6
TBA		 47/* Linux target op definitions for the PowerPC architecture. */
48
49class ppc_target : public linux_process_target
50{
51public:
52
aa8d21c9
TBA		 53 const regs_info *get_regs_info () override;
54
3ca4edb6
TBA		 55 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
56
007c9b97
TBA		 57 bool supports_z_point_type (char z_type) override;
58
b35db733
TBA		 59
60 void low_collect_ptrace_register (regcache *regcache, int regno,
61 char *buf) override;
62
63 void low_supply_ptrace_register (regcache *regcache, int regno,
64 const char *buf) override;
47f70aa7
TBA		 65
66 bool supports_tracepoints () override;
67
797bcff5
TBA		 68protected:
69
70 void low_arch_setup () override;
daca57a7
TBA		 71
72 bool low_cannot_fetch_register (int regno) override;
73
74 bool low_cannot_store_register (int regno) override;
bf9ae9d8
TBA		 75
76 bool low_supports_breakpoints () override;
77
78 CORE_ADDR low_get_pc (regcache *regcache) override;
79
80 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
d7146cda
TBA		 81
82 bool low_breakpoint_at (CORE_ADDR pc) override;
9db9aa23
TBA		 83
84 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
85 int size, raw_breakpoint *bp) override;
86
87 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
88 int size, raw_breakpoint *bp) override;
ef0478f6
TBA		 89};
90
91/* The singleton target ops object. */
92
93static ppc_target the_ppc_target;
94
7ca18ed6
EBM		 95/* Holds the AT_HWCAP auxv entry. */
96
b6430ec3
UW		 97static unsigned long ppc_hwcap;
98
7ca18ed6
EBM		 99/* Holds the AT_HWCAP2 auxv entry. */
100
101static unsigned long ppc_hwcap2;
102
b6430ec3 103
7284e1be
UW		 104#define ppc_num_regs 73
105
5b0a002e
UW		 106#ifdef __powerpc64__
107/* We use a constant for FPSCR instead of PT_FPSCR, because
108 many shipped PPC64 kernels had the wrong value in ptrace.h. */
109static int ppc_regmap[] =
110 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
111 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
112 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
113 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
114 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
115 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
116 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
117 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
118 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
119 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
120 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
121 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
122 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
123 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
124 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
125 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
126 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 127 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
128 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 129#else
0a30fbc4 130/* Currently, don't check/send MQ. */
2ec06d2e 131static int ppc_regmap[] =
0a30fbc4
DJ		 132 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
133 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
134 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
135 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
136 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
137 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
138 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
139 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
140 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
141 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
142 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
143 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
144 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
145 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
146 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
147 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
148 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 149 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
150 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 151 };
152
153static int ppc_regmap_e500[] =
154 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
155 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
156 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
157 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
158 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
159 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
160 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
161 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
162 -1, -1, -1, -1,
163 -1, -1, -1, -1,
164 -1, -1, -1, -1,
165 -1, -1, -1, -1,
166 -1, -1, -1, -1,
167 -1, -1, -1, -1,
168 -1, -1, -1, -1,
169 -1, -1, -1, -1,
170 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 171 PT_CTR * 4, PT_XER * 4, -1,
172 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 173 };
5b0a002e 174#endif
0a30fbc4 175
7ca18ed6
EBM		 176/* Check whether the kernel provides a register set with number
177 REGSET_ID of size REGSETSIZE for process/thread TID. */
178
179static int
180ppc_check_regset (int tid, int regset_id, int regsetsize)
181{
182 void *buf = alloca (regsetsize);
183 struct iovec iov;
184
185 iov.iov_base = buf;
186 iov.iov_len = regsetsize;
187
188 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
189 || errno == ENODATA)
190 return 1;
191 return 0;
192}
193
daca57a7
TBA		 194bool
195ppc_target::low_cannot_store_register (int regno)
0a30fbc4 196{
3aee8918
PA		 197 const struct target_desc *tdesc = current_process ()->tdesc;
198
b6430ec3 199#ifndef __powerpc64__
bc1e36ca 200 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 201 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
202 && regno == find_regno (tdesc, "fpscr"))
daca57a7 203 return true;
30ed0a8f 204#endif
bc1e36ca 205
7284e1be 206 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 207 if (regno == find_regno (tdesc, "orig_r3")
208 || regno == find_regno (tdesc, "trap"))
daca57a7 209 return true;
7284e1be 210
daca57a7 211 return false;
0a30fbc4
DJ		 212}
213
daca57a7
TBA		 214bool
215ppc_target::low_cannot_fetch_register (int regno)
0a30fbc4 216{
daca57a7 217 return false;
0a30fbc4
DJ		 218}
219
b35db733
TBA		 220void
221ppc_target::low_collect_ptrace_register (regcache *regcache, int regno,
222 char *buf)
5b0a002e 223{
76b233dd
UW		 224 memset (buf, 0, sizeof (long));
225
2e4bb98a
EBM		 226 if (__BYTE_ORDER == __LITTLE_ENDIAN)
227 {
228 /* Little-endian values always sit at the left end of the buffer. */
229 collect_register (regcache, regno, buf);
230 }
231 else if (__BYTE_ORDER == __BIG_ENDIAN)
232 {
233 /* Big-endian values sit at the right end of the buffer. In case of
234 registers whose sizes are smaller than sizeof (long), we must use a
235 padding to access them correctly. */
236 int size = register_size (regcache->tdesc, regno);
237
238 if (size < sizeof (long))
239 collect_register (regcache, regno, buf + sizeof (long) - size);
240 else
241 collect_register (regcache, regno, buf);
242 }
5b0a002e 243 else
2e4bb98a 244 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 245}
246
b35db733
TBA		 247void
248ppc_target::low_supply_ptrace_register (regcache *regcache, int regno,
249 const char *buf)
5b0a002e 250{
2e4bb98a
EBM		 251 if (__BYTE_ORDER == __LITTLE_ENDIAN)
252 {
253 /* Little-endian values always sit at the left end of the buffer. */
254 supply_register (regcache, regno, buf);
255 }
256 else if (__BYTE_ORDER == __BIG_ENDIAN)
257 {
258 /* Big-endian values sit at the right end of the buffer. In case of
259 registers whose sizes are smaller than sizeof (long), we must use a
260 padding to access them correctly. */
261 int size = register_size (regcache->tdesc, regno);
262
263 if (size < sizeof (long))
264 supply_register (regcache, regno, buf + sizeof (long) - size);
265 else
266 supply_register (regcache, regno, buf);
267 }
5b0a002e 268 else
2e4bb98a 269 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 270}
271
bf9ae9d8
TBA		 272bool
273ppc_target::low_supports_breakpoints ()
274{
275 return true;
276}
277
278CORE_ADDR
279ppc_target::low_get_pc (regcache *regcache)
0d62e5e8 280{
abf516c6 281 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 282 {
283 unsigned int pc;
442ea881 284 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 285 return (CORE_ADDR) pc;
286 }
287 else
288 {
289 unsigned long pc;
442ea881 290 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 291 return (CORE_ADDR) pc;
292 }
0d62e5e8
DJ		 293}
294
bf9ae9d8
TBA		 295void
296ppc_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
0d62e5e8 297{
abf516c6 298 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 299 {
300 unsigned int newpc = pc;
442ea881 301 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 302 }
303 else
304 {
305 unsigned long newpc = pc;
442ea881 306 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 307 }
308}
309
3aee8918
PA		 310#ifndef __powerpc64__
311static int ppc_regmap_adjusted;
312#endif
313
0d62e5e8 314
5b0a002e 315/* Correct in either endianness.
0d62e5e8
DJ		 316 This instruction is "twge r2, r2", which GDB uses as a software
317 breakpoint. */
5b0a002e 318static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 319#define ppc_breakpoint_len 4
320
3ca4edb6 321/* Implementation of target ops method "sw_breakpoint_from_kind". */
dd373349 322
3ca4edb6
TBA		 323const gdb_byte *
324ppc_target::sw_breakpoint_from_kind (int kind, int *size)
dd373349
AT		 325{
326 *size = ppc_breakpoint_len;
327 return (const gdb_byte *) &ppc_breakpoint;
328}
329
d7146cda
TBA		 330bool
331ppc_target::low_breakpoint_at (CORE_ADDR where)
0d62e5e8 332{
5b0a002e 333 unsigned int insn;
0d62e5e8 334
d7146cda 335 read_memory (where, (unsigned char *) &insn, 4);
abf516c6 336 if (insn == ppc_breakpoint)
d7146cda 337 return true;
abf516c6
UW		 338 /* If necessary, recognize more trap instructions here. GDB only uses
339 the one. */
0b9ff2c0 340
d7146cda 341 return false;
0d62e5e8
DJ		 342}
343
657f9cde
WW		 344/* Implement supports_z_point_type target-ops.
345 Returns true if type Z_TYPE breakpoint is supported.
346
347 Handling software breakpoint at server side, so tracepoints
348 and breakpoints can be inserted at the same location. */
349
007c9b97
TBA		 350bool
351ppc_target::supports_z_point_type (char z_type)
657f9cde
WW		 352{
353 switch (z_type)
354 {
355 case Z_PACKET_SW_BP:
007c9b97 356 return true;
657f9cde
WW		 357 case Z_PACKET_HW_BP:
358 case Z_PACKET_WRITE_WP:
359 case Z_PACKET_ACCESS_WP:
360 default:
007c9b97 361 return false;
657f9cde
WW		 362 }
363}
364
9db9aa23 365/* Implement the low_insert_point linux target op.
657f9cde
WW		 366 Returns 0 on success, -1 on failure and 1 on unsupported. */
367
9db9aa23
TBA		 368int
369ppc_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
370 int size, raw_breakpoint *bp)
657f9cde
WW		 371{
372 switch (type)
373 {
374 case raw_bkpt_type_sw:
375 return insert_memory_breakpoint (bp);
376
377 case raw_bkpt_type_hw:
378 case raw_bkpt_type_write_wp:
379 case raw_bkpt_type_access_wp:
380 default:
381 /* Unsupported. */
382 return 1;
383 }
384}
385
9db9aa23 386/* Implement the low_remove_point linux target op.
657f9cde
WW		 387 Returns 0 on success, -1 on failure and 1 on unsupported. */
388
9db9aa23
TBA		 389int
390ppc_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
391 int size, raw_breakpoint *bp)
657f9cde
WW		 392{
393 switch (type)
394 {
395 case raw_bkpt_type_sw:
396 return remove_memory_breakpoint (bp);
397
398 case raw_bkpt_type_hw:
399 case raw_bkpt_type_write_wp:
400 case raw_bkpt_type_access_wp:
401 default:
402 /* Unsupported. */
403 return 1;
404 }
405}
406
e9d25b98
DJ		 407/* Provide only a fill function for the general register set. ps_lgetregs
408 will use this for NPTL support. */
409
442ea881 410static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 411{
412 int i;
413
b35db733
TBA		 414 ppc_target *my_ppc_target = (ppc_target *) the_linux_target;
415
e9d25b98 416 for (i = 0; i < 32; i++)
b35db733
TBA		 417 my_ppc_target->low_collect_ptrace_register (regcache, i,
418 (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 419
420 for (i = 64; i < 70; i++)
b35db733
TBA		 421 my_ppc_target->low_collect_ptrace_register (regcache, i,
422 (char *) buf + ppc_regmap[i]);
7284e1be
UW		 423
424 for (i = 71; i < 73; i++)
b35db733
TBA		 425 my_ppc_target->low_collect_ptrace_register (regcache, i,
426 (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 427}
428
7ca18ed6
EBM		 429/* Program Priority Register regset fill function. */
430
431static void
432ppc_fill_pprregset (struct regcache *regcache, void *buf)
433{
434 char *ppr = (char *) buf;
435
436 collect_register_by_name (regcache, "ppr", ppr);
437}
438
439/* Program Priority Register regset store function. */
440
441static void
442ppc_store_pprregset (struct regcache *regcache, const void *buf)
443{
444 const char *ppr = (const char *) buf;
445
446 supply_register_by_name (regcache, "ppr", ppr);
447}
448
449/* Data Stream Control Register regset fill function. */
450
451static void
452ppc_fill_dscrregset (struct regcache *regcache, void *buf)
453{
454 char *dscr = (char *) buf;
455
456 collect_register_by_name (regcache, "dscr", dscr);
457}
458
459/* Data Stream Control Register regset store function. */
460
461static void
462ppc_store_dscrregset (struct regcache *regcache, const void *buf)
463{
464 const char *dscr = (const char *) buf;
465
466 supply_register_by_name (regcache, "dscr", dscr);
467}
468
f2cf6173
EBM		 469/* Target Address Register regset fill function. */
470
471static void
472ppc_fill_tarregset (struct regcache *regcache, void *buf)
473{
474 char *tar = (char *) buf;
475
476 collect_register_by_name (regcache, "tar", tar);
477}
478
479/* Target Address Register regset store function. */
480
481static void
482ppc_store_tarregset (struct regcache *regcache, const void *buf)
483{
484 const char *tar = (const char *) buf;
485
486 supply_register_by_name (regcache, "tar", tar);
487}
488
232bfb86
EBM		 489/* Event-Based Branching regset store function. Unless the inferior
490 has a perf event open, ptrace can return in error when reading and
491 writing to the regset, with ENODATA. For reading, the registers
492 will correctly show as unavailable. For writing, gdbserver
493 currently only caches any register writes from P and G packets and
494 the stub always tries to write all the regsets when resuming the
495 inferior, which would result in frequent warnings. For this
496 reason, we don't define a fill function. This also means that the
497 client-side regcache will be dirty if the user tries to write to
498 the EBB registers. G packets that the client sends to write to
499 unrelated registers will also include data for EBB registers, even
500 if they are unavailable. */
501
502static void
503ppc_store_ebbregset (struct regcache *regcache, const void *buf)
504{
505 const char *regset = (const char *) buf;
506
507 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
508 .dat file is BESCR, EBBHR, EBBRR. */
509 supply_register_by_name (regcache, "ebbrr", &regset[0]);
510 supply_register_by_name (regcache, "ebbhr", &regset[8]);
511 supply_register_by_name (regcache, "bescr", &regset[16]);
512}
513
514/* Performance Monitoring Unit regset fill function. */
515
516static void
517ppc_fill_pmuregset (struct regcache *regcache, void *buf)
518{
519 char *regset = (char *) buf;
520
521 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
522 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
523 collect_register_by_name (regcache, "siar", &regset[0]);
524 collect_register_by_name (regcache, "sdar", &regset[8]);
525 collect_register_by_name (regcache, "sier", &regset[16]);
526 collect_register_by_name (regcache, "mmcr2", &regset[24]);
527 collect_register_by_name (regcache, "mmcr0", &regset[32]);
528}
529
530/* Performance Monitoring Unit regset store function. */
531
532static void
533ppc_store_pmuregset (struct regcache *regcache, const void *buf)
534{
535 const char *regset = (const char *) buf;
536
537 supply_register_by_name (regcache, "siar", &regset[0]);
538 supply_register_by_name (regcache, "sdar", &regset[8]);
539 supply_register_by_name (regcache, "sier", &regset[16]);
540 supply_register_by_name (regcache, "mmcr2", &regset[24]);
541 supply_register_by_name (regcache, "mmcr0", &regset[32]);
542}
543
8d619c01
EBM		 544/* Hardware Transactional Memory special-purpose register regset fill
545 function. */
546
547static void
548ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
549{
550 int i, base;
551 char *regset = (char *) buf;
552
553 base = find_regno (regcache->tdesc, "tfhar");
554 for (i = 0; i < 3; i++)
555 collect_register (regcache, base + i, &regset[i * 8]);
556}
557
558/* Hardware Transactional Memory special-purpose register regset store
559 function. */
560
561static void
562ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
563{
564 int i, base;
565 const char *regset = (const char *) buf;
566
567 base = find_regno (regcache->tdesc, "tfhar");
568 for (i = 0; i < 3; i++)
569 supply_register (regcache, base + i, &regset[i * 8]);
570}
571
572/* For the same reasons as the EBB regset, none of the HTM
573 checkpointed regsets have a fill function. These registers are
574 only available if the inferior is in a transaction. */
575
576/* Hardware Transactional Memory checkpointed general-purpose regset
577 store function. */
578
579static void
580ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
581{
582 int i, base, size, endian_offset;
583 const char *regset = (const char *) buf;
584
585 base = find_regno (regcache->tdesc, "cr0");
586 size = register_size (regcache->tdesc, base);
587
588 gdb_assert (size == 4 || size == 8);
589
590 for (i = 0; i < 32; i++)
591 supply_register (regcache, base + i, &regset[i * size]);
592
593 endian_offset = 0;
594
595 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
596 endian_offset = 4;
597
598 supply_register_by_name (regcache, "ccr",
599 &regset[PT_CCR * size + endian_offset]);
600
601 supply_register_by_name (regcache, "cxer",
602 &regset[PT_XER * size + endian_offset]);
603
604 supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
605 supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
606}
607
608/* Hardware Transactional Memory checkpointed floating-point regset
609 store function. */
610
611static void
612ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
613{
614 int i, base;
615 const char *regset = (const char *) buf;
616
617 base = find_regno (regcache->tdesc, "cf0");
618
619 for (i = 0; i < 32; i++)
620 supply_register (regcache, base + i, &regset[i * 8]);
621
622 supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
623}
624
625/* Hardware Transactional Memory checkpointed vector regset store
626 function. */
627
628static void
629ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
630{
631 int i, base;
632 const char *regset = (const char *) buf;
633 int vscr_offset = 0;
634
635 base = find_regno (regcache->tdesc, "cvr0");
636
637 for (i = 0; i < 32; i++)
638 supply_register (regcache, base + i, &regset[i * 16]);
639
640 if (__BYTE_ORDER == __BIG_ENDIAN)
641 vscr_offset = 12;
642
643 supply_register_by_name (regcache, "cvscr",
644 &regset[32 * 16 + vscr_offset]);
645
646 supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
647}
648
649/* Hardware Transactional Memory checkpointed vector-scalar regset
650 store function. */
651
652static void
653ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
654{
655 int i, base;
656 const char *regset = (const char *) buf;
657
658 base = find_regno (regcache->tdesc, "cvs0h");
659 for (i = 0; i < 32; i++)
660 supply_register (regcache, base + i, &regset[i * 8]);
661}
662
663/* Hardware Transactional Memory checkpointed Program Priority
664 Register regset store function. */
665
666static void
667ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
668{
669 const char *cppr = (const char *) buf;
670
671 supply_register_by_name (regcache, "cppr", cppr);
672}
673
674/* Hardware Transactional Memory checkpointed Data Stream Control
675 Register regset store function. */
676
677static void
678ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
679{
680 const char *cdscr = (const char *) buf;
681
682 supply_register_by_name (regcache, "cdscr", cdscr);
683}
684
685/* Hardware Transactional Memory checkpointed Target Address Register
686 regset store function. */
687
688static void
689ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
690{
691 const char *ctar = (const char *) buf;
692
693 supply_register_by_name (regcache, "ctar", ctar);
694}
695
677c5bb1 696static void
442ea881 697ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 698{
699 int i, base;
2bc84e8a 700 char *regset = (char *) buf;
677c5bb1 701
3aee8918 702 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 703 for (i = 0; i < 32; i++)
442ea881 704 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 705}
706
707static void
442ea881 708ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 709{
710 int i, base;
2bc84e8a 711 const char *regset = (const char *) buf;
677c5bb1 712
3aee8918 713 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 714 for (i = 0; i < 32; i++)
442ea881 715 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 716}
717
30ed0a8f 718static void
442ea881 719ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 720{
721 int i, base;
2bc84e8a 722 char *regset = (char *) buf;
1d75a658 723 int vscr_offset = 0;
30ed0a8f 724
3aee8918 725 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 726 for (i = 0; i < 32; i++)
442ea881 727 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 728
1d75a658
PFC		 729 if (__BYTE_ORDER == __BIG_ENDIAN)
730 vscr_offset = 12;
731
1d75a658
PFC		 732 collect_register_by_name (regcache, "vscr",
733 &regset[32 * 16 + vscr_offset]);
734
442ea881 735 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 736}
737
738static void
442ea881 739ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 740{
741 int i, base;
2bc84e8a 742 const char *regset = (const char *) buf;
1d75a658 743 int vscr_offset = 0;
30ed0a8f 744
3aee8918 745 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 746 for (i = 0; i < 32; i++)
442ea881 747 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 748
1d75a658
PFC		 749 if (__BYTE_ORDER == __BIG_ENDIAN)
750 vscr_offset = 12;
751
752 supply_register_by_name (regcache, "vscr",
753 &regset[32 * 16 + vscr_offset]);
442ea881 754 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 755}
756
30ed0a8f
DJ		 757struct gdb_evrregset_t
758{
759 unsigned long evr[32];
760 unsigned long long acc;
761 unsigned long spefscr;
762};
763
764static void
442ea881 765ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 766{
767 int i, ev0;
2bc84e8a 768 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 769
3aee8918 770 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 771 for (i = 0; i < 32; i++)
442ea881 772 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 773
442ea881
PA		 774 collect_register_by_name (regcache, "acc", &regset->acc);
775 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 776}
777
778static void
442ea881 779ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 780{
781 int i, ev0;
2bc84e8a 782 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 783
3aee8918 784 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 785 for (i = 0; i < 32; i++)
442ea881 786 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 787
442ea881
PA		 788 supply_register_by_name (regcache, "acc", &regset->acc);
789 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 790}
30ed0a8f 791
7d00775e
AT		 792/* Support for hardware single step. */
793
794static int
795ppc_supports_hardware_single_step (void)
796{
797 return 1;
798}
799
3aee8918 800static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 801 /* List the extra register sets before GENERAL_REGS. That way we will
802 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
803 general registers. Some kernels support these, but not the newer
804 PPC_PTRACE_GETREGS. */
8d619c01
EBM		 805 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
806 NULL, ppc_store_tm_ctarregset },
807 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
808 NULL, ppc_store_tm_cdscrregset },
809 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
810 NULL, ppc_store_tm_cpprregset },
811 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
812 NULL, ppc_store_tm_cvsxregset },
813 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
814 NULL, ppc_store_tm_cvrregset },
815 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
816 NULL, ppc_store_tm_cfprregset },
817 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
818 NULL, ppc_store_tm_cgprregset },
819 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
820 ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
232bfb86
EBM		 821 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
822 NULL, ppc_store_ebbregset },
823 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
824 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 825 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
826 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 827 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
828 ppc_fill_pprregset, ppc_store_pprregset },
829 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
830 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 831 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 832 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 833 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 834 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 835 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 836 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 837 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 838 NULL_REGSET
e9d25b98
DJ		 839};
840
3aee8918
PA		 841static struct usrregs_info ppc_usrregs_info =
842 {
843 ppc_num_regs,
844 ppc_regmap,
845 };
846
847static struct regsets_info ppc_regsets_info =
848 {
849 ppc_regsets, /* regsets */
850 0, /* num_regsets */
851 NULL, /* disabled_regsets */
852 };
853
aa8d21c9 854static struct regs_info myregs_info =
3aee8918
PA		 855 {
856 NULL, /* regset_bitmap */
857 &ppc_usrregs_info,
858 &ppc_regsets_info
859 };
860
aa8d21c9
TBA		 861const regs_info *
862ppc_target::get_regs_info ()
3aee8918 863{
aa8d21c9 864 return &myregs_info;
3aee8918
PA		 865}
866
797bcff5
TBA		 867void
868ppc_target::low_arch_setup ()
e6c5bb05
SM		 869{
870 const struct target_desc *tdesc;
7273b5fc 871 struct regset_info *regset;
bd64614e 872 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 873
2e077f5e 874 int tid = lwpid_of (current_thread);
bd64614e 875
2e077f5e 876 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 877
bd64614e 878 if (features.wordsize == 4)
bd64614e 879 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 880 else
881 tdesc = tdesc_powerpc_64l;
882
883 current_process ()->tdesc = tdesc;
e6c5bb05 884
bd64614e
PFC		 885 /* The value of current_process ()->tdesc needs to be set for this
886 call. */
974c89e0
AH		 887 ppc_hwcap = linux_get_hwcap (features.wordsize);
888 ppc_hwcap2 = linux_get_hwcap2 (features.wordsize);
bd64614e
PFC		 889
890 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
891
892 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
893 features.vsx = true;
894
895 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
896 features.altivec = true;
897
7ca18ed6
EBM		 898 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
899 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
900 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 901 {
902 features.ppr_dscr = true;
903 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
904 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 905 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 906 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 907 PPC_LINUX_SIZEOF_TARREGSET)
908 && ppc_check_regset (tid, NT_PPC_EBB,
909 PPC_LINUX_SIZEOF_EBBREGSET)
910 && ppc_check_regset (tid, NT_PPC_PMU,
911 PPC_LINUX_SIZEOF_PMUREGSET))
8d619c01
EBM		 912 {
913 features.isa207 = true;
914 if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
915 && ppc_check_regset (tid, NT_PPC_TM_SPR,
916 PPC_LINUX_SIZEOF_TM_SPRREGSET))
917 features.htm = true;
918 }
f2cf6173 919 }
7ca18ed6 920
bd64614e 921 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 922
923 /* On 32-bit machines, check for SPE registers.
924 Set the low target's regmap field as appropriately. */
925#ifndef __powerpc64__
926 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
927 tdesc = tdesc_powerpc_e500l;
928
929 if (!ppc_regmap_adjusted)
930 {
931 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
932 ppc_usrregs_info.regmap = ppc_regmap_e500;
933
934 /* If the FPSCR is 64-bit wide, we need to fetch the whole
935 64-bit slot and not just its second word. The PT_FPSCR
936 supplied in a 32-bit GDB compilation doesn't reflect
937 this. */
938 if (register_size (tdesc, 70) == 8)
939 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
940
941 ppc_regmap_adjusted = 1;
942 }
943#endif
bd64614e 944
e6c5bb05 945 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 946
947 for (regset = ppc_regsets; regset->size >= 0; regset++)
948 switch (regset->get_request)
949 {
950 case PTRACE_GETVRREGS:
d078308a 951 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 952 break;
953 case PTRACE_GETVSXREGS:
d078308a 954 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 955 break;
956 case PTRACE_GETEVRREGS:
957 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
958 regset->size = 32 * 4 + 8 + 4;
959 else
960 regset->size = 0;
961 break;
7ca18ed6
EBM		 962 case PTRACE_GETREGSET:
963 switch (regset->nt_type)
964 {
965 case NT_PPC_PPR:
966 regset->size = (features.ppr_dscr ?
967 PPC_LINUX_SIZEOF_PPRREGSET : 0);
968 break;
969 case NT_PPC_DSCR:
970 regset->size = (features.ppr_dscr ?
971 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
972 break;
f2cf6173
EBM		 973 case NT_PPC_TAR:
974 regset->size = (features.isa207 ?
975 PPC_LINUX_SIZEOF_TARREGSET : 0);
976 break;
232bfb86
EBM		 977 case NT_PPC_EBB:
978 regset->size = (features.isa207 ?
979 PPC_LINUX_SIZEOF_EBBREGSET : 0);
980 break;
981 case NT_PPC_PMU:
982 regset->size = (features.isa207 ?
983 PPC_LINUX_SIZEOF_PMUREGSET : 0);
984 break;
8d619c01
EBM		 985 case NT_PPC_TM_SPR:
986 regset->size = (features.htm ?
987 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
988 break;
989 case NT_PPC_TM_CGPR:
990 if (features.wordsize == 4)
991 regset->size = (features.htm ?
992 PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
993 else
994 regset->size = (features.htm ?
995 PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
996 break;
997 case NT_PPC_TM_CFPR:
998 regset->size = (features.htm ?
999 PPC_LINUX_SIZEOF_CFPRREGSET : 0);
1000 break;
1001 case NT_PPC_TM_CVMX:
1002 regset->size = (features.htm ?
1003 PPC_LINUX_SIZEOF_CVMXREGSET : 0);
1004 break;
1005 case NT_PPC_TM_CVSX:
1006 regset->size = (features.htm ?
1007 PPC_LINUX_SIZEOF_CVSXREGSET : 0);
1008 break;
1009 case NT_PPC_TM_CPPR:
1010 regset->size = (features.htm ?
1011 PPC_LINUX_SIZEOF_CPPRREGSET : 0);
1012 break;
1013 case NT_PPC_TM_CDSCR:
1014 regset->size = (features.htm ?
1015 PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
1016 break;
1017 case NT_PPC_TM_CTAR:
1018 regset->size = (features.htm ?
1019 PPC_LINUX_SIZEOF_CTARREGSET : 0);
1020 break;
7ca18ed6
EBM		 1021 default:
1022 break;
1023 }
1024 break;
7273b5fc
PFC		 1025 default:
1026 break;
1027 }
e6c5bb05
SM		 1028}
1029
47f70aa7 1030/* Implementation of target ops method "supports_tracepoints". */
a2174ba4 1031
47f70aa7
TBA		 1032bool
1033ppc_target::supports_tracepoints ()
b04fd3be 1034{
47f70aa7 1035 return true;
b04fd3be
MK		 1036}
1037
a2174ba4
MK		 1038/* Get the thread area address. This is used to recognize which
1039 thread is which when tracing with the in-process agent library. We
1040 don't read anything from the address, and treat it as opaque; it's
1041 the address itself that we assume is unique per-thread. */
1042
1043static int
1044ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
1045{
f2907e49 1046 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 1047 struct thread_info *thr = get_lwp_thread (lwp);
1048 struct regcache *regcache = get_thread_regcache (thr, 1);
1049 ULONGEST tp = 0;
1050
1051#ifdef __powerpc64__
1052 if (register_size (regcache->tdesc, 0) == 8)
1053 collect_register_by_name (regcache, "r13", &tp);
1054 else
1055#endif
1056 collect_register_by_name (regcache, "r2", &tp);
1057
1058 *addr = tp;
1059
1060 return 0;
1061}
1062
1063#ifdef __powerpc64__
1064
1065/* Older glibc doesn't provide this. */
1066
1067#ifndef EF_PPC64_ABI
1068#define EF_PPC64_ABI 3
1069#endif
1070
1071/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1072 inferiors. */
1073
1074static int
1075is_elfv2_inferior (void)
1076{
1077 /* To be used as fallback if we're unable to determine the right result -
1078 assume inferior uses the same ABI as gdbserver. */
1079#if _CALL_ELF == 2
1080 const int def_res = 1;
1081#else
1082 const int def_res = 0;
1083#endif
0570503d 1084 CORE_ADDR phdr;
a2174ba4
MK		 1085 Elf64_Ehdr ehdr;
1086
0570503d
PFC		 1087 const struct target_desc *tdesc = current_process ()->tdesc;
1088 int wordsize = register_size (tdesc, 0);
1089
1090 if (!linux_get_auxv (wordsize, AT_PHDR, &phdr))
a2174ba4
MK		 1091 return def_res;
1092
1093 /* Assume ELF header is at the beginning of the page where program headers
1094 are located. If it doesn't look like one, bail. */
1095
1096 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
1097 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
1098 return def_res;
1099
1100 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
1101}
1102
1103#endif
1104
1105/* Generate a ds-form instruction in BUF and return the number of bytes written
1106
1107 0 6 11 16 30 32
1108 | OPCD | RST | RA | DS |XO| */
1109
1110__attribute__((unused)) /* Maybe unused due to conditional compilation. */
1111static int
1112gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
1113{
1114 uint32_t insn;
1115
1116 gdb_assert ((opcd & ~0x3f) == 0);
1117 gdb_assert ((rst & ~0x1f) == 0);
1118 gdb_assert ((ra & ~0x1f) == 0);
1119 gdb_assert ((xo & ~0x3) == 0);
1120
1121 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
1122 *buf = (opcd << 26) | insn;
1123 return 1;
1124}
1125
1126/* Followings are frequently used ds-form instructions. */
1127
1128#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1129#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1130#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1131#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1132
1133/* Generate a d-form instruction in BUF.
1134
1135 0 6 11 16 32
1136 | OPCD | RST | RA | D | */
1137
1138static int
1139gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
1140{
1141 uint32_t insn;
1142
1143 gdb_assert ((opcd & ~0x3f) == 0);
1144 gdb_assert ((rst & ~0x1f) == 0);
1145 gdb_assert ((ra & ~0x1f) == 0);
1146
1147 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
1148 *buf = (opcd << 26) | insn;
1149 return 1;
1150}
1151
1152/* Followings are frequently used d-form instructions. */
1153
1154#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1155#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1156#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1157#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1158#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1159#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1160#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1161#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1162#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1163
1164/* Generate a xfx-form instruction in BUF and return the number of bytes
1165 written.
1166
1167 0 6 11 21 31 32
1168 | OPCD | RST | RI | XO |/| */
1169
1170static int
1171gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1172{
1173 uint32_t insn;
1174 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1175
1176 gdb_assert ((opcd & ~0x3f) == 0);
1177 gdb_assert ((rst & ~0x1f) == 0);
1178 gdb_assert ((xo & ~0x3ff) == 0);
1179
1180 insn = (rst << 21) | (n << 11) | (xo << 1);
1181 *buf = (opcd << 26) | insn;
1182 return 1;
1183}
1184
1185/* Followings are frequently used xfx-form instructions. */
1186
1187#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1188#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1189#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1190#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1191#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1192 E & 0xf, 598)
1193#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1194
1195
1196/* Generate a x-form instruction in BUF and return the number of bytes written.
1197
1198 0 6 11 16 21 31 32
1199 | OPCD | RST | RA | RB | XO |RC| */
1200
1201static int
1202gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1203{
1204 uint32_t insn;
1205
1206 gdb_assert ((opcd & ~0x3f) == 0);
1207 gdb_assert ((rst & ~0x1f) == 0);
1208 gdb_assert ((ra & ~0x1f) == 0);
1209 gdb_assert ((rb & ~0x1f) == 0);
1210 gdb_assert ((xo & ~0x3ff) == 0);
1211 gdb_assert ((rc & ~1) == 0);
1212
1213 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1214 *buf = (opcd << 26) | insn;
1215 return 1;
1216}
1217
1218/* Followings are frequently used x-form instructions. */
1219
1220#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1221#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1222#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1223#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1224/* Assume bf = cr7. */
1225#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1226
1227
1228/* Generate a md-form instruction in BUF and return the number of bytes written.
1229
1230 0 6 11 16 21 27 30 31 32
1231 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1232
1233static int
1234gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1235 int xo, int rc)
1236{
1237 uint32_t insn;
1238 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1239 unsigned int sh0_4 = sh & 0x1f;
1240 unsigned int sh5 = (sh >> 5) & 1;
1241
1242 gdb_assert ((opcd & ~0x3f) == 0);
1243 gdb_assert ((rs & ~0x1f) == 0);
1244 gdb_assert ((ra & ~0x1f) == 0);
1245 gdb_assert ((sh & ~0x3f) == 0);
1246 gdb_assert ((mb & ~0x3f) == 0);
1247 gdb_assert ((xo & ~0x7) == 0);
1248 gdb_assert ((rc & ~0x1) == 0);
1249
1250 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1251 | (sh5 << 1) | (xo << 2) | (rc & 1);
1252 *buf = (opcd << 26) | insn;
1253 return 1;
1254}
1255
1256/* The following are frequently used md-form instructions. */
1257
1258#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1259 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1260#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1261 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1262
1263/* Generate a i-form instruction in BUF and return the number of bytes written.
1264
1265 0 6 30 31 32
1266 | OPCD | LI |AA|LK| */
1267
1268static int
1269gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1270{
1271 uint32_t insn;
1272
1273 gdb_assert ((opcd & ~0x3f) == 0);
1274
1275 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1276 *buf = (opcd << 26) | insn;
1277 return 1;
1278}
1279
1280/* The following are frequently used i-form instructions. */
1281
1282#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1283#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1284
1285/* Generate a b-form instruction in BUF and return the number of bytes written.
1286
1287 0 6 11 16 30 31 32
1288 | OPCD | BO | BI | BD |AA|LK| */
1289
1290static int
1291gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1292 int aa, int lk)
1293{
1294 uint32_t insn;
1295
1296 gdb_assert ((opcd & ~0x3f) == 0);
1297 gdb_assert ((bo & ~0x1f) == 0);
1298 gdb_assert ((bi & ~0x1f) == 0);
1299
1300 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1301 *buf = (opcd << 26) | insn;
1302 return 1;
1303}
1304
1305/* The following are frequently used b-form instructions. */
1306/* Assume bi = cr7. */
1307#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1308
1309/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1310 respectively. They are primary used for save/restore GPRs in jump-pad,
1311 not used for bytecode compiling. */
1312
1313#ifdef __powerpc64__
1314#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1315 GEN_LD (buf, rt, ra, si) : \
1316 GEN_LWZ (buf, rt, ra, si))
1317#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1318 GEN_STD (buf, rt, ra, si) : \
1319 GEN_STW (buf, rt, ra, si))
1320#else
1321#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1322#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1323#endif
1324
1325/* Generate a sequence of instructions to load IMM in the register REG.
1326 Write the instructions in BUF and return the number of bytes written. */
1327
1328static int
1329gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1330{
1331 uint32_t *p = buf;
1332
1333 if ((imm + 32768) < 65536)
1334 {
1335 /* li reg, imm[15:0] */
1336 p += GEN_LI (p, reg, imm);
1337 }
1338 else if ((imm >> 32) == 0)
1339 {
1340 /* lis reg, imm[31:16]
1341 ori reg, reg, imm[15:0]
1342 rldicl reg, reg, 0, 32 */
1343 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1344 if ((imm & 0xffff) != 0)
1345 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1346 /* Clear upper 32-bit if sign-bit is set. */
1347 if (imm & (1u << 31) && is_64)
1348 p += GEN_RLDICL (p, reg, reg, 0, 32);
1349 }
1350 else
1351 {
1352 gdb_assert (is_64);
1353 /* lis reg, <imm[63:48]>
1354 ori reg, reg, <imm[48:32]>
1355 rldicr reg, reg, 32, 31
1356 oris reg, reg, <imm[31:16]>
1357 ori reg, reg, <imm[15:0]> */
1358 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1359 if (((imm >> 32) & 0xffff) != 0)
1360 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1361 p += GEN_RLDICR (p, reg, reg, 32, 31);
1362 if (((imm >> 16) & 0xffff) != 0)
1363 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1364 if ((imm & 0xffff) != 0)
1365 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1366 }
1367
1368 return p - buf;
1369}
1370
1371/* Generate a sequence for atomically exchange at location LOCK.
1372 This code sequence clobbers r6, r7, r8. LOCK is the location for
1373 the atomic-xchg, OLD_VALUE is expected old value stored in the
1374 location, and R_NEW is a register for the new value. */
1375
1376static int
1377gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1378 int is_64)
1379{
1380 const int r_lock = 6;
1381 const int r_old = 7;
1382 const int r_tmp = 8;
1383 uint32_t *p = buf;
1384
1385 /*
1386 1: lwarx TMP, 0, LOCK
1387 cmpwi TMP, OLD
1388 bne 1b
1389 stwcx. NEW, 0, LOCK
1390 bne 1b */
1391
1392 p += gen_limm (p, r_lock, lock, is_64);
1393 p += gen_limm (p, r_old, old_value, is_64);
1394
1395 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1396 p += GEN_CMPW (p, r_tmp, r_old);
1397 p += GEN_BNE (p, -8);
1398 p += GEN_STWCX (p, r_new, 0, r_lock);
1399 p += GEN_BNE (p, -16);
1400
1401 return p - buf;
1402}
1403
1404/* Generate a sequence of instructions for calling a function
1405 at address of FN. Return the number of bytes are written in BUF. */
1406
1407static int
1408gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1409{
1410 uint32_t *p = buf;
1411
1412 /* Must be called by r12 for caller to calculate TOC address. */
1413 p += gen_limm (p, 12, fn, is_64);
1414 if (is_opd)
1415 {
1416 p += GEN_LOAD (p, 11, 12, 16, is_64);
1417 p += GEN_LOAD (p, 2, 12, 8, is_64);
1418 p += GEN_LOAD (p, 12, 12, 0, is_64);
1419 }
1420 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1421 *p++ = 0x4e800421; /* bctrl */
1422
1423 return p - buf;
1424}
1425
1426/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1427 of instruction. This function is used to adjust pc-relative instructions
1428 when copying. */
1429
1430static void
1431ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1432{
1433 uint32_t insn, op6;
1434 long rel, newrel;
1435
1436 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1437 op6 = PPC_OP6 (insn);
1438
1439 if (op6 == 18 && (insn & 2) == 0)
1440 {
1441 /* branch && AA = 0 */
1442 rel = PPC_LI (insn);
1443 newrel = (oldloc - *to) + rel;
1444
1445 /* Out of range. Cannot relocate instruction. */
1446 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1447 return;
1448
1449 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1450 }
1451 else if (op6 == 16 && (insn & 2) == 0)
1452 {
1453 /* conditional branch && AA = 0 */
1454
1455 /* If the new relocation is too big for even a 26-bit unconditional
1456 branch, there is nothing we can do. Just abort.
1457
1458 Otherwise, if it can be fit in 16-bit conditional branch, just
1459 copy the instruction and relocate the address.
1460
1461 If the it's big for conditional-branch (16-bit), try to invert the
1462 condition and jump with 26-bit branch. For example,
1463
1464 beq .Lgoto
1465 INSN1
1466
1467 =>
1468
1469 bne 1f (+8)
1470 b .Lgoto
1471 1:INSN1
1472
1473 After this transform, we are actually jump from *TO+4 instead of *TO,
1474 so check the relocation again because it will be 1-insn farther then
1475 before if *TO is after OLDLOC.
1476
1477
1478 For BDNZT (or so) is transformed from
1479
1480 bdnzt eq, .Lgoto
1481 INSN1
1482
1483 =>
1484
1485 bdz 1f (+12)
1486 bf eq, 1f (+8)
1487 b .Lgoto
1488 1:INSN1
1489
1490 See also "BO field encodings". */
1491
1492 rel = PPC_BD (insn);
1493 newrel = (oldloc - *to) + rel;
1494
1495 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1496 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1497 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1498 {
1499 newrel -= 4;
1500
1501 /* Out of range. Cannot relocate instruction. */
1502 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1503 return;
1504
1505 if ((PPC_BO (insn) & 0x14) == 0x4)
1506 insn ^= (1 << 24);
1507 else if ((PPC_BO (insn) & 0x14) == 0x10)
1508 insn ^= (1 << 22);
1509
1510 /* Jump over the unconditional branch. */
1511 insn = (insn & ~0xfffc) | 0x8;
4196ab2a 1512 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1513 *to += 4;
1514
1515 /* Build a unconditional branch and copy LK bit. */
1516 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1517 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1518 *to += 4;
1519
1520 return;
1521 }
1522 else if ((PPC_BO (insn) & 0x14) == 0)
1523 {
1524 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1525 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1526
1527 newrel -= 8;
1528
1529 /* Out of range. Cannot relocate instruction. */
1530 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1531 return;
1532
1533 /* Copy BI field. */
1534 bf_insn |= (insn & 0x1f0000);
1535
1536 /* Invert condition. */
1537 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1538 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1539
4196ab2a 1540 target_write_memory (*to, (unsigned char *) &bdnz_insn, 4);
a2174ba4 1541 *to += 4;
4196ab2a 1542 target_write_memory (*to, (unsigned char *) &bf_insn, 4);
a2174ba4
MK		 1543 *to += 4;
1544
1545 /* Build a unconditional branch and copy LK bit. */
1546 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1547 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1548 *to += 4;
1549
1550 return;
1551 }
1552 else /* (BO & 0x14) == 0x14, branch always. */
1553 {
1554 /* Out of range. Cannot relocate instruction. */
1555 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1556 return;
1557
1558 /* Build a unconditional branch and copy LK bit. */
1559 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1560 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1561 *to += 4;
1562
1563 return;
1564 }
1565 }
1566
4196ab2a 1567 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1568 *to += 4;
1569}
1570
1571/* Implement install_fast_tracepoint_jump_pad of target_ops.
1572 See target.h for details. */
1573
1574static int
1575ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1576 CORE_ADDR collector,
1577 CORE_ADDR lockaddr,
1578 ULONGEST orig_size,
1579 CORE_ADDR *jump_entry,
1580 CORE_ADDR *trampoline,
1581 ULONGEST *trampoline_size,
1582 unsigned char *jjump_pad_insn,
1583 ULONGEST *jjump_pad_insn_size,
1584 CORE_ADDR *adjusted_insn_addr,
1585 CORE_ADDR *adjusted_insn_addr_end,
1586 char *err)
1587{
1588 uint32_t buf[256];
1589 uint32_t *p = buf;
1590 int j, offset;
1591 CORE_ADDR buildaddr = *jump_entry;
1592 const CORE_ADDR entryaddr = *jump_entry;
1593 int rsz, min_frame, frame_size, tp_reg;
1594#ifdef __powerpc64__
1595 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1596 int is_64 = register_size (regcache->tdesc, 0) == 8;
1597 int is_opd = is_64 && !is_elfv2_inferior ();
1598#else
1599 int is_64 = 0, is_opd = 0;
1600#endif
1601
1602#ifdef __powerpc64__
1603 if (is_64)
1604 {
1605 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1606 rsz = 8;
1607 min_frame = 112;
1608 frame_size = (40 * rsz) + min_frame;
1609 tp_reg = 13;
1610 }
1611 else
1612 {
1613#endif
1614 rsz = 4;
1615 min_frame = 16;
1616 frame_size = (40 * rsz) + min_frame;
1617 tp_reg = 2;
1618#ifdef __powerpc64__
1619 }
1620#endif
1621
1622 /* Stack frame layout for this jump pad,
1623
1624 High thread_area (r13/r2) |
1625 tpoint - collecting_t obj
1626 PC/<tpaddr> | +36
1627 CTR | +35
1628 LR | +34
1629 XER | +33
1630 CR | +32
1631 R31 |
1632 R29 |
1633 ... |
1634 R1 | +1
1635 R0 - collected registers
1636 ... |
1637 ... |
1638 Low Back-chain -
1639
1640
1641 The code flow of this jump pad,
1642
1643 1. Adjust SP
1644 2. Save GPR and SPR
1645 3. Prepare argument
1646 4. Call gdb_collector
1647 5. Restore GPR and SPR
1648 6. Restore SP
1649 7. Build a jump for back to the program
1650 8. Copy/relocate original instruction
30baf67b 1651 9. Build a jump for replacing original instruction. */
a2174ba4
MK		 1652
1653 /* Adjust stack pointer. */
1654 if (is_64)
1655 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1656 else
1657 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1658
1659 /* Store GPRs. Save R1 later, because it had just been modified, but
1660 we want the original value. */
1661 for (j = 2; j < 32; j++)
1662 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1663 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1664 /* Set r0 to the original value of r1 before adjusting stack frame,
1665 and then save it. */
1666 p += GEN_ADDI (p, 0, 1, frame_size);
1667 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1668
1669 /* Save CR, XER, LR, and CTR. */
1670 p += GEN_MFCR (p, 3); /* mfcr r3 */
1671 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1672 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1673 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1674 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1675 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1676 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1677 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1678
1679 /* Save PC<tpaddr> */
1680 p += gen_limm (p, 3, tpaddr, is_64);
1681 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1682
1683
1684 /* Setup arguments to collector. */
1685 /* Set r4 to collected registers. */
1686 p += GEN_ADDI (p, 4, 1, min_frame);
1687 /* Set r3 to TPOINT. */
1688 p += gen_limm (p, 3, tpoint, is_64);
1689
1690 /* Prepare collecting_t object for lock. */
1691 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1692 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1693 /* Set R5 to collecting object. */
1694 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1695
1696 p += GEN_LWSYNC (p);
1697 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1698 p += GEN_LWSYNC (p);
1699
1700 /* Call to collector. */
1701 p += gen_call (p, collector, is_64, is_opd);
1702
1703 /* Simply write 0 to release the lock. */
1704 p += gen_limm (p, 3, lockaddr, is_64);
1705 p += gen_limm (p, 4, 0, is_64);
1706 p += GEN_LWSYNC (p);
1707 p += GEN_STORE (p, 4, 3, 0, is_64);
1708
1709 /* Restore stack and registers. */
1710 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1711 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1712 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1713 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1714 p += GEN_MTCR (p, 3); /* mtcr r3 */
1715 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1716 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1717 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1718
1719 /* Restore GPRs. */
1720 for (j = 2; j < 32; j++)
1721 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1722 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1723 /* Restore SP. */
1724 p += GEN_ADDI (p, 1, 1, frame_size);
1725
1726 /* Flush instructions to inferior memory. */
4196ab2a 1727 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1728
1729 /* Now, insert the original instruction to execute in the jump pad. */
1730 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1731 *adjusted_insn_addr_end = *adjusted_insn_addr;
1732 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1733
1734 /* Verify the relocation size. If should be 4 for normal copy,
1735 8 or 12 for some conditional branch. */
1736 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1737 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1738 {
1739 sprintf (err, "E.Unexpected instruction length = %d"
1740 "when relocate instruction.",
1741 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1742 return 1;
1743 }
1744
1745 buildaddr = *adjusted_insn_addr_end;
1746 p = buf;
1747 /* Finally, write a jump back to the program. */
1748 offset = (tpaddr + 4) - buildaddr;
1749 if (offset >= (1 << 25) || offset < -(1 << 25))
1750 {
1751 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1752 "(offset 0x%x > 26-bit).", offset);
1753 return 1;
1754 }
1755 /* b <tpaddr+4> */
1756 p += GEN_B (p, offset);
4196ab2a 1757 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1758 *jump_entry = buildaddr + (p - buf) * 4;
1759
1760 /* The jump pad is now built. Wire in a jump to our jump pad. This
1761 is always done last (by our caller actually), so that we can
1762 install fast tracepoints with threads running. This relies on
1763 the agent's atomic write support. */
1764 offset = entryaddr - tpaddr;
1765 if (offset >= (1 << 25) || offset < -(1 << 25))
1766 {
1767 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1768 "(offset 0x%x > 26-bit).", offset);
1769 return 1;
1770 }
1771 /* b <jentry> */
1772 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1773 *jjump_pad_insn_size = 4;
1774
1775 return 0;
1776}
1777
1778/* Returns the minimum instruction length for installing a tracepoint. */
1779
1780static int
1781ppc_get_min_fast_tracepoint_insn_len (void)
1782{
1783 return 4;
1784}
1785
14e2b6d9
MK		 1786/* Emits a given buffer into the target at current_insn_ptr. Length
1787 is in units of 32-bit words. */
1788
1789static void
1790emit_insns (uint32_t *buf, int n)
1791{
1792 n = n * sizeof (uint32_t);
4196ab2a 1793 target_write_memory (current_insn_ptr, (unsigned char *) buf, n);
14e2b6d9
MK		 1794 current_insn_ptr += n;
1795}
1796
1797#define __EMIT_ASM(NAME, INSNS) \
1798 do \
1799 { \
1800 extern uint32_t start_bcax_ ## NAME []; \
1801 extern uint32_t end_bcax_ ## NAME []; \
1802 emit_insns (start_bcax_ ## NAME, \
1803 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1804 __asm__ (".section .text.__ppcbcax\n\t" \
1805 "start_bcax_" #NAME ":\n\t" \
1806 INSNS "\n\t" \
1807 "end_bcax_" #NAME ":\n\t" \
1808 ".previous\n\t"); \
1809 } while (0)
1810
1811#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1812#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1813
1814/*
1815
1816 Bytecode execution stack frame - 32-bit
1817
1818 | LR save area (SP + 4)
1819 SP' -> +- Back chain (SP + 0)
1820 | Save r31 for access saved arguments
1821 | Save r30 for bytecode stack pointer
1822 | Save r4 for incoming argument *value
1823 | Save r3 for incoming argument regs
1824 r30 -> +- Bytecode execution stack
1825 |
1826 | 64-byte (8 doublewords) at initial.
1827 | Expand stack as needed.
1828 |
1829 +-
1830 | Some padding for minimum stack frame and 16-byte alignment.
1831 | 16 bytes.
1832 SP +- Back-chain (SP')
1833
1834 initial frame size
1835 = 16 + (4 * 4) + 64
1836 = 96
1837
1838 r30 is the stack-pointer for bytecode machine.
1839 It should point to next-empty, so we can use LDU for pop.
1840 r3 is used for cache of the high part of TOP value.
1841 It was the first argument, pointer to regs.
1842 r4 is used for cache of the low part of TOP value.
1843 It was the second argument, pointer to the result.
1844 We should set *result = TOP after leaving this function.
1845
1846 Note:
1847 * To restore stack at epilogue
1848 => sp = r31
1849 * To check stack is big enough for bytecode execution.
1850 => r30 - 8 > SP + 8
1851 * To return execution result.
1852 => 0(r4) = TOP
1853
1854 */
1855
1856/* Regardless of endian, register 3 is always high part, 4 is low part.
1857 These defines are used when the register pair is stored/loaded.
1858 Likewise, to simplify code, have a similiar define for 5:6. */
1859
1860#if __BYTE_ORDER == __LITTLE_ENDIAN
1861#define TOP_FIRST "4"
1862#define TOP_SECOND "3"
1863#define TMP_FIRST "6"
1864#define TMP_SECOND "5"
1865#else
1866#define TOP_FIRST "3"
1867#define TOP_SECOND "4"
1868#define TMP_FIRST "5"
1869#define TMP_SECOND "6"
1870#endif
1871
1872/* Emit prologue in inferior memory. See above comments. */
1873
1874static void
1875ppc_emit_prologue (void)
1876{
1877 EMIT_ASM (/* Save return address. */
1878 "mflr 0 \n"
1879 "stw 0, 4(1) \n"
1880 /* Adjust SP. 96 is the initial frame size. */
1881 "stwu 1, -96(1) \n"
1882 /* Save r30 and incoming arguments. */
1883 "stw 31, 96-4(1) \n"
1884 "stw 30, 96-8(1) \n"
1885 "stw 4, 96-12(1) \n"
1886 "stw 3, 96-16(1) \n"
1887 /* Point r31 to original r1 for access arguments. */
1888 "addi 31, 1, 96 \n"
1889 /* Set r30 to pointing stack-top. */
1890 "addi 30, 1, 64 \n"
1891 /* Initial r3/TOP to 0. */
1892 "li 3, 0 \n"
1893 "li 4, 0 \n");
1894}
1895
1896/* Emit epilogue in inferior memory. See above comments. */
1897
1898static void
1899ppc_emit_epilogue (void)
1900{
1901 EMIT_ASM (/* *result = TOP */
1902 "lwz 5, -12(31) \n"
1903 "stw " TOP_FIRST ", 0(5) \n"
1904 "stw " TOP_SECOND ", 4(5) \n"
1905 /* Restore registers. */
1906 "lwz 31, -4(31) \n"
1907 "lwz 30, -8(31) \n"
1908 /* Restore SP. */
1909 "lwz 1, 0(1) \n"
1910 /* Restore LR. */
1911 "lwz 0, 4(1) \n"
1912 /* Return 0 for no-error. */
1913 "li 3, 0 \n"
1914 "mtlr 0 \n"
1915 "blr \n");
1916}
1917
1918/* TOP = stack[--sp] + TOP */
1919
1920static void
1921ppc_emit_add (void)
1922{
1923 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1924 "lwz " TMP_SECOND ", 4(30)\n"
1925 "addc 4, 6, 4 \n"
1926 "adde 3, 5, 3 \n");
1927}
1928
1929/* TOP = stack[--sp] - TOP */
1930
1931static void
1932ppc_emit_sub (void)
1933{
1934 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1935 "lwz " TMP_SECOND ", 4(30) \n"
1936 "subfc 4, 4, 6 \n"
1937 "subfe 3, 3, 5 \n");
1938}
1939
1940/* TOP = stack[--sp] * TOP */
1941
1942static void
1943ppc_emit_mul (void)
1944{
1945 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1946 "lwz " TMP_SECOND ", 4(30) \n"
1947 "mulhwu 7, 6, 4 \n"
1948 "mullw 3, 6, 3 \n"
1949 "mullw 5, 4, 5 \n"
1950 "mullw 4, 6, 4 \n"
1951 "add 3, 5, 3 \n"
1952 "add 3, 7, 3 \n");
1953}
1954
1955/* TOP = stack[--sp] << TOP */
1956
1957static void
1958ppc_emit_lsh (void)
1959{
1960 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1961 "lwz " TMP_SECOND ", 4(30) \n"
1962 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1963 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1964 "slw 5, 5, 4\n" /* Shift high part left */
1965 "slw 4, 6, 4\n" /* Shift low part left */
1966 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1967 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1968 "or 3, 5, 3\n"
1969 "or 3, 7, 3\n"); /* Assemble high part */
1970}
1971
1972/* Top = stack[--sp] >> TOP
1973 (Arithmetic shift right) */
1974
1975static void
1976ppc_emit_rsh_signed (void)
1977{
1978 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1979 "lwz " TMP_SECOND ", 4(30) \n"
1980 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1981 "sraw 3, 5, 4\n" /* Shift high part right */
1982 "cmpwi 7, 1\n"
1983 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1984 "sraw 4, 5, 7\n" /* Shift high to low */
1985 "b 2f\n"
1986 "1:\n"
1987 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1988 "srw 4, 6, 4\n" /* Shift low part right */
1989 "slw 5, 5, 7\n" /* Shift high to low */
1990 "or 4, 4, 5\n" /* Assemble low part */
1991 "2:\n");
1992}
1993
1994/* Top = stack[--sp] >> TOP
1995 (Logical shift right) */
1996
1997static void
1998ppc_emit_rsh_unsigned (void)
1999{
2000 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2001 "lwz " TMP_SECOND ", 4(30) \n"
2002 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2003 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2004 "srw 6, 6, 4\n" /* Shift low part right */
2005 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2006 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2007 "or 6, 6, 3\n"
2008 "srw 3, 5, 4\n" /* Shift high part right */
2009 "or 4, 6, 7\n"); /* Assemble low part */
2010}
2011
2012/* Emit code for signed-extension specified by ARG. */
2013
2014static void
2015ppc_emit_ext (int arg)
2016{
2017 switch (arg)
2018 {
2019 case 8:
2020 EMIT_ASM ("extsb 4, 4\n"
2021 "srawi 3, 4, 31");
2022 break;
2023 case 16:
2024 EMIT_ASM ("extsh 4, 4\n"
2025 "srawi 3, 4, 31");
2026 break;
2027 case 32:
2028 EMIT_ASM ("srawi 3, 4, 31");
2029 break;
2030 default:
2031 emit_error = 1;
2032 }
2033}
2034
2035/* Emit code for zero-extension specified by ARG. */
2036
2037static void
2038ppc_emit_zero_ext (int arg)
2039{
2040 switch (arg)
2041 {
2042 case 8:
2043 EMIT_ASM ("clrlwi 4,4,24\n"
2044 "li 3, 0\n");
2045 break;
2046 case 16:
2047 EMIT_ASM ("clrlwi 4,4,16\n"
2048 "li 3, 0\n");
2049 break;
2050 case 32:
2051 EMIT_ASM ("li 3, 0");
2052 break;
2053 default:
2054 emit_error = 1;
2055 }
2056}
2057
2058/* TOP = !TOP
2059 i.e., TOP = (TOP == 0) ? 1 : 0; */
2060
2061static void
2062ppc_emit_log_not (void)
2063{
2064 EMIT_ASM ("or 4, 3, 4 \n"
2065 "cntlzw 4, 4 \n"
2066 "srwi 4, 4, 5 \n"
2067 "li 3, 0 \n");
2068}
2069
2070/* TOP = stack[--sp] & TOP */
2071
2072static void
2073ppc_emit_bit_and (void)
2074{
2075 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2076 "lwz " TMP_SECOND ", 4(30) \n"
2077 "and 4, 6, 4 \n"
2078 "and 3, 5, 3 \n");
2079}
2080
2081/* TOP = stack[--sp] | TOP */
2082
2083static void
2084ppc_emit_bit_or (void)
2085{
2086 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2087 "lwz " TMP_SECOND ", 4(30) \n"
2088 "or 4, 6, 4 \n"
2089 "or 3, 5, 3 \n");
2090}
2091
2092/* TOP = stack[--sp] ^ TOP */
2093
2094static void
2095ppc_emit_bit_xor (void)
2096{
2097 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2098 "lwz " TMP_SECOND ", 4(30) \n"
2099 "xor 4, 6, 4 \n"
2100 "xor 3, 5, 3 \n");
2101}
2102
2103/* TOP = ~TOP
2104 i.e., TOP = ~(TOP | TOP) */
2105
2106static void
2107ppc_emit_bit_not (void)
2108{
2109 EMIT_ASM ("nor 3, 3, 3 \n"
2110 "nor 4, 4, 4 \n");
2111}
2112
2113/* TOP = stack[--sp] == TOP */
2114
2115static void
2116ppc_emit_equal (void)
2117{
2118 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2119 "lwz " TMP_SECOND ", 4(30) \n"
2120 "xor 4, 6, 4 \n"
2121 "xor 3, 5, 3 \n"
2122 "or 4, 3, 4 \n"
2123 "cntlzw 4, 4 \n"
2124 "srwi 4, 4, 5 \n"
2125 "li 3, 0 \n");
2126}
2127
2128/* TOP = stack[--sp] < TOP
2129 (Signed comparison) */
2130
2131static void
2132ppc_emit_less_signed (void)
2133{
2134 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2135 "lwz " TMP_SECOND ", 4(30) \n"
2136 "cmplw 6, 6, 4 \n"
2137 "cmpw 7, 5, 3 \n"
2138 /* CR6 bit 0 = low less and high equal */
2139 "crand 6*4+0, 6*4+0, 7*4+2\n"
2140 /* CR7 bit 0 = (low less and high equal) or high less */
2141 "cror 7*4+0, 7*4+0, 6*4+0\n"
2142 "mfcr 4 \n"
2143 "rlwinm 4, 4, 29, 31, 31 \n"
2144 "li 3, 0 \n");
2145}
2146
2147/* TOP = stack[--sp] < TOP
2148 (Unsigned comparison) */
2149
2150static void
2151ppc_emit_less_unsigned (void)
2152{
2153 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2154 "lwz " TMP_SECOND ", 4(30) \n"
2155 "cmplw 6, 6, 4 \n"
2156 "cmplw 7, 5, 3 \n"
2157 /* CR6 bit 0 = low less and high equal */
2158 "crand 6*4+0, 6*4+0, 7*4+2\n"
2159 /* CR7 bit 0 = (low less and high equal) or high less */
2160 "cror 7*4+0, 7*4+0, 6*4+0\n"
2161 "mfcr 4 \n"
2162 "rlwinm 4, 4, 29, 31, 31 \n"
2163 "li 3, 0 \n");
2164}
2165
2166/* Access the memory address in TOP in size of SIZE.
2167 Zero-extend the read value. */
2168
2169static void
2170ppc_emit_ref (int size)
2171{
2172 switch (size)
2173 {
2174 case 1:
2175 EMIT_ASM ("lbz 4, 0(4)\n"
2176 "li 3, 0");
2177 break;
2178 case 2:
2179 EMIT_ASM ("lhz 4, 0(4)\n"
2180 "li 3, 0");
2181 break;
2182 case 4:
2183 EMIT_ASM ("lwz 4, 0(4)\n"
2184 "li 3, 0");
2185 break;
2186 case 8:
2187 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2188 EMIT_ASM ("lwz 3, 4(4)\n"
2189 "lwz 4, 0(4)");
2190 else
2191 EMIT_ASM ("lwz 3, 0(4)\n"
2192 "lwz 4, 4(4)");
2193 break;
2194 }
2195}
2196
2197/* TOP = NUM */
2198
2199static void
2200ppc_emit_const (LONGEST num)
2201{
2202 uint32_t buf[10];
2203 uint32_t *p = buf;
2204
2205 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2206 p += gen_limm (p, 4, num & 0xffffffff, 0);
2207
2208 emit_insns (buf, p - buf);
2209 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2210}
2211
2212/* Set TOP to the value of register REG by calling get_raw_reg function
2213 with two argument, collected buffer and register number. */
2214
2215static void
2216ppc_emit_reg (int reg)
2217{
2218 uint32_t buf[13];
2219 uint32_t *p = buf;
2220
2221 /* fctx->regs is passed in r3 and then saved in -16(31). */
2222 p += GEN_LWZ (p, 3, 31, -16);
2223 p += GEN_LI (p, 4, reg); /* li r4, reg */
2224 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2225
2226 emit_insns (buf, p - buf);
2227 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2228
2229 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2230 {
2231 EMIT_ASM ("mr 5, 4\n"
2232 "mr 4, 3\n"
2233 "mr 3, 5\n");
2234 }
2235}
2236
2237/* TOP = stack[--sp] */
2238
2239static void
2240ppc_emit_pop (void)
2241{
2242 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2243 "lwz " TOP_SECOND ", 4(30) \n");
2244}
2245
2246/* stack[sp++] = TOP
2247
2248 Because we may use up bytecode stack, expand 8 doublewords more
2249 if needed. */
2250
2251static void
2252ppc_emit_stack_flush (void)
2253{
2254 /* Make sure bytecode stack is big enough before push.
2255 Otherwise, expand 64-byte more. */
2256
2257 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2258 " stw " TOP_SECOND ", 4(30)\n"
2259 " addi 5, 30, -(8 + 8) \n"
2260 " cmpw 7, 5, 1 \n"
2261 " bgt 7, 1f \n"
2262 " stwu 31, -64(1) \n"
2263 "1:addi 30, 30, -8 \n");
2264}
2265
2266/* Swap TOP and stack[sp-1] */
2267
2268static void
2269ppc_emit_swap (void)
2270{
2271 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2272 "lwz " TMP_SECOND ", 12(30) \n"
2273 "stw " TOP_FIRST ", 8(30) \n"
2274 "stw " TOP_SECOND ", 12(30) \n"
2275 "mr 3, 5 \n"
2276 "mr 4, 6 \n");
2277}
2278
2279/* Discard N elements in the stack. Also used for ppc64. */
2280
2281static void
2282ppc_emit_stack_adjust (int n)
2283{
2284 uint32_t buf[6];
2285 uint32_t *p = buf;
2286
2287 n = n << 3;
2288 if ((n >> 15) != 0)
2289 {
2290 emit_error = 1;
2291 return;
2292 }
2293
2294 p += GEN_ADDI (p, 30, 30, n);
2295
2296 emit_insns (buf, p - buf);
2297 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2298}
2299
2300/* Call function FN. */
2301
2302static void
2303ppc_emit_call (CORE_ADDR fn)
2304{
2305 uint32_t buf[11];
2306 uint32_t *p = buf;
2307
2308 p += gen_call (p, fn, 0, 0);
2309
2310 emit_insns (buf, p - buf);
2311 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2312}
2313
2314/* FN's prototype is `LONGEST(*fn)(int)'.
2315 TOP = fn (arg1)
2316 */
2317
2318static void
2319ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2320{
2321 uint32_t buf[15];
2322 uint32_t *p = buf;
2323
2324 /* Setup argument. arg1 is a 16-bit value. */
2325 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2326 p += gen_call (p, fn, 0, 0);
2327
2328 emit_insns (buf, p - buf);
2329 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2330
2331 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2332 {
2333 EMIT_ASM ("mr 5, 4\n"
2334 "mr 4, 3\n"
2335 "mr 3, 5\n");
2336 }
2337}
2338
2339/* FN's prototype is `void(*fn)(int,LONGEST)'.
2340 fn (arg1, TOP)
2341
2342 TOP should be preserved/restored before/after the call. */
2343
2344static void
2345ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2346{
2347 uint32_t buf[21];
2348 uint32_t *p = buf;
2349
2350 /* Save TOP. 0(30) is next-empty. */
2351 p += GEN_STW (p, 3, 30, 0);
2352 p += GEN_STW (p, 4, 30, 4);
2353
2354 /* Setup argument. arg1 is a 16-bit value. */
2355 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2356 {
2357 p += GEN_MR (p, 5, 4);
2358 p += GEN_MR (p, 6, 3);
2359 }
2360 else
2361 {
2362 p += GEN_MR (p, 5, 3);
2363 p += GEN_MR (p, 6, 4);
2364 }
2365 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2366 p += gen_call (p, fn, 0, 0);
2367
2368 /* Restore TOP */
2369 p += GEN_LWZ (p, 3, 30, 0);
2370 p += GEN_LWZ (p, 4, 30, 4);
2371
2372 emit_insns (buf, p - buf);
2373 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2374}
2375
2376/* Note in the following goto ops:
2377
2378 When emitting goto, the target address is later relocated by
2379 write_goto_address. OFFSET_P is the offset of the branch instruction
2380 in the code sequence, and SIZE_P is how to relocate the instruction,
2381 recognized by ppc_write_goto_address. In current implementation,
2382 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2383 */
2384
2385/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2386
2387static void
2388ppc_emit_if_goto (int *offset_p, int *size_p)
2389{
2390 EMIT_ASM ("or. 3, 3, 4 \n"
2391 "lwzu " TOP_FIRST ", 8(30) \n"
2392 "lwz " TOP_SECOND ", 4(30) \n"
2393 "1:bne 0, 1b \n");
2394
2395 if (offset_p)
2396 *offset_p = 12;
2397 if (size_p)
2398 *size_p = 14;
2399}
2400
2401/* Unconditional goto. Also used for ppc64. */
2402
2403static void
2404ppc_emit_goto (int *offset_p, int *size_p)
2405{
2406 EMIT_ASM ("1:b 1b");
2407
2408 if (offset_p)
2409 *offset_p = 0;
2410 if (size_p)
2411 *size_p = 24;
2412}
2413
2414/* Goto if stack[--sp] == TOP */
2415
2416static void
2417ppc_emit_eq_goto (int *offset_p, int *size_p)
2418{
2419 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2420 "lwz " TMP_SECOND ", 4(30) \n"
2421 "xor 4, 6, 4 \n"
2422 "xor 3, 5, 3 \n"
2423 "or. 3, 3, 4 \n"
2424 "lwzu " TOP_FIRST ", 8(30) \n"
2425 "lwz " TOP_SECOND ", 4(30) \n"
2426 "1:beq 0, 1b \n");
2427
2428 if (offset_p)
2429 *offset_p = 28;
2430 if (size_p)
2431 *size_p = 14;
2432}
2433
2434/* Goto if stack[--sp] != TOP */
2435
2436static void
2437ppc_emit_ne_goto (int *offset_p, int *size_p)
2438{
2439 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2440 "lwz " TMP_SECOND ", 4(30) \n"
2441 "xor 4, 6, 4 \n"
2442 "xor 3, 5, 3 \n"
2443 "or. 3, 3, 4 \n"
2444 "lwzu " TOP_FIRST ", 8(30) \n"
2445 "lwz " TOP_SECOND ", 4(30) \n"
2446 "1:bne 0, 1b \n");
2447
2448 if (offset_p)
2449 *offset_p = 28;
2450 if (size_p)
2451 *size_p = 14;
2452}
2453
2454/* Goto if stack[--sp] < TOP */
2455
2456static void
2457ppc_emit_lt_goto (int *offset_p, int *size_p)
2458{
2459 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2460 "lwz " TMP_SECOND ", 4(30) \n"
2461 "cmplw 6, 6, 4 \n"
2462 "cmpw 7, 5, 3 \n"
2463 /* CR6 bit 0 = low less and high equal */
2464 "crand 6*4+0, 6*4+0, 7*4+2\n"
2465 /* CR7 bit 0 = (low less and high equal) or high less */
2466 "cror 7*4+0, 7*4+0, 6*4+0\n"
2467 "lwzu " TOP_FIRST ", 8(30) \n"
2468 "lwz " TOP_SECOND ", 4(30)\n"
2469 "1:blt 7, 1b \n");
2470
2471 if (offset_p)
2472 *offset_p = 32;
2473 if (size_p)
2474 *size_p = 14;
2475}
2476
2477/* Goto if stack[--sp] <= TOP */
2478
2479static void
2480ppc_emit_le_goto (int *offset_p, int *size_p)
2481{
2482 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2483 "lwz " TMP_SECOND ", 4(30) \n"
2484 "cmplw 6, 6, 4 \n"
2485 "cmpw 7, 5, 3 \n"
2486 /* CR6 bit 0 = low less/equal and high equal */
2487 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2488 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2489 "cror 7*4+0, 7*4+0, 6*4+0\n"
2490 "lwzu " TOP_FIRST ", 8(30) \n"
2491 "lwz " TOP_SECOND ", 4(30)\n"
2492 "1:blt 7, 1b \n");
2493
2494 if (offset_p)
2495 *offset_p = 32;
2496 if (size_p)
2497 *size_p = 14;
2498}
2499
2500/* Goto if stack[--sp] > TOP */
2501
2502static void
2503ppc_emit_gt_goto (int *offset_p, int *size_p)
2504{
2505 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2506 "lwz " TMP_SECOND ", 4(30) \n"
2507 "cmplw 6, 6, 4 \n"
2508 "cmpw 7, 5, 3 \n"
2509 /* CR6 bit 0 = low greater and high equal */
2510 "crand 6*4+0, 6*4+1, 7*4+2\n"
2511 /* CR7 bit 0 = (low greater and high equal) or high greater */
2512 "cror 7*4+0, 7*4+1, 6*4+0\n"
2513 "lwzu " TOP_FIRST ", 8(30) \n"
2514 "lwz " TOP_SECOND ", 4(30)\n"
2515 "1:blt 7, 1b \n");
2516
2517 if (offset_p)
2518 *offset_p = 32;
2519 if (size_p)
2520 *size_p = 14;
2521}
2522
2523/* Goto if stack[--sp] >= TOP */
2524
2525static void
2526ppc_emit_ge_goto (int *offset_p, int *size_p)
2527{
2528 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2529 "lwz " TMP_SECOND ", 4(30) \n"
2530 "cmplw 6, 6, 4 \n"
2531 "cmpw 7, 5, 3 \n"
2532 /* CR6 bit 0 = low ge and high equal */
2533 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2534 /* CR7 bit 0 = (low ge and high equal) or high greater */
2535 "cror 7*4+0, 7*4+1, 6*4+0\n"
2536 "lwzu " TOP_FIRST ", 8(30)\n"
2537 "lwz " TOP_SECOND ", 4(30)\n"
2538 "1:blt 7, 1b \n");
2539
2540 if (offset_p)
2541 *offset_p = 32;
2542 if (size_p)
2543 *size_p = 14;
2544}
2545
2546/* Relocate previous emitted branch instruction. FROM is the address
2547 of the branch instruction, TO is the goto target address, and SIZE
2548 if the value we set by *SIZE_P before. Currently, it is either
2549 24 or 14 of branch and conditional-branch instruction.
2550 Also used for ppc64. */
2551
2552static void
2553ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2554{
2555 long rel = to - from;
2556 uint32_t insn;
2557 int opcd;
2558
2559 read_inferior_memory (from, (unsigned char *) &insn, 4);
2560 opcd = (insn >> 26) & 0x3f;
2561
2562 switch (size)
2563 {
2564 case 14:
2565 if (opcd != 16
2566 || (rel >= (1 << 15) || rel < -(1 << 15)))
2567 emit_error = 1;
2568 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2569 break;
2570 case 24:
2571 if (opcd != 18
2572 || (rel >= (1 << 25) || rel < -(1 << 25)))
2573 emit_error = 1;
2574 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2575 break;
2576 default:
2577 emit_error = 1;
2578 }
2579
2580 if (!emit_error)
4196ab2a 2581 target_write_memory (from, (unsigned char *) &insn, 4);
14e2b6d9
MK		 2582}
2583
2584/* Table of emit ops for 32-bit. */
2585
2586static struct emit_ops ppc_emit_ops_impl =
2587{
2588 ppc_emit_prologue,
2589 ppc_emit_epilogue,
2590 ppc_emit_add,
2591 ppc_emit_sub,
2592 ppc_emit_mul,
2593 ppc_emit_lsh,
2594 ppc_emit_rsh_signed,
2595 ppc_emit_rsh_unsigned,
2596 ppc_emit_ext,
2597 ppc_emit_log_not,
2598 ppc_emit_bit_and,
2599 ppc_emit_bit_or,
2600 ppc_emit_bit_xor,
2601 ppc_emit_bit_not,
2602 ppc_emit_equal,
2603 ppc_emit_less_signed,
2604 ppc_emit_less_unsigned,
2605 ppc_emit_ref,
2606 ppc_emit_if_goto,
2607 ppc_emit_goto,
2608 ppc_write_goto_address,
2609 ppc_emit_const,
2610 ppc_emit_call,
2611 ppc_emit_reg,
2612 ppc_emit_pop,
2613 ppc_emit_stack_flush,
2614 ppc_emit_zero_ext,
2615 ppc_emit_swap,
2616 ppc_emit_stack_adjust,
2617 ppc_emit_int_call_1,
2618 ppc_emit_void_call_2,
2619 ppc_emit_eq_goto,
2620 ppc_emit_ne_goto,
2621 ppc_emit_lt_goto,
2622 ppc_emit_le_goto,
2623 ppc_emit_gt_goto,
2624 ppc_emit_ge_goto
2625};
2626
2627#ifdef __powerpc64__
2628
2629/*
2630
2631 Bytecode execution stack frame - 64-bit
2632
2633 | LR save area (SP + 16)
2634 | CR save area (SP + 8)
2635 SP' -> +- Back chain (SP + 0)
2636 | Save r31 for access saved arguments
2637 | Save r30 for bytecode stack pointer
2638 | Save r4 for incoming argument *value
2639 | Save r3 for incoming argument regs
2640 r30 -> +- Bytecode execution stack
2641 |
2642 | 64-byte (8 doublewords) at initial.
2643 | Expand stack as needed.
2644 |
2645 +-
2646 | Some padding for minimum stack frame.
2647 | 112 for ELFv1.
2648 SP +- Back-chain (SP')
2649
2650 initial frame size
2651 = 112 + (4 * 8) + 64
2652 = 208
2653
2654 r30 is the stack-pointer for bytecode machine.
2655 It should point to next-empty, so we can use LDU for pop.
2656 r3 is used for cache of TOP value.
2657 It was the first argument, pointer to regs.
2658 r4 is the second argument, pointer to the result.
2659 We should set *result = TOP after leaving this function.
2660
2661 Note:
2662 * To restore stack at epilogue
2663 => sp = r31
2664 * To check stack is big enough for bytecode execution.
2665 => r30 - 8 > SP + 112
2666 * To return execution result.
2667 => 0(r4) = TOP
2668
2669 */
2670
2671/* Emit prologue in inferior memory. See above comments. */
2672
2673static void
2674ppc64v1_emit_prologue (void)
2675{
2676 /* On ELFv1, function pointers really point to function descriptor,
2677 so emit one here. We don't care about contents of words 1 and 2,
2678 so let them just overlap out code. */
2679 uint64_t opd = current_insn_ptr + 8;
2680 uint32_t buf[2];
2681
2682 /* Mind the strict aliasing rules. */
2683 memcpy (buf, &opd, sizeof buf);
2684 emit_insns(buf, 2);
2685 EMIT_ASM (/* Save return address. */
2686 "mflr 0 \n"
2687 "std 0, 16(1) \n"
2688 /* Save r30 and incoming arguments. */
2689 "std 31, -8(1) \n"
2690 "std 30, -16(1) \n"
2691 "std 4, -24(1) \n"
2692 "std 3, -32(1) \n"
2693 /* Point r31 to current r1 for access arguments. */
2694 "mr 31, 1 \n"
2695 /* Adjust SP. 208 is the initial frame size. */
2696 "stdu 1, -208(1) \n"
2697 /* Set r30 to pointing stack-top. */
2698 "addi 30, 1, 168 \n"
2699 /* Initial r3/TOP to 0. */
2700 "li 3, 0 \n");
2701}
2702
2703/* Emit prologue in inferior memory. See above comments. */
2704
2705static void
2706ppc64v2_emit_prologue (void)
2707{
2708 EMIT_ASM (/* Save return address. */
2709 "mflr 0 \n"
2710 "std 0, 16(1) \n"
2711 /* Save r30 and incoming arguments. */
2712 "std 31, -8(1) \n"
2713 "std 30, -16(1) \n"
2714 "std 4, -24(1) \n"
2715 "std 3, -32(1) \n"
2716 /* Point r31 to current r1 for access arguments. */
2717 "mr 31, 1 \n"
2718 /* Adjust SP. 208 is the initial frame size. */
2719 "stdu 1, -208(1) \n"
2720 /* Set r30 to pointing stack-top. */
2721 "addi 30, 1, 168 \n"
2722 /* Initial r3/TOP to 0. */
2723 "li 3, 0 \n");
2724}
2725
2726/* Emit epilogue in inferior memory. See above comments. */
2727
2728static void
2729ppc64_emit_epilogue (void)
2730{
2731 EMIT_ASM (/* Restore SP. */
2732 "ld 1, 0(1) \n"
2733 /* *result = TOP */
2734 "ld 4, -24(1) \n"
2735 "std 3, 0(4) \n"
2736 /* Restore registers. */
2737 "ld 31, -8(1) \n"
2738 "ld 30, -16(1) \n"
2739 /* Restore LR. */
2740 "ld 0, 16(1) \n"
2741 /* Return 0 for no-error. */
2742 "li 3, 0 \n"
2743 "mtlr 0 \n"
2744 "blr \n");
2745}
2746
2747/* TOP = stack[--sp] + TOP */
2748
2749static void
2750ppc64_emit_add (void)
2751{
2752 EMIT_ASM ("ldu 4, 8(30) \n"
2753 "add 3, 4, 3 \n");
2754}
2755
2756/* TOP = stack[--sp] - TOP */
2757
2758static void
2759ppc64_emit_sub (void)
2760{
2761 EMIT_ASM ("ldu 4, 8(30) \n"
2762 "sub 3, 4, 3 \n");
2763}
2764
2765/* TOP = stack[--sp] * TOP */
2766
2767static void
2768ppc64_emit_mul (void)
2769{
2770 EMIT_ASM ("ldu 4, 8(30) \n"
2771 "mulld 3, 4, 3 \n");
2772}
2773
2774/* TOP = stack[--sp] << TOP */
2775
2776static void
2777ppc64_emit_lsh (void)
2778{
2779 EMIT_ASM ("ldu 4, 8(30) \n"
2780 "sld 3, 4, 3 \n");
2781}
2782
2783/* Top = stack[--sp] >> TOP
2784 (Arithmetic shift right) */
2785
2786static void
2787ppc64_emit_rsh_signed (void)
2788{
2789 EMIT_ASM ("ldu 4, 8(30) \n"
2790 "srad 3, 4, 3 \n");
2791}
2792
2793/* Top = stack[--sp] >> TOP
2794 (Logical shift right) */
2795
2796static void
2797ppc64_emit_rsh_unsigned (void)
2798{
2799 EMIT_ASM ("ldu 4, 8(30) \n"
2800 "srd 3, 4, 3 \n");
2801}
2802
2803/* Emit code for signed-extension specified by ARG. */
2804
2805static void
2806ppc64_emit_ext (int arg)
2807{
2808 switch (arg)
2809 {
2810 case 8:
2811 EMIT_ASM ("extsb 3, 3");
2812 break;
2813 case 16:
2814 EMIT_ASM ("extsh 3, 3");
2815 break;
2816 case 32:
2817 EMIT_ASM ("extsw 3, 3");
2818 break;
2819 default:
2820 emit_error = 1;
2821 }
2822}
2823
2824/* Emit code for zero-extension specified by ARG. */
2825
2826static void
2827ppc64_emit_zero_ext (int arg)
2828{
2829 switch (arg)
2830 {
2831 case 8:
2832 EMIT_ASM ("rldicl 3,3,0,56");
2833 break;
2834 case 16:
2835 EMIT_ASM ("rldicl 3,3,0,48");
2836 break;
2837 case 32:
2838 EMIT_ASM ("rldicl 3,3,0,32");
2839 break;
2840 default:
2841 emit_error = 1;
2842 }
2843}
2844
2845/* TOP = !TOP
2846 i.e., TOP = (TOP == 0) ? 1 : 0; */
2847
2848static void
2849ppc64_emit_log_not (void)
2850{
2851 EMIT_ASM ("cntlzd 3, 3 \n"
2852 "srdi 3, 3, 6 \n");
2853}
2854
2855/* TOP = stack[--sp] & TOP */
2856
2857static void
2858ppc64_emit_bit_and (void)
2859{
2860 EMIT_ASM ("ldu 4, 8(30) \n"
2861 "and 3, 4, 3 \n");
2862}
2863
2864/* TOP = stack[--sp] | TOP */
2865
2866static void
2867ppc64_emit_bit_or (void)
2868{
2869 EMIT_ASM ("ldu 4, 8(30) \n"
2870 "or 3, 4, 3 \n");
2871}
2872
2873/* TOP = stack[--sp] ^ TOP */
2874
2875static void
2876ppc64_emit_bit_xor (void)
2877{
2878 EMIT_ASM ("ldu 4, 8(30) \n"
2879 "xor 3, 4, 3 \n");
2880}
2881
2882/* TOP = ~TOP
2883 i.e., TOP = ~(TOP | TOP) */
2884
2885static void
2886ppc64_emit_bit_not (void)
2887{
2888 EMIT_ASM ("nor 3, 3, 3 \n");
2889}
2890
2891/* TOP = stack[--sp] == TOP */
2892
2893static void
2894ppc64_emit_equal (void)
2895{
2896 EMIT_ASM ("ldu 4, 8(30) \n"
2897 "xor 3, 3, 4 \n"
2898 "cntlzd 3, 3 \n"
2899 "srdi 3, 3, 6 \n");
2900}
2901
2902/* TOP = stack[--sp] < TOP
2903 (Signed comparison) */
2904
2905static void
2906ppc64_emit_less_signed (void)
2907{
2908 EMIT_ASM ("ldu 4, 8(30) \n"
2909 "cmpd 7, 4, 3 \n"
2910 "mfcr 3 \n"
2911 "rlwinm 3, 3, 29, 31, 31 \n");
2912}
2913
2914/* TOP = stack[--sp] < TOP
2915 (Unsigned comparison) */
2916
2917static void
2918ppc64_emit_less_unsigned (void)
2919{
2920 EMIT_ASM ("ldu 4, 8(30) \n"
2921 "cmpld 7, 4, 3 \n"
2922 "mfcr 3 \n"
2923 "rlwinm 3, 3, 29, 31, 31 \n");
2924}
2925
2926/* Access the memory address in TOP in size of SIZE.
2927 Zero-extend the read value. */
2928
2929static void
2930ppc64_emit_ref (int size)
2931{
2932 switch (size)
2933 {
2934 case 1:
2935 EMIT_ASM ("lbz 3, 0(3)");
2936 break;
2937 case 2:
2938 EMIT_ASM ("lhz 3, 0(3)");
2939 break;
2940 case 4:
2941 EMIT_ASM ("lwz 3, 0(3)");
2942 break;
2943 case 8:
2944 EMIT_ASM ("ld 3, 0(3)");
2945 break;
2946 }
2947}
2948
2949/* TOP = NUM */
2950
2951static void
2952ppc64_emit_const (LONGEST num)
2953{
2954 uint32_t buf[5];
2955 uint32_t *p = buf;
2956
2957 p += gen_limm (p, 3, num, 1);
2958
2959 emit_insns (buf, p - buf);
2960 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2961}
2962
2963/* Set TOP to the value of register REG by calling get_raw_reg function
2964 with two argument, collected buffer and register number. */
2965
2966static void
2967ppc64v1_emit_reg (int reg)
2968{
2969 uint32_t buf[15];
2970 uint32_t *p = buf;
2971
2972 /* fctx->regs is passed in r3 and then saved in 176(1). */
2973 p += GEN_LD (p, 3, 31, -32);
2974 p += GEN_LI (p, 4, reg);
2975 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2976 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2977 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2978
2979 emit_insns (buf, p - buf);
2980 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2981}
2982
2983/* Likewise, for ELFv2. */
2984
2985static void
2986ppc64v2_emit_reg (int reg)
2987{
2988 uint32_t buf[12];
2989 uint32_t *p = buf;
2990
2991 /* fctx->regs is passed in r3 and then saved in 176(1). */
2992 p += GEN_LD (p, 3, 31, -32);
2993 p += GEN_LI (p, 4, reg);
2994 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2995 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2996 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2997
2998 emit_insns (buf, p - buf);
2999 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3000}
3001
3002/* TOP = stack[--sp] */
3003
3004static void
3005ppc64_emit_pop (void)
3006{
3007 EMIT_ASM ("ldu 3, 8(30)");
3008}
3009
3010/* stack[sp++] = TOP
3011
3012 Because we may use up bytecode stack, expand 8 doublewords more
3013 if needed. */
3014
3015static void
3016ppc64_emit_stack_flush (void)
3017{
3018 /* Make sure bytecode stack is big enough before push.
3019 Otherwise, expand 64-byte more. */
3020
3021 EMIT_ASM (" std 3, 0(30) \n"
3022 " addi 4, 30, -(112 + 8) \n"
3023 " cmpd 7, 4, 1 \n"
3024 " bgt 7, 1f \n"
3025 " stdu 31, -64(1) \n"
3026 "1:addi 30, 30, -8 \n");
3027}
3028
3029/* Swap TOP and stack[sp-1] */
3030
3031static void
3032ppc64_emit_swap (void)
3033{
3034 EMIT_ASM ("ld 4, 8(30) \n"
3035 "std 3, 8(30) \n"
3036 "mr 3, 4 \n");
3037}
3038
3039/* Call function FN - ELFv1. */
3040
3041static void
3042ppc64v1_emit_call (CORE_ADDR fn)
3043{
3044 uint32_t buf[13];
3045 uint32_t *p = buf;
3046
3047 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3048 p += gen_call (p, fn, 1, 1);
3049 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3050
3051 emit_insns (buf, p - buf);
3052 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3053}
3054
3055/* Call function FN - ELFv2. */
3056
3057static void
3058ppc64v2_emit_call (CORE_ADDR fn)
3059{
3060 uint32_t buf[10];
3061 uint32_t *p = buf;
3062
3063 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3064 p += gen_call (p, fn, 1, 0);
3065 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3066
3067 emit_insns (buf, p - buf);
3068 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3069}
3070
3071/* FN's prototype is `LONGEST(*fn)(int)'.
3072 TOP = fn (arg1)
3073 */
3074
3075static void
3076ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
3077{
3078 uint32_t buf[13];
3079 uint32_t *p = buf;
3080
3081 /* Setup argument. arg1 is a 16-bit value. */
3082 p += gen_limm (p, 3, arg1, 1);
3083 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3084 p += gen_call (p, fn, 1, 1);
3085 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3086
3087 emit_insns (buf, p - buf);
3088 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3089}
3090
3091/* Likewise for ELFv2. */
3092
3093static void
3094ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
3095{
3096 uint32_t buf[10];
3097 uint32_t *p = buf;
3098
3099 /* Setup argument. arg1 is a 16-bit value. */
3100 p += gen_limm (p, 3, arg1, 1);
3101 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3102 p += gen_call (p, fn, 1, 0);
3103 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3104
3105 emit_insns (buf, p - buf);
3106 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3107}
3108
3109/* FN's prototype is `void(*fn)(int,LONGEST)'.
3110 fn (arg1, TOP)
3111
3112 TOP should be preserved/restored before/after the call. */
3113
3114static void
3115ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
3116{
3117 uint32_t buf[17];
3118 uint32_t *p = buf;
3119
3120 /* Save TOP. 0(30) is next-empty. */
3121 p += GEN_STD (p, 3, 30, 0);
3122
3123 /* Setup argument. arg1 is a 16-bit value. */
3124 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3125 p += gen_limm (p, 3, arg1, 1);
3126 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3127 p += gen_call (p, fn, 1, 1);
3128 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3129
3130 /* Restore TOP */
3131 p += GEN_LD (p, 3, 30, 0);
3132
3133 emit_insns (buf, p - buf);
3134 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3135}
3136
3137/* Likewise for ELFv2. */
3138
3139static void
3140ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
3141{
3142 uint32_t buf[14];
3143 uint32_t *p = buf;
3144
3145 /* Save TOP. 0(30) is next-empty. */
3146 p += GEN_STD (p, 3, 30, 0);
3147
3148 /* Setup argument. arg1 is a 16-bit value. */
3149 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3150 p += gen_limm (p, 3, arg1, 1);
3151 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3152 p += gen_call (p, fn, 1, 0);
3153 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3154
3155 /* Restore TOP */
3156 p += GEN_LD (p, 3, 30, 0);
3157
3158 emit_insns (buf, p - buf);
3159 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3160}
3161
3162/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3163
3164static void
3165ppc64_emit_if_goto (int *offset_p, int *size_p)
3166{
3167 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3168 "ldu 3, 8(30) \n"
3169 "1:bne 7, 1b \n");
3170
3171 if (offset_p)
3172 *offset_p = 8;
3173 if (size_p)
3174 *size_p = 14;
3175}
3176
3177/* Goto if stack[--sp] == TOP */
3178
3179static void
3180ppc64_emit_eq_goto (int *offset_p, int *size_p)
3181{
3182 EMIT_ASM ("ldu 4, 8(30) \n"
3183 "cmpd 7, 4, 3 \n"
3184 "ldu 3, 8(30) \n"
3185 "1:beq 7, 1b \n");
3186
3187 if (offset_p)
3188 *offset_p = 12;
3189 if (size_p)
3190 *size_p = 14;
3191}
3192
3193/* Goto if stack[--sp] != TOP */
3194
3195static void
3196ppc64_emit_ne_goto (int *offset_p, int *size_p)
3197{
3198 EMIT_ASM ("ldu 4, 8(30) \n"
3199 "cmpd 7, 4, 3 \n"
3200 "ldu 3, 8(30) \n"
3201 "1:bne 7, 1b \n");
3202
3203 if (offset_p)
3204 *offset_p = 12;
3205 if (size_p)
3206 *size_p = 14;
3207}
3208
3209/* Goto if stack[--sp] < TOP */
3210
3211static void
3212ppc64_emit_lt_goto (int *offset_p, int *size_p)
3213{
3214 EMIT_ASM ("ldu 4, 8(30) \n"
3215 "cmpd 7, 4, 3 \n"
3216 "ldu 3, 8(30) \n"
3217 "1:blt 7, 1b \n");
3218
3219 if (offset_p)
3220 *offset_p = 12;
3221 if (size_p)
3222 *size_p = 14;
3223}
3224
3225/* Goto if stack[--sp] <= TOP */
3226
3227static void
3228ppc64_emit_le_goto (int *offset_p, int *size_p)
3229{
3230 EMIT_ASM ("ldu 4, 8(30) \n"
3231 "cmpd 7, 4, 3 \n"
3232 "ldu 3, 8(30) \n"
3233 "1:ble 7, 1b \n");
3234
3235 if (offset_p)
3236 *offset_p = 12;
3237 if (size_p)
3238 *size_p = 14;
3239}
3240
3241/* Goto if stack[--sp] > TOP */
3242
3243static void
3244ppc64_emit_gt_goto (int *offset_p, int *size_p)
3245{
3246 EMIT_ASM ("ldu 4, 8(30) \n"
3247 "cmpd 7, 4, 3 \n"
3248 "ldu 3, 8(30) \n"
3249 "1:bgt 7, 1b \n");
3250
3251 if (offset_p)
3252 *offset_p = 12;
3253 if (size_p)
3254 *size_p = 14;
3255}
3256
3257/* Goto if stack[--sp] >= TOP */
3258
3259static void
3260ppc64_emit_ge_goto (int *offset_p, int *size_p)
3261{
3262 EMIT_ASM ("ldu 4, 8(30) \n"
3263 "cmpd 7, 4, 3 \n"
3264 "ldu 3, 8(30) \n"
3265 "1:bge 7, 1b \n");
3266
3267 if (offset_p)
3268 *offset_p = 12;
3269 if (size_p)
3270 *size_p = 14;
3271}
3272
3273/* Table of emit ops for 64-bit ELFv1. */
3274
3275static struct emit_ops ppc64v1_emit_ops_impl =
3276{
3277 ppc64v1_emit_prologue,
3278 ppc64_emit_epilogue,
3279 ppc64_emit_add,
3280 ppc64_emit_sub,
3281 ppc64_emit_mul,
3282 ppc64_emit_lsh,
3283 ppc64_emit_rsh_signed,
3284 ppc64_emit_rsh_unsigned,
3285 ppc64_emit_ext,
3286 ppc64_emit_log_not,
3287 ppc64_emit_bit_and,
3288 ppc64_emit_bit_or,
3289 ppc64_emit_bit_xor,
3290 ppc64_emit_bit_not,
3291 ppc64_emit_equal,
3292 ppc64_emit_less_signed,
3293 ppc64_emit_less_unsigned,
3294 ppc64_emit_ref,
3295 ppc64_emit_if_goto,
3296 ppc_emit_goto,
3297 ppc_write_goto_address,
3298 ppc64_emit_const,
3299 ppc64v1_emit_call,
3300 ppc64v1_emit_reg,
3301 ppc64_emit_pop,
3302 ppc64_emit_stack_flush,
3303 ppc64_emit_zero_ext,
3304 ppc64_emit_swap,
3305 ppc_emit_stack_adjust,
3306 ppc64v1_emit_int_call_1,
3307 ppc64v1_emit_void_call_2,
3308 ppc64_emit_eq_goto,
3309 ppc64_emit_ne_goto,
3310 ppc64_emit_lt_goto,
3311 ppc64_emit_le_goto,
3312 ppc64_emit_gt_goto,
3313 ppc64_emit_ge_goto
3314};
3315
3316/* Table of emit ops for 64-bit ELFv2. */
3317
3318static struct emit_ops ppc64v2_emit_ops_impl =
3319{
3320 ppc64v2_emit_prologue,
3321 ppc64_emit_epilogue,
3322 ppc64_emit_add,
3323 ppc64_emit_sub,
3324 ppc64_emit_mul,
3325 ppc64_emit_lsh,
3326 ppc64_emit_rsh_signed,
3327 ppc64_emit_rsh_unsigned,
3328 ppc64_emit_ext,
3329 ppc64_emit_log_not,
3330 ppc64_emit_bit_and,
3331 ppc64_emit_bit_or,
3332 ppc64_emit_bit_xor,
3333 ppc64_emit_bit_not,
3334 ppc64_emit_equal,
3335 ppc64_emit_less_signed,
3336 ppc64_emit_less_unsigned,
3337 ppc64_emit_ref,
3338 ppc64_emit_if_goto,
3339 ppc_emit_goto,
3340 ppc_write_goto_address,
3341 ppc64_emit_const,
3342 ppc64v2_emit_call,
3343 ppc64v2_emit_reg,
3344 ppc64_emit_pop,
3345 ppc64_emit_stack_flush,
3346 ppc64_emit_zero_ext,
3347 ppc64_emit_swap,
3348 ppc_emit_stack_adjust,
3349 ppc64v2_emit_int_call_1,
3350 ppc64v2_emit_void_call_2,
3351 ppc64_emit_eq_goto,
3352 ppc64_emit_ne_goto,
3353 ppc64_emit_lt_goto,
3354 ppc64_emit_le_goto,
3355 ppc64_emit_gt_goto,
3356 ppc64_emit_ge_goto
3357};
3358
3359#endif
3360
3361/* Implementation of linux_target_ops method "emit_ops". */
3362
3363static struct emit_ops *
3364ppc_emit_ops (void)
3365{
3366#ifdef __powerpc64__
3367 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3368
3369 if (register_size (regcache->tdesc, 0) == 8)
3370 {
3371 if (is_elfv2_inferior ())
3372 return &ppc64v2_emit_ops_impl;
3373 else
3374 return &ppc64v1_emit_ops_impl;
3375 }
3376#endif
3377 return &ppc_emit_ops_impl;
3378}
3379
a2174ba4
MK		 3380/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3381
3382static int
3383ppc_get_ipa_tdesc_idx (void)
3384{
3385 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3386 const struct target_desc *tdesc = regcache->tdesc;
3387
3388#ifdef __powerpc64__
3389 if (tdesc == tdesc_powerpc_64l)
3390 return PPC_TDESC_BASE;
3391 if (tdesc == tdesc_powerpc_altivec64l)
3392 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3393 if (tdesc == tdesc_powerpc_vsx64l)
3394 return PPC_TDESC_VSX;
3395 if (tdesc == tdesc_powerpc_isa205_64l)
3396 return PPC_TDESC_ISA205;
3397 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3398 return PPC_TDESC_ISA205_ALTIVEC;
3399 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3400 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3401 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3402 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3403 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3404 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3405 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
3406 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3407#endif
3408
3409 if (tdesc == tdesc_powerpc_32l)
3410 return PPC_TDESC_BASE;
3411 if (tdesc == tdesc_powerpc_altivec32l)
3412 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3413 if (tdesc == tdesc_powerpc_vsx32l)
3414 return PPC_TDESC_VSX;
3415 if (tdesc == tdesc_powerpc_isa205_32l)
3416 return PPC_TDESC_ISA205;
3417 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3418 return PPC_TDESC_ISA205_ALTIVEC;
3419 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3420 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3421 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3422 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3423 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3424 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3425 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
3426 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3427 if (tdesc == tdesc_powerpc_e500l)
3428 return PPC_TDESC_E500;
3429
3430 return 0;
3431}
3432
2ec06d2e 3433struct linux_target_ops the_low_target = {
a2174ba4
MK		 3434 ppc_get_thread_area,
3435 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3436 ppc_emit_ops,
a2174ba4 3437 ppc_get_min_fast_tracepoint_insn_len,
7d00775e 3438 NULL, /* supports_range_stepping */
7d00775e 3439 ppc_supports_hardware_single_step,
a2174ba4
MK		 3440 NULL, /* get_syscall_trapinfo */
3441 ppc_get_ipa_tdesc_idx,
2ec06d2e 3442};
3aee8918 3443
ef0478f6
TBA		 3444/* The linux target ops object. */
3445
3446linux_process_target *the_linux_target = &the_ppc_target;
3447
3aee8918
PA		 3448void
3449initialize_low_arch (void)
3450{
3451 /* Initialize the Linux target descriptions. */
3452
3453 init_registers_powerpc_32l ();
3454 init_registers_powerpc_altivec32l ();
3aee8918
PA		 3455 init_registers_powerpc_vsx32l ();
3456 init_registers_powerpc_isa205_32l ();
3457 init_registers_powerpc_isa205_altivec32l ();
3458 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3459 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3460 init_registers_powerpc_isa207_vsx32l ();
8d619c01 3461 init_registers_powerpc_isa207_htm_vsx32l ();
3aee8918 3462 init_registers_powerpc_e500l ();
a2174ba4 3463#if __powerpc64__
3aee8918
PA		 3464 init_registers_powerpc_64l ();
3465 init_registers_powerpc_altivec64l ();
3aee8918
PA		 3466 init_registers_powerpc_vsx64l ();
3467 init_registers_powerpc_isa205_64l ();
3468 init_registers_powerpc_isa205_altivec64l ();
3469 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3470 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3471 init_registers_powerpc_isa207_vsx64l ();
8d619c01 3472 init_registers_powerpc_isa207_htm_vsx64l ();
a2174ba4 3473#endif
3aee8918
PA		 3474
3475 initialize_regsets_info (&ppc_regsets_info);
3476}
GDB Binutils - Deliverables
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