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gdbserver/linux-low: turn 'insert_point' and 'remove_point' into methods
[deliverable/binutils-gdb.git] / gdbserver / linux-ppc-low.cc
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
b811d2c2 3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
64f57f3d 31#include "nat/linux-ptrace.h"
bd64614e 32#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 33#include "ax.h"
34#include "tracepoint.h"
35
36#define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38#define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 46
ef0478f6
TBA		 47/* Linux target op definitions for the PowerPC architecture. */
48
49class ppc_target : public linux_process_target
50{
51public:
52
aa8d21c9
TBA		 53 const regs_info *get_regs_info () override;
54
3ca4edb6
TBA		 55 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
56
007c9b97
TBA		 57 bool supports_z_point_type (char z_type) override;
58
797bcff5
TBA		 59protected:
60
61 void low_arch_setup () override;
daca57a7
TBA		 62
63 bool low_cannot_fetch_register (int regno) override;
64
65 bool low_cannot_store_register (int regno) override;
bf9ae9d8
TBA		 66
67 bool low_supports_breakpoints () override;
68
69 CORE_ADDR low_get_pc (regcache *regcache) override;
70
71 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
d7146cda
TBA		 72
73 bool low_breakpoint_at (CORE_ADDR pc) override;
9db9aa23
TBA		 74
75 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
76 int size, raw_breakpoint *bp) override;
77
78 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
79 int size, raw_breakpoint *bp) override;
ef0478f6
TBA		 80};
81
82/* The singleton target ops object. */
83
84static ppc_target the_ppc_target;
85
7ca18ed6
EBM		 86/* Holds the AT_HWCAP auxv entry. */
87
b6430ec3
UW		 88static unsigned long ppc_hwcap;
89
7ca18ed6
EBM		 90/* Holds the AT_HWCAP2 auxv entry. */
91
92static unsigned long ppc_hwcap2;
93
b6430ec3 94
7284e1be
UW		 95#define ppc_num_regs 73
96
5b0a002e
UW		 97#ifdef __powerpc64__
98/* We use a constant for FPSCR instead of PT_FPSCR, because
99 many shipped PPC64 kernels had the wrong value in ptrace.h. */
100static int ppc_regmap[] =
101 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
102 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
103 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
104 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
105 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
106 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
107 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
108 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
109 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
110 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
111 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
112 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
113 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
114 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
115 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
116 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
117 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 118 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
119 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 120#else
0a30fbc4 121/* Currently, don't check/send MQ. */
2ec06d2e 122static int ppc_regmap[] =
0a30fbc4
DJ		 123 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
124 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
125 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
126 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
127 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
128 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
129 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
130 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
131 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
132 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
133 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
134 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
135 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
136 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
137 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
138 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
139 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 140 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
141 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 142 };
143
144static int ppc_regmap_e500[] =
145 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
146 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
147 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
148 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
149 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
150 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
151 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
152 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
153 -1, -1, -1, -1,
154 -1, -1, -1, -1,
155 -1, -1, -1, -1,
156 -1, -1, -1, -1,
157 -1, -1, -1, -1,
158 -1, -1, -1, -1,
159 -1, -1, -1, -1,
160 -1, -1, -1, -1,
161 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 162 PT_CTR * 4, PT_XER * 4, -1,
163 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 164 };
5b0a002e 165#endif
0a30fbc4 166
7ca18ed6
EBM		 167/* Check whether the kernel provides a register set with number
168 REGSET_ID of size REGSETSIZE for process/thread TID. */
169
170static int
171ppc_check_regset (int tid, int regset_id, int regsetsize)
172{
173 void *buf = alloca (regsetsize);
174 struct iovec iov;
175
176 iov.iov_base = buf;
177 iov.iov_len = regsetsize;
178
179 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
180 || errno == ENODATA)
181 return 1;
182 return 0;
183}
184
daca57a7
TBA		 185bool
186ppc_target::low_cannot_store_register (int regno)
0a30fbc4 187{
3aee8918
PA		 188 const struct target_desc *tdesc = current_process ()->tdesc;
189
b6430ec3 190#ifndef __powerpc64__
bc1e36ca 191 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 192 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
193 && regno == find_regno (tdesc, "fpscr"))
daca57a7 194 return true;
30ed0a8f 195#endif
bc1e36ca 196
7284e1be 197 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 198 if (regno == find_regno (tdesc, "orig_r3")
199 || regno == find_regno (tdesc, "trap"))
daca57a7 200 return true;
7284e1be 201
daca57a7 202 return false;
0a30fbc4
DJ		 203}
204
daca57a7
TBA		 205bool
206ppc_target::low_cannot_fetch_register (int regno)
0a30fbc4 207{
daca57a7 208 return false;
0a30fbc4
DJ		 209}
210
5b0a002e 211static void
442ea881 212ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 213{
76b233dd
UW		 214 memset (buf, 0, sizeof (long));
215
2e4bb98a
EBM		 216 if (__BYTE_ORDER == __LITTLE_ENDIAN)
217 {
218 /* Little-endian values always sit at the left end of the buffer. */
219 collect_register (regcache, regno, buf);
220 }
221 else if (__BYTE_ORDER == __BIG_ENDIAN)
222 {
223 /* Big-endian values sit at the right end of the buffer. In case of
224 registers whose sizes are smaller than sizeof (long), we must use a
225 padding to access them correctly. */
226 int size = register_size (regcache->tdesc, regno);
227
228 if (size < sizeof (long))
229 collect_register (regcache, regno, buf + sizeof (long) - size);
230 else
231 collect_register (regcache, regno, buf);
232 }
5b0a002e 233 else
2e4bb98a 234 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 235}
236
237static void
442ea881
PA		 238ppc_supply_ptrace_register (struct regcache *regcache,
239 int regno, const char *buf)
5b0a002e 240{
2e4bb98a
EBM		 241 if (__BYTE_ORDER == __LITTLE_ENDIAN)
242 {
243 /* Little-endian values always sit at the left end of the buffer. */
244 supply_register (regcache, regno, buf);
245 }
246 else if (__BYTE_ORDER == __BIG_ENDIAN)
247 {
248 /* Big-endian values sit at the right end of the buffer. In case of
249 registers whose sizes are smaller than sizeof (long), we must use a
250 padding to access them correctly. */
251 int size = register_size (regcache->tdesc, regno);
252
253 if (size < sizeof (long))
254 supply_register (regcache, regno, buf + sizeof (long) - size);
255 else
256 supply_register (regcache, regno, buf);
257 }
5b0a002e 258 else
2e4bb98a 259 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 260}
261
bf9ae9d8
TBA		 262bool
263ppc_target::low_supports_breakpoints ()
264{
265 return true;
266}
267
268CORE_ADDR
269ppc_target::low_get_pc (regcache *regcache)
0d62e5e8 270{
abf516c6 271 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 272 {
273 unsigned int pc;
442ea881 274 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 275 return (CORE_ADDR) pc;
276 }
277 else
278 {
279 unsigned long pc;
442ea881 280 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 281 return (CORE_ADDR) pc;
282 }
0d62e5e8
DJ		 283}
284
bf9ae9d8
TBA		 285void
286ppc_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
0d62e5e8 287{
abf516c6 288 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 289 {
290 unsigned int newpc = pc;
442ea881 291 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 292 }
293 else
294 {
295 unsigned long newpc = pc;
442ea881 296 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 297 }
298}
299
3aee8918
PA		 300#ifndef __powerpc64__
301static int ppc_regmap_adjusted;
302#endif
303
0d62e5e8 304
5b0a002e 305/* Correct in either endianness.
0d62e5e8
DJ		 306 This instruction is "twge r2, r2", which GDB uses as a software
307 breakpoint. */
5b0a002e 308static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 309#define ppc_breakpoint_len 4
310
3ca4edb6 311/* Implementation of target ops method "sw_breakpoint_from_kind". */
dd373349 312
3ca4edb6
TBA		 313const gdb_byte *
314ppc_target::sw_breakpoint_from_kind (int kind, int *size)
dd373349
AT		 315{
316 *size = ppc_breakpoint_len;
317 return (const gdb_byte *) &ppc_breakpoint;
318}
319
d7146cda
TBA		 320bool
321ppc_target::low_breakpoint_at (CORE_ADDR where)
0d62e5e8 322{
5b0a002e 323 unsigned int insn;
0d62e5e8 324
d7146cda 325 read_memory (where, (unsigned char *) &insn, 4);
abf516c6 326 if (insn == ppc_breakpoint)
d7146cda 327 return true;
abf516c6
UW		 328 /* If necessary, recognize more trap instructions here. GDB only uses
329 the one. */
0b9ff2c0 330
d7146cda 331 return false;
0d62e5e8
DJ		 332}
333
657f9cde
WW		 334/* Implement supports_z_point_type target-ops.
335 Returns true if type Z_TYPE breakpoint is supported.
336
337 Handling software breakpoint at server side, so tracepoints
338 and breakpoints can be inserted at the same location. */
339
007c9b97
TBA		 340bool
341ppc_target::supports_z_point_type (char z_type)
657f9cde
WW		 342{
343 switch (z_type)
344 {
345 case Z_PACKET_SW_BP:
007c9b97 346 return true;
657f9cde
WW		 347 case Z_PACKET_HW_BP:
348 case Z_PACKET_WRITE_WP:
349 case Z_PACKET_ACCESS_WP:
350 default:
007c9b97 351 return false;
657f9cde
WW		 352 }
353}
354
9db9aa23 355/* Implement the low_insert_point linux target op.
657f9cde
WW		 356 Returns 0 on success, -1 on failure and 1 on unsupported. */
357
9db9aa23
TBA		 358int
359ppc_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
360 int size, raw_breakpoint *bp)
657f9cde
WW		 361{
362 switch (type)
363 {
364 case raw_bkpt_type_sw:
365 return insert_memory_breakpoint (bp);
366
367 case raw_bkpt_type_hw:
368 case raw_bkpt_type_write_wp:
369 case raw_bkpt_type_access_wp:
370 default:
371 /* Unsupported. */
372 return 1;
373 }
374}
375
9db9aa23 376/* Implement the low_remove_point linux target op.
657f9cde
WW		 377 Returns 0 on success, -1 on failure and 1 on unsupported. */
378
9db9aa23
TBA		 379int
380ppc_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
381 int size, raw_breakpoint *bp)
657f9cde
WW		 382{
383 switch (type)
384 {
385 case raw_bkpt_type_sw:
386 return remove_memory_breakpoint (bp);
387
388 case raw_bkpt_type_hw:
389 case raw_bkpt_type_write_wp:
390 case raw_bkpt_type_access_wp:
391 default:
392 /* Unsupported. */
393 return 1;
394 }
395}
396
e9d25b98
DJ		 397/* Provide only a fill function for the general register set. ps_lgetregs
398 will use this for NPTL support. */
399
442ea881 400static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 401{
402 int i;
403
404 for (i = 0; i < 32; i++)
442ea881 405 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 406
407 for (i = 64; i < 70; i++)
442ea881 408 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 409
410 for (i = 71; i < 73; i++)
442ea881 411 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 412}
413
7ca18ed6
EBM		 414/* Program Priority Register regset fill function. */
415
416static void
417ppc_fill_pprregset (struct regcache *regcache, void *buf)
418{
419 char *ppr = (char *) buf;
420
421 collect_register_by_name (regcache, "ppr", ppr);
422}
423
424/* Program Priority Register regset store function. */
425
426static void
427ppc_store_pprregset (struct regcache *regcache, const void *buf)
428{
429 const char *ppr = (const char *) buf;
430
431 supply_register_by_name (regcache, "ppr", ppr);
432}
433
434/* Data Stream Control Register regset fill function. */
435
436static void
437ppc_fill_dscrregset (struct regcache *regcache, void *buf)
438{
439 char *dscr = (char *) buf;
440
441 collect_register_by_name (regcache, "dscr", dscr);
442}
443
444/* Data Stream Control Register regset store function. */
445
446static void
447ppc_store_dscrregset (struct regcache *regcache, const void *buf)
448{
449 const char *dscr = (const char *) buf;
450
451 supply_register_by_name (regcache, "dscr", dscr);
452}
453
f2cf6173
EBM		 454/* Target Address Register regset fill function. */
455
456static void
457ppc_fill_tarregset (struct regcache *regcache, void *buf)
458{
459 char *tar = (char *) buf;
460
461 collect_register_by_name (regcache, "tar", tar);
462}
463
464/* Target Address Register regset store function. */
465
466static void
467ppc_store_tarregset (struct regcache *regcache, const void *buf)
468{
469 const char *tar = (const char *) buf;
470
471 supply_register_by_name (regcache, "tar", tar);
472}
473
232bfb86
EBM		 474/* Event-Based Branching regset store function. Unless the inferior
475 has a perf event open, ptrace can return in error when reading and
476 writing to the regset, with ENODATA. For reading, the registers
477 will correctly show as unavailable. For writing, gdbserver
478 currently only caches any register writes from P and G packets and
479 the stub always tries to write all the regsets when resuming the
480 inferior, which would result in frequent warnings. For this
481 reason, we don't define a fill function. This also means that the
482 client-side regcache will be dirty if the user tries to write to
483 the EBB registers. G packets that the client sends to write to
484 unrelated registers will also include data for EBB registers, even
485 if they are unavailable. */
486
487static void
488ppc_store_ebbregset (struct regcache *regcache, const void *buf)
489{
490 const char *regset = (const char *) buf;
491
492 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
493 .dat file is BESCR, EBBHR, EBBRR. */
494 supply_register_by_name (regcache, "ebbrr", &regset[0]);
495 supply_register_by_name (regcache, "ebbhr", &regset[8]);
496 supply_register_by_name (regcache, "bescr", &regset[16]);
497}
498
499/* Performance Monitoring Unit regset fill function. */
500
501static void
502ppc_fill_pmuregset (struct regcache *regcache, void *buf)
503{
504 char *regset = (char *) buf;
505
506 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
507 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
508 collect_register_by_name (regcache, "siar", &regset[0]);
509 collect_register_by_name (regcache, "sdar", &regset[8]);
510 collect_register_by_name (regcache, "sier", &regset[16]);
511 collect_register_by_name (regcache, "mmcr2", &regset[24]);
512 collect_register_by_name (regcache, "mmcr0", &regset[32]);
513}
514
515/* Performance Monitoring Unit regset store function. */
516
517static void
518ppc_store_pmuregset (struct regcache *regcache, const void *buf)
519{
520 const char *regset = (const char *) buf;
521
522 supply_register_by_name (regcache, "siar", &regset[0]);
523 supply_register_by_name (regcache, "sdar", &regset[8]);
524 supply_register_by_name (regcache, "sier", &regset[16]);
525 supply_register_by_name (regcache, "mmcr2", &regset[24]);
526 supply_register_by_name (regcache, "mmcr0", &regset[32]);
527}
528
8d619c01
EBM		 529/* Hardware Transactional Memory special-purpose register regset fill
530 function. */
531
532static void
533ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
534{
535 int i, base;
536 char *regset = (char *) buf;
537
538 base = find_regno (regcache->tdesc, "tfhar");
539 for (i = 0; i < 3; i++)
540 collect_register (regcache, base + i, &regset[i * 8]);
541}
542
543/* Hardware Transactional Memory special-purpose register regset store
544 function. */
545
546static void
547ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
548{
549 int i, base;
550 const char *regset = (const char *) buf;
551
552 base = find_regno (regcache->tdesc, "tfhar");
553 for (i = 0; i < 3; i++)
554 supply_register (regcache, base + i, &regset[i * 8]);
555}
556
557/* For the same reasons as the EBB regset, none of the HTM
558 checkpointed regsets have a fill function. These registers are
559 only available if the inferior is in a transaction. */
560
561/* Hardware Transactional Memory checkpointed general-purpose regset
562 store function. */
563
564static void
565ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
566{
567 int i, base, size, endian_offset;
568 const char *regset = (const char *) buf;
569
570 base = find_regno (regcache->tdesc, "cr0");
571 size = register_size (regcache->tdesc, base);
572
573 gdb_assert (size == 4 || size == 8);
574
575 for (i = 0; i < 32; i++)
576 supply_register (regcache, base + i, &regset[i * size]);
577
578 endian_offset = 0;
579
580 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
581 endian_offset = 4;
582
583 supply_register_by_name (regcache, "ccr",
584 &regset[PT_CCR * size + endian_offset]);
585
586 supply_register_by_name (regcache, "cxer",
587 &regset[PT_XER * size + endian_offset]);
588
589 supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
590 supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
591}
592
593/* Hardware Transactional Memory checkpointed floating-point regset
594 store function. */
595
596static void
597ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
598{
599 int i, base;
600 const char *regset = (const char *) buf;
601
602 base = find_regno (regcache->tdesc, "cf0");
603
604 for (i = 0; i < 32; i++)
605 supply_register (regcache, base + i, &regset[i * 8]);
606
607 supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
608}
609
610/* Hardware Transactional Memory checkpointed vector regset store
611 function. */
612
613static void
614ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
615{
616 int i, base;
617 const char *regset = (const char *) buf;
618 int vscr_offset = 0;
619
620 base = find_regno (regcache->tdesc, "cvr0");
621
622 for (i = 0; i < 32; i++)
623 supply_register (regcache, base + i, &regset[i * 16]);
624
625 if (__BYTE_ORDER == __BIG_ENDIAN)
626 vscr_offset = 12;
627
628 supply_register_by_name (regcache, "cvscr",
629 &regset[32 * 16 + vscr_offset]);
630
631 supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
632}
633
634/* Hardware Transactional Memory checkpointed vector-scalar regset
635 store function. */
636
637static void
638ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
639{
640 int i, base;
641 const char *regset = (const char *) buf;
642
643 base = find_regno (regcache->tdesc, "cvs0h");
644 for (i = 0; i < 32; i++)
645 supply_register (regcache, base + i, &regset[i * 8]);
646}
647
648/* Hardware Transactional Memory checkpointed Program Priority
649 Register regset store function. */
650
651static void
652ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
653{
654 const char *cppr = (const char *) buf;
655
656 supply_register_by_name (regcache, "cppr", cppr);
657}
658
659/* Hardware Transactional Memory checkpointed Data Stream Control
660 Register regset store function. */
661
662static void
663ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
664{
665 const char *cdscr = (const char *) buf;
666
667 supply_register_by_name (regcache, "cdscr", cdscr);
668}
669
670/* Hardware Transactional Memory checkpointed Target Address Register
671 regset store function. */
672
673static void
674ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
675{
676 const char *ctar = (const char *) buf;
677
678 supply_register_by_name (regcache, "ctar", ctar);
679}
680
677c5bb1 681static void
442ea881 682ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 683{
684 int i, base;
2bc84e8a 685 char *regset = (char *) buf;
677c5bb1 686
3aee8918 687 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 688 for (i = 0; i < 32; i++)
442ea881 689 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 690}
691
692static void
442ea881 693ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 694{
695 int i, base;
2bc84e8a 696 const char *regset = (const char *) buf;
677c5bb1 697
3aee8918 698 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 699 for (i = 0; i < 32; i++)
442ea881 700 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 701}
702
30ed0a8f 703static void
442ea881 704ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 705{
706 int i, base;
2bc84e8a 707 char *regset = (char *) buf;
1d75a658 708 int vscr_offset = 0;
30ed0a8f 709
3aee8918 710 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 711 for (i = 0; i < 32; i++)
442ea881 712 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 713
1d75a658
PFC		 714 if (__BYTE_ORDER == __BIG_ENDIAN)
715 vscr_offset = 12;
716
1d75a658
PFC		 717 collect_register_by_name (regcache, "vscr",
718 &regset[32 * 16 + vscr_offset]);
719
442ea881 720 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 721}
722
723static void
442ea881 724ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 725{
726 int i, base;
2bc84e8a 727 const char *regset = (const char *) buf;
1d75a658 728 int vscr_offset = 0;
30ed0a8f 729
3aee8918 730 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 731 for (i = 0; i < 32; i++)
442ea881 732 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 733
1d75a658
PFC		 734 if (__BYTE_ORDER == __BIG_ENDIAN)
735 vscr_offset = 12;
736
737 supply_register_by_name (regcache, "vscr",
738 &regset[32 * 16 + vscr_offset]);
442ea881 739 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 740}
741
30ed0a8f
DJ		 742struct gdb_evrregset_t
743{
744 unsigned long evr[32];
745 unsigned long long acc;
746 unsigned long spefscr;
747};
748
749static void
442ea881 750ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 751{
752 int i, ev0;
2bc84e8a 753 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 754
3aee8918 755 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 756 for (i = 0; i < 32; i++)
442ea881 757 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 758
442ea881
PA		 759 collect_register_by_name (regcache, "acc", &regset->acc);
760 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 761}
762
763static void
442ea881 764ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 765{
766 int i, ev0;
2bc84e8a 767 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 768
3aee8918 769 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 770 for (i = 0; i < 32; i++)
442ea881 771 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 772
442ea881
PA		 773 supply_register_by_name (regcache, "acc", &regset->acc);
774 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 775}
30ed0a8f 776
7d00775e
AT		 777/* Support for hardware single step. */
778
779static int
780ppc_supports_hardware_single_step (void)
781{
782 return 1;
783}
784
3aee8918 785static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 786 /* List the extra register sets before GENERAL_REGS. That way we will
787 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
788 general registers. Some kernels support these, but not the newer
789 PPC_PTRACE_GETREGS. */
8d619c01
EBM		 790 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
791 NULL, ppc_store_tm_ctarregset },
792 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
793 NULL, ppc_store_tm_cdscrregset },
794 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
795 NULL, ppc_store_tm_cpprregset },
796 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
797 NULL, ppc_store_tm_cvsxregset },
798 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
799 NULL, ppc_store_tm_cvrregset },
800 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
801 NULL, ppc_store_tm_cfprregset },
802 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
803 NULL, ppc_store_tm_cgprregset },
804 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
805 ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
232bfb86
EBM		 806 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
807 NULL, ppc_store_ebbregset },
808 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
809 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 810 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
811 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 812 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
813 ppc_fill_pprregset, ppc_store_pprregset },
814 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
815 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 816 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 817 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 818 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 819 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 820 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 821 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 822 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 823 NULL_REGSET
e9d25b98
DJ		 824};
825
3aee8918
PA		 826static struct usrregs_info ppc_usrregs_info =
827 {
828 ppc_num_regs,
829 ppc_regmap,
830 };
831
832static struct regsets_info ppc_regsets_info =
833 {
834 ppc_regsets, /* regsets */
835 0, /* num_regsets */
836 NULL, /* disabled_regsets */
837 };
838
aa8d21c9 839static struct regs_info myregs_info =
3aee8918
PA		 840 {
841 NULL, /* regset_bitmap */
842 &ppc_usrregs_info,
843 &ppc_regsets_info
844 };
845
aa8d21c9
TBA		 846const regs_info *
847ppc_target::get_regs_info ()
3aee8918 848{
aa8d21c9 849 return &myregs_info;
3aee8918
PA		 850}
851
797bcff5
TBA		 852void
853ppc_target::low_arch_setup ()
e6c5bb05
SM		 854{
855 const struct target_desc *tdesc;
7273b5fc 856 struct regset_info *regset;
bd64614e 857 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 858
2e077f5e 859 int tid = lwpid_of (current_thread);
bd64614e 860
2e077f5e 861 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 862
bd64614e 863 if (features.wordsize == 4)
bd64614e 864 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 865 else
866 tdesc = tdesc_powerpc_64l;
867
868 current_process ()->tdesc = tdesc;
e6c5bb05 869
bd64614e
PFC		 870 /* The value of current_process ()->tdesc needs to be set for this
871 call. */
974c89e0
AH		 872 ppc_hwcap = linux_get_hwcap (features.wordsize);
873 ppc_hwcap2 = linux_get_hwcap2 (features.wordsize);
bd64614e
PFC		 874
875 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
876
877 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
878 features.vsx = true;
879
880 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
881 features.altivec = true;
882
7ca18ed6
EBM		 883 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
884 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
885 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 886 {
887 features.ppr_dscr = true;
888 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
889 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 890 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 891 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 892 PPC_LINUX_SIZEOF_TARREGSET)
893 && ppc_check_regset (tid, NT_PPC_EBB,
894 PPC_LINUX_SIZEOF_EBBREGSET)
895 && ppc_check_regset (tid, NT_PPC_PMU,
896 PPC_LINUX_SIZEOF_PMUREGSET))
8d619c01
EBM		 897 {
898 features.isa207 = true;
899 if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
900 && ppc_check_regset (tid, NT_PPC_TM_SPR,
901 PPC_LINUX_SIZEOF_TM_SPRREGSET))
902 features.htm = true;
903 }
f2cf6173 904 }
7ca18ed6 905
bd64614e 906 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 907
908 /* On 32-bit machines, check for SPE registers.
909 Set the low target's regmap field as appropriately. */
910#ifndef __powerpc64__
911 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
912 tdesc = tdesc_powerpc_e500l;
913
914 if (!ppc_regmap_adjusted)
915 {
916 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
917 ppc_usrregs_info.regmap = ppc_regmap_e500;
918
919 /* If the FPSCR is 64-bit wide, we need to fetch the whole
920 64-bit slot and not just its second word. The PT_FPSCR
921 supplied in a 32-bit GDB compilation doesn't reflect
922 this. */
923 if (register_size (tdesc, 70) == 8)
924 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
925
926 ppc_regmap_adjusted = 1;
927 }
928#endif
bd64614e 929
e6c5bb05 930 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 931
932 for (regset = ppc_regsets; regset->size >= 0; regset++)
933 switch (regset->get_request)
934 {
935 case PTRACE_GETVRREGS:
d078308a 936 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 937 break;
938 case PTRACE_GETVSXREGS:
d078308a 939 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 940 break;
941 case PTRACE_GETEVRREGS:
942 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
943 regset->size = 32 * 4 + 8 + 4;
944 else
945 regset->size = 0;
946 break;
7ca18ed6
EBM		 947 case PTRACE_GETREGSET:
948 switch (regset->nt_type)
949 {
950 case NT_PPC_PPR:
951 regset->size = (features.ppr_dscr ?
952 PPC_LINUX_SIZEOF_PPRREGSET : 0);
953 break;
954 case NT_PPC_DSCR:
955 regset->size = (features.ppr_dscr ?
956 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
957 break;
f2cf6173
EBM		 958 case NT_PPC_TAR:
959 regset->size = (features.isa207 ?
960 PPC_LINUX_SIZEOF_TARREGSET : 0);
961 break;
232bfb86
EBM		 962 case NT_PPC_EBB:
963 regset->size = (features.isa207 ?
964 PPC_LINUX_SIZEOF_EBBREGSET : 0);
965 break;
966 case NT_PPC_PMU:
967 regset->size = (features.isa207 ?
968 PPC_LINUX_SIZEOF_PMUREGSET : 0);
969 break;
8d619c01
EBM		 970 case NT_PPC_TM_SPR:
971 regset->size = (features.htm ?
972 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
973 break;
974 case NT_PPC_TM_CGPR:
975 if (features.wordsize == 4)
976 regset->size = (features.htm ?
977 PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
978 else
979 regset->size = (features.htm ?
980 PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
981 break;
982 case NT_PPC_TM_CFPR:
983 regset->size = (features.htm ?
984 PPC_LINUX_SIZEOF_CFPRREGSET : 0);
985 break;
986 case NT_PPC_TM_CVMX:
987 regset->size = (features.htm ?
988 PPC_LINUX_SIZEOF_CVMXREGSET : 0);
989 break;
990 case NT_PPC_TM_CVSX:
991 regset->size = (features.htm ?
992 PPC_LINUX_SIZEOF_CVSXREGSET : 0);
993 break;
994 case NT_PPC_TM_CPPR:
995 regset->size = (features.htm ?
996 PPC_LINUX_SIZEOF_CPPRREGSET : 0);
997 break;
998 case NT_PPC_TM_CDSCR:
999 regset->size = (features.htm ?
1000 PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
1001 break;
1002 case NT_PPC_TM_CTAR:
1003 regset->size = (features.htm ?
1004 PPC_LINUX_SIZEOF_CTARREGSET : 0);
1005 break;
7ca18ed6
EBM		 1006 default:
1007 break;
1008 }
1009 break;
7273b5fc
PFC		 1010 default:
1011 break;
1012 }
e6c5bb05
SM		 1013}
1014
a2174ba4
MK		 1015/* Implementation of linux_target_ops method "supports_tracepoints". */
1016
b04fd3be
MK		 1017static int
1018ppc_supports_tracepoints (void)
1019{
1020 return 1;
1021}
1022
a2174ba4
MK		 1023/* Get the thread area address. This is used to recognize which
1024 thread is which when tracing with the in-process agent library. We
1025 don't read anything from the address, and treat it as opaque; it's
1026 the address itself that we assume is unique per-thread. */
1027
1028static int
1029ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
1030{
f2907e49 1031 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 1032 struct thread_info *thr = get_lwp_thread (lwp);
1033 struct regcache *regcache = get_thread_regcache (thr, 1);
1034 ULONGEST tp = 0;
1035
1036#ifdef __powerpc64__
1037 if (register_size (regcache->tdesc, 0) == 8)
1038 collect_register_by_name (regcache, "r13", &tp);
1039 else
1040#endif
1041 collect_register_by_name (regcache, "r2", &tp);
1042
1043 *addr = tp;
1044
1045 return 0;
1046}
1047
1048#ifdef __powerpc64__
1049
1050/* Older glibc doesn't provide this. */
1051
1052#ifndef EF_PPC64_ABI
1053#define EF_PPC64_ABI 3
1054#endif
1055
1056/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1057 inferiors. */
1058
1059static int
1060is_elfv2_inferior (void)
1061{
1062 /* To be used as fallback if we're unable to determine the right result -
1063 assume inferior uses the same ABI as gdbserver. */
1064#if _CALL_ELF == 2
1065 const int def_res = 1;
1066#else
1067 const int def_res = 0;
1068#endif
0570503d 1069 CORE_ADDR phdr;
a2174ba4
MK		 1070 Elf64_Ehdr ehdr;
1071
0570503d
PFC		 1072 const struct target_desc *tdesc = current_process ()->tdesc;
1073 int wordsize = register_size (tdesc, 0);
1074
1075 if (!linux_get_auxv (wordsize, AT_PHDR, &phdr))
a2174ba4
MK		 1076 return def_res;
1077
1078 /* Assume ELF header is at the beginning of the page where program headers
1079 are located. If it doesn't look like one, bail. */
1080
1081 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
1082 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
1083 return def_res;
1084
1085 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
1086}
1087
1088#endif
1089
1090/* Generate a ds-form instruction in BUF and return the number of bytes written
1091
1092 0 6 11 16 30 32
1093 | OPCD | RST | RA | DS |XO| */
1094
1095__attribute__((unused)) /* Maybe unused due to conditional compilation. */
1096static int
1097gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
1098{
1099 uint32_t insn;
1100
1101 gdb_assert ((opcd & ~0x3f) == 0);
1102 gdb_assert ((rst & ~0x1f) == 0);
1103 gdb_assert ((ra & ~0x1f) == 0);
1104 gdb_assert ((xo & ~0x3) == 0);
1105
1106 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
1107 *buf = (opcd << 26) | insn;
1108 return 1;
1109}
1110
1111/* Followings are frequently used ds-form instructions. */
1112
1113#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1114#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1115#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1116#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1117
1118/* Generate a d-form instruction in BUF.
1119
1120 0 6 11 16 32
1121 | OPCD | RST | RA | D | */
1122
1123static int
1124gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
1125{
1126 uint32_t insn;
1127
1128 gdb_assert ((opcd & ~0x3f) == 0);
1129 gdb_assert ((rst & ~0x1f) == 0);
1130 gdb_assert ((ra & ~0x1f) == 0);
1131
1132 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
1133 *buf = (opcd << 26) | insn;
1134 return 1;
1135}
1136
1137/* Followings are frequently used d-form instructions. */
1138
1139#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1140#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1141#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1142#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1143#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1144#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1145#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1146#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1147#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1148
1149/* Generate a xfx-form instruction in BUF and return the number of bytes
1150 written.
1151
1152 0 6 11 21 31 32
1153 | OPCD | RST | RI | XO |/| */
1154
1155static int
1156gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1157{
1158 uint32_t insn;
1159 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1160
1161 gdb_assert ((opcd & ~0x3f) == 0);
1162 gdb_assert ((rst & ~0x1f) == 0);
1163 gdb_assert ((xo & ~0x3ff) == 0);
1164
1165 insn = (rst << 21) | (n << 11) | (xo << 1);
1166 *buf = (opcd << 26) | insn;
1167 return 1;
1168}
1169
1170/* Followings are frequently used xfx-form instructions. */
1171
1172#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1173#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1174#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1175#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1176#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1177 E & 0xf, 598)
1178#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1179
1180
1181/* Generate a x-form instruction in BUF and return the number of bytes written.
1182
1183 0 6 11 16 21 31 32
1184 | OPCD | RST | RA | RB | XO |RC| */
1185
1186static int
1187gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1188{
1189 uint32_t insn;
1190
1191 gdb_assert ((opcd & ~0x3f) == 0);
1192 gdb_assert ((rst & ~0x1f) == 0);
1193 gdb_assert ((ra & ~0x1f) == 0);
1194 gdb_assert ((rb & ~0x1f) == 0);
1195 gdb_assert ((xo & ~0x3ff) == 0);
1196 gdb_assert ((rc & ~1) == 0);
1197
1198 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1199 *buf = (opcd << 26) | insn;
1200 return 1;
1201}
1202
1203/* Followings are frequently used x-form instructions. */
1204
1205#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1206#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1207#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1208#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1209/* Assume bf = cr7. */
1210#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1211
1212
1213/* Generate a md-form instruction in BUF and return the number of bytes written.
1214
1215 0 6 11 16 21 27 30 31 32
1216 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1217
1218static int
1219gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1220 int xo, int rc)
1221{
1222 uint32_t insn;
1223 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1224 unsigned int sh0_4 = sh & 0x1f;
1225 unsigned int sh5 = (sh >> 5) & 1;
1226
1227 gdb_assert ((opcd & ~0x3f) == 0);
1228 gdb_assert ((rs & ~0x1f) == 0);
1229 gdb_assert ((ra & ~0x1f) == 0);
1230 gdb_assert ((sh & ~0x3f) == 0);
1231 gdb_assert ((mb & ~0x3f) == 0);
1232 gdb_assert ((xo & ~0x7) == 0);
1233 gdb_assert ((rc & ~0x1) == 0);
1234
1235 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1236 | (sh5 << 1) | (xo << 2) | (rc & 1);
1237 *buf = (opcd << 26) | insn;
1238 return 1;
1239}
1240
1241/* The following are frequently used md-form instructions. */
1242
1243#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1244 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1245#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1246 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1247
1248/* Generate a i-form instruction in BUF and return the number of bytes written.
1249
1250 0 6 30 31 32
1251 | OPCD | LI |AA|LK| */
1252
1253static int
1254gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1255{
1256 uint32_t insn;
1257
1258 gdb_assert ((opcd & ~0x3f) == 0);
1259
1260 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1261 *buf = (opcd << 26) | insn;
1262 return 1;
1263}
1264
1265/* The following are frequently used i-form instructions. */
1266
1267#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1268#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1269
1270/* Generate a b-form instruction in BUF and return the number of bytes written.
1271
1272 0 6 11 16 30 31 32
1273 | OPCD | BO | BI | BD |AA|LK| */
1274
1275static int
1276gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1277 int aa, int lk)
1278{
1279 uint32_t insn;
1280
1281 gdb_assert ((opcd & ~0x3f) == 0);
1282 gdb_assert ((bo & ~0x1f) == 0);
1283 gdb_assert ((bi & ~0x1f) == 0);
1284
1285 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1286 *buf = (opcd << 26) | insn;
1287 return 1;
1288}
1289
1290/* The following are frequently used b-form instructions. */
1291/* Assume bi = cr7. */
1292#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1293
1294/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1295 respectively. They are primary used for save/restore GPRs in jump-pad,
1296 not used for bytecode compiling. */
1297
1298#ifdef __powerpc64__
1299#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1300 GEN_LD (buf, rt, ra, si) : \
1301 GEN_LWZ (buf, rt, ra, si))
1302#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1303 GEN_STD (buf, rt, ra, si) : \
1304 GEN_STW (buf, rt, ra, si))
1305#else
1306#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1307#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1308#endif
1309
1310/* Generate a sequence of instructions to load IMM in the register REG.
1311 Write the instructions in BUF and return the number of bytes written. */
1312
1313static int
1314gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1315{
1316 uint32_t *p = buf;
1317
1318 if ((imm + 32768) < 65536)
1319 {
1320 /* li reg, imm[15:0] */
1321 p += GEN_LI (p, reg, imm);
1322 }
1323 else if ((imm >> 32) == 0)
1324 {
1325 /* lis reg, imm[31:16]
1326 ori reg, reg, imm[15:0]
1327 rldicl reg, reg, 0, 32 */
1328 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1329 if ((imm & 0xffff) != 0)
1330 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1331 /* Clear upper 32-bit if sign-bit is set. */
1332 if (imm & (1u << 31) && is_64)
1333 p += GEN_RLDICL (p, reg, reg, 0, 32);
1334 }
1335 else
1336 {
1337 gdb_assert (is_64);
1338 /* lis reg, <imm[63:48]>
1339 ori reg, reg, <imm[48:32]>
1340 rldicr reg, reg, 32, 31
1341 oris reg, reg, <imm[31:16]>
1342 ori reg, reg, <imm[15:0]> */
1343 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1344 if (((imm >> 32) & 0xffff) != 0)
1345 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1346 p += GEN_RLDICR (p, reg, reg, 32, 31);
1347 if (((imm >> 16) & 0xffff) != 0)
1348 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1349 if ((imm & 0xffff) != 0)
1350 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1351 }
1352
1353 return p - buf;
1354}
1355
1356/* Generate a sequence for atomically exchange at location LOCK.
1357 This code sequence clobbers r6, r7, r8. LOCK is the location for
1358 the atomic-xchg, OLD_VALUE is expected old value stored in the
1359 location, and R_NEW is a register for the new value. */
1360
1361static int
1362gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1363 int is_64)
1364{
1365 const int r_lock = 6;
1366 const int r_old = 7;
1367 const int r_tmp = 8;
1368 uint32_t *p = buf;
1369
1370 /*
1371 1: lwarx TMP, 0, LOCK
1372 cmpwi TMP, OLD
1373 bne 1b
1374 stwcx. NEW, 0, LOCK
1375 bne 1b */
1376
1377 p += gen_limm (p, r_lock, lock, is_64);
1378 p += gen_limm (p, r_old, old_value, is_64);
1379
1380 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1381 p += GEN_CMPW (p, r_tmp, r_old);
1382 p += GEN_BNE (p, -8);
1383 p += GEN_STWCX (p, r_new, 0, r_lock);
1384 p += GEN_BNE (p, -16);
1385
1386 return p - buf;
1387}
1388
1389/* Generate a sequence of instructions for calling a function
1390 at address of FN. Return the number of bytes are written in BUF. */
1391
1392static int
1393gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1394{
1395 uint32_t *p = buf;
1396
1397 /* Must be called by r12 for caller to calculate TOC address. */
1398 p += gen_limm (p, 12, fn, is_64);
1399 if (is_opd)
1400 {
1401 p += GEN_LOAD (p, 11, 12, 16, is_64);
1402 p += GEN_LOAD (p, 2, 12, 8, is_64);
1403 p += GEN_LOAD (p, 12, 12, 0, is_64);
1404 }
1405 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1406 *p++ = 0x4e800421; /* bctrl */
1407
1408 return p - buf;
1409}
1410
1411/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1412 of instruction. This function is used to adjust pc-relative instructions
1413 when copying. */
1414
1415static void
1416ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1417{
1418 uint32_t insn, op6;
1419 long rel, newrel;
1420
1421 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1422 op6 = PPC_OP6 (insn);
1423
1424 if (op6 == 18 && (insn & 2) == 0)
1425 {
1426 /* branch && AA = 0 */
1427 rel = PPC_LI (insn);
1428 newrel = (oldloc - *to) + rel;
1429
1430 /* Out of range. Cannot relocate instruction. */
1431 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1432 return;
1433
1434 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1435 }
1436 else if (op6 == 16 && (insn & 2) == 0)
1437 {
1438 /* conditional branch && AA = 0 */
1439
1440 /* If the new relocation is too big for even a 26-bit unconditional
1441 branch, there is nothing we can do. Just abort.
1442
1443 Otherwise, if it can be fit in 16-bit conditional branch, just
1444 copy the instruction and relocate the address.
1445
1446 If the it's big for conditional-branch (16-bit), try to invert the
1447 condition and jump with 26-bit branch. For example,
1448
1449 beq .Lgoto
1450 INSN1
1451
1452 =>
1453
1454 bne 1f (+8)
1455 b .Lgoto
1456 1:INSN1
1457
1458 After this transform, we are actually jump from *TO+4 instead of *TO,
1459 so check the relocation again because it will be 1-insn farther then
1460 before if *TO is after OLDLOC.
1461
1462
1463 For BDNZT (or so) is transformed from
1464
1465 bdnzt eq, .Lgoto
1466 INSN1
1467
1468 =>
1469
1470 bdz 1f (+12)
1471 bf eq, 1f (+8)
1472 b .Lgoto
1473 1:INSN1
1474
1475 See also "BO field encodings". */
1476
1477 rel = PPC_BD (insn);
1478 newrel = (oldloc - *to) + rel;
1479
1480 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1481 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1482 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1483 {
1484 newrel -= 4;
1485
1486 /* Out of range. Cannot relocate instruction. */
1487 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1488 return;
1489
1490 if ((PPC_BO (insn) & 0x14) == 0x4)
1491 insn ^= (1 << 24);
1492 else if ((PPC_BO (insn) & 0x14) == 0x10)
1493 insn ^= (1 << 22);
1494
1495 /* Jump over the unconditional branch. */
1496 insn = (insn & ~0xfffc) | 0x8;
4196ab2a 1497 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1498 *to += 4;
1499
1500 /* Build a unconditional branch and copy LK bit. */
1501 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1502 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1503 *to += 4;
1504
1505 return;
1506 }
1507 else if ((PPC_BO (insn) & 0x14) == 0)
1508 {
1509 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1510 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1511
1512 newrel -= 8;
1513
1514 /* Out of range. Cannot relocate instruction. */
1515 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1516 return;
1517
1518 /* Copy BI field. */
1519 bf_insn |= (insn & 0x1f0000);
1520
1521 /* Invert condition. */
1522 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1523 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1524
4196ab2a 1525 target_write_memory (*to, (unsigned char *) &bdnz_insn, 4);
a2174ba4 1526 *to += 4;
4196ab2a 1527 target_write_memory (*to, (unsigned char *) &bf_insn, 4);
a2174ba4
MK		 1528 *to += 4;
1529
1530 /* Build a unconditional branch and copy LK bit. */
1531 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1532 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1533 *to += 4;
1534
1535 return;
1536 }
1537 else /* (BO & 0x14) == 0x14, branch always. */
1538 {
1539 /* Out of range. Cannot relocate instruction. */
1540 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1541 return;
1542
1543 /* Build a unconditional branch and copy LK bit. */
1544 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1545 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1546 *to += 4;
1547
1548 return;
1549 }
1550 }
1551
4196ab2a 1552 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1553 *to += 4;
1554}
1555
1556/* Implement install_fast_tracepoint_jump_pad of target_ops.
1557 See target.h for details. */
1558
1559static int
1560ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1561 CORE_ADDR collector,
1562 CORE_ADDR lockaddr,
1563 ULONGEST orig_size,
1564 CORE_ADDR *jump_entry,
1565 CORE_ADDR *trampoline,
1566 ULONGEST *trampoline_size,
1567 unsigned char *jjump_pad_insn,
1568 ULONGEST *jjump_pad_insn_size,
1569 CORE_ADDR *adjusted_insn_addr,
1570 CORE_ADDR *adjusted_insn_addr_end,
1571 char *err)
1572{
1573 uint32_t buf[256];
1574 uint32_t *p = buf;
1575 int j, offset;
1576 CORE_ADDR buildaddr = *jump_entry;
1577 const CORE_ADDR entryaddr = *jump_entry;
1578 int rsz, min_frame, frame_size, tp_reg;
1579#ifdef __powerpc64__
1580 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1581 int is_64 = register_size (regcache->tdesc, 0) == 8;
1582 int is_opd = is_64 && !is_elfv2_inferior ();
1583#else
1584 int is_64 = 0, is_opd = 0;
1585#endif
1586
1587#ifdef __powerpc64__
1588 if (is_64)
1589 {
1590 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1591 rsz = 8;
1592 min_frame = 112;
1593 frame_size = (40 * rsz) + min_frame;
1594 tp_reg = 13;
1595 }
1596 else
1597 {
1598#endif
1599 rsz = 4;
1600 min_frame = 16;
1601 frame_size = (40 * rsz) + min_frame;
1602 tp_reg = 2;
1603#ifdef __powerpc64__
1604 }
1605#endif
1606
1607 /* Stack frame layout for this jump pad,
1608
1609 High thread_area (r13/r2) |
1610 tpoint - collecting_t obj
1611 PC/<tpaddr> | +36
1612 CTR | +35
1613 LR | +34
1614 XER | +33
1615 CR | +32
1616 R31 |
1617 R29 |
1618 ... |
1619 R1 | +1
1620 R0 - collected registers
1621 ... |
1622 ... |
1623 Low Back-chain -
1624
1625
1626 The code flow of this jump pad,
1627
1628 1. Adjust SP
1629 2. Save GPR and SPR
1630 3. Prepare argument
1631 4. Call gdb_collector
1632 5. Restore GPR and SPR
1633 6. Restore SP
1634 7. Build a jump for back to the program
1635 8. Copy/relocate original instruction
30baf67b 1636 9. Build a jump for replacing original instruction. */
a2174ba4
MK		 1637
1638 /* Adjust stack pointer. */
1639 if (is_64)
1640 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1641 else
1642 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1643
1644 /* Store GPRs. Save R1 later, because it had just been modified, but
1645 we want the original value. */
1646 for (j = 2; j < 32; j++)
1647 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1648 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1649 /* Set r0 to the original value of r1 before adjusting stack frame,
1650 and then save it. */
1651 p += GEN_ADDI (p, 0, 1, frame_size);
1652 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1653
1654 /* Save CR, XER, LR, and CTR. */
1655 p += GEN_MFCR (p, 3); /* mfcr r3 */
1656 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1657 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1658 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1659 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1660 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1661 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1662 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1663
1664 /* Save PC<tpaddr> */
1665 p += gen_limm (p, 3, tpaddr, is_64);
1666 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1667
1668
1669 /* Setup arguments to collector. */
1670 /* Set r4 to collected registers. */
1671 p += GEN_ADDI (p, 4, 1, min_frame);
1672 /* Set r3 to TPOINT. */
1673 p += gen_limm (p, 3, tpoint, is_64);
1674
1675 /* Prepare collecting_t object for lock. */
1676 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1677 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1678 /* Set R5 to collecting object. */
1679 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1680
1681 p += GEN_LWSYNC (p);
1682 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1683 p += GEN_LWSYNC (p);
1684
1685 /* Call to collector. */
1686 p += gen_call (p, collector, is_64, is_opd);
1687
1688 /* Simply write 0 to release the lock. */
1689 p += gen_limm (p, 3, lockaddr, is_64);
1690 p += gen_limm (p, 4, 0, is_64);
1691 p += GEN_LWSYNC (p);
1692 p += GEN_STORE (p, 4, 3, 0, is_64);
1693
1694 /* Restore stack and registers. */
1695 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1696 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1697 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1698 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1699 p += GEN_MTCR (p, 3); /* mtcr r3 */
1700 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1701 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1702 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1703
1704 /* Restore GPRs. */
1705 for (j = 2; j < 32; j++)
1706 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1707 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1708 /* Restore SP. */
1709 p += GEN_ADDI (p, 1, 1, frame_size);
1710
1711 /* Flush instructions to inferior memory. */
4196ab2a 1712 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1713
1714 /* Now, insert the original instruction to execute in the jump pad. */
1715 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1716 *adjusted_insn_addr_end = *adjusted_insn_addr;
1717 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1718
1719 /* Verify the relocation size. If should be 4 for normal copy,
1720 8 or 12 for some conditional branch. */
1721 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1722 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1723 {
1724 sprintf (err, "E.Unexpected instruction length = %d"
1725 "when relocate instruction.",
1726 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1727 return 1;
1728 }
1729
1730 buildaddr = *adjusted_insn_addr_end;
1731 p = buf;
1732 /* Finally, write a jump back to the program. */
1733 offset = (tpaddr + 4) - buildaddr;
1734 if (offset >= (1 << 25) || offset < -(1 << 25))
1735 {
1736 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1737 "(offset 0x%x > 26-bit).", offset);
1738 return 1;
1739 }
1740 /* b <tpaddr+4> */
1741 p += GEN_B (p, offset);
4196ab2a 1742 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1743 *jump_entry = buildaddr + (p - buf) * 4;
1744
1745 /* The jump pad is now built. Wire in a jump to our jump pad. This
1746 is always done last (by our caller actually), so that we can
1747 install fast tracepoints with threads running. This relies on
1748 the agent's atomic write support. */
1749 offset = entryaddr - tpaddr;
1750 if (offset >= (1 << 25) || offset < -(1 << 25))
1751 {
1752 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1753 "(offset 0x%x > 26-bit).", offset);
1754 return 1;
1755 }
1756 /* b <jentry> */
1757 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1758 *jjump_pad_insn_size = 4;
1759
1760 return 0;
1761}
1762
1763/* Returns the minimum instruction length for installing a tracepoint. */
1764
1765static int
1766ppc_get_min_fast_tracepoint_insn_len (void)
1767{
1768 return 4;
1769}
1770
14e2b6d9
MK		 1771/* Emits a given buffer into the target at current_insn_ptr. Length
1772 is in units of 32-bit words. */
1773
1774static void
1775emit_insns (uint32_t *buf, int n)
1776{
1777 n = n * sizeof (uint32_t);
4196ab2a 1778 target_write_memory (current_insn_ptr, (unsigned char *) buf, n);
14e2b6d9
MK		 1779 current_insn_ptr += n;
1780}
1781
1782#define __EMIT_ASM(NAME, INSNS) \
1783 do \
1784 { \
1785 extern uint32_t start_bcax_ ## NAME []; \
1786 extern uint32_t end_bcax_ ## NAME []; \
1787 emit_insns (start_bcax_ ## NAME, \
1788 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1789 __asm__ (".section .text.__ppcbcax\n\t" \
1790 "start_bcax_" #NAME ":\n\t" \
1791 INSNS "\n\t" \
1792 "end_bcax_" #NAME ":\n\t" \
1793 ".previous\n\t"); \
1794 } while (0)
1795
1796#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1797#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1798
1799/*
1800
1801 Bytecode execution stack frame - 32-bit
1802
1803 | LR save area (SP + 4)
1804 SP' -> +- Back chain (SP + 0)
1805 | Save r31 for access saved arguments
1806 | Save r30 for bytecode stack pointer
1807 | Save r4 for incoming argument *value
1808 | Save r3 for incoming argument regs
1809 r30 -> +- Bytecode execution stack
1810 |
1811 | 64-byte (8 doublewords) at initial.
1812 | Expand stack as needed.
1813 |
1814 +-
1815 | Some padding for minimum stack frame and 16-byte alignment.
1816 | 16 bytes.
1817 SP +- Back-chain (SP')
1818
1819 initial frame size
1820 = 16 + (4 * 4) + 64
1821 = 96
1822
1823 r30 is the stack-pointer for bytecode machine.
1824 It should point to next-empty, so we can use LDU for pop.
1825 r3 is used for cache of the high part of TOP value.
1826 It was the first argument, pointer to regs.
1827 r4 is used for cache of the low part of TOP value.
1828 It was the second argument, pointer to the result.
1829 We should set *result = TOP after leaving this function.
1830
1831 Note:
1832 * To restore stack at epilogue
1833 => sp = r31
1834 * To check stack is big enough for bytecode execution.
1835 => r30 - 8 > SP + 8
1836 * To return execution result.
1837 => 0(r4) = TOP
1838
1839 */
1840
1841/* Regardless of endian, register 3 is always high part, 4 is low part.
1842 These defines are used when the register pair is stored/loaded.
1843 Likewise, to simplify code, have a similiar define for 5:6. */
1844
1845#if __BYTE_ORDER == __LITTLE_ENDIAN
1846#define TOP_FIRST "4"
1847#define TOP_SECOND "3"
1848#define TMP_FIRST "6"
1849#define TMP_SECOND "5"
1850#else
1851#define TOP_FIRST "3"
1852#define TOP_SECOND "4"
1853#define TMP_FIRST "5"
1854#define TMP_SECOND "6"
1855#endif
1856
1857/* Emit prologue in inferior memory. See above comments. */
1858
1859static void
1860ppc_emit_prologue (void)
1861{
1862 EMIT_ASM (/* Save return address. */
1863 "mflr 0 \n"
1864 "stw 0, 4(1) \n"
1865 /* Adjust SP. 96 is the initial frame size. */
1866 "stwu 1, -96(1) \n"
1867 /* Save r30 and incoming arguments. */
1868 "stw 31, 96-4(1) \n"
1869 "stw 30, 96-8(1) \n"
1870 "stw 4, 96-12(1) \n"
1871 "stw 3, 96-16(1) \n"
1872 /* Point r31 to original r1 for access arguments. */
1873 "addi 31, 1, 96 \n"
1874 /* Set r30 to pointing stack-top. */
1875 "addi 30, 1, 64 \n"
1876 /* Initial r3/TOP to 0. */
1877 "li 3, 0 \n"
1878 "li 4, 0 \n");
1879}
1880
1881/* Emit epilogue in inferior memory. See above comments. */
1882
1883static void
1884ppc_emit_epilogue (void)
1885{
1886 EMIT_ASM (/* *result = TOP */
1887 "lwz 5, -12(31) \n"
1888 "stw " TOP_FIRST ", 0(5) \n"
1889 "stw " TOP_SECOND ", 4(5) \n"
1890 /* Restore registers. */
1891 "lwz 31, -4(31) \n"
1892 "lwz 30, -8(31) \n"
1893 /* Restore SP. */
1894 "lwz 1, 0(1) \n"
1895 /* Restore LR. */
1896 "lwz 0, 4(1) \n"
1897 /* Return 0 for no-error. */
1898 "li 3, 0 \n"
1899 "mtlr 0 \n"
1900 "blr \n");
1901}
1902
1903/* TOP = stack[--sp] + TOP */
1904
1905static void
1906ppc_emit_add (void)
1907{
1908 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1909 "lwz " TMP_SECOND ", 4(30)\n"
1910 "addc 4, 6, 4 \n"
1911 "adde 3, 5, 3 \n");
1912}
1913
1914/* TOP = stack[--sp] - TOP */
1915
1916static void
1917ppc_emit_sub (void)
1918{
1919 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1920 "lwz " TMP_SECOND ", 4(30) \n"
1921 "subfc 4, 4, 6 \n"
1922 "subfe 3, 3, 5 \n");
1923}
1924
1925/* TOP = stack[--sp] * TOP */
1926
1927static void
1928ppc_emit_mul (void)
1929{
1930 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1931 "lwz " TMP_SECOND ", 4(30) \n"
1932 "mulhwu 7, 6, 4 \n"
1933 "mullw 3, 6, 3 \n"
1934 "mullw 5, 4, 5 \n"
1935 "mullw 4, 6, 4 \n"
1936 "add 3, 5, 3 \n"
1937 "add 3, 7, 3 \n");
1938}
1939
1940/* TOP = stack[--sp] << TOP */
1941
1942static void
1943ppc_emit_lsh (void)
1944{
1945 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1946 "lwz " TMP_SECOND ", 4(30) \n"
1947 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1948 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1949 "slw 5, 5, 4\n" /* Shift high part left */
1950 "slw 4, 6, 4\n" /* Shift low part left */
1951 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1952 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1953 "or 3, 5, 3\n"
1954 "or 3, 7, 3\n"); /* Assemble high part */
1955}
1956
1957/* Top = stack[--sp] >> TOP
1958 (Arithmetic shift right) */
1959
1960static void
1961ppc_emit_rsh_signed (void)
1962{
1963 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1964 "lwz " TMP_SECOND ", 4(30) \n"
1965 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1966 "sraw 3, 5, 4\n" /* Shift high part right */
1967 "cmpwi 7, 1\n"
1968 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1969 "sraw 4, 5, 7\n" /* Shift high to low */
1970 "b 2f\n"
1971 "1:\n"
1972 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1973 "srw 4, 6, 4\n" /* Shift low part right */
1974 "slw 5, 5, 7\n" /* Shift high to low */
1975 "or 4, 4, 5\n" /* Assemble low part */
1976 "2:\n");
1977}
1978
1979/* Top = stack[--sp] >> TOP
1980 (Logical shift right) */
1981
1982static void
1983ppc_emit_rsh_unsigned (void)
1984{
1985 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1986 "lwz " TMP_SECOND ", 4(30) \n"
1987 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1988 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1989 "srw 6, 6, 4\n" /* Shift low part right */
1990 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1991 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1992 "or 6, 6, 3\n"
1993 "srw 3, 5, 4\n" /* Shift high part right */
1994 "or 4, 6, 7\n"); /* Assemble low part */
1995}
1996
1997/* Emit code for signed-extension specified by ARG. */
1998
1999static void
2000ppc_emit_ext (int arg)
2001{
2002 switch (arg)
2003 {
2004 case 8:
2005 EMIT_ASM ("extsb 4, 4\n"
2006 "srawi 3, 4, 31");
2007 break;
2008 case 16:
2009 EMIT_ASM ("extsh 4, 4\n"
2010 "srawi 3, 4, 31");
2011 break;
2012 case 32:
2013 EMIT_ASM ("srawi 3, 4, 31");
2014 break;
2015 default:
2016 emit_error = 1;
2017 }
2018}
2019
2020/* Emit code for zero-extension specified by ARG. */
2021
2022static void
2023ppc_emit_zero_ext (int arg)
2024{
2025 switch (arg)
2026 {
2027 case 8:
2028 EMIT_ASM ("clrlwi 4,4,24\n"
2029 "li 3, 0\n");
2030 break;
2031 case 16:
2032 EMIT_ASM ("clrlwi 4,4,16\n"
2033 "li 3, 0\n");
2034 break;
2035 case 32:
2036 EMIT_ASM ("li 3, 0");
2037 break;
2038 default:
2039 emit_error = 1;
2040 }
2041}
2042
2043/* TOP = !TOP
2044 i.e., TOP = (TOP == 0) ? 1 : 0; */
2045
2046static void
2047ppc_emit_log_not (void)
2048{
2049 EMIT_ASM ("or 4, 3, 4 \n"
2050 "cntlzw 4, 4 \n"
2051 "srwi 4, 4, 5 \n"
2052 "li 3, 0 \n");
2053}
2054
2055/* TOP = stack[--sp] & TOP */
2056
2057static void
2058ppc_emit_bit_and (void)
2059{
2060 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2061 "lwz " TMP_SECOND ", 4(30) \n"
2062 "and 4, 6, 4 \n"
2063 "and 3, 5, 3 \n");
2064}
2065
2066/* TOP = stack[--sp] | TOP */
2067
2068static void
2069ppc_emit_bit_or (void)
2070{
2071 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2072 "lwz " TMP_SECOND ", 4(30) \n"
2073 "or 4, 6, 4 \n"
2074 "or 3, 5, 3 \n");
2075}
2076
2077/* TOP = stack[--sp] ^ TOP */
2078
2079static void
2080ppc_emit_bit_xor (void)
2081{
2082 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2083 "lwz " TMP_SECOND ", 4(30) \n"
2084 "xor 4, 6, 4 \n"
2085 "xor 3, 5, 3 \n");
2086}
2087
2088/* TOP = ~TOP
2089 i.e., TOP = ~(TOP | TOP) */
2090
2091static void
2092ppc_emit_bit_not (void)
2093{
2094 EMIT_ASM ("nor 3, 3, 3 \n"
2095 "nor 4, 4, 4 \n");
2096}
2097
2098/* TOP = stack[--sp] == TOP */
2099
2100static void
2101ppc_emit_equal (void)
2102{
2103 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2104 "lwz " TMP_SECOND ", 4(30) \n"
2105 "xor 4, 6, 4 \n"
2106 "xor 3, 5, 3 \n"
2107 "or 4, 3, 4 \n"
2108 "cntlzw 4, 4 \n"
2109 "srwi 4, 4, 5 \n"
2110 "li 3, 0 \n");
2111}
2112
2113/* TOP = stack[--sp] < TOP
2114 (Signed comparison) */
2115
2116static void
2117ppc_emit_less_signed (void)
2118{
2119 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2120 "lwz " TMP_SECOND ", 4(30) \n"
2121 "cmplw 6, 6, 4 \n"
2122 "cmpw 7, 5, 3 \n"
2123 /* CR6 bit 0 = low less and high equal */
2124 "crand 6*4+0, 6*4+0, 7*4+2\n"
2125 /* CR7 bit 0 = (low less and high equal) or high less */
2126 "cror 7*4+0, 7*4+0, 6*4+0\n"
2127 "mfcr 4 \n"
2128 "rlwinm 4, 4, 29, 31, 31 \n"
2129 "li 3, 0 \n");
2130}
2131
2132/* TOP = stack[--sp] < TOP
2133 (Unsigned comparison) */
2134
2135static void
2136ppc_emit_less_unsigned (void)
2137{
2138 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2139 "lwz " TMP_SECOND ", 4(30) \n"
2140 "cmplw 6, 6, 4 \n"
2141 "cmplw 7, 5, 3 \n"
2142 /* CR6 bit 0 = low less and high equal */
2143 "crand 6*4+0, 6*4+0, 7*4+2\n"
2144 /* CR7 bit 0 = (low less and high equal) or high less */
2145 "cror 7*4+0, 7*4+0, 6*4+0\n"
2146 "mfcr 4 \n"
2147 "rlwinm 4, 4, 29, 31, 31 \n"
2148 "li 3, 0 \n");
2149}
2150
2151/* Access the memory address in TOP in size of SIZE.
2152 Zero-extend the read value. */
2153
2154static void
2155ppc_emit_ref (int size)
2156{
2157 switch (size)
2158 {
2159 case 1:
2160 EMIT_ASM ("lbz 4, 0(4)\n"
2161 "li 3, 0");
2162 break;
2163 case 2:
2164 EMIT_ASM ("lhz 4, 0(4)\n"
2165 "li 3, 0");
2166 break;
2167 case 4:
2168 EMIT_ASM ("lwz 4, 0(4)\n"
2169 "li 3, 0");
2170 break;
2171 case 8:
2172 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2173 EMIT_ASM ("lwz 3, 4(4)\n"
2174 "lwz 4, 0(4)");
2175 else
2176 EMIT_ASM ("lwz 3, 0(4)\n"
2177 "lwz 4, 4(4)");
2178 break;
2179 }
2180}
2181
2182/* TOP = NUM */
2183
2184static void
2185ppc_emit_const (LONGEST num)
2186{
2187 uint32_t buf[10];
2188 uint32_t *p = buf;
2189
2190 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2191 p += gen_limm (p, 4, num & 0xffffffff, 0);
2192
2193 emit_insns (buf, p - buf);
2194 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2195}
2196
2197/* Set TOP to the value of register REG by calling get_raw_reg function
2198 with two argument, collected buffer and register number. */
2199
2200static void
2201ppc_emit_reg (int reg)
2202{
2203 uint32_t buf[13];
2204 uint32_t *p = buf;
2205
2206 /* fctx->regs is passed in r3 and then saved in -16(31). */
2207 p += GEN_LWZ (p, 3, 31, -16);
2208 p += GEN_LI (p, 4, reg); /* li r4, reg */
2209 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2210
2211 emit_insns (buf, p - buf);
2212 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2213
2214 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2215 {
2216 EMIT_ASM ("mr 5, 4\n"
2217 "mr 4, 3\n"
2218 "mr 3, 5\n");
2219 }
2220}
2221
2222/* TOP = stack[--sp] */
2223
2224static void
2225ppc_emit_pop (void)
2226{
2227 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2228 "lwz " TOP_SECOND ", 4(30) \n");
2229}
2230
2231/* stack[sp++] = TOP
2232
2233 Because we may use up bytecode stack, expand 8 doublewords more
2234 if needed. */
2235
2236static void
2237ppc_emit_stack_flush (void)
2238{
2239 /* Make sure bytecode stack is big enough before push.
2240 Otherwise, expand 64-byte more. */
2241
2242 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2243 " stw " TOP_SECOND ", 4(30)\n"
2244 " addi 5, 30, -(8 + 8) \n"
2245 " cmpw 7, 5, 1 \n"
2246 " bgt 7, 1f \n"
2247 " stwu 31, -64(1) \n"
2248 "1:addi 30, 30, -8 \n");
2249}
2250
2251/* Swap TOP and stack[sp-1] */
2252
2253static void
2254ppc_emit_swap (void)
2255{
2256 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2257 "lwz " TMP_SECOND ", 12(30) \n"
2258 "stw " TOP_FIRST ", 8(30) \n"
2259 "stw " TOP_SECOND ", 12(30) \n"
2260 "mr 3, 5 \n"
2261 "mr 4, 6 \n");
2262}
2263
2264/* Discard N elements in the stack. Also used for ppc64. */
2265
2266static void
2267ppc_emit_stack_adjust (int n)
2268{
2269 uint32_t buf[6];
2270 uint32_t *p = buf;
2271
2272 n = n << 3;
2273 if ((n >> 15) != 0)
2274 {
2275 emit_error = 1;
2276 return;
2277 }
2278
2279 p += GEN_ADDI (p, 30, 30, n);
2280
2281 emit_insns (buf, p - buf);
2282 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2283}
2284
2285/* Call function FN. */
2286
2287static void
2288ppc_emit_call (CORE_ADDR fn)
2289{
2290 uint32_t buf[11];
2291 uint32_t *p = buf;
2292
2293 p += gen_call (p, fn, 0, 0);
2294
2295 emit_insns (buf, p - buf);
2296 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2297}
2298
2299/* FN's prototype is `LONGEST(*fn)(int)'.
2300 TOP = fn (arg1)
2301 */
2302
2303static void
2304ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2305{
2306 uint32_t buf[15];
2307 uint32_t *p = buf;
2308
2309 /* Setup argument. arg1 is a 16-bit value. */
2310 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2311 p += gen_call (p, fn, 0, 0);
2312
2313 emit_insns (buf, p - buf);
2314 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2315
2316 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2317 {
2318 EMIT_ASM ("mr 5, 4\n"
2319 "mr 4, 3\n"
2320 "mr 3, 5\n");
2321 }
2322}
2323
2324/* FN's prototype is `void(*fn)(int,LONGEST)'.
2325 fn (arg1, TOP)
2326
2327 TOP should be preserved/restored before/after the call. */
2328
2329static void
2330ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2331{
2332 uint32_t buf[21];
2333 uint32_t *p = buf;
2334
2335 /* Save TOP. 0(30) is next-empty. */
2336 p += GEN_STW (p, 3, 30, 0);
2337 p += GEN_STW (p, 4, 30, 4);
2338
2339 /* Setup argument. arg1 is a 16-bit value. */
2340 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2341 {
2342 p += GEN_MR (p, 5, 4);
2343 p += GEN_MR (p, 6, 3);
2344 }
2345 else
2346 {
2347 p += GEN_MR (p, 5, 3);
2348 p += GEN_MR (p, 6, 4);
2349 }
2350 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2351 p += gen_call (p, fn, 0, 0);
2352
2353 /* Restore TOP */
2354 p += GEN_LWZ (p, 3, 30, 0);
2355 p += GEN_LWZ (p, 4, 30, 4);
2356
2357 emit_insns (buf, p - buf);
2358 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2359}
2360
2361/* Note in the following goto ops:
2362
2363 When emitting goto, the target address is later relocated by
2364 write_goto_address. OFFSET_P is the offset of the branch instruction
2365 in the code sequence, and SIZE_P is how to relocate the instruction,
2366 recognized by ppc_write_goto_address. In current implementation,
2367 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2368 */
2369
2370/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2371
2372static void
2373ppc_emit_if_goto (int *offset_p, int *size_p)
2374{
2375 EMIT_ASM ("or. 3, 3, 4 \n"
2376 "lwzu " TOP_FIRST ", 8(30) \n"
2377 "lwz " TOP_SECOND ", 4(30) \n"
2378 "1:bne 0, 1b \n");
2379
2380 if (offset_p)
2381 *offset_p = 12;
2382 if (size_p)
2383 *size_p = 14;
2384}
2385
2386/* Unconditional goto. Also used for ppc64. */
2387
2388static void
2389ppc_emit_goto (int *offset_p, int *size_p)
2390{
2391 EMIT_ASM ("1:b 1b");
2392
2393 if (offset_p)
2394 *offset_p = 0;
2395 if (size_p)
2396 *size_p = 24;
2397}
2398
2399/* Goto if stack[--sp] == TOP */
2400
2401static void
2402ppc_emit_eq_goto (int *offset_p, int *size_p)
2403{
2404 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2405 "lwz " TMP_SECOND ", 4(30) \n"
2406 "xor 4, 6, 4 \n"
2407 "xor 3, 5, 3 \n"
2408 "or. 3, 3, 4 \n"
2409 "lwzu " TOP_FIRST ", 8(30) \n"
2410 "lwz " TOP_SECOND ", 4(30) \n"
2411 "1:beq 0, 1b \n");
2412
2413 if (offset_p)
2414 *offset_p = 28;
2415 if (size_p)
2416 *size_p = 14;
2417}
2418
2419/* Goto if stack[--sp] != TOP */
2420
2421static void
2422ppc_emit_ne_goto (int *offset_p, int *size_p)
2423{
2424 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2425 "lwz " TMP_SECOND ", 4(30) \n"
2426 "xor 4, 6, 4 \n"
2427 "xor 3, 5, 3 \n"
2428 "or. 3, 3, 4 \n"
2429 "lwzu " TOP_FIRST ", 8(30) \n"
2430 "lwz " TOP_SECOND ", 4(30) \n"
2431 "1:bne 0, 1b \n");
2432
2433 if (offset_p)
2434 *offset_p = 28;
2435 if (size_p)
2436 *size_p = 14;
2437}
2438
2439/* Goto if stack[--sp] < TOP */
2440
2441static void
2442ppc_emit_lt_goto (int *offset_p, int *size_p)
2443{
2444 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2445 "lwz " TMP_SECOND ", 4(30) \n"
2446 "cmplw 6, 6, 4 \n"
2447 "cmpw 7, 5, 3 \n"
2448 /* CR6 bit 0 = low less and high equal */
2449 "crand 6*4+0, 6*4+0, 7*4+2\n"
2450 /* CR7 bit 0 = (low less and high equal) or high less */
2451 "cror 7*4+0, 7*4+0, 6*4+0\n"
2452 "lwzu " TOP_FIRST ", 8(30) \n"
2453 "lwz " TOP_SECOND ", 4(30)\n"
2454 "1:blt 7, 1b \n");
2455
2456 if (offset_p)
2457 *offset_p = 32;
2458 if (size_p)
2459 *size_p = 14;
2460}
2461
2462/* Goto if stack[--sp] <= TOP */
2463
2464static void
2465ppc_emit_le_goto (int *offset_p, int *size_p)
2466{
2467 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2468 "lwz " TMP_SECOND ", 4(30) \n"
2469 "cmplw 6, 6, 4 \n"
2470 "cmpw 7, 5, 3 \n"
2471 /* CR6 bit 0 = low less/equal and high equal */
2472 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2473 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2474 "cror 7*4+0, 7*4+0, 6*4+0\n"
2475 "lwzu " TOP_FIRST ", 8(30) \n"
2476 "lwz " TOP_SECOND ", 4(30)\n"
2477 "1:blt 7, 1b \n");
2478
2479 if (offset_p)
2480 *offset_p = 32;
2481 if (size_p)
2482 *size_p = 14;
2483}
2484
2485/* Goto if stack[--sp] > TOP */
2486
2487static void
2488ppc_emit_gt_goto (int *offset_p, int *size_p)
2489{
2490 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2491 "lwz " TMP_SECOND ", 4(30) \n"
2492 "cmplw 6, 6, 4 \n"
2493 "cmpw 7, 5, 3 \n"
2494 /* CR6 bit 0 = low greater and high equal */
2495 "crand 6*4+0, 6*4+1, 7*4+2\n"
2496 /* CR7 bit 0 = (low greater and high equal) or high greater */
2497 "cror 7*4+0, 7*4+1, 6*4+0\n"
2498 "lwzu " TOP_FIRST ", 8(30) \n"
2499 "lwz " TOP_SECOND ", 4(30)\n"
2500 "1:blt 7, 1b \n");
2501
2502 if (offset_p)
2503 *offset_p = 32;
2504 if (size_p)
2505 *size_p = 14;
2506}
2507
2508/* Goto if stack[--sp] >= TOP */
2509
2510static void
2511ppc_emit_ge_goto (int *offset_p, int *size_p)
2512{
2513 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2514 "lwz " TMP_SECOND ", 4(30) \n"
2515 "cmplw 6, 6, 4 \n"
2516 "cmpw 7, 5, 3 \n"
2517 /* CR6 bit 0 = low ge and high equal */
2518 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2519 /* CR7 bit 0 = (low ge and high equal) or high greater */
2520 "cror 7*4+0, 7*4+1, 6*4+0\n"
2521 "lwzu " TOP_FIRST ", 8(30)\n"
2522 "lwz " TOP_SECOND ", 4(30)\n"
2523 "1:blt 7, 1b \n");
2524
2525 if (offset_p)
2526 *offset_p = 32;
2527 if (size_p)
2528 *size_p = 14;
2529}
2530
2531/* Relocate previous emitted branch instruction. FROM is the address
2532 of the branch instruction, TO is the goto target address, and SIZE
2533 if the value we set by *SIZE_P before. Currently, it is either
2534 24 or 14 of branch and conditional-branch instruction.
2535 Also used for ppc64. */
2536
2537static void
2538ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2539{
2540 long rel = to - from;
2541 uint32_t insn;
2542 int opcd;
2543
2544 read_inferior_memory (from, (unsigned char *) &insn, 4);
2545 opcd = (insn >> 26) & 0x3f;
2546
2547 switch (size)
2548 {
2549 case 14:
2550 if (opcd != 16
2551 || (rel >= (1 << 15) || rel < -(1 << 15)))
2552 emit_error = 1;
2553 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2554 break;
2555 case 24:
2556 if (opcd != 18
2557 || (rel >= (1 << 25) || rel < -(1 << 25)))
2558 emit_error = 1;
2559 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2560 break;
2561 default:
2562 emit_error = 1;
2563 }
2564
2565 if (!emit_error)
4196ab2a 2566 target_write_memory (from, (unsigned char *) &insn, 4);
14e2b6d9
MK		 2567}
2568
2569/* Table of emit ops for 32-bit. */
2570
2571static struct emit_ops ppc_emit_ops_impl =
2572{
2573 ppc_emit_prologue,
2574 ppc_emit_epilogue,
2575 ppc_emit_add,
2576 ppc_emit_sub,
2577 ppc_emit_mul,
2578 ppc_emit_lsh,
2579 ppc_emit_rsh_signed,
2580 ppc_emit_rsh_unsigned,
2581 ppc_emit_ext,
2582 ppc_emit_log_not,
2583 ppc_emit_bit_and,
2584 ppc_emit_bit_or,
2585 ppc_emit_bit_xor,
2586 ppc_emit_bit_not,
2587 ppc_emit_equal,
2588 ppc_emit_less_signed,
2589 ppc_emit_less_unsigned,
2590 ppc_emit_ref,
2591 ppc_emit_if_goto,
2592 ppc_emit_goto,
2593 ppc_write_goto_address,
2594 ppc_emit_const,
2595 ppc_emit_call,
2596 ppc_emit_reg,
2597 ppc_emit_pop,
2598 ppc_emit_stack_flush,
2599 ppc_emit_zero_ext,
2600 ppc_emit_swap,
2601 ppc_emit_stack_adjust,
2602 ppc_emit_int_call_1,
2603 ppc_emit_void_call_2,
2604 ppc_emit_eq_goto,
2605 ppc_emit_ne_goto,
2606 ppc_emit_lt_goto,
2607 ppc_emit_le_goto,
2608 ppc_emit_gt_goto,
2609 ppc_emit_ge_goto
2610};
2611
2612#ifdef __powerpc64__
2613
2614/*
2615
2616 Bytecode execution stack frame - 64-bit
2617
2618 | LR save area (SP + 16)
2619 | CR save area (SP + 8)
2620 SP' -> +- Back chain (SP + 0)
2621 | Save r31 for access saved arguments
2622 | Save r30 for bytecode stack pointer
2623 | Save r4 for incoming argument *value
2624 | Save r3 for incoming argument regs
2625 r30 -> +- Bytecode execution stack
2626 |
2627 | 64-byte (8 doublewords) at initial.
2628 | Expand stack as needed.
2629 |
2630 +-
2631 | Some padding for minimum stack frame.
2632 | 112 for ELFv1.
2633 SP +- Back-chain (SP')
2634
2635 initial frame size
2636 = 112 + (4 * 8) + 64
2637 = 208
2638
2639 r30 is the stack-pointer for bytecode machine.
2640 It should point to next-empty, so we can use LDU for pop.
2641 r3 is used for cache of TOP value.
2642 It was the first argument, pointer to regs.
2643 r4 is the second argument, pointer to the result.
2644 We should set *result = TOP after leaving this function.
2645
2646 Note:
2647 * To restore stack at epilogue
2648 => sp = r31
2649 * To check stack is big enough for bytecode execution.
2650 => r30 - 8 > SP + 112
2651 * To return execution result.
2652 => 0(r4) = TOP
2653
2654 */
2655
2656/* Emit prologue in inferior memory. See above comments. */
2657
2658static void
2659ppc64v1_emit_prologue (void)
2660{
2661 /* On ELFv1, function pointers really point to function descriptor,
2662 so emit one here. We don't care about contents of words 1 and 2,
2663 so let them just overlap out code. */
2664 uint64_t opd = current_insn_ptr + 8;
2665 uint32_t buf[2];
2666
2667 /* Mind the strict aliasing rules. */
2668 memcpy (buf, &opd, sizeof buf);
2669 emit_insns(buf, 2);
2670 EMIT_ASM (/* Save return address. */
2671 "mflr 0 \n"
2672 "std 0, 16(1) \n"
2673 /* Save r30 and incoming arguments. */
2674 "std 31, -8(1) \n"
2675 "std 30, -16(1) \n"
2676 "std 4, -24(1) \n"
2677 "std 3, -32(1) \n"
2678 /* Point r31 to current r1 for access arguments. */
2679 "mr 31, 1 \n"
2680 /* Adjust SP. 208 is the initial frame size. */
2681 "stdu 1, -208(1) \n"
2682 /* Set r30 to pointing stack-top. */
2683 "addi 30, 1, 168 \n"
2684 /* Initial r3/TOP to 0. */
2685 "li 3, 0 \n");
2686}
2687
2688/* Emit prologue in inferior memory. See above comments. */
2689
2690static void
2691ppc64v2_emit_prologue (void)
2692{
2693 EMIT_ASM (/* Save return address. */
2694 "mflr 0 \n"
2695 "std 0, 16(1) \n"
2696 /* Save r30 and incoming arguments. */
2697 "std 31, -8(1) \n"
2698 "std 30, -16(1) \n"
2699 "std 4, -24(1) \n"
2700 "std 3, -32(1) \n"
2701 /* Point r31 to current r1 for access arguments. */
2702 "mr 31, 1 \n"
2703 /* Adjust SP. 208 is the initial frame size. */
2704 "stdu 1, -208(1) \n"
2705 /* Set r30 to pointing stack-top. */
2706 "addi 30, 1, 168 \n"
2707 /* Initial r3/TOP to 0. */
2708 "li 3, 0 \n");
2709}
2710
2711/* Emit epilogue in inferior memory. See above comments. */
2712
2713static void
2714ppc64_emit_epilogue (void)
2715{
2716 EMIT_ASM (/* Restore SP. */
2717 "ld 1, 0(1) \n"
2718 /* *result = TOP */
2719 "ld 4, -24(1) \n"
2720 "std 3, 0(4) \n"
2721 /* Restore registers. */
2722 "ld 31, -8(1) \n"
2723 "ld 30, -16(1) \n"
2724 /* Restore LR. */
2725 "ld 0, 16(1) \n"
2726 /* Return 0 for no-error. */
2727 "li 3, 0 \n"
2728 "mtlr 0 \n"
2729 "blr \n");
2730}
2731
2732/* TOP = stack[--sp] + TOP */
2733
2734static void
2735ppc64_emit_add (void)
2736{
2737 EMIT_ASM ("ldu 4, 8(30) \n"
2738 "add 3, 4, 3 \n");
2739}
2740
2741/* TOP = stack[--sp] - TOP */
2742
2743static void
2744ppc64_emit_sub (void)
2745{
2746 EMIT_ASM ("ldu 4, 8(30) \n"
2747 "sub 3, 4, 3 \n");
2748}
2749
2750/* TOP = stack[--sp] * TOP */
2751
2752static void
2753ppc64_emit_mul (void)
2754{
2755 EMIT_ASM ("ldu 4, 8(30) \n"
2756 "mulld 3, 4, 3 \n");
2757}
2758
2759/* TOP = stack[--sp] << TOP */
2760
2761static void
2762ppc64_emit_lsh (void)
2763{
2764 EMIT_ASM ("ldu 4, 8(30) \n"
2765 "sld 3, 4, 3 \n");
2766}
2767
2768/* Top = stack[--sp] >> TOP
2769 (Arithmetic shift right) */
2770
2771static void
2772ppc64_emit_rsh_signed (void)
2773{
2774 EMIT_ASM ("ldu 4, 8(30) \n"
2775 "srad 3, 4, 3 \n");
2776}
2777
2778/* Top = stack[--sp] >> TOP
2779 (Logical shift right) */
2780
2781static void
2782ppc64_emit_rsh_unsigned (void)
2783{
2784 EMIT_ASM ("ldu 4, 8(30) \n"
2785 "srd 3, 4, 3 \n");
2786}
2787
2788/* Emit code for signed-extension specified by ARG. */
2789
2790static void
2791ppc64_emit_ext (int arg)
2792{
2793 switch (arg)
2794 {
2795 case 8:
2796 EMIT_ASM ("extsb 3, 3");
2797 break;
2798 case 16:
2799 EMIT_ASM ("extsh 3, 3");
2800 break;
2801 case 32:
2802 EMIT_ASM ("extsw 3, 3");
2803 break;
2804 default:
2805 emit_error = 1;
2806 }
2807}
2808
2809/* Emit code for zero-extension specified by ARG. */
2810
2811static void
2812ppc64_emit_zero_ext (int arg)
2813{
2814 switch (arg)
2815 {
2816 case 8:
2817 EMIT_ASM ("rldicl 3,3,0,56");
2818 break;
2819 case 16:
2820 EMIT_ASM ("rldicl 3,3,0,48");
2821 break;
2822 case 32:
2823 EMIT_ASM ("rldicl 3,3,0,32");
2824 break;
2825 default:
2826 emit_error = 1;
2827 }
2828}
2829
2830/* TOP = !TOP
2831 i.e., TOP = (TOP == 0) ? 1 : 0; */
2832
2833static void
2834ppc64_emit_log_not (void)
2835{
2836 EMIT_ASM ("cntlzd 3, 3 \n"
2837 "srdi 3, 3, 6 \n");
2838}
2839
2840/* TOP = stack[--sp] & TOP */
2841
2842static void
2843ppc64_emit_bit_and (void)
2844{
2845 EMIT_ASM ("ldu 4, 8(30) \n"
2846 "and 3, 4, 3 \n");
2847}
2848
2849/* TOP = stack[--sp] | TOP */
2850
2851static void
2852ppc64_emit_bit_or (void)
2853{
2854 EMIT_ASM ("ldu 4, 8(30) \n"
2855 "or 3, 4, 3 \n");
2856}
2857
2858/* TOP = stack[--sp] ^ TOP */
2859
2860static void
2861ppc64_emit_bit_xor (void)
2862{
2863 EMIT_ASM ("ldu 4, 8(30) \n"
2864 "xor 3, 4, 3 \n");
2865}
2866
2867/* TOP = ~TOP
2868 i.e., TOP = ~(TOP | TOP) */
2869
2870static void
2871ppc64_emit_bit_not (void)
2872{
2873 EMIT_ASM ("nor 3, 3, 3 \n");
2874}
2875
2876/* TOP = stack[--sp] == TOP */
2877
2878static void
2879ppc64_emit_equal (void)
2880{
2881 EMIT_ASM ("ldu 4, 8(30) \n"
2882 "xor 3, 3, 4 \n"
2883 "cntlzd 3, 3 \n"
2884 "srdi 3, 3, 6 \n");
2885}
2886
2887/* TOP = stack[--sp] < TOP
2888 (Signed comparison) */
2889
2890static void
2891ppc64_emit_less_signed (void)
2892{
2893 EMIT_ASM ("ldu 4, 8(30) \n"
2894 "cmpd 7, 4, 3 \n"
2895 "mfcr 3 \n"
2896 "rlwinm 3, 3, 29, 31, 31 \n");
2897}
2898
2899/* TOP = stack[--sp] < TOP
2900 (Unsigned comparison) */
2901
2902static void
2903ppc64_emit_less_unsigned (void)
2904{
2905 EMIT_ASM ("ldu 4, 8(30) \n"
2906 "cmpld 7, 4, 3 \n"
2907 "mfcr 3 \n"
2908 "rlwinm 3, 3, 29, 31, 31 \n");
2909}
2910
2911/* Access the memory address in TOP in size of SIZE.
2912 Zero-extend the read value. */
2913
2914static void
2915ppc64_emit_ref (int size)
2916{
2917 switch (size)
2918 {
2919 case 1:
2920 EMIT_ASM ("lbz 3, 0(3)");
2921 break;
2922 case 2:
2923 EMIT_ASM ("lhz 3, 0(3)");
2924 break;
2925 case 4:
2926 EMIT_ASM ("lwz 3, 0(3)");
2927 break;
2928 case 8:
2929 EMIT_ASM ("ld 3, 0(3)");
2930 break;
2931 }
2932}
2933
2934/* TOP = NUM */
2935
2936static void
2937ppc64_emit_const (LONGEST num)
2938{
2939 uint32_t buf[5];
2940 uint32_t *p = buf;
2941
2942 p += gen_limm (p, 3, num, 1);
2943
2944 emit_insns (buf, p - buf);
2945 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2946}
2947
2948/* Set TOP to the value of register REG by calling get_raw_reg function
2949 with two argument, collected buffer and register number. */
2950
2951static void
2952ppc64v1_emit_reg (int reg)
2953{
2954 uint32_t buf[15];
2955 uint32_t *p = buf;
2956
2957 /* fctx->regs is passed in r3 and then saved in 176(1). */
2958 p += GEN_LD (p, 3, 31, -32);
2959 p += GEN_LI (p, 4, reg);
2960 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2961 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2962 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2963
2964 emit_insns (buf, p - buf);
2965 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2966}
2967
2968/* Likewise, for ELFv2. */
2969
2970static void
2971ppc64v2_emit_reg (int reg)
2972{
2973 uint32_t buf[12];
2974 uint32_t *p = buf;
2975
2976 /* fctx->regs is passed in r3 and then saved in 176(1). */
2977 p += GEN_LD (p, 3, 31, -32);
2978 p += GEN_LI (p, 4, reg);
2979 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2980 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2981 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2982
2983 emit_insns (buf, p - buf);
2984 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2985}
2986
2987/* TOP = stack[--sp] */
2988
2989static void
2990ppc64_emit_pop (void)
2991{
2992 EMIT_ASM ("ldu 3, 8(30)");
2993}
2994
2995/* stack[sp++] = TOP
2996
2997 Because we may use up bytecode stack, expand 8 doublewords more
2998 if needed. */
2999
3000static void
3001ppc64_emit_stack_flush (void)
3002{
3003 /* Make sure bytecode stack is big enough before push.
3004 Otherwise, expand 64-byte more. */
3005
3006 EMIT_ASM (" std 3, 0(30) \n"
3007 " addi 4, 30, -(112 + 8) \n"
3008 " cmpd 7, 4, 1 \n"
3009 " bgt 7, 1f \n"
3010 " stdu 31, -64(1) \n"
3011 "1:addi 30, 30, -8 \n");
3012}
3013
3014/* Swap TOP and stack[sp-1] */
3015
3016static void
3017ppc64_emit_swap (void)
3018{
3019 EMIT_ASM ("ld 4, 8(30) \n"
3020 "std 3, 8(30) \n"
3021 "mr 3, 4 \n");
3022}
3023
3024/* Call function FN - ELFv1. */
3025
3026static void
3027ppc64v1_emit_call (CORE_ADDR fn)
3028{
3029 uint32_t buf[13];
3030 uint32_t *p = buf;
3031
3032 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3033 p += gen_call (p, fn, 1, 1);
3034 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3035
3036 emit_insns (buf, p - buf);
3037 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3038}
3039
3040/* Call function FN - ELFv2. */
3041
3042static void
3043ppc64v2_emit_call (CORE_ADDR fn)
3044{
3045 uint32_t buf[10];
3046 uint32_t *p = buf;
3047
3048 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3049 p += gen_call (p, fn, 1, 0);
3050 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3051
3052 emit_insns (buf, p - buf);
3053 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3054}
3055
3056/* FN's prototype is `LONGEST(*fn)(int)'.
3057 TOP = fn (arg1)
3058 */
3059
3060static void
3061ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
3062{
3063 uint32_t buf[13];
3064 uint32_t *p = buf;
3065
3066 /* Setup argument. arg1 is a 16-bit value. */
3067 p += gen_limm (p, 3, arg1, 1);
3068 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3069 p += gen_call (p, fn, 1, 1);
3070 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3071
3072 emit_insns (buf, p - buf);
3073 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3074}
3075
3076/* Likewise for ELFv2. */
3077
3078static void
3079ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
3080{
3081 uint32_t buf[10];
3082 uint32_t *p = buf;
3083
3084 /* Setup argument. arg1 is a 16-bit value. */
3085 p += gen_limm (p, 3, arg1, 1);
3086 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3087 p += gen_call (p, fn, 1, 0);
3088 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3089
3090 emit_insns (buf, p - buf);
3091 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3092}
3093
3094/* FN's prototype is `void(*fn)(int,LONGEST)'.
3095 fn (arg1, TOP)
3096
3097 TOP should be preserved/restored before/after the call. */
3098
3099static void
3100ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
3101{
3102 uint32_t buf[17];
3103 uint32_t *p = buf;
3104
3105 /* Save TOP. 0(30) is next-empty. */
3106 p += GEN_STD (p, 3, 30, 0);
3107
3108 /* Setup argument. arg1 is a 16-bit value. */
3109 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3110 p += gen_limm (p, 3, arg1, 1);
3111 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3112 p += gen_call (p, fn, 1, 1);
3113 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3114
3115 /* Restore TOP */
3116 p += GEN_LD (p, 3, 30, 0);
3117
3118 emit_insns (buf, p - buf);
3119 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3120}
3121
3122/* Likewise for ELFv2. */
3123
3124static void
3125ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
3126{
3127 uint32_t buf[14];
3128 uint32_t *p = buf;
3129
3130 /* Save TOP. 0(30) is next-empty. */
3131 p += GEN_STD (p, 3, 30, 0);
3132
3133 /* Setup argument. arg1 is a 16-bit value. */
3134 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3135 p += gen_limm (p, 3, arg1, 1);
3136 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3137 p += gen_call (p, fn, 1, 0);
3138 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3139
3140 /* Restore TOP */
3141 p += GEN_LD (p, 3, 30, 0);
3142
3143 emit_insns (buf, p - buf);
3144 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3145}
3146
3147/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3148
3149static void
3150ppc64_emit_if_goto (int *offset_p, int *size_p)
3151{
3152 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3153 "ldu 3, 8(30) \n"
3154 "1:bne 7, 1b \n");
3155
3156 if (offset_p)
3157 *offset_p = 8;
3158 if (size_p)
3159 *size_p = 14;
3160}
3161
3162/* Goto if stack[--sp] == TOP */
3163
3164static void
3165ppc64_emit_eq_goto (int *offset_p, int *size_p)
3166{
3167 EMIT_ASM ("ldu 4, 8(30) \n"
3168 "cmpd 7, 4, 3 \n"
3169 "ldu 3, 8(30) \n"
3170 "1:beq 7, 1b \n");
3171
3172 if (offset_p)
3173 *offset_p = 12;
3174 if (size_p)
3175 *size_p = 14;
3176}
3177
3178/* Goto if stack[--sp] != TOP */
3179
3180static void
3181ppc64_emit_ne_goto (int *offset_p, int *size_p)
3182{
3183 EMIT_ASM ("ldu 4, 8(30) \n"
3184 "cmpd 7, 4, 3 \n"
3185 "ldu 3, 8(30) \n"
3186 "1:bne 7, 1b \n");
3187
3188 if (offset_p)
3189 *offset_p = 12;
3190 if (size_p)
3191 *size_p = 14;
3192}
3193
3194/* Goto if stack[--sp] < TOP */
3195
3196static void
3197ppc64_emit_lt_goto (int *offset_p, int *size_p)
3198{
3199 EMIT_ASM ("ldu 4, 8(30) \n"
3200 "cmpd 7, 4, 3 \n"
3201 "ldu 3, 8(30) \n"
3202 "1:blt 7, 1b \n");
3203
3204 if (offset_p)
3205 *offset_p = 12;
3206 if (size_p)
3207 *size_p = 14;
3208}
3209
3210/* Goto if stack[--sp] <= TOP */
3211
3212static void
3213ppc64_emit_le_goto (int *offset_p, int *size_p)
3214{
3215 EMIT_ASM ("ldu 4, 8(30) \n"
3216 "cmpd 7, 4, 3 \n"
3217 "ldu 3, 8(30) \n"
3218 "1:ble 7, 1b \n");
3219
3220 if (offset_p)
3221 *offset_p = 12;
3222 if (size_p)
3223 *size_p = 14;
3224}
3225
3226/* Goto if stack[--sp] > TOP */
3227
3228static void
3229ppc64_emit_gt_goto (int *offset_p, int *size_p)
3230{
3231 EMIT_ASM ("ldu 4, 8(30) \n"
3232 "cmpd 7, 4, 3 \n"
3233 "ldu 3, 8(30) \n"
3234 "1:bgt 7, 1b \n");
3235
3236 if (offset_p)
3237 *offset_p = 12;
3238 if (size_p)
3239 *size_p = 14;
3240}
3241
3242/* Goto if stack[--sp] >= TOP */
3243
3244static void
3245ppc64_emit_ge_goto (int *offset_p, int *size_p)
3246{
3247 EMIT_ASM ("ldu 4, 8(30) \n"
3248 "cmpd 7, 4, 3 \n"
3249 "ldu 3, 8(30) \n"
3250 "1:bge 7, 1b \n");
3251
3252 if (offset_p)
3253 *offset_p = 12;
3254 if (size_p)
3255 *size_p = 14;
3256}
3257
3258/* Table of emit ops for 64-bit ELFv1. */
3259
3260static struct emit_ops ppc64v1_emit_ops_impl =
3261{
3262 ppc64v1_emit_prologue,
3263 ppc64_emit_epilogue,
3264 ppc64_emit_add,
3265 ppc64_emit_sub,
3266 ppc64_emit_mul,
3267 ppc64_emit_lsh,
3268 ppc64_emit_rsh_signed,
3269 ppc64_emit_rsh_unsigned,
3270 ppc64_emit_ext,
3271 ppc64_emit_log_not,
3272 ppc64_emit_bit_and,
3273 ppc64_emit_bit_or,
3274 ppc64_emit_bit_xor,
3275 ppc64_emit_bit_not,
3276 ppc64_emit_equal,
3277 ppc64_emit_less_signed,
3278 ppc64_emit_less_unsigned,
3279 ppc64_emit_ref,
3280 ppc64_emit_if_goto,
3281 ppc_emit_goto,
3282 ppc_write_goto_address,
3283 ppc64_emit_const,
3284 ppc64v1_emit_call,
3285 ppc64v1_emit_reg,
3286 ppc64_emit_pop,
3287 ppc64_emit_stack_flush,
3288 ppc64_emit_zero_ext,
3289 ppc64_emit_swap,
3290 ppc_emit_stack_adjust,
3291 ppc64v1_emit_int_call_1,
3292 ppc64v1_emit_void_call_2,
3293 ppc64_emit_eq_goto,
3294 ppc64_emit_ne_goto,
3295 ppc64_emit_lt_goto,
3296 ppc64_emit_le_goto,
3297 ppc64_emit_gt_goto,
3298 ppc64_emit_ge_goto
3299};
3300
3301/* Table of emit ops for 64-bit ELFv2. */
3302
3303static struct emit_ops ppc64v2_emit_ops_impl =
3304{
3305 ppc64v2_emit_prologue,
3306 ppc64_emit_epilogue,
3307 ppc64_emit_add,
3308 ppc64_emit_sub,
3309 ppc64_emit_mul,
3310 ppc64_emit_lsh,
3311 ppc64_emit_rsh_signed,
3312 ppc64_emit_rsh_unsigned,
3313 ppc64_emit_ext,
3314 ppc64_emit_log_not,
3315 ppc64_emit_bit_and,
3316 ppc64_emit_bit_or,
3317 ppc64_emit_bit_xor,
3318 ppc64_emit_bit_not,
3319 ppc64_emit_equal,
3320 ppc64_emit_less_signed,
3321 ppc64_emit_less_unsigned,
3322 ppc64_emit_ref,
3323 ppc64_emit_if_goto,
3324 ppc_emit_goto,
3325 ppc_write_goto_address,
3326 ppc64_emit_const,
3327 ppc64v2_emit_call,
3328 ppc64v2_emit_reg,
3329 ppc64_emit_pop,
3330 ppc64_emit_stack_flush,
3331 ppc64_emit_zero_ext,
3332 ppc64_emit_swap,
3333 ppc_emit_stack_adjust,
3334 ppc64v2_emit_int_call_1,
3335 ppc64v2_emit_void_call_2,
3336 ppc64_emit_eq_goto,
3337 ppc64_emit_ne_goto,
3338 ppc64_emit_lt_goto,
3339 ppc64_emit_le_goto,
3340 ppc64_emit_gt_goto,
3341 ppc64_emit_ge_goto
3342};
3343
3344#endif
3345
3346/* Implementation of linux_target_ops method "emit_ops". */
3347
3348static struct emit_ops *
3349ppc_emit_ops (void)
3350{
3351#ifdef __powerpc64__
3352 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3353
3354 if (register_size (regcache->tdesc, 0) == 8)
3355 {
3356 if (is_elfv2_inferior ())
3357 return &ppc64v2_emit_ops_impl;
3358 else
3359 return &ppc64v1_emit_ops_impl;
3360 }
3361#endif
3362 return &ppc_emit_ops_impl;
3363}
3364
a2174ba4
MK		 3365/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3366
3367static int
3368ppc_get_ipa_tdesc_idx (void)
3369{
3370 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3371 const struct target_desc *tdesc = regcache->tdesc;
3372
3373#ifdef __powerpc64__
3374 if (tdesc == tdesc_powerpc_64l)
3375 return PPC_TDESC_BASE;
3376 if (tdesc == tdesc_powerpc_altivec64l)
3377 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3378 if (tdesc == tdesc_powerpc_vsx64l)
3379 return PPC_TDESC_VSX;
3380 if (tdesc == tdesc_powerpc_isa205_64l)
3381 return PPC_TDESC_ISA205;
3382 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3383 return PPC_TDESC_ISA205_ALTIVEC;
3384 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3385 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3386 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3387 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3388 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3389 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3390 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
3391 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3392#endif
3393
3394 if (tdesc == tdesc_powerpc_32l)
3395 return PPC_TDESC_BASE;
3396 if (tdesc == tdesc_powerpc_altivec32l)
3397 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3398 if (tdesc == tdesc_powerpc_vsx32l)
3399 return PPC_TDESC_VSX;
3400 if (tdesc == tdesc_powerpc_isa205_32l)
3401 return PPC_TDESC_ISA205;
3402 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3403 return PPC_TDESC_ISA205_ALTIVEC;
3404 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3405 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3406 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3407 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3408 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3409 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3410 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
3411 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3412 if (tdesc == tdesc_powerpc_e500l)
3413 return PPC_TDESC_E500;
3414
3415 return 0;
3416}
3417
2ec06d2e 3418struct linux_target_ops the_low_target = {
5b0a002e
UW		 3419 NULL,
3420 NULL,
3421 ppc_collect_ptrace_register,
3422 ppc_supply_ptrace_register,
7d00775e
AT		 3423 NULL, /* siginfo_fixup */
3424 NULL, /* new_process */
04ec7890 3425 NULL, /* delete_process */
7d00775e 3426 NULL, /* new_thread */
466eecee 3427 NULL, /* delete_thread */
7d00775e
AT		 3428 NULL, /* new_fork */
3429 NULL, /* prepare_to_resume */
3430 NULL, /* process_qsupported */
b04fd3be 3431 ppc_supports_tracepoints,
a2174ba4
MK		 3432 ppc_get_thread_area,
3433 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3434 ppc_emit_ops,
a2174ba4 3435 ppc_get_min_fast_tracepoint_insn_len,
7d00775e 3436 NULL, /* supports_range_stepping */
7d00775e 3437 ppc_supports_hardware_single_step,
a2174ba4
MK		 3438 NULL, /* get_syscall_trapinfo */
3439 ppc_get_ipa_tdesc_idx,
2ec06d2e 3440};
3aee8918 3441
ef0478f6
TBA		 3442/* The linux target ops object. */
3443
3444linux_process_target *the_linux_target = &the_ppc_target;
3445
3aee8918
PA		 3446void
3447initialize_low_arch (void)
3448{
3449 /* Initialize the Linux target descriptions. */
3450
3451 init_registers_powerpc_32l ();
3452 init_registers_powerpc_altivec32l ();
3aee8918
PA		 3453 init_registers_powerpc_vsx32l ();
3454 init_registers_powerpc_isa205_32l ();
3455 init_registers_powerpc_isa205_altivec32l ();
3456 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3457 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3458 init_registers_powerpc_isa207_vsx32l ();
8d619c01 3459 init_registers_powerpc_isa207_htm_vsx32l ();
3aee8918 3460 init_registers_powerpc_e500l ();
a2174ba4 3461#if __powerpc64__
3aee8918
PA		 3462 init_registers_powerpc_64l ();
3463 init_registers_powerpc_altivec64l ();
3aee8918
PA		 3464 init_registers_powerpc_vsx64l ();
3465 init_registers_powerpc_isa205_64l ();
3466 init_registers_powerpc_isa205_altivec64l ();
3467 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3468 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3469 init_registers_powerpc_isa207_vsx64l ();
8d619c01 3470 init_registers_powerpc_isa207_htm_vsx64l ();
a2174ba4 3471#endif
3aee8918
PA		 3472
3473 initialize_regsets_info (&ppc_regsets_info);
3474}
GDB Binutils - Deliverables
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