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gdbserver/linux-low: turn 'emit_ops' into a method
[deliverable/binutils-gdb.git] / gdbserver / linux-ppc-low.cc
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
b811d2c2 3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
64f57f3d 31#include "nat/linux-ptrace.h"
bd64614e 32#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 33#include "ax.h"
34#include "tracepoint.h"
35
36#define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38#define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 46
ef0478f6
TBA		 47/* Linux target op definitions for the PowerPC architecture. */
48
49class ppc_target : public linux_process_target
50{
51public:
52
aa8d21c9
TBA		 53 const regs_info *get_regs_info () override;
54
3ca4edb6
TBA		 55 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
56
007c9b97
TBA		 57 bool supports_z_point_type (char z_type) override;
58
b35db733
TBA		 59
60 void low_collect_ptrace_register (regcache *regcache, int regno,
61 char *buf) override;
62
63 void low_supply_ptrace_register (regcache *regcache, int regno,
64 const char *buf) override;
47f70aa7
TBA		 65
66 bool supports_tracepoints () override;
67
809a0c35
TBA		 68 bool supports_fast_tracepoints () override;
69
70 int install_fast_tracepoint_jump_pad
71 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector,
72 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry,
73 CORE_ADDR *trampoline, ULONGEST *trampoline_size,
74 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size,
75 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end,
76 char *err) override;
77
78 int get_min_fast_tracepoint_insn_len () override;
79
ab64c999
TBA		 80 struct emit_ops *emit_ops () override;
81
797bcff5
TBA		 82protected:
83
84 void low_arch_setup () override;
daca57a7
TBA		 85
86 bool low_cannot_fetch_register (int regno) override;
87
88 bool low_cannot_store_register (int regno) override;
bf9ae9d8
TBA		 89
90 bool low_supports_breakpoints () override;
91
92 CORE_ADDR low_get_pc (regcache *regcache) override;
93
94 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
d7146cda
TBA		 95
96 bool low_breakpoint_at (CORE_ADDR pc) override;
9db9aa23
TBA		 97
98 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
99 int size, raw_breakpoint *bp) override;
100
101 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
102 int size, raw_breakpoint *bp) override;
13e567af
TBA		 103
104 int low_get_thread_area (int lwpid, CORE_ADDR *addrp) override;
ef0478f6
TBA		 105};
106
107/* The singleton target ops object. */
108
109static ppc_target the_ppc_target;
110
7ca18ed6
EBM		 111/* Holds the AT_HWCAP auxv entry. */
112
b6430ec3
UW		 113static unsigned long ppc_hwcap;
114
7ca18ed6
EBM		 115/* Holds the AT_HWCAP2 auxv entry. */
116
117static unsigned long ppc_hwcap2;
118
b6430ec3 119
7284e1be
UW		 120#define ppc_num_regs 73
121
5b0a002e
UW		 122#ifdef __powerpc64__
123/* We use a constant for FPSCR instead of PT_FPSCR, because
124 many shipped PPC64 kernels had the wrong value in ptrace.h. */
125static int ppc_regmap[] =
126 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
127 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
128 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
129 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
130 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
131 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
132 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
133 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
134 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
135 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
136 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
137 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
138 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
139 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
140 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
141 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
142 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 143 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
144 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 145#else
0a30fbc4 146/* Currently, don't check/send MQ. */
2ec06d2e 147static int ppc_regmap[] =
0a30fbc4
DJ		 148 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
149 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
150 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
151 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
152 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
153 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
154 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
155 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
156 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
157 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
158 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
159 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
160 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
161 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
162 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
163 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
164 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 165 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
166 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 167 };
168
169static int ppc_regmap_e500[] =
170 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
171 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
172 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
173 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
174 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
175 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
176 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
177 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
178 -1, -1, -1, -1,
179 -1, -1, -1, -1,
180 -1, -1, -1, -1,
181 -1, -1, -1, -1,
182 -1, -1, -1, -1,
183 -1, -1, -1, -1,
184 -1, -1, -1, -1,
185 -1, -1, -1, -1,
186 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 187 PT_CTR * 4, PT_XER * 4, -1,
188 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 189 };
5b0a002e 190#endif
0a30fbc4 191
7ca18ed6
EBM		 192/* Check whether the kernel provides a register set with number
193 REGSET_ID of size REGSETSIZE for process/thread TID. */
194
195static int
196ppc_check_regset (int tid, int regset_id, int regsetsize)
197{
198 void *buf = alloca (regsetsize);
199 struct iovec iov;
200
201 iov.iov_base = buf;
202 iov.iov_len = regsetsize;
203
204 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
205 || errno == ENODATA)
206 return 1;
207 return 0;
208}
209
daca57a7
TBA		 210bool
211ppc_target::low_cannot_store_register (int regno)
0a30fbc4 212{
3aee8918
PA		 213 const struct target_desc *tdesc = current_process ()->tdesc;
214
b6430ec3 215#ifndef __powerpc64__
bc1e36ca 216 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 217 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
218 && regno == find_regno (tdesc, "fpscr"))
daca57a7 219 return true;
30ed0a8f 220#endif
bc1e36ca 221
7284e1be 222 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 223 if (regno == find_regno (tdesc, "orig_r3")
224 || regno == find_regno (tdesc, "trap"))
daca57a7 225 return true;
7284e1be 226
daca57a7 227 return false;
0a30fbc4
DJ		 228}
229
daca57a7
TBA		 230bool
231ppc_target::low_cannot_fetch_register (int regno)
0a30fbc4 232{
daca57a7 233 return false;
0a30fbc4
DJ		 234}
235
b35db733
TBA		 236void
237ppc_target::low_collect_ptrace_register (regcache *regcache, int regno,
238 char *buf)
5b0a002e 239{
76b233dd
UW		 240 memset (buf, 0, sizeof (long));
241
2e4bb98a
EBM		 242 if (__BYTE_ORDER == __LITTLE_ENDIAN)
243 {
244 /* Little-endian values always sit at the left end of the buffer. */
245 collect_register (regcache, regno, buf);
246 }
247 else if (__BYTE_ORDER == __BIG_ENDIAN)
248 {
249 /* Big-endian values sit at the right end of the buffer. In case of
250 registers whose sizes are smaller than sizeof (long), we must use a
251 padding to access them correctly. */
252 int size = register_size (regcache->tdesc, regno);
253
254 if (size < sizeof (long))
255 collect_register (regcache, regno, buf + sizeof (long) - size);
256 else
257 collect_register (regcache, regno, buf);
258 }
5b0a002e 259 else
2e4bb98a 260 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 261}
262
b35db733
TBA		 263void
264ppc_target::low_supply_ptrace_register (regcache *regcache, int regno,
265 const char *buf)
5b0a002e 266{
2e4bb98a
EBM		 267 if (__BYTE_ORDER == __LITTLE_ENDIAN)
268 {
269 /* Little-endian values always sit at the left end of the buffer. */
270 supply_register (regcache, regno, buf);
271 }
272 else if (__BYTE_ORDER == __BIG_ENDIAN)
273 {
274 /* Big-endian values sit at the right end of the buffer. In case of
275 registers whose sizes are smaller than sizeof (long), we must use a
276 padding to access them correctly. */
277 int size = register_size (regcache->tdesc, regno);
278
279 if (size < sizeof (long))
280 supply_register (regcache, regno, buf + sizeof (long) - size);
281 else
282 supply_register (regcache, regno, buf);
283 }
5b0a002e 284 else
2e4bb98a 285 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 286}
287
bf9ae9d8
TBA		 288bool
289ppc_target::low_supports_breakpoints ()
290{
291 return true;
292}
293
294CORE_ADDR
295ppc_target::low_get_pc (regcache *regcache)
0d62e5e8 296{
abf516c6 297 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 298 {
299 unsigned int pc;
442ea881 300 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 301 return (CORE_ADDR) pc;
302 }
303 else
304 {
305 unsigned long pc;
442ea881 306 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 307 return (CORE_ADDR) pc;
308 }
0d62e5e8
DJ		 309}
310
bf9ae9d8
TBA		 311void
312ppc_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
0d62e5e8 313{
abf516c6 314 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 315 {
316 unsigned int newpc = pc;
442ea881 317 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 318 }
319 else
320 {
321 unsigned long newpc = pc;
442ea881 322 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 323 }
324}
325
3aee8918
PA		 326#ifndef __powerpc64__
327static int ppc_regmap_adjusted;
328#endif
329
0d62e5e8 330
5b0a002e 331/* Correct in either endianness.
0d62e5e8
DJ		 332 This instruction is "twge r2, r2", which GDB uses as a software
333 breakpoint. */
5b0a002e 334static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 335#define ppc_breakpoint_len 4
336
3ca4edb6 337/* Implementation of target ops method "sw_breakpoint_from_kind". */
dd373349 338
3ca4edb6
TBA		 339const gdb_byte *
340ppc_target::sw_breakpoint_from_kind (int kind, int *size)
dd373349
AT		 341{
342 *size = ppc_breakpoint_len;
343 return (const gdb_byte *) &ppc_breakpoint;
344}
345
d7146cda
TBA		 346bool
347ppc_target::low_breakpoint_at (CORE_ADDR where)
0d62e5e8 348{
5b0a002e 349 unsigned int insn;
0d62e5e8 350
d7146cda 351 read_memory (where, (unsigned char *) &insn, 4);
abf516c6 352 if (insn == ppc_breakpoint)
d7146cda 353 return true;
abf516c6
UW		 354 /* If necessary, recognize more trap instructions here. GDB only uses
355 the one. */
0b9ff2c0 356
d7146cda 357 return false;
0d62e5e8
DJ		 358}
359
657f9cde
WW		 360/* Implement supports_z_point_type target-ops.
361 Returns true if type Z_TYPE breakpoint is supported.
362
363 Handling software breakpoint at server side, so tracepoints
364 and breakpoints can be inserted at the same location. */
365
007c9b97
TBA		 366bool
367ppc_target::supports_z_point_type (char z_type)
657f9cde
WW		 368{
369 switch (z_type)
370 {
371 case Z_PACKET_SW_BP:
007c9b97 372 return true;
657f9cde
WW		 373 case Z_PACKET_HW_BP:
374 case Z_PACKET_WRITE_WP:
375 case Z_PACKET_ACCESS_WP:
376 default:
007c9b97 377 return false;
657f9cde
WW		 378 }
379}
380
9db9aa23 381/* Implement the low_insert_point linux target op.
657f9cde
WW		 382 Returns 0 on success, -1 on failure and 1 on unsupported. */
383
9db9aa23
TBA		 384int
385ppc_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
386 int size, raw_breakpoint *bp)
657f9cde
WW		 387{
388 switch (type)
389 {
390 case raw_bkpt_type_sw:
391 return insert_memory_breakpoint (bp);
392
393 case raw_bkpt_type_hw:
394 case raw_bkpt_type_write_wp:
395 case raw_bkpt_type_access_wp:
396 default:
397 /* Unsupported. */
398 return 1;
399 }
400}
401
9db9aa23 402/* Implement the low_remove_point linux target op.
657f9cde
WW		 403 Returns 0 on success, -1 on failure and 1 on unsupported. */
404
9db9aa23
TBA		 405int
406ppc_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
407 int size, raw_breakpoint *bp)
657f9cde
WW		 408{
409 switch (type)
410 {
411 case raw_bkpt_type_sw:
412 return remove_memory_breakpoint (bp);
413
414 case raw_bkpt_type_hw:
415 case raw_bkpt_type_write_wp:
416 case raw_bkpt_type_access_wp:
417 default:
418 /* Unsupported. */
419 return 1;
420 }
421}
422
e9d25b98
DJ		 423/* Provide only a fill function for the general register set. ps_lgetregs
424 will use this for NPTL support. */
425
442ea881 426static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 427{
428 int i;
429
b35db733
TBA		 430 ppc_target *my_ppc_target = (ppc_target *) the_linux_target;
431
e9d25b98 432 for (i = 0; i < 32; i++)
b35db733
TBA		 433 my_ppc_target->low_collect_ptrace_register (regcache, i,
434 (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 435
436 for (i = 64; i < 70; i++)
b35db733
TBA		 437 my_ppc_target->low_collect_ptrace_register (regcache, i,
438 (char *) buf + ppc_regmap[i]);
7284e1be
UW		 439
440 for (i = 71; i < 73; i++)
b35db733
TBA		 441 my_ppc_target->low_collect_ptrace_register (regcache, i,
442 (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 443}
444
7ca18ed6
EBM		 445/* Program Priority Register regset fill function. */
446
447static void
448ppc_fill_pprregset (struct regcache *regcache, void *buf)
449{
450 char *ppr = (char *) buf;
451
452 collect_register_by_name (regcache, "ppr", ppr);
453}
454
455/* Program Priority Register regset store function. */
456
457static void
458ppc_store_pprregset (struct regcache *regcache, const void *buf)
459{
460 const char *ppr = (const char *) buf;
461
462 supply_register_by_name (regcache, "ppr", ppr);
463}
464
465/* Data Stream Control Register regset fill function. */
466
467static void
468ppc_fill_dscrregset (struct regcache *regcache, void *buf)
469{
470 char *dscr = (char *) buf;
471
472 collect_register_by_name (regcache, "dscr", dscr);
473}
474
475/* Data Stream Control Register regset store function. */
476
477static void
478ppc_store_dscrregset (struct regcache *regcache, const void *buf)
479{
480 const char *dscr = (const char *) buf;
481
482 supply_register_by_name (regcache, "dscr", dscr);
483}
484
f2cf6173
EBM		 485/* Target Address Register regset fill function. */
486
487static void
488ppc_fill_tarregset (struct regcache *regcache, void *buf)
489{
490 char *tar = (char *) buf;
491
492 collect_register_by_name (regcache, "tar", tar);
493}
494
495/* Target Address Register regset store function. */
496
497static void
498ppc_store_tarregset (struct regcache *regcache, const void *buf)
499{
500 const char *tar = (const char *) buf;
501
502 supply_register_by_name (regcache, "tar", tar);
503}
504
232bfb86
EBM		 505/* Event-Based Branching regset store function. Unless the inferior
506 has a perf event open, ptrace can return in error when reading and
507 writing to the regset, with ENODATA. For reading, the registers
508 will correctly show as unavailable. For writing, gdbserver
509 currently only caches any register writes from P and G packets and
510 the stub always tries to write all the regsets when resuming the
511 inferior, which would result in frequent warnings. For this
512 reason, we don't define a fill function. This also means that the
513 client-side regcache will be dirty if the user tries to write to
514 the EBB registers. G packets that the client sends to write to
515 unrelated registers will also include data for EBB registers, even
516 if they are unavailable. */
517
518static void
519ppc_store_ebbregset (struct regcache *regcache, const void *buf)
520{
521 const char *regset = (const char *) buf;
522
523 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
524 .dat file is BESCR, EBBHR, EBBRR. */
525 supply_register_by_name (regcache, "ebbrr", &regset[0]);
526 supply_register_by_name (regcache, "ebbhr", &regset[8]);
527 supply_register_by_name (regcache, "bescr", &regset[16]);
528}
529
530/* Performance Monitoring Unit regset fill function. */
531
532static void
533ppc_fill_pmuregset (struct regcache *regcache, void *buf)
534{
535 char *regset = (char *) buf;
536
537 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
538 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
539 collect_register_by_name (regcache, "siar", &regset[0]);
540 collect_register_by_name (regcache, "sdar", &regset[8]);
541 collect_register_by_name (regcache, "sier", &regset[16]);
542 collect_register_by_name (regcache, "mmcr2", &regset[24]);
543 collect_register_by_name (regcache, "mmcr0", &regset[32]);
544}
545
546/* Performance Monitoring Unit regset store function. */
547
548static void
549ppc_store_pmuregset (struct regcache *regcache, const void *buf)
550{
551 const char *regset = (const char *) buf;
552
553 supply_register_by_name (regcache, "siar", &regset[0]);
554 supply_register_by_name (regcache, "sdar", &regset[8]);
555 supply_register_by_name (regcache, "sier", &regset[16]);
556 supply_register_by_name (regcache, "mmcr2", &regset[24]);
557 supply_register_by_name (regcache, "mmcr0", &regset[32]);
558}
559
8d619c01
EBM		 560/* Hardware Transactional Memory special-purpose register regset fill
561 function. */
562
563static void
564ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
565{
566 int i, base;
567 char *regset = (char *) buf;
568
569 base = find_regno (regcache->tdesc, "tfhar");
570 for (i = 0; i < 3; i++)
571 collect_register (regcache, base + i, &regset[i * 8]);
572}
573
574/* Hardware Transactional Memory special-purpose register regset store
575 function. */
576
577static void
578ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
579{
580 int i, base;
581 const char *regset = (const char *) buf;
582
583 base = find_regno (regcache->tdesc, "tfhar");
584 for (i = 0; i < 3; i++)
585 supply_register (regcache, base + i, &regset[i * 8]);
586}
587
588/* For the same reasons as the EBB regset, none of the HTM
589 checkpointed regsets have a fill function. These registers are
590 only available if the inferior is in a transaction. */
591
592/* Hardware Transactional Memory checkpointed general-purpose regset
593 store function. */
594
595static void
596ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
597{
598 int i, base, size, endian_offset;
599 const char *regset = (const char *) buf;
600
601 base = find_regno (regcache->tdesc, "cr0");
602 size = register_size (regcache->tdesc, base);
603
604 gdb_assert (size == 4 || size == 8);
605
606 for (i = 0; i < 32; i++)
607 supply_register (regcache, base + i, &regset[i * size]);
608
609 endian_offset = 0;
610
611 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
612 endian_offset = 4;
613
614 supply_register_by_name (regcache, "ccr",
615 &regset[PT_CCR * size + endian_offset]);
616
617 supply_register_by_name (regcache, "cxer",
618 &regset[PT_XER * size + endian_offset]);
619
620 supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
621 supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
622}
623
624/* Hardware Transactional Memory checkpointed floating-point regset
625 store function. */
626
627static void
628ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
629{
630 int i, base;
631 const char *regset = (const char *) buf;
632
633 base = find_regno (regcache->tdesc, "cf0");
634
635 for (i = 0; i < 32; i++)
636 supply_register (regcache, base + i, &regset[i * 8]);
637
638 supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
639}
640
641/* Hardware Transactional Memory checkpointed vector regset store
642 function. */
643
644static void
645ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
646{
647 int i, base;
648 const char *regset = (const char *) buf;
649 int vscr_offset = 0;
650
651 base = find_regno (regcache->tdesc, "cvr0");
652
653 for (i = 0; i < 32; i++)
654 supply_register (regcache, base + i, &regset[i * 16]);
655
656 if (__BYTE_ORDER == __BIG_ENDIAN)
657 vscr_offset = 12;
658
659 supply_register_by_name (regcache, "cvscr",
660 &regset[32 * 16 + vscr_offset]);
661
662 supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
663}
664
665/* Hardware Transactional Memory checkpointed vector-scalar regset
666 store function. */
667
668static void
669ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
670{
671 int i, base;
672 const char *regset = (const char *) buf;
673
674 base = find_regno (regcache->tdesc, "cvs0h");
675 for (i = 0; i < 32; i++)
676 supply_register (regcache, base + i, &regset[i * 8]);
677}
678
679/* Hardware Transactional Memory checkpointed Program Priority
680 Register regset store function. */
681
682static void
683ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
684{
685 const char *cppr = (const char *) buf;
686
687 supply_register_by_name (regcache, "cppr", cppr);
688}
689
690/* Hardware Transactional Memory checkpointed Data Stream Control
691 Register regset store function. */
692
693static void
694ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
695{
696 const char *cdscr = (const char *) buf;
697
698 supply_register_by_name (regcache, "cdscr", cdscr);
699}
700
701/* Hardware Transactional Memory checkpointed Target Address Register
702 regset store function. */
703
704static void
705ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
706{
707 const char *ctar = (const char *) buf;
708
709 supply_register_by_name (regcache, "ctar", ctar);
710}
711
677c5bb1 712static void
442ea881 713ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 714{
715 int i, base;
2bc84e8a 716 char *regset = (char *) buf;
677c5bb1 717
3aee8918 718 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 719 for (i = 0; i < 32; i++)
442ea881 720 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 721}
722
723static void
442ea881 724ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 725{
726 int i, base;
2bc84e8a 727 const char *regset = (const char *) buf;
677c5bb1 728
3aee8918 729 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 730 for (i = 0; i < 32; i++)
442ea881 731 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 732}
733
30ed0a8f 734static void
442ea881 735ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 736{
737 int i, base;
2bc84e8a 738 char *regset = (char *) buf;
1d75a658 739 int vscr_offset = 0;
30ed0a8f 740
3aee8918 741 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 742 for (i = 0; i < 32; i++)
442ea881 743 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 744
1d75a658
PFC		 745 if (__BYTE_ORDER == __BIG_ENDIAN)
746 vscr_offset = 12;
747
1d75a658
PFC		 748 collect_register_by_name (regcache, "vscr",
749 &regset[32 * 16 + vscr_offset]);
750
442ea881 751 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 752}
753
754static void
442ea881 755ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 756{
757 int i, base;
2bc84e8a 758 const char *regset = (const char *) buf;
1d75a658 759 int vscr_offset = 0;
30ed0a8f 760
3aee8918 761 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 762 for (i = 0; i < 32; i++)
442ea881 763 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 764
1d75a658
PFC		 765 if (__BYTE_ORDER == __BIG_ENDIAN)
766 vscr_offset = 12;
767
768 supply_register_by_name (regcache, "vscr",
769 &regset[32 * 16 + vscr_offset]);
442ea881 770 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 771}
772
30ed0a8f
DJ		 773struct gdb_evrregset_t
774{
775 unsigned long evr[32];
776 unsigned long long acc;
777 unsigned long spefscr;
778};
779
780static void
442ea881 781ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 782{
783 int i, ev0;
2bc84e8a 784 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 785
3aee8918 786 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 787 for (i = 0; i < 32; i++)
442ea881 788 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 789
442ea881
PA		 790 collect_register_by_name (regcache, "acc", &regset->acc);
791 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 792}
793
794static void
442ea881 795ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 796{
797 int i, ev0;
2bc84e8a 798 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 799
3aee8918 800 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 801 for (i = 0; i < 32; i++)
442ea881 802 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 803
442ea881
PA		 804 supply_register_by_name (regcache, "acc", &regset->acc);
805 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 806}
30ed0a8f 807
7d00775e
AT		 808/* Support for hardware single step. */
809
810static int
811ppc_supports_hardware_single_step (void)
812{
813 return 1;
814}
815
3aee8918 816static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 817 /* List the extra register sets before GENERAL_REGS. That way we will
818 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
819 general registers. Some kernels support these, but not the newer
820 PPC_PTRACE_GETREGS. */
8d619c01
EBM		 821 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
822 NULL, ppc_store_tm_ctarregset },
823 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
824 NULL, ppc_store_tm_cdscrregset },
825 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
826 NULL, ppc_store_tm_cpprregset },
827 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
828 NULL, ppc_store_tm_cvsxregset },
829 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
830 NULL, ppc_store_tm_cvrregset },
831 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
832 NULL, ppc_store_tm_cfprregset },
833 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
834 NULL, ppc_store_tm_cgprregset },
835 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
836 ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
232bfb86
EBM		 837 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
838 NULL, ppc_store_ebbregset },
839 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
840 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 841 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
842 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 843 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
844 ppc_fill_pprregset, ppc_store_pprregset },
845 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
846 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 847 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 848 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 849 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 850 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 851 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 852 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 853 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 854 NULL_REGSET
e9d25b98
DJ		 855};
856
3aee8918
PA		 857static struct usrregs_info ppc_usrregs_info =
858 {
859 ppc_num_regs,
860 ppc_regmap,
861 };
862
863static struct regsets_info ppc_regsets_info =
864 {
865 ppc_regsets, /* regsets */
866 0, /* num_regsets */
867 NULL, /* disabled_regsets */
868 };
869
aa8d21c9 870static struct regs_info myregs_info =
3aee8918
PA		 871 {
872 NULL, /* regset_bitmap */
873 &ppc_usrregs_info,
874 &ppc_regsets_info
875 };
876
aa8d21c9
TBA		 877const regs_info *
878ppc_target::get_regs_info ()
3aee8918 879{
aa8d21c9 880 return &myregs_info;
3aee8918
PA		 881}
882
797bcff5
TBA		 883void
884ppc_target::low_arch_setup ()
e6c5bb05
SM		 885{
886 const struct target_desc *tdesc;
7273b5fc 887 struct regset_info *regset;
bd64614e 888 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 889
2e077f5e 890 int tid = lwpid_of (current_thread);
bd64614e 891
2e077f5e 892 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 893
bd64614e 894 if (features.wordsize == 4)
bd64614e 895 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 896 else
897 tdesc = tdesc_powerpc_64l;
898
899 current_process ()->tdesc = tdesc;
e6c5bb05 900
bd64614e
PFC		 901 /* The value of current_process ()->tdesc needs to be set for this
902 call. */
974c89e0
AH		 903 ppc_hwcap = linux_get_hwcap (features.wordsize);
904 ppc_hwcap2 = linux_get_hwcap2 (features.wordsize);
bd64614e
PFC		 905
906 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
907
908 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
909 features.vsx = true;
910
911 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
912 features.altivec = true;
913
7ca18ed6
EBM		 914 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
915 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
916 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 917 {
918 features.ppr_dscr = true;
919 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
920 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 921 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 922 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 923 PPC_LINUX_SIZEOF_TARREGSET)
924 && ppc_check_regset (tid, NT_PPC_EBB,
925 PPC_LINUX_SIZEOF_EBBREGSET)
926 && ppc_check_regset (tid, NT_PPC_PMU,
927 PPC_LINUX_SIZEOF_PMUREGSET))
8d619c01
EBM		 928 {
929 features.isa207 = true;
930 if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
931 && ppc_check_regset (tid, NT_PPC_TM_SPR,
932 PPC_LINUX_SIZEOF_TM_SPRREGSET))
933 features.htm = true;
934 }
f2cf6173 935 }
7ca18ed6 936
bd64614e 937 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 938
939 /* On 32-bit machines, check for SPE registers.
940 Set the low target's regmap field as appropriately. */
941#ifndef __powerpc64__
942 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
943 tdesc = tdesc_powerpc_e500l;
944
945 if (!ppc_regmap_adjusted)
946 {
947 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
948 ppc_usrregs_info.regmap = ppc_regmap_e500;
949
950 /* If the FPSCR is 64-bit wide, we need to fetch the whole
951 64-bit slot and not just its second word. The PT_FPSCR
952 supplied in a 32-bit GDB compilation doesn't reflect
953 this. */
954 if (register_size (tdesc, 70) == 8)
955 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
956
957 ppc_regmap_adjusted = 1;
958 }
959#endif
bd64614e 960
e6c5bb05 961 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 962
963 for (regset = ppc_regsets; regset->size >= 0; regset++)
964 switch (regset->get_request)
965 {
966 case PTRACE_GETVRREGS:
d078308a 967 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 968 break;
969 case PTRACE_GETVSXREGS:
d078308a 970 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 971 break;
972 case PTRACE_GETEVRREGS:
973 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
974 regset->size = 32 * 4 + 8 + 4;
975 else
976 regset->size = 0;
977 break;
7ca18ed6
EBM		 978 case PTRACE_GETREGSET:
979 switch (regset->nt_type)
980 {
981 case NT_PPC_PPR:
982 regset->size = (features.ppr_dscr ?
983 PPC_LINUX_SIZEOF_PPRREGSET : 0);
984 break;
985 case NT_PPC_DSCR:
986 regset->size = (features.ppr_dscr ?
987 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
988 break;
f2cf6173
EBM		 989 case NT_PPC_TAR:
990 regset->size = (features.isa207 ?
991 PPC_LINUX_SIZEOF_TARREGSET : 0);
992 break;
232bfb86
EBM		 993 case NT_PPC_EBB:
994 regset->size = (features.isa207 ?
995 PPC_LINUX_SIZEOF_EBBREGSET : 0);
996 break;
997 case NT_PPC_PMU:
998 regset->size = (features.isa207 ?
999 PPC_LINUX_SIZEOF_PMUREGSET : 0);
1000 break;
8d619c01
EBM		 1001 case NT_PPC_TM_SPR:
1002 regset->size = (features.htm ?
1003 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
1004 break;
1005 case NT_PPC_TM_CGPR:
1006 if (features.wordsize == 4)
1007 regset->size = (features.htm ?
1008 PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
1009 else
1010 regset->size = (features.htm ?
1011 PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
1012 break;
1013 case NT_PPC_TM_CFPR:
1014 regset->size = (features.htm ?
1015 PPC_LINUX_SIZEOF_CFPRREGSET : 0);
1016 break;
1017 case NT_PPC_TM_CVMX:
1018 regset->size = (features.htm ?
1019 PPC_LINUX_SIZEOF_CVMXREGSET : 0);
1020 break;
1021 case NT_PPC_TM_CVSX:
1022 regset->size = (features.htm ?
1023 PPC_LINUX_SIZEOF_CVSXREGSET : 0);
1024 break;
1025 case NT_PPC_TM_CPPR:
1026 regset->size = (features.htm ?
1027 PPC_LINUX_SIZEOF_CPPRREGSET : 0);
1028 break;
1029 case NT_PPC_TM_CDSCR:
1030 regset->size = (features.htm ?
1031 PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
1032 break;
1033 case NT_PPC_TM_CTAR:
1034 regset->size = (features.htm ?
1035 PPC_LINUX_SIZEOF_CTARREGSET : 0);
1036 break;
7ca18ed6
EBM		 1037 default:
1038 break;
1039 }
1040 break;
7273b5fc
PFC		 1041 default:
1042 break;
1043 }
e6c5bb05
SM		 1044}
1045
47f70aa7 1046/* Implementation of target ops method "supports_tracepoints". */
a2174ba4 1047
47f70aa7
TBA		 1048bool
1049ppc_target::supports_tracepoints ()
b04fd3be 1050{
47f70aa7 1051 return true;
b04fd3be
MK		 1052}
1053
a2174ba4
MK		 1054/* Get the thread area address. This is used to recognize which
1055 thread is which when tracing with the in-process agent library. We
1056 don't read anything from the address, and treat it as opaque; it's
1057 the address itself that we assume is unique per-thread. */
1058
13e567af
TBA		 1059int
1060ppc_target::low_get_thread_area (int lwpid, CORE_ADDR *addr)
a2174ba4 1061{
f2907e49 1062 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 1063 struct thread_info *thr = get_lwp_thread (lwp);
1064 struct regcache *regcache = get_thread_regcache (thr, 1);
1065 ULONGEST tp = 0;
1066
1067#ifdef __powerpc64__
1068 if (register_size (regcache->tdesc, 0) == 8)
1069 collect_register_by_name (regcache, "r13", &tp);
1070 else
1071#endif
1072 collect_register_by_name (regcache, "r2", &tp);
1073
1074 *addr = tp;
1075
1076 return 0;
1077}
1078
1079#ifdef __powerpc64__
1080
1081/* Older glibc doesn't provide this. */
1082
1083#ifndef EF_PPC64_ABI
1084#define EF_PPC64_ABI 3
1085#endif
1086
1087/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1088 inferiors. */
1089
1090static int
1091is_elfv2_inferior (void)
1092{
1093 /* To be used as fallback if we're unable to determine the right result -
1094 assume inferior uses the same ABI as gdbserver. */
1095#if _CALL_ELF == 2
1096 const int def_res = 1;
1097#else
1098 const int def_res = 0;
1099#endif
0570503d 1100 CORE_ADDR phdr;
a2174ba4
MK		 1101 Elf64_Ehdr ehdr;
1102
0570503d
PFC		 1103 const struct target_desc *tdesc = current_process ()->tdesc;
1104 int wordsize = register_size (tdesc, 0);
1105
1106 if (!linux_get_auxv (wordsize, AT_PHDR, &phdr))
a2174ba4
MK		 1107 return def_res;
1108
1109 /* Assume ELF header is at the beginning of the page where program headers
1110 are located. If it doesn't look like one, bail. */
1111
1112 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
1113 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
1114 return def_res;
1115
1116 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
1117}
1118
1119#endif
1120
1121/* Generate a ds-form instruction in BUF and return the number of bytes written
1122
1123 0 6 11 16 30 32
1124 | OPCD | RST | RA | DS |XO| */
1125
1126__attribute__((unused)) /* Maybe unused due to conditional compilation. */
1127static int
1128gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
1129{
1130 uint32_t insn;
1131
1132 gdb_assert ((opcd & ~0x3f) == 0);
1133 gdb_assert ((rst & ~0x1f) == 0);
1134 gdb_assert ((ra & ~0x1f) == 0);
1135 gdb_assert ((xo & ~0x3) == 0);
1136
1137 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
1138 *buf = (opcd << 26) | insn;
1139 return 1;
1140}
1141
1142/* Followings are frequently used ds-form instructions. */
1143
1144#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1145#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1146#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1147#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1148
1149/* Generate a d-form instruction in BUF.
1150
1151 0 6 11 16 32
1152 | OPCD | RST | RA | D | */
1153
1154static int
1155gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
1156{
1157 uint32_t insn;
1158
1159 gdb_assert ((opcd & ~0x3f) == 0);
1160 gdb_assert ((rst & ~0x1f) == 0);
1161 gdb_assert ((ra & ~0x1f) == 0);
1162
1163 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
1164 *buf = (opcd << 26) | insn;
1165 return 1;
1166}
1167
1168/* Followings are frequently used d-form instructions. */
1169
1170#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1171#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1172#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1173#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1174#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1175#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1176#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1177#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1178#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1179
1180/* Generate a xfx-form instruction in BUF and return the number of bytes
1181 written.
1182
1183 0 6 11 21 31 32
1184 | OPCD | RST | RI | XO |/| */
1185
1186static int
1187gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1188{
1189 uint32_t insn;
1190 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1191
1192 gdb_assert ((opcd & ~0x3f) == 0);
1193 gdb_assert ((rst & ~0x1f) == 0);
1194 gdb_assert ((xo & ~0x3ff) == 0);
1195
1196 insn = (rst << 21) | (n << 11) | (xo << 1);
1197 *buf = (opcd << 26) | insn;
1198 return 1;
1199}
1200
1201/* Followings are frequently used xfx-form instructions. */
1202
1203#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1204#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1205#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1206#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1207#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1208 E & 0xf, 598)
1209#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1210
1211
1212/* Generate a x-form instruction in BUF and return the number of bytes written.
1213
1214 0 6 11 16 21 31 32
1215 | OPCD | RST | RA | RB | XO |RC| */
1216
1217static int
1218gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1219{
1220 uint32_t insn;
1221
1222 gdb_assert ((opcd & ~0x3f) == 0);
1223 gdb_assert ((rst & ~0x1f) == 0);
1224 gdb_assert ((ra & ~0x1f) == 0);
1225 gdb_assert ((rb & ~0x1f) == 0);
1226 gdb_assert ((xo & ~0x3ff) == 0);
1227 gdb_assert ((rc & ~1) == 0);
1228
1229 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1230 *buf = (opcd << 26) | insn;
1231 return 1;
1232}
1233
1234/* Followings are frequently used x-form instructions. */
1235
1236#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1237#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1238#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1239#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1240/* Assume bf = cr7. */
1241#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1242
1243
1244/* Generate a md-form instruction in BUF and return the number of bytes written.
1245
1246 0 6 11 16 21 27 30 31 32
1247 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1248
1249static int
1250gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1251 int xo, int rc)
1252{
1253 uint32_t insn;
1254 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1255 unsigned int sh0_4 = sh & 0x1f;
1256 unsigned int sh5 = (sh >> 5) & 1;
1257
1258 gdb_assert ((opcd & ~0x3f) == 0);
1259 gdb_assert ((rs & ~0x1f) == 0);
1260 gdb_assert ((ra & ~0x1f) == 0);
1261 gdb_assert ((sh & ~0x3f) == 0);
1262 gdb_assert ((mb & ~0x3f) == 0);
1263 gdb_assert ((xo & ~0x7) == 0);
1264 gdb_assert ((rc & ~0x1) == 0);
1265
1266 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1267 | (sh5 << 1) | (xo << 2) | (rc & 1);
1268 *buf = (opcd << 26) | insn;
1269 return 1;
1270}
1271
1272/* The following are frequently used md-form instructions. */
1273
1274#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1275 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1276#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1277 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1278
1279/* Generate a i-form instruction in BUF and return the number of bytes written.
1280
1281 0 6 30 31 32
1282 | OPCD | LI |AA|LK| */
1283
1284static int
1285gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1286{
1287 uint32_t insn;
1288
1289 gdb_assert ((opcd & ~0x3f) == 0);
1290
1291 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1292 *buf = (opcd << 26) | insn;
1293 return 1;
1294}
1295
1296/* The following are frequently used i-form instructions. */
1297
1298#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1299#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1300
1301/* Generate a b-form instruction in BUF and return the number of bytes written.
1302
1303 0 6 11 16 30 31 32
1304 | OPCD | BO | BI | BD |AA|LK| */
1305
1306static int
1307gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1308 int aa, int lk)
1309{
1310 uint32_t insn;
1311
1312 gdb_assert ((opcd & ~0x3f) == 0);
1313 gdb_assert ((bo & ~0x1f) == 0);
1314 gdb_assert ((bi & ~0x1f) == 0);
1315
1316 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1317 *buf = (opcd << 26) | insn;
1318 return 1;
1319}
1320
1321/* The following are frequently used b-form instructions. */
1322/* Assume bi = cr7. */
1323#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1324
1325/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1326 respectively. They are primary used for save/restore GPRs in jump-pad,
1327 not used for bytecode compiling. */
1328
1329#ifdef __powerpc64__
1330#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1331 GEN_LD (buf, rt, ra, si) : \
1332 GEN_LWZ (buf, rt, ra, si))
1333#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1334 GEN_STD (buf, rt, ra, si) : \
1335 GEN_STW (buf, rt, ra, si))
1336#else
1337#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1338#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1339#endif
1340
1341/* Generate a sequence of instructions to load IMM in the register REG.
1342 Write the instructions in BUF and return the number of bytes written. */
1343
1344static int
1345gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1346{
1347 uint32_t *p = buf;
1348
1349 if ((imm + 32768) < 65536)
1350 {
1351 /* li reg, imm[15:0] */
1352 p += GEN_LI (p, reg, imm);
1353 }
1354 else if ((imm >> 32) == 0)
1355 {
1356 /* lis reg, imm[31:16]
1357 ori reg, reg, imm[15:0]
1358 rldicl reg, reg, 0, 32 */
1359 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1360 if ((imm & 0xffff) != 0)
1361 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1362 /* Clear upper 32-bit if sign-bit is set. */
1363 if (imm & (1u << 31) && is_64)
1364 p += GEN_RLDICL (p, reg, reg, 0, 32);
1365 }
1366 else
1367 {
1368 gdb_assert (is_64);
1369 /* lis reg, <imm[63:48]>
1370 ori reg, reg, <imm[48:32]>
1371 rldicr reg, reg, 32, 31
1372 oris reg, reg, <imm[31:16]>
1373 ori reg, reg, <imm[15:0]> */
1374 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1375 if (((imm >> 32) & 0xffff) != 0)
1376 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1377 p += GEN_RLDICR (p, reg, reg, 32, 31);
1378 if (((imm >> 16) & 0xffff) != 0)
1379 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1380 if ((imm & 0xffff) != 0)
1381 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1382 }
1383
1384 return p - buf;
1385}
1386
1387/* Generate a sequence for atomically exchange at location LOCK.
1388 This code sequence clobbers r6, r7, r8. LOCK is the location for
1389 the atomic-xchg, OLD_VALUE is expected old value stored in the
1390 location, and R_NEW is a register for the new value. */
1391
1392static int
1393gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1394 int is_64)
1395{
1396 const int r_lock = 6;
1397 const int r_old = 7;
1398 const int r_tmp = 8;
1399 uint32_t *p = buf;
1400
1401 /*
1402 1: lwarx TMP, 0, LOCK
1403 cmpwi TMP, OLD
1404 bne 1b
1405 stwcx. NEW, 0, LOCK
1406 bne 1b */
1407
1408 p += gen_limm (p, r_lock, lock, is_64);
1409 p += gen_limm (p, r_old, old_value, is_64);
1410
1411 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1412 p += GEN_CMPW (p, r_tmp, r_old);
1413 p += GEN_BNE (p, -8);
1414 p += GEN_STWCX (p, r_new, 0, r_lock);
1415 p += GEN_BNE (p, -16);
1416
1417 return p - buf;
1418}
1419
1420/* Generate a sequence of instructions for calling a function
1421 at address of FN. Return the number of bytes are written in BUF. */
1422
1423static int
1424gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1425{
1426 uint32_t *p = buf;
1427
1428 /* Must be called by r12 for caller to calculate TOC address. */
1429 p += gen_limm (p, 12, fn, is_64);
1430 if (is_opd)
1431 {
1432 p += GEN_LOAD (p, 11, 12, 16, is_64);
1433 p += GEN_LOAD (p, 2, 12, 8, is_64);
1434 p += GEN_LOAD (p, 12, 12, 0, is_64);
1435 }
1436 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1437 *p++ = 0x4e800421; /* bctrl */
1438
1439 return p - buf;
1440}
1441
1442/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1443 of instruction. This function is used to adjust pc-relative instructions
1444 when copying. */
1445
1446static void
1447ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1448{
1449 uint32_t insn, op6;
1450 long rel, newrel;
1451
1452 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1453 op6 = PPC_OP6 (insn);
1454
1455 if (op6 == 18 && (insn & 2) == 0)
1456 {
1457 /* branch && AA = 0 */
1458 rel = PPC_LI (insn);
1459 newrel = (oldloc - *to) + rel;
1460
1461 /* Out of range. Cannot relocate instruction. */
1462 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1463 return;
1464
1465 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1466 }
1467 else if (op6 == 16 && (insn & 2) == 0)
1468 {
1469 /* conditional branch && AA = 0 */
1470
1471 /* If the new relocation is too big for even a 26-bit unconditional
1472 branch, there is nothing we can do. Just abort.
1473
1474 Otherwise, if it can be fit in 16-bit conditional branch, just
1475 copy the instruction and relocate the address.
1476
1477 If the it's big for conditional-branch (16-bit), try to invert the
1478 condition and jump with 26-bit branch. For example,
1479
1480 beq .Lgoto
1481 INSN1
1482
1483 =>
1484
1485 bne 1f (+8)
1486 b .Lgoto
1487 1:INSN1
1488
1489 After this transform, we are actually jump from *TO+4 instead of *TO,
1490 so check the relocation again because it will be 1-insn farther then
1491 before if *TO is after OLDLOC.
1492
1493
1494 For BDNZT (or so) is transformed from
1495
1496 bdnzt eq, .Lgoto
1497 INSN1
1498
1499 =>
1500
1501 bdz 1f (+12)
1502 bf eq, 1f (+8)
1503 b .Lgoto
1504 1:INSN1
1505
1506 See also "BO field encodings". */
1507
1508 rel = PPC_BD (insn);
1509 newrel = (oldloc - *to) + rel;
1510
1511 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1512 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1513 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1514 {
1515 newrel -= 4;
1516
1517 /* Out of range. Cannot relocate instruction. */
1518 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1519 return;
1520
1521 if ((PPC_BO (insn) & 0x14) == 0x4)
1522 insn ^= (1 << 24);
1523 else if ((PPC_BO (insn) & 0x14) == 0x10)
1524 insn ^= (1 << 22);
1525
1526 /* Jump over the unconditional branch. */
1527 insn = (insn & ~0xfffc) | 0x8;
4196ab2a 1528 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1529 *to += 4;
1530
1531 /* Build a unconditional branch and copy LK bit. */
1532 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1533 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1534 *to += 4;
1535
1536 return;
1537 }
1538 else if ((PPC_BO (insn) & 0x14) == 0)
1539 {
1540 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1541 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1542
1543 newrel -= 8;
1544
1545 /* Out of range. Cannot relocate instruction. */
1546 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1547 return;
1548
1549 /* Copy BI field. */
1550 bf_insn |= (insn & 0x1f0000);
1551
1552 /* Invert condition. */
1553 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1554 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1555
4196ab2a 1556 target_write_memory (*to, (unsigned char *) &bdnz_insn, 4);
a2174ba4 1557 *to += 4;
4196ab2a 1558 target_write_memory (*to, (unsigned char *) &bf_insn, 4);
a2174ba4
MK		 1559 *to += 4;
1560
1561 /* Build a unconditional branch and copy LK bit. */
1562 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1563 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1564 *to += 4;
1565
1566 return;
1567 }
1568 else /* (BO & 0x14) == 0x14, branch always. */
1569 {
1570 /* Out of range. Cannot relocate instruction. */
1571 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1572 return;
1573
1574 /* Build a unconditional branch and copy LK bit. */
1575 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1576 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1577 *to += 4;
1578
1579 return;
1580 }
1581 }
1582
4196ab2a 1583 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1584 *to += 4;
1585}
1586
809a0c35
TBA		 1587bool
1588ppc_target::supports_fast_tracepoints ()
1589{
1590 return true;
1591}
1592
a2174ba4
MK		 1593/* Implement install_fast_tracepoint_jump_pad of target_ops.
1594 See target.h for details. */
1595
809a0c35
TBA		 1596int
1597ppc_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
1598 CORE_ADDR tpaddr,
1599 CORE_ADDR collector,
1600 CORE_ADDR lockaddr,
1601 ULONGEST orig_size,
1602 CORE_ADDR *jump_entry,
1603 CORE_ADDR *trampoline,
1604 ULONGEST *trampoline_size,
1605 unsigned char *jjump_pad_insn,
1606 ULONGEST *jjump_pad_insn_size,
1607 CORE_ADDR *adjusted_insn_addr,
1608 CORE_ADDR *adjusted_insn_addr_end,
1609 char *err)
a2174ba4
MK		 1610{
1611 uint32_t buf[256];
1612 uint32_t *p = buf;
1613 int j, offset;
1614 CORE_ADDR buildaddr = *jump_entry;
1615 const CORE_ADDR entryaddr = *jump_entry;
1616 int rsz, min_frame, frame_size, tp_reg;
1617#ifdef __powerpc64__
1618 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1619 int is_64 = register_size (regcache->tdesc, 0) == 8;
1620 int is_opd = is_64 && !is_elfv2_inferior ();
1621#else
1622 int is_64 = 0, is_opd = 0;
1623#endif
1624
1625#ifdef __powerpc64__
1626 if (is_64)
1627 {
1628 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1629 rsz = 8;
1630 min_frame = 112;
1631 frame_size = (40 * rsz) + min_frame;
1632 tp_reg = 13;
1633 }
1634 else
1635 {
1636#endif
1637 rsz = 4;
1638 min_frame = 16;
1639 frame_size = (40 * rsz) + min_frame;
1640 tp_reg = 2;
1641#ifdef __powerpc64__
1642 }
1643#endif
1644
1645 /* Stack frame layout for this jump pad,
1646
1647 High thread_area (r13/r2) |
1648 tpoint - collecting_t obj
1649 PC/<tpaddr> | +36
1650 CTR | +35
1651 LR | +34
1652 XER | +33
1653 CR | +32
1654 R31 |
1655 R29 |
1656 ... |
1657 R1 | +1
1658 R0 - collected registers
1659 ... |
1660 ... |
1661 Low Back-chain -
1662
1663
1664 The code flow of this jump pad,
1665
1666 1. Adjust SP
1667 2. Save GPR and SPR
1668 3. Prepare argument
1669 4. Call gdb_collector
1670 5. Restore GPR and SPR
1671 6. Restore SP
1672 7. Build a jump for back to the program
1673 8. Copy/relocate original instruction
30baf67b 1674 9. Build a jump for replacing original instruction. */
a2174ba4
MK		 1675
1676 /* Adjust stack pointer. */
1677 if (is_64)
1678 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1679 else
1680 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1681
1682 /* Store GPRs. Save R1 later, because it had just been modified, but
1683 we want the original value. */
1684 for (j = 2; j < 32; j++)
1685 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1686 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1687 /* Set r0 to the original value of r1 before adjusting stack frame,
1688 and then save it. */
1689 p += GEN_ADDI (p, 0, 1, frame_size);
1690 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1691
1692 /* Save CR, XER, LR, and CTR. */
1693 p += GEN_MFCR (p, 3); /* mfcr r3 */
1694 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1695 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1696 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1697 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1698 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1699 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1700 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1701
1702 /* Save PC<tpaddr> */
1703 p += gen_limm (p, 3, tpaddr, is_64);
1704 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1705
1706
1707 /* Setup arguments to collector. */
1708 /* Set r4 to collected registers. */
1709 p += GEN_ADDI (p, 4, 1, min_frame);
1710 /* Set r3 to TPOINT. */
1711 p += gen_limm (p, 3, tpoint, is_64);
1712
1713 /* Prepare collecting_t object for lock. */
1714 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1715 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1716 /* Set R5 to collecting object. */
1717 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1718
1719 p += GEN_LWSYNC (p);
1720 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1721 p += GEN_LWSYNC (p);
1722
1723 /* Call to collector. */
1724 p += gen_call (p, collector, is_64, is_opd);
1725
1726 /* Simply write 0 to release the lock. */
1727 p += gen_limm (p, 3, lockaddr, is_64);
1728 p += gen_limm (p, 4, 0, is_64);
1729 p += GEN_LWSYNC (p);
1730 p += GEN_STORE (p, 4, 3, 0, is_64);
1731
1732 /* Restore stack and registers. */
1733 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1734 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1735 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1736 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1737 p += GEN_MTCR (p, 3); /* mtcr r3 */
1738 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1739 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1740 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1741
1742 /* Restore GPRs. */
1743 for (j = 2; j < 32; j++)
1744 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1745 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1746 /* Restore SP. */
1747 p += GEN_ADDI (p, 1, 1, frame_size);
1748
1749 /* Flush instructions to inferior memory. */
4196ab2a 1750 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1751
1752 /* Now, insert the original instruction to execute in the jump pad. */
1753 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1754 *adjusted_insn_addr_end = *adjusted_insn_addr;
1755 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1756
1757 /* Verify the relocation size. If should be 4 for normal copy,
1758 8 or 12 for some conditional branch. */
1759 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1760 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1761 {
1762 sprintf (err, "E.Unexpected instruction length = %d"
1763 "when relocate instruction.",
1764 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1765 return 1;
1766 }
1767
1768 buildaddr = *adjusted_insn_addr_end;
1769 p = buf;
1770 /* Finally, write a jump back to the program. */
1771 offset = (tpaddr + 4) - buildaddr;
1772 if (offset >= (1 << 25) || offset < -(1 << 25))
1773 {
1774 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1775 "(offset 0x%x > 26-bit).", offset);
1776 return 1;
1777 }
1778 /* b <tpaddr+4> */
1779 p += GEN_B (p, offset);
4196ab2a 1780 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1781 *jump_entry = buildaddr + (p - buf) * 4;
1782
1783 /* The jump pad is now built. Wire in a jump to our jump pad. This
1784 is always done last (by our caller actually), so that we can
1785 install fast tracepoints with threads running. This relies on
1786 the agent's atomic write support. */
1787 offset = entryaddr - tpaddr;
1788 if (offset >= (1 << 25) || offset < -(1 << 25))
1789 {
1790 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1791 "(offset 0x%x > 26-bit).", offset);
1792 return 1;
1793 }
1794 /* b <jentry> */
1795 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1796 *jjump_pad_insn_size = 4;
1797
1798 return 0;
1799}
1800
1801/* Returns the minimum instruction length for installing a tracepoint. */
1802
809a0c35
TBA		 1803int
1804ppc_target::get_min_fast_tracepoint_insn_len ()
a2174ba4
MK		 1805{
1806 return 4;
1807}
1808
14e2b6d9
MK		 1809/* Emits a given buffer into the target at current_insn_ptr. Length
1810 is in units of 32-bit words. */
1811
1812static void
1813emit_insns (uint32_t *buf, int n)
1814{
1815 n = n * sizeof (uint32_t);
4196ab2a 1816 target_write_memory (current_insn_ptr, (unsigned char *) buf, n);
14e2b6d9
MK		 1817 current_insn_ptr += n;
1818}
1819
1820#define __EMIT_ASM(NAME, INSNS) \
1821 do \
1822 { \
1823 extern uint32_t start_bcax_ ## NAME []; \
1824 extern uint32_t end_bcax_ ## NAME []; \
1825 emit_insns (start_bcax_ ## NAME, \
1826 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1827 __asm__ (".section .text.__ppcbcax\n\t" \
1828 "start_bcax_" #NAME ":\n\t" \
1829 INSNS "\n\t" \
1830 "end_bcax_" #NAME ":\n\t" \
1831 ".previous\n\t"); \
1832 } while (0)
1833
1834#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1835#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1836
1837/*
1838
1839 Bytecode execution stack frame - 32-bit
1840
1841 | LR save area (SP + 4)
1842 SP' -> +- Back chain (SP + 0)
1843 | Save r31 for access saved arguments
1844 | Save r30 for bytecode stack pointer
1845 | Save r4 for incoming argument *value
1846 | Save r3 for incoming argument regs
1847 r30 -> +- Bytecode execution stack
1848 |
1849 | 64-byte (8 doublewords) at initial.
1850 | Expand stack as needed.
1851 |
1852 +-
1853 | Some padding for minimum stack frame and 16-byte alignment.
1854 | 16 bytes.
1855 SP +- Back-chain (SP')
1856
1857 initial frame size
1858 = 16 + (4 * 4) + 64
1859 = 96
1860
1861 r30 is the stack-pointer for bytecode machine.
1862 It should point to next-empty, so we can use LDU for pop.
1863 r3 is used for cache of the high part of TOP value.
1864 It was the first argument, pointer to regs.
1865 r4 is used for cache of the low part of TOP value.
1866 It was the second argument, pointer to the result.
1867 We should set *result = TOP after leaving this function.
1868
1869 Note:
1870 * To restore stack at epilogue
1871 => sp = r31
1872 * To check stack is big enough for bytecode execution.
1873 => r30 - 8 > SP + 8
1874 * To return execution result.
1875 => 0(r4) = TOP
1876
1877 */
1878
1879/* Regardless of endian, register 3 is always high part, 4 is low part.
1880 These defines are used when the register pair is stored/loaded.
1881 Likewise, to simplify code, have a similiar define for 5:6. */
1882
1883#if __BYTE_ORDER == __LITTLE_ENDIAN
1884#define TOP_FIRST "4"
1885#define TOP_SECOND "3"
1886#define TMP_FIRST "6"
1887#define TMP_SECOND "5"
1888#else
1889#define TOP_FIRST "3"
1890#define TOP_SECOND "4"
1891#define TMP_FIRST "5"
1892#define TMP_SECOND "6"
1893#endif
1894
1895/* Emit prologue in inferior memory. See above comments. */
1896
1897static void
1898ppc_emit_prologue (void)
1899{
1900 EMIT_ASM (/* Save return address. */
1901 "mflr 0 \n"
1902 "stw 0, 4(1) \n"
1903 /* Adjust SP. 96 is the initial frame size. */
1904 "stwu 1, -96(1) \n"
1905 /* Save r30 and incoming arguments. */
1906 "stw 31, 96-4(1) \n"
1907 "stw 30, 96-8(1) \n"
1908 "stw 4, 96-12(1) \n"
1909 "stw 3, 96-16(1) \n"
1910 /* Point r31 to original r1 for access arguments. */
1911 "addi 31, 1, 96 \n"
1912 /* Set r30 to pointing stack-top. */
1913 "addi 30, 1, 64 \n"
1914 /* Initial r3/TOP to 0. */
1915 "li 3, 0 \n"
1916 "li 4, 0 \n");
1917}
1918
1919/* Emit epilogue in inferior memory. See above comments. */
1920
1921static void
1922ppc_emit_epilogue (void)
1923{
1924 EMIT_ASM (/* *result = TOP */
1925 "lwz 5, -12(31) \n"
1926 "stw " TOP_FIRST ", 0(5) \n"
1927 "stw " TOP_SECOND ", 4(5) \n"
1928 /* Restore registers. */
1929 "lwz 31, -4(31) \n"
1930 "lwz 30, -8(31) \n"
1931 /* Restore SP. */
1932 "lwz 1, 0(1) \n"
1933 /* Restore LR. */
1934 "lwz 0, 4(1) \n"
1935 /* Return 0 for no-error. */
1936 "li 3, 0 \n"
1937 "mtlr 0 \n"
1938 "blr \n");
1939}
1940
1941/* TOP = stack[--sp] + TOP */
1942
1943static void
1944ppc_emit_add (void)
1945{
1946 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1947 "lwz " TMP_SECOND ", 4(30)\n"
1948 "addc 4, 6, 4 \n"
1949 "adde 3, 5, 3 \n");
1950}
1951
1952/* TOP = stack[--sp] - TOP */
1953
1954static void
1955ppc_emit_sub (void)
1956{
1957 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1958 "lwz " TMP_SECOND ", 4(30) \n"
1959 "subfc 4, 4, 6 \n"
1960 "subfe 3, 3, 5 \n");
1961}
1962
1963/* TOP = stack[--sp] * TOP */
1964
1965static void
1966ppc_emit_mul (void)
1967{
1968 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1969 "lwz " TMP_SECOND ", 4(30) \n"
1970 "mulhwu 7, 6, 4 \n"
1971 "mullw 3, 6, 3 \n"
1972 "mullw 5, 4, 5 \n"
1973 "mullw 4, 6, 4 \n"
1974 "add 3, 5, 3 \n"
1975 "add 3, 7, 3 \n");
1976}
1977
1978/* TOP = stack[--sp] << TOP */
1979
1980static void
1981ppc_emit_lsh (void)
1982{
1983 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1984 "lwz " TMP_SECOND ", 4(30) \n"
1985 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1986 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1987 "slw 5, 5, 4\n" /* Shift high part left */
1988 "slw 4, 6, 4\n" /* Shift low part left */
1989 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1990 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1991 "or 3, 5, 3\n"
1992 "or 3, 7, 3\n"); /* Assemble high part */
1993}
1994
1995/* Top = stack[--sp] >> TOP
1996 (Arithmetic shift right) */
1997
1998static void
1999ppc_emit_rsh_signed (void)
2000{
2001 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2002 "lwz " TMP_SECOND ", 4(30) \n"
2003 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2004 "sraw 3, 5, 4\n" /* Shift high part right */
2005 "cmpwi 7, 1\n"
2006 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
2007 "sraw 4, 5, 7\n" /* Shift high to low */
2008 "b 2f\n"
2009 "1:\n"
2010 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
2011 "srw 4, 6, 4\n" /* Shift low part right */
2012 "slw 5, 5, 7\n" /* Shift high to low */
2013 "or 4, 4, 5\n" /* Assemble low part */
2014 "2:\n");
2015}
2016
2017/* Top = stack[--sp] >> TOP
2018 (Logical shift right) */
2019
2020static void
2021ppc_emit_rsh_unsigned (void)
2022{
2023 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2024 "lwz " TMP_SECOND ", 4(30) \n"
2025 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2026 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2027 "srw 6, 6, 4\n" /* Shift low part right */
2028 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2029 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2030 "or 6, 6, 3\n"
2031 "srw 3, 5, 4\n" /* Shift high part right */
2032 "or 4, 6, 7\n"); /* Assemble low part */
2033}
2034
2035/* Emit code for signed-extension specified by ARG. */
2036
2037static void
2038ppc_emit_ext (int arg)
2039{
2040 switch (arg)
2041 {
2042 case 8:
2043 EMIT_ASM ("extsb 4, 4\n"
2044 "srawi 3, 4, 31");
2045 break;
2046 case 16:
2047 EMIT_ASM ("extsh 4, 4\n"
2048 "srawi 3, 4, 31");
2049 break;
2050 case 32:
2051 EMIT_ASM ("srawi 3, 4, 31");
2052 break;
2053 default:
2054 emit_error = 1;
2055 }
2056}
2057
2058/* Emit code for zero-extension specified by ARG. */
2059
2060static void
2061ppc_emit_zero_ext (int arg)
2062{
2063 switch (arg)
2064 {
2065 case 8:
2066 EMIT_ASM ("clrlwi 4,4,24\n"
2067 "li 3, 0\n");
2068 break;
2069 case 16:
2070 EMIT_ASM ("clrlwi 4,4,16\n"
2071 "li 3, 0\n");
2072 break;
2073 case 32:
2074 EMIT_ASM ("li 3, 0");
2075 break;
2076 default:
2077 emit_error = 1;
2078 }
2079}
2080
2081/* TOP = !TOP
2082 i.e., TOP = (TOP == 0) ? 1 : 0; */
2083
2084static void
2085ppc_emit_log_not (void)
2086{
2087 EMIT_ASM ("or 4, 3, 4 \n"
2088 "cntlzw 4, 4 \n"
2089 "srwi 4, 4, 5 \n"
2090 "li 3, 0 \n");
2091}
2092
2093/* TOP = stack[--sp] & TOP */
2094
2095static void
2096ppc_emit_bit_and (void)
2097{
2098 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2099 "lwz " TMP_SECOND ", 4(30) \n"
2100 "and 4, 6, 4 \n"
2101 "and 3, 5, 3 \n");
2102}
2103
2104/* TOP = stack[--sp] | TOP */
2105
2106static void
2107ppc_emit_bit_or (void)
2108{
2109 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2110 "lwz " TMP_SECOND ", 4(30) \n"
2111 "or 4, 6, 4 \n"
2112 "or 3, 5, 3 \n");
2113}
2114
2115/* TOP = stack[--sp] ^ TOP */
2116
2117static void
2118ppc_emit_bit_xor (void)
2119{
2120 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2121 "lwz " TMP_SECOND ", 4(30) \n"
2122 "xor 4, 6, 4 \n"
2123 "xor 3, 5, 3 \n");
2124}
2125
2126/* TOP = ~TOP
2127 i.e., TOP = ~(TOP | TOP) */
2128
2129static void
2130ppc_emit_bit_not (void)
2131{
2132 EMIT_ASM ("nor 3, 3, 3 \n"
2133 "nor 4, 4, 4 \n");
2134}
2135
2136/* TOP = stack[--sp] == TOP */
2137
2138static void
2139ppc_emit_equal (void)
2140{
2141 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2142 "lwz " TMP_SECOND ", 4(30) \n"
2143 "xor 4, 6, 4 \n"
2144 "xor 3, 5, 3 \n"
2145 "or 4, 3, 4 \n"
2146 "cntlzw 4, 4 \n"
2147 "srwi 4, 4, 5 \n"
2148 "li 3, 0 \n");
2149}
2150
2151/* TOP = stack[--sp] < TOP
2152 (Signed comparison) */
2153
2154static void
2155ppc_emit_less_signed (void)
2156{
2157 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2158 "lwz " TMP_SECOND ", 4(30) \n"
2159 "cmplw 6, 6, 4 \n"
2160 "cmpw 7, 5, 3 \n"
2161 /* CR6 bit 0 = low less and high equal */
2162 "crand 6*4+0, 6*4+0, 7*4+2\n"
2163 /* CR7 bit 0 = (low less and high equal) or high less */
2164 "cror 7*4+0, 7*4+0, 6*4+0\n"
2165 "mfcr 4 \n"
2166 "rlwinm 4, 4, 29, 31, 31 \n"
2167 "li 3, 0 \n");
2168}
2169
2170/* TOP = stack[--sp] < TOP
2171 (Unsigned comparison) */
2172
2173static void
2174ppc_emit_less_unsigned (void)
2175{
2176 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2177 "lwz " TMP_SECOND ", 4(30) \n"
2178 "cmplw 6, 6, 4 \n"
2179 "cmplw 7, 5, 3 \n"
2180 /* CR6 bit 0 = low less and high equal */
2181 "crand 6*4+0, 6*4+0, 7*4+2\n"
2182 /* CR7 bit 0 = (low less and high equal) or high less */
2183 "cror 7*4+0, 7*4+0, 6*4+0\n"
2184 "mfcr 4 \n"
2185 "rlwinm 4, 4, 29, 31, 31 \n"
2186 "li 3, 0 \n");
2187}
2188
2189/* Access the memory address in TOP in size of SIZE.
2190 Zero-extend the read value. */
2191
2192static void
2193ppc_emit_ref (int size)
2194{
2195 switch (size)
2196 {
2197 case 1:
2198 EMIT_ASM ("lbz 4, 0(4)\n"
2199 "li 3, 0");
2200 break;
2201 case 2:
2202 EMIT_ASM ("lhz 4, 0(4)\n"
2203 "li 3, 0");
2204 break;
2205 case 4:
2206 EMIT_ASM ("lwz 4, 0(4)\n"
2207 "li 3, 0");
2208 break;
2209 case 8:
2210 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2211 EMIT_ASM ("lwz 3, 4(4)\n"
2212 "lwz 4, 0(4)");
2213 else
2214 EMIT_ASM ("lwz 3, 0(4)\n"
2215 "lwz 4, 4(4)");
2216 break;
2217 }
2218}
2219
2220/* TOP = NUM */
2221
2222static void
2223ppc_emit_const (LONGEST num)
2224{
2225 uint32_t buf[10];
2226 uint32_t *p = buf;
2227
2228 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2229 p += gen_limm (p, 4, num & 0xffffffff, 0);
2230
2231 emit_insns (buf, p - buf);
2232 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2233}
2234
2235/* Set TOP to the value of register REG by calling get_raw_reg function
2236 with two argument, collected buffer and register number. */
2237
2238static void
2239ppc_emit_reg (int reg)
2240{
2241 uint32_t buf[13];
2242 uint32_t *p = buf;
2243
2244 /* fctx->regs is passed in r3 and then saved in -16(31). */
2245 p += GEN_LWZ (p, 3, 31, -16);
2246 p += GEN_LI (p, 4, reg); /* li r4, reg */
2247 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2248
2249 emit_insns (buf, p - buf);
2250 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2251
2252 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2253 {
2254 EMIT_ASM ("mr 5, 4\n"
2255 "mr 4, 3\n"
2256 "mr 3, 5\n");
2257 }
2258}
2259
2260/* TOP = stack[--sp] */
2261
2262static void
2263ppc_emit_pop (void)
2264{
2265 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2266 "lwz " TOP_SECOND ", 4(30) \n");
2267}
2268
2269/* stack[sp++] = TOP
2270
2271 Because we may use up bytecode stack, expand 8 doublewords more
2272 if needed. */
2273
2274static void
2275ppc_emit_stack_flush (void)
2276{
2277 /* Make sure bytecode stack is big enough before push.
2278 Otherwise, expand 64-byte more. */
2279
2280 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2281 " stw " TOP_SECOND ", 4(30)\n"
2282 " addi 5, 30, -(8 + 8) \n"
2283 " cmpw 7, 5, 1 \n"
2284 " bgt 7, 1f \n"
2285 " stwu 31, -64(1) \n"
2286 "1:addi 30, 30, -8 \n");
2287}
2288
2289/* Swap TOP and stack[sp-1] */
2290
2291static void
2292ppc_emit_swap (void)
2293{
2294 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2295 "lwz " TMP_SECOND ", 12(30) \n"
2296 "stw " TOP_FIRST ", 8(30) \n"
2297 "stw " TOP_SECOND ", 12(30) \n"
2298 "mr 3, 5 \n"
2299 "mr 4, 6 \n");
2300}
2301
2302/* Discard N elements in the stack. Also used for ppc64. */
2303
2304static void
2305ppc_emit_stack_adjust (int n)
2306{
2307 uint32_t buf[6];
2308 uint32_t *p = buf;
2309
2310 n = n << 3;
2311 if ((n >> 15) != 0)
2312 {
2313 emit_error = 1;
2314 return;
2315 }
2316
2317 p += GEN_ADDI (p, 30, 30, n);
2318
2319 emit_insns (buf, p - buf);
2320 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2321}
2322
2323/* Call function FN. */
2324
2325static void
2326ppc_emit_call (CORE_ADDR fn)
2327{
2328 uint32_t buf[11];
2329 uint32_t *p = buf;
2330
2331 p += gen_call (p, fn, 0, 0);
2332
2333 emit_insns (buf, p - buf);
2334 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2335}
2336
2337/* FN's prototype is `LONGEST(*fn)(int)'.
2338 TOP = fn (arg1)
2339 */
2340
2341static void
2342ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2343{
2344 uint32_t buf[15];
2345 uint32_t *p = buf;
2346
2347 /* Setup argument. arg1 is a 16-bit value. */
2348 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2349 p += gen_call (p, fn, 0, 0);
2350
2351 emit_insns (buf, p - buf);
2352 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2353
2354 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2355 {
2356 EMIT_ASM ("mr 5, 4\n"
2357 "mr 4, 3\n"
2358 "mr 3, 5\n");
2359 }
2360}
2361
2362/* FN's prototype is `void(*fn)(int,LONGEST)'.
2363 fn (arg1, TOP)
2364
2365 TOP should be preserved/restored before/after the call. */
2366
2367static void
2368ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2369{
2370 uint32_t buf[21];
2371 uint32_t *p = buf;
2372
2373 /* Save TOP. 0(30) is next-empty. */
2374 p += GEN_STW (p, 3, 30, 0);
2375 p += GEN_STW (p, 4, 30, 4);
2376
2377 /* Setup argument. arg1 is a 16-bit value. */
2378 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2379 {
2380 p += GEN_MR (p, 5, 4);
2381 p += GEN_MR (p, 6, 3);
2382 }
2383 else
2384 {
2385 p += GEN_MR (p, 5, 3);
2386 p += GEN_MR (p, 6, 4);
2387 }
2388 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2389 p += gen_call (p, fn, 0, 0);
2390
2391 /* Restore TOP */
2392 p += GEN_LWZ (p, 3, 30, 0);
2393 p += GEN_LWZ (p, 4, 30, 4);
2394
2395 emit_insns (buf, p - buf);
2396 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2397}
2398
2399/* Note in the following goto ops:
2400
2401 When emitting goto, the target address is later relocated by
2402 write_goto_address. OFFSET_P is the offset of the branch instruction
2403 in the code sequence, and SIZE_P is how to relocate the instruction,
2404 recognized by ppc_write_goto_address. In current implementation,
2405 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2406 */
2407
2408/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2409
2410static void
2411ppc_emit_if_goto (int *offset_p, int *size_p)
2412{
2413 EMIT_ASM ("or. 3, 3, 4 \n"
2414 "lwzu " TOP_FIRST ", 8(30) \n"
2415 "lwz " TOP_SECOND ", 4(30) \n"
2416 "1:bne 0, 1b \n");
2417
2418 if (offset_p)
2419 *offset_p = 12;
2420 if (size_p)
2421 *size_p = 14;
2422}
2423
2424/* Unconditional goto. Also used for ppc64. */
2425
2426static void
2427ppc_emit_goto (int *offset_p, int *size_p)
2428{
2429 EMIT_ASM ("1:b 1b");
2430
2431 if (offset_p)
2432 *offset_p = 0;
2433 if (size_p)
2434 *size_p = 24;
2435}
2436
2437/* Goto if stack[--sp] == TOP */
2438
2439static void
2440ppc_emit_eq_goto (int *offset_p, int *size_p)
2441{
2442 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2443 "lwz " TMP_SECOND ", 4(30) \n"
2444 "xor 4, 6, 4 \n"
2445 "xor 3, 5, 3 \n"
2446 "or. 3, 3, 4 \n"
2447 "lwzu " TOP_FIRST ", 8(30) \n"
2448 "lwz " TOP_SECOND ", 4(30) \n"
2449 "1:beq 0, 1b \n");
2450
2451 if (offset_p)
2452 *offset_p = 28;
2453 if (size_p)
2454 *size_p = 14;
2455}
2456
2457/* Goto if stack[--sp] != TOP */
2458
2459static void
2460ppc_emit_ne_goto (int *offset_p, int *size_p)
2461{
2462 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2463 "lwz " TMP_SECOND ", 4(30) \n"
2464 "xor 4, 6, 4 \n"
2465 "xor 3, 5, 3 \n"
2466 "or. 3, 3, 4 \n"
2467 "lwzu " TOP_FIRST ", 8(30) \n"
2468 "lwz " TOP_SECOND ", 4(30) \n"
2469 "1:bne 0, 1b \n");
2470
2471 if (offset_p)
2472 *offset_p = 28;
2473 if (size_p)
2474 *size_p = 14;
2475}
2476
2477/* Goto if stack[--sp] < TOP */
2478
2479static void
2480ppc_emit_lt_goto (int *offset_p, int *size_p)
2481{
2482 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2483 "lwz " TMP_SECOND ", 4(30) \n"
2484 "cmplw 6, 6, 4 \n"
2485 "cmpw 7, 5, 3 \n"
2486 /* CR6 bit 0 = low less and high equal */
2487 "crand 6*4+0, 6*4+0, 7*4+2\n"
2488 /* CR7 bit 0 = (low less and high equal) or high less */
2489 "cror 7*4+0, 7*4+0, 6*4+0\n"
2490 "lwzu " TOP_FIRST ", 8(30) \n"
2491 "lwz " TOP_SECOND ", 4(30)\n"
2492 "1:blt 7, 1b \n");
2493
2494 if (offset_p)
2495 *offset_p = 32;
2496 if (size_p)
2497 *size_p = 14;
2498}
2499
2500/* Goto if stack[--sp] <= TOP */
2501
2502static void
2503ppc_emit_le_goto (int *offset_p, int *size_p)
2504{
2505 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2506 "lwz " TMP_SECOND ", 4(30) \n"
2507 "cmplw 6, 6, 4 \n"
2508 "cmpw 7, 5, 3 \n"
2509 /* CR6 bit 0 = low less/equal and high equal */
2510 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2511 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2512 "cror 7*4+0, 7*4+0, 6*4+0\n"
2513 "lwzu " TOP_FIRST ", 8(30) \n"
2514 "lwz " TOP_SECOND ", 4(30)\n"
2515 "1:blt 7, 1b \n");
2516
2517 if (offset_p)
2518 *offset_p = 32;
2519 if (size_p)
2520 *size_p = 14;
2521}
2522
2523/* Goto if stack[--sp] > TOP */
2524
2525static void
2526ppc_emit_gt_goto (int *offset_p, int *size_p)
2527{
2528 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2529 "lwz " TMP_SECOND ", 4(30) \n"
2530 "cmplw 6, 6, 4 \n"
2531 "cmpw 7, 5, 3 \n"
2532 /* CR6 bit 0 = low greater and high equal */
2533 "crand 6*4+0, 6*4+1, 7*4+2\n"
2534 /* CR7 bit 0 = (low greater and high equal) or high greater */
2535 "cror 7*4+0, 7*4+1, 6*4+0\n"
2536 "lwzu " TOP_FIRST ", 8(30) \n"
2537 "lwz " TOP_SECOND ", 4(30)\n"
2538 "1:blt 7, 1b \n");
2539
2540 if (offset_p)
2541 *offset_p = 32;
2542 if (size_p)
2543 *size_p = 14;
2544}
2545
2546/* Goto if stack[--sp] >= TOP */
2547
2548static void
2549ppc_emit_ge_goto (int *offset_p, int *size_p)
2550{
2551 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2552 "lwz " TMP_SECOND ", 4(30) \n"
2553 "cmplw 6, 6, 4 \n"
2554 "cmpw 7, 5, 3 \n"
2555 /* CR6 bit 0 = low ge and high equal */
2556 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2557 /* CR7 bit 0 = (low ge and high equal) or high greater */
2558 "cror 7*4+0, 7*4+1, 6*4+0\n"
2559 "lwzu " TOP_FIRST ", 8(30)\n"
2560 "lwz " TOP_SECOND ", 4(30)\n"
2561 "1:blt 7, 1b \n");
2562
2563 if (offset_p)
2564 *offset_p = 32;
2565 if (size_p)
2566 *size_p = 14;
2567}
2568
2569/* Relocate previous emitted branch instruction. FROM is the address
2570 of the branch instruction, TO is the goto target address, and SIZE
2571 if the value we set by *SIZE_P before. Currently, it is either
2572 24 or 14 of branch and conditional-branch instruction.
2573 Also used for ppc64. */
2574
2575static void
2576ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2577{
2578 long rel = to - from;
2579 uint32_t insn;
2580 int opcd;
2581
2582 read_inferior_memory (from, (unsigned char *) &insn, 4);
2583 opcd = (insn >> 26) & 0x3f;
2584
2585 switch (size)
2586 {
2587 case 14:
2588 if (opcd != 16
2589 || (rel >= (1 << 15) || rel < -(1 << 15)))
2590 emit_error = 1;
2591 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2592 break;
2593 case 24:
2594 if (opcd != 18
2595 || (rel >= (1 << 25) || rel < -(1 << 25)))
2596 emit_error = 1;
2597 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2598 break;
2599 default:
2600 emit_error = 1;
2601 }
2602
2603 if (!emit_error)
4196ab2a 2604 target_write_memory (from, (unsigned char *) &insn, 4);
14e2b6d9
MK		 2605}
2606
2607/* Table of emit ops for 32-bit. */
2608
2609static struct emit_ops ppc_emit_ops_impl =
2610{
2611 ppc_emit_prologue,
2612 ppc_emit_epilogue,
2613 ppc_emit_add,
2614 ppc_emit_sub,
2615 ppc_emit_mul,
2616 ppc_emit_lsh,
2617 ppc_emit_rsh_signed,
2618 ppc_emit_rsh_unsigned,
2619 ppc_emit_ext,
2620 ppc_emit_log_not,
2621 ppc_emit_bit_and,
2622 ppc_emit_bit_or,
2623 ppc_emit_bit_xor,
2624 ppc_emit_bit_not,
2625 ppc_emit_equal,
2626 ppc_emit_less_signed,
2627 ppc_emit_less_unsigned,
2628 ppc_emit_ref,
2629 ppc_emit_if_goto,
2630 ppc_emit_goto,
2631 ppc_write_goto_address,
2632 ppc_emit_const,
2633 ppc_emit_call,
2634 ppc_emit_reg,
2635 ppc_emit_pop,
2636 ppc_emit_stack_flush,
2637 ppc_emit_zero_ext,
2638 ppc_emit_swap,
2639 ppc_emit_stack_adjust,
2640 ppc_emit_int_call_1,
2641 ppc_emit_void_call_2,
2642 ppc_emit_eq_goto,
2643 ppc_emit_ne_goto,
2644 ppc_emit_lt_goto,
2645 ppc_emit_le_goto,
2646 ppc_emit_gt_goto,
2647 ppc_emit_ge_goto
2648};
2649
2650#ifdef __powerpc64__
2651
2652/*
2653
2654 Bytecode execution stack frame - 64-bit
2655
2656 | LR save area (SP + 16)
2657 | CR save area (SP + 8)
2658 SP' -> +- Back chain (SP + 0)
2659 | Save r31 for access saved arguments
2660 | Save r30 for bytecode stack pointer
2661 | Save r4 for incoming argument *value
2662 | Save r3 for incoming argument regs
2663 r30 -> +- Bytecode execution stack
2664 |
2665 | 64-byte (8 doublewords) at initial.
2666 | Expand stack as needed.
2667 |
2668 +-
2669 | Some padding for minimum stack frame.
2670 | 112 for ELFv1.
2671 SP +- Back-chain (SP')
2672
2673 initial frame size
2674 = 112 + (4 * 8) + 64
2675 = 208
2676
2677 r30 is the stack-pointer for bytecode machine.
2678 It should point to next-empty, so we can use LDU for pop.
2679 r3 is used for cache of TOP value.
2680 It was the first argument, pointer to regs.
2681 r4 is the second argument, pointer to the result.
2682 We should set *result = TOP after leaving this function.
2683
2684 Note:
2685 * To restore stack at epilogue
2686 => sp = r31
2687 * To check stack is big enough for bytecode execution.
2688 => r30 - 8 > SP + 112
2689 * To return execution result.
2690 => 0(r4) = TOP
2691
2692 */
2693
2694/* Emit prologue in inferior memory. See above comments. */
2695
2696static void
2697ppc64v1_emit_prologue (void)
2698{
2699 /* On ELFv1, function pointers really point to function descriptor,
2700 so emit one here. We don't care about contents of words 1 and 2,
2701 so let them just overlap out code. */
2702 uint64_t opd = current_insn_ptr + 8;
2703 uint32_t buf[2];
2704
2705 /* Mind the strict aliasing rules. */
2706 memcpy (buf, &opd, sizeof buf);
2707 emit_insns(buf, 2);
2708 EMIT_ASM (/* Save return address. */
2709 "mflr 0 \n"
2710 "std 0, 16(1) \n"
2711 /* Save r30 and incoming arguments. */
2712 "std 31, -8(1) \n"
2713 "std 30, -16(1) \n"
2714 "std 4, -24(1) \n"
2715 "std 3, -32(1) \n"
2716 /* Point r31 to current r1 for access arguments. */
2717 "mr 31, 1 \n"
2718 /* Adjust SP. 208 is the initial frame size. */
2719 "stdu 1, -208(1) \n"
2720 /* Set r30 to pointing stack-top. */
2721 "addi 30, 1, 168 \n"
2722 /* Initial r3/TOP to 0. */
2723 "li 3, 0 \n");
2724}
2725
2726/* Emit prologue in inferior memory. See above comments. */
2727
2728static void
2729ppc64v2_emit_prologue (void)
2730{
2731 EMIT_ASM (/* Save return address. */
2732 "mflr 0 \n"
2733 "std 0, 16(1) \n"
2734 /* Save r30 and incoming arguments. */
2735 "std 31, -8(1) \n"
2736 "std 30, -16(1) \n"
2737 "std 4, -24(1) \n"
2738 "std 3, -32(1) \n"
2739 /* Point r31 to current r1 for access arguments. */
2740 "mr 31, 1 \n"
2741 /* Adjust SP. 208 is the initial frame size. */
2742 "stdu 1, -208(1) \n"
2743 /* Set r30 to pointing stack-top. */
2744 "addi 30, 1, 168 \n"
2745 /* Initial r3/TOP to 0. */
2746 "li 3, 0 \n");
2747}
2748
2749/* Emit epilogue in inferior memory. See above comments. */
2750
2751static void
2752ppc64_emit_epilogue (void)
2753{
2754 EMIT_ASM (/* Restore SP. */
2755 "ld 1, 0(1) \n"
2756 /* *result = TOP */
2757 "ld 4, -24(1) \n"
2758 "std 3, 0(4) \n"
2759 /* Restore registers. */
2760 "ld 31, -8(1) \n"
2761 "ld 30, -16(1) \n"
2762 /* Restore LR. */
2763 "ld 0, 16(1) \n"
2764 /* Return 0 for no-error. */
2765 "li 3, 0 \n"
2766 "mtlr 0 \n"
2767 "blr \n");
2768}
2769
2770/* TOP = stack[--sp] + TOP */
2771
2772static void
2773ppc64_emit_add (void)
2774{
2775 EMIT_ASM ("ldu 4, 8(30) \n"
2776 "add 3, 4, 3 \n");
2777}
2778
2779/* TOP = stack[--sp] - TOP */
2780
2781static void
2782ppc64_emit_sub (void)
2783{
2784 EMIT_ASM ("ldu 4, 8(30) \n"
2785 "sub 3, 4, 3 \n");
2786}
2787
2788/* TOP = stack[--sp] * TOP */
2789
2790static void
2791ppc64_emit_mul (void)
2792{
2793 EMIT_ASM ("ldu 4, 8(30) \n"
2794 "mulld 3, 4, 3 \n");
2795}
2796
2797/* TOP = stack[--sp] << TOP */
2798
2799static void
2800ppc64_emit_lsh (void)
2801{
2802 EMIT_ASM ("ldu 4, 8(30) \n"
2803 "sld 3, 4, 3 \n");
2804}
2805
2806/* Top = stack[--sp] >> TOP
2807 (Arithmetic shift right) */
2808
2809static void
2810ppc64_emit_rsh_signed (void)
2811{
2812 EMIT_ASM ("ldu 4, 8(30) \n"
2813 "srad 3, 4, 3 \n");
2814}
2815
2816/* Top = stack[--sp] >> TOP
2817 (Logical shift right) */
2818
2819static void
2820ppc64_emit_rsh_unsigned (void)
2821{
2822 EMIT_ASM ("ldu 4, 8(30) \n"
2823 "srd 3, 4, 3 \n");
2824}
2825
2826/* Emit code for signed-extension specified by ARG. */
2827
2828static void
2829ppc64_emit_ext (int arg)
2830{
2831 switch (arg)
2832 {
2833 case 8:
2834 EMIT_ASM ("extsb 3, 3");
2835 break;
2836 case 16:
2837 EMIT_ASM ("extsh 3, 3");
2838 break;
2839 case 32:
2840 EMIT_ASM ("extsw 3, 3");
2841 break;
2842 default:
2843 emit_error = 1;
2844 }
2845}
2846
2847/* Emit code for zero-extension specified by ARG. */
2848
2849static void
2850ppc64_emit_zero_ext (int arg)
2851{
2852 switch (arg)
2853 {
2854 case 8:
2855 EMIT_ASM ("rldicl 3,3,0,56");
2856 break;
2857 case 16:
2858 EMIT_ASM ("rldicl 3,3,0,48");
2859 break;
2860 case 32:
2861 EMIT_ASM ("rldicl 3,3,0,32");
2862 break;
2863 default:
2864 emit_error = 1;
2865 }
2866}
2867
2868/* TOP = !TOP
2869 i.e., TOP = (TOP == 0) ? 1 : 0; */
2870
2871static void
2872ppc64_emit_log_not (void)
2873{
2874 EMIT_ASM ("cntlzd 3, 3 \n"
2875 "srdi 3, 3, 6 \n");
2876}
2877
2878/* TOP = stack[--sp] & TOP */
2879
2880static void
2881ppc64_emit_bit_and (void)
2882{
2883 EMIT_ASM ("ldu 4, 8(30) \n"
2884 "and 3, 4, 3 \n");
2885}
2886
2887/* TOP = stack[--sp] | TOP */
2888
2889static void
2890ppc64_emit_bit_or (void)
2891{
2892 EMIT_ASM ("ldu 4, 8(30) \n"
2893 "or 3, 4, 3 \n");
2894}
2895
2896/* TOP = stack[--sp] ^ TOP */
2897
2898static void
2899ppc64_emit_bit_xor (void)
2900{
2901 EMIT_ASM ("ldu 4, 8(30) \n"
2902 "xor 3, 4, 3 \n");
2903}
2904
2905/* TOP = ~TOP
2906 i.e., TOP = ~(TOP | TOP) */
2907
2908static void
2909ppc64_emit_bit_not (void)
2910{
2911 EMIT_ASM ("nor 3, 3, 3 \n");
2912}
2913
2914/* TOP = stack[--sp] == TOP */
2915
2916static void
2917ppc64_emit_equal (void)
2918{
2919 EMIT_ASM ("ldu 4, 8(30) \n"
2920 "xor 3, 3, 4 \n"
2921 "cntlzd 3, 3 \n"
2922 "srdi 3, 3, 6 \n");
2923}
2924
2925/* TOP = stack[--sp] < TOP
2926 (Signed comparison) */
2927
2928static void
2929ppc64_emit_less_signed (void)
2930{
2931 EMIT_ASM ("ldu 4, 8(30) \n"
2932 "cmpd 7, 4, 3 \n"
2933 "mfcr 3 \n"
2934 "rlwinm 3, 3, 29, 31, 31 \n");
2935}
2936
2937/* TOP = stack[--sp] < TOP
2938 (Unsigned comparison) */
2939
2940static void
2941ppc64_emit_less_unsigned (void)
2942{
2943 EMIT_ASM ("ldu 4, 8(30) \n"
2944 "cmpld 7, 4, 3 \n"
2945 "mfcr 3 \n"
2946 "rlwinm 3, 3, 29, 31, 31 \n");
2947}
2948
2949/* Access the memory address in TOP in size of SIZE.
2950 Zero-extend the read value. */
2951
2952static void
2953ppc64_emit_ref (int size)
2954{
2955 switch (size)
2956 {
2957 case 1:
2958 EMIT_ASM ("lbz 3, 0(3)");
2959 break;
2960 case 2:
2961 EMIT_ASM ("lhz 3, 0(3)");
2962 break;
2963 case 4:
2964 EMIT_ASM ("lwz 3, 0(3)");
2965 break;
2966 case 8:
2967 EMIT_ASM ("ld 3, 0(3)");
2968 break;
2969 }
2970}
2971
2972/* TOP = NUM */
2973
2974static void
2975ppc64_emit_const (LONGEST num)
2976{
2977 uint32_t buf[5];
2978 uint32_t *p = buf;
2979
2980 p += gen_limm (p, 3, num, 1);
2981
2982 emit_insns (buf, p - buf);
2983 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2984}
2985
2986/* Set TOP to the value of register REG by calling get_raw_reg function
2987 with two argument, collected buffer and register number. */
2988
2989static void
2990ppc64v1_emit_reg (int reg)
2991{
2992 uint32_t buf[15];
2993 uint32_t *p = buf;
2994
2995 /* fctx->regs is passed in r3 and then saved in 176(1). */
2996 p += GEN_LD (p, 3, 31, -32);
2997 p += GEN_LI (p, 4, reg);
2998 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2999 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
3000 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3001
3002 emit_insns (buf, p - buf);
3003 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3004}
3005
3006/* Likewise, for ELFv2. */
3007
3008static void
3009ppc64v2_emit_reg (int reg)
3010{
3011 uint32_t buf[12];
3012 uint32_t *p = buf;
3013
3014 /* fctx->regs is passed in r3 and then saved in 176(1). */
3015 p += GEN_LD (p, 3, 31, -32);
3016 p += GEN_LI (p, 4, reg);
3017 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3018 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
3019 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3020
3021 emit_insns (buf, p - buf);
3022 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3023}
3024
3025/* TOP = stack[--sp] */
3026
3027static void
3028ppc64_emit_pop (void)
3029{
3030 EMIT_ASM ("ldu 3, 8(30)");
3031}
3032
3033/* stack[sp++] = TOP
3034
3035 Because we may use up bytecode stack, expand 8 doublewords more
3036 if needed. */
3037
3038static void
3039ppc64_emit_stack_flush (void)
3040{
3041 /* Make sure bytecode stack is big enough before push.
3042 Otherwise, expand 64-byte more. */
3043
3044 EMIT_ASM (" std 3, 0(30) \n"
3045 " addi 4, 30, -(112 + 8) \n"
3046 " cmpd 7, 4, 1 \n"
3047 " bgt 7, 1f \n"
3048 " stdu 31, -64(1) \n"
3049 "1:addi 30, 30, -8 \n");
3050}
3051
3052/* Swap TOP and stack[sp-1] */
3053
3054static void
3055ppc64_emit_swap (void)
3056{
3057 EMIT_ASM ("ld 4, 8(30) \n"
3058 "std 3, 8(30) \n"
3059 "mr 3, 4 \n");
3060}
3061
3062/* Call function FN - ELFv1. */
3063
3064static void
3065ppc64v1_emit_call (CORE_ADDR fn)
3066{
3067 uint32_t buf[13];
3068 uint32_t *p = buf;
3069
3070 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3071 p += gen_call (p, fn, 1, 1);
3072 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3073
3074 emit_insns (buf, p - buf);
3075 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3076}
3077
3078/* Call function FN - ELFv2. */
3079
3080static void
3081ppc64v2_emit_call (CORE_ADDR fn)
3082{
3083 uint32_t buf[10];
3084 uint32_t *p = buf;
3085
3086 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3087 p += gen_call (p, fn, 1, 0);
3088 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3089
3090 emit_insns (buf, p - buf);
3091 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3092}
3093
3094/* FN's prototype is `LONGEST(*fn)(int)'.
3095 TOP = fn (arg1)
3096 */
3097
3098static void
3099ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
3100{
3101 uint32_t buf[13];
3102 uint32_t *p = buf;
3103
3104 /* Setup argument. arg1 is a 16-bit value. */
3105 p += gen_limm (p, 3, arg1, 1);
3106 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3107 p += gen_call (p, fn, 1, 1);
3108 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3109
3110 emit_insns (buf, p - buf);
3111 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3112}
3113
3114/* Likewise for ELFv2. */
3115
3116static void
3117ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
3118{
3119 uint32_t buf[10];
3120 uint32_t *p = buf;
3121
3122 /* Setup argument. arg1 is a 16-bit value. */
3123 p += gen_limm (p, 3, arg1, 1);
3124 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3125 p += gen_call (p, fn, 1, 0);
3126 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3127
3128 emit_insns (buf, p - buf);
3129 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3130}
3131
3132/* FN's prototype is `void(*fn)(int,LONGEST)'.
3133 fn (arg1, TOP)
3134
3135 TOP should be preserved/restored before/after the call. */
3136
3137static void
3138ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
3139{
3140 uint32_t buf[17];
3141 uint32_t *p = buf;
3142
3143 /* Save TOP. 0(30) is next-empty. */
3144 p += GEN_STD (p, 3, 30, 0);
3145
3146 /* Setup argument. arg1 is a 16-bit value. */
3147 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3148 p += gen_limm (p, 3, arg1, 1);
3149 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3150 p += gen_call (p, fn, 1, 1);
3151 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3152
3153 /* Restore TOP */
3154 p += GEN_LD (p, 3, 30, 0);
3155
3156 emit_insns (buf, p - buf);
3157 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3158}
3159
3160/* Likewise for ELFv2. */
3161
3162static void
3163ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
3164{
3165 uint32_t buf[14];
3166 uint32_t *p = buf;
3167
3168 /* Save TOP. 0(30) is next-empty. */
3169 p += GEN_STD (p, 3, 30, 0);
3170
3171 /* Setup argument. arg1 is a 16-bit value. */
3172 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3173 p += gen_limm (p, 3, arg1, 1);
3174 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3175 p += gen_call (p, fn, 1, 0);
3176 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3177
3178 /* Restore TOP */
3179 p += GEN_LD (p, 3, 30, 0);
3180
3181 emit_insns (buf, p - buf);
3182 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3183}
3184
3185/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3186
3187static void
3188ppc64_emit_if_goto (int *offset_p, int *size_p)
3189{
3190 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3191 "ldu 3, 8(30) \n"
3192 "1:bne 7, 1b \n");
3193
3194 if (offset_p)
3195 *offset_p = 8;
3196 if (size_p)
3197 *size_p = 14;
3198}
3199
3200/* Goto if stack[--sp] == TOP */
3201
3202static void
3203ppc64_emit_eq_goto (int *offset_p, int *size_p)
3204{
3205 EMIT_ASM ("ldu 4, 8(30) \n"
3206 "cmpd 7, 4, 3 \n"
3207 "ldu 3, 8(30) \n"
3208 "1:beq 7, 1b \n");
3209
3210 if (offset_p)
3211 *offset_p = 12;
3212 if (size_p)
3213 *size_p = 14;
3214}
3215
3216/* Goto if stack[--sp] != TOP */
3217
3218static void
3219ppc64_emit_ne_goto (int *offset_p, int *size_p)
3220{
3221 EMIT_ASM ("ldu 4, 8(30) \n"
3222 "cmpd 7, 4, 3 \n"
3223 "ldu 3, 8(30) \n"
3224 "1:bne 7, 1b \n");
3225
3226 if (offset_p)
3227 *offset_p = 12;
3228 if (size_p)
3229 *size_p = 14;
3230}
3231
3232/* Goto if stack[--sp] < TOP */
3233
3234static void
3235ppc64_emit_lt_goto (int *offset_p, int *size_p)
3236{
3237 EMIT_ASM ("ldu 4, 8(30) \n"
3238 "cmpd 7, 4, 3 \n"
3239 "ldu 3, 8(30) \n"
3240 "1:blt 7, 1b \n");
3241
3242 if (offset_p)
3243 *offset_p = 12;
3244 if (size_p)
3245 *size_p = 14;
3246}
3247
3248/* Goto if stack[--sp] <= TOP */
3249
3250static void
3251ppc64_emit_le_goto (int *offset_p, int *size_p)
3252{
3253 EMIT_ASM ("ldu 4, 8(30) \n"
3254 "cmpd 7, 4, 3 \n"
3255 "ldu 3, 8(30) \n"
3256 "1:ble 7, 1b \n");
3257
3258 if (offset_p)
3259 *offset_p = 12;
3260 if (size_p)
3261 *size_p = 14;
3262}
3263
3264/* Goto if stack[--sp] > TOP */
3265
3266static void
3267ppc64_emit_gt_goto (int *offset_p, int *size_p)
3268{
3269 EMIT_ASM ("ldu 4, 8(30) \n"
3270 "cmpd 7, 4, 3 \n"
3271 "ldu 3, 8(30) \n"
3272 "1:bgt 7, 1b \n");
3273
3274 if (offset_p)
3275 *offset_p = 12;
3276 if (size_p)
3277 *size_p = 14;
3278}
3279
3280/* Goto if stack[--sp] >= TOP */
3281
3282static void
3283ppc64_emit_ge_goto (int *offset_p, int *size_p)
3284{
3285 EMIT_ASM ("ldu 4, 8(30) \n"
3286 "cmpd 7, 4, 3 \n"
3287 "ldu 3, 8(30) \n"
3288 "1:bge 7, 1b \n");
3289
3290 if (offset_p)
3291 *offset_p = 12;
3292 if (size_p)
3293 *size_p = 14;
3294}
3295
3296/* Table of emit ops for 64-bit ELFv1. */
3297
3298static struct emit_ops ppc64v1_emit_ops_impl =
3299{
3300 ppc64v1_emit_prologue,
3301 ppc64_emit_epilogue,
3302 ppc64_emit_add,
3303 ppc64_emit_sub,
3304 ppc64_emit_mul,
3305 ppc64_emit_lsh,
3306 ppc64_emit_rsh_signed,
3307 ppc64_emit_rsh_unsigned,
3308 ppc64_emit_ext,
3309 ppc64_emit_log_not,
3310 ppc64_emit_bit_and,
3311 ppc64_emit_bit_or,
3312 ppc64_emit_bit_xor,
3313 ppc64_emit_bit_not,
3314 ppc64_emit_equal,
3315 ppc64_emit_less_signed,
3316 ppc64_emit_less_unsigned,
3317 ppc64_emit_ref,
3318 ppc64_emit_if_goto,
3319 ppc_emit_goto,
3320 ppc_write_goto_address,
3321 ppc64_emit_const,
3322 ppc64v1_emit_call,
3323 ppc64v1_emit_reg,
3324 ppc64_emit_pop,
3325 ppc64_emit_stack_flush,
3326 ppc64_emit_zero_ext,
3327 ppc64_emit_swap,
3328 ppc_emit_stack_adjust,
3329 ppc64v1_emit_int_call_1,
3330 ppc64v1_emit_void_call_2,
3331 ppc64_emit_eq_goto,
3332 ppc64_emit_ne_goto,
3333 ppc64_emit_lt_goto,
3334 ppc64_emit_le_goto,
3335 ppc64_emit_gt_goto,
3336 ppc64_emit_ge_goto
3337};
3338
3339/* Table of emit ops for 64-bit ELFv2. */
3340
3341static struct emit_ops ppc64v2_emit_ops_impl =
3342{
3343 ppc64v2_emit_prologue,
3344 ppc64_emit_epilogue,
3345 ppc64_emit_add,
3346 ppc64_emit_sub,
3347 ppc64_emit_mul,
3348 ppc64_emit_lsh,
3349 ppc64_emit_rsh_signed,
3350 ppc64_emit_rsh_unsigned,
3351 ppc64_emit_ext,
3352 ppc64_emit_log_not,
3353 ppc64_emit_bit_and,
3354 ppc64_emit_bit_or,
3355 ppc64_emit_bit_xor,
3356 ppc64_emit_bit_not,
3357 ppc64_emit_equal,
3358 ppc64_emit_less_signed,
3359 ppc64_emit_less_unsigned,
3360 ppc64_emit_ref,
3361 ppc64_emit_if_goto,
3362 ppc_emit_goto,
3363 ppc_write_goto_address,
3364 ppc64_emit_const,
3365 ppc64v2_emit_call,
3366 ppc64v2_emit_reg,
3367 ppc64_emit_pop,
3368 ppc64_emit_stack_flush,
3369 ppc64_emit_zero_ext,
3370 ppc64_emit_swap,
3371 ppc_emit_stack_adjust,
3372 ppc64v2_emit_int_call_1,
3373 ppc64v2_emit_void_call_2,
3374 ppc64_emit_eq_goto,
3375 ppc64_emit_ne_goto,
3376 ppc64_emit_lt_goto,
3377 ppc64_emit_le_goto,
3378 ppc64_emit_gt_goto,
3379 ppc64_emit_ge_goto
3380};
3381
3382#endif
3383
ab64c999 3384/* Implementation of target ops method "emit_ops". */
14e2b6d9 3385
ab64c999
TBA		 3386emit_ops *
3387ppc_target::emit_ops ()
14e2b6d9
MK		 3388{
3389#ifdef __powerpc64__
3390 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3391
3392 if (register_size (regcache->tdesc, 0) == 8)
3393 {
3394 if (is_elfv2_inferior ())
3395 return &ppc64v2_emit_ops_impl;
3396 else
3397 return &ppc64v1_emit_ops_impl;
3398 }
3399#endif
3400 return &ppc_emit_ops_impl;
3401}
3402
a2174ba4
MK		 3403/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3404
3405static int
3406ppc_get_ipa_tdesc_idx (void)
3407{
3408 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3409 const struct target_desc *tdesc = regcache->tdesc;
3410
3411#ifdef __powerpc64__
3412 if (tdesc == tdesc_powerpc_64l)
3413 return PPC_TDESC_BASE;
3414 if (tdesc == tdesc_powerpc_altivec64l)
3415 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3416 if (tdesc == tdesc_powerpc_vsx64l)
3417 return PPC_TDESC_VSX;
3418 if (tdesc == tdesc_powerpc_isa205_64l)
3419 return PPC_TDESC_ISA205;
3420 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3421 return PPC_TDESC_ISA205_ALTIVEC;
3422 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3423 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3424 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3425 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3426 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3427 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3428 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
3429 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3430#endif
3431
3432 if (tdesc == tdesc_powerpc_32l)
3433 return PPC_TDESC_BASE;
3434 if (tdesc == tdesc_powerpc_altivec32l)
3435 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3436 if (tdesc == tdesc_powerpc_vsx32l)
3437 return PPC_TDESC_VSX;
3438 if (tdesc == tdesc_powerpc_isa205_32l)
3439 return PPC_TDESC_ISA205;
3440 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3441 return PPC_TDESC_ISA205_ALTIVEC;
3442 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3443 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3444 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3445 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3446 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3447 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3448 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
3449 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3450 if (tdesc == tdesc_powerpc_e500l)
3451 return PPC_TDESC_E500;
3452
3453 return 0;
3454}
3455
2ec06d2e 3456struct linux_target_ops the_low_target = {
7d00775e 3457 NULL, /* supports_range_stepping */
7d00775e 3458 ppc_supports_hardware_single_step,
a2174ba4
MK		 3459 NULL, /* get_syscall_trapinfo */
3460 ppc_get_ipa_tdesc_idx,
2ec06d2e 3461};
3aee8918 3462
ef0478f6
TBA		 3463/* The linux target ops object. */
3464
3465linux_process_target *the_linux_target = &the_ppc_target;
3466
3aee8918
PA		 3467void
3468initialize_low_arch (void)
3469{
3470 /* Initialize the Linux target descriptions. */
3471
3472 init_registers_powerpc_32l ();
3473 init_registers_powerpc_altivec32l ();
3aee8918
PA		 3474 init_registers_powerpc_vsx32l ();
3475 init_registers_powerpc_isa205_32l ();
3476 init_registers_powerpc_isa205_altivec32l ();
3477 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3478 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3479 init_registers_powerpc_isa207_vsx32l ();
8d619c01 3480 init_registers_powerpc_isa207_htm_vsx32l ();
3aee8918 3481 init_registers_powerpc_e500l ();
a2174ba4 3482#if __powerpc64__
3aee8918
PA		 3483 init_registers_powerpc_64l ();
3484 init_registers_powerpc_altivec64l ();
3aee8918
PA		 3485 init_registers_powerpc_vsx64l ();
3486 init_registers_powerpc_isa205_64l ();
3487 init_registers_powerpc_isa205_altivec64l ();
3488 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3489 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3490 init_registers_powerpc_isa207_vsx64l ();
8d619c01 3491 init_registers_powerpc_isa207_htm_vsx64l ();
a2174ba4 3492#endif
3aee8918
PA		 3493
3494 initialize_regsets_info (&ppc_regsets_info);
3495}
GDB Binutils - Deliverables
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