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gdbserver/linux-low: start turning linux target ops into methods
[deliverable/binutils-gdb.git] / gdbserver / linux-ppc-low.cc
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
b811d2c2 3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
64f57f3d 31#include "nat/linux-ptrace.h"
bd64614e 32#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 33#include "ax.h"
34#include "tracepoint.h"
35
36#define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38#define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 46
ef0478f6
TBA		 47/* Linux target op definitions for the PowerPC architecture. */
48
49class ppc_target : public linux_process_target
50{
51public:
52
53};
54
55/* The singleton target ops object. */
56
57static ppc_target the_ppc_target;
58
7ca18ed6
EBM		 59/* Holds the AT_HWCAP auxv entry. */
60
b6430ec3
UW		 61static unsigned long ppc_hwcap;
62
7ca18ed6
EBM		 63/* Holds the AT_HWCAP2 auxv entry. */
64
65static unsigned long ppc_hwcap2;
66
b6430ec3 67
7284e1be
UW		 68#define ppc_num_regs 73
69
5b0a002e
UW		 70#ifdef __powerpc64__
71/* We use a constant for FPSCR instead of PT_FPSCR, because
72 many shipped PPC64 kernels had the wrong value in ptrace.h. */
73static int ppc_regmap[] =
74 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
75 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
76 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
77 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
78 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
79 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
80 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
81 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
82 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
83 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
84 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
85 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
86 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
87 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
88 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
89 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
90 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 91 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
92 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 93#else
0a30fbc4 94/* Currently, don't check/send MQ. */
2ec06d2e 95static int ppc_regmap[] =
0a30fbc4
DJ		 96 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
97 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
98 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
99 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
100 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
101 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
102 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
103 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
104 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
105 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
106 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
107 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
108 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
109 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
110 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
111 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
112 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 113 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
114 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 115 };
116
117static int ppc_regmap_e500[] =
118 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
119 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
120 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
121 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
122 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
123 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
124 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
125 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
126 -1, -1, -1, -1,
127 -1, -1, -1, -1,
128 -1, -1, -1, -1,
129 -1, -1, -1, -1,
130 -1, -1, -1, -1,
131 -1, -1, -1, -1,
132 -1, -1, -1, -1,
133 -1, -1, -1, -1,
134 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 135 PT_CTR * 4, PT_XER * 4, -1,
136 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 137 };
5b0a002e 138#endif
0a30fbc4 139
7ca18ed6
EBM		 140/* Check whether the kernel provides a register set with number
141 REGSET_ID of size REGSETSIZE for process/thread TID. */
142
143static int
144ppc_check_regset (int tid, int regset_id, int regsetsize)
145{
146 void *buf = alloca (regsetsize);
147 struct iovec iov;
148
149 iov.iov_base = buf;
150 iov.iov_len = regsetsize;
151
152 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
153 || errno == ENODATA)
154 return 1;
155 return 0;
156}
157
2ec06d2e
DJ		 158static int
159ppc_cannot_store_register (int regno)
0a30fbc4 160{
3aee8918
PA		 161 const struct target_desc *tdesc = current_process ()->tdesc;
162
b6430ec3 163#ifndef __powerpc64__
bc1e36ca 164 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 165 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
166 && regno == find_regno (tdesc, "fpscr"))
a5863204 167 return 1;
30ed0a8f 168#endif
bc1e36ca 169
7284e1be 170 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 171 if (regno == find_regno (tdesc, "orig_r3")
172 || regno == find_regno (tdesc, "trap"))
a5863204 173 return 1;
7284e1be 174
0a30fbc4
DJ		 175 return 0;
176}
177
2ec06d2e
DJ		 178static int
179ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 180{
181 return 0;
182}
183
5b0a002e 184static void
442ea881 185ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 186{
76b233dd
UW		 187 memset (buf, 0, sizeof (long));
188
2e4bb98a
EBM		 189 if (__BYTE_ORDER == __LITTLE_ENDIAN)
190 {
191 /* Little-endian values always sit at the left end of the buffer. */
192 collect_register (regcache, regno, buf);
193 }
194 else if (__BYTE_ORDER == __BIG_ENDIAN)
195 {
196 /* Big-endian values sit at the right end of the buffer. In case of
197 registers whose sizes are smaller than sizeof (long), we must use a
198 padding to access them correctly. */
199 int size = register_size (regcache->tdesc, regno);
200
201 if (size < sizeof (long))
202 collect_register (regcache, regno, buf + sizeof (long) - size);
203 else
204 collect_register (regcache, regno, buf);
205 }
5b0a002e 206 else
2e4bb98a 207 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 208}
209
210static void
442ea881
PA		 211ppc_supply_ptrace_register (struct regcache *regcache,
212 int regno, const char *buf)
5b0a002e 213{
2e4bb98a
EBM		 214 if (__BYTE_ORDER == __LITTLE_ENDIAN)
215 {
216 /* Little-endian values always sit at the left end of the buffer. */
217 supply_register (regcache, regno, buf);
218 }
219 else if (__BYTE_ORDER == __BIG_ENDIAN)
220 {
221 /* Big-endian values sit at the right end of the buffer. In case of
222 registers whose sizes are smaller than sizeof (long), we must use a
223 padding to access them correctly. */
224 int size = register_size (regcache->tdesc, regno);
225
226 if (size < sizeof (long))
227 supply_register (regcache, regno, buf + sizeof (long) - size);
228 else
229 supply_register (regcache, regno, buf);
230 }
5b0a002e 231 else
2e4bb98a 232 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 233}
234
0d62e5e8 235static CORE_ADDR
442ea881 236ppc_get_pc (struct regcache *regcache)
0d62e5e8 237{
abf516c6 238 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 239 {
240 unsigned int pc;
442ea881 241 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 242 return (CORE_ADDR) pc;
243 }
244 else
245 {
246 unsigned long pc;
442ea881 247 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 248 return (CORE_ADDR) pc;
249 }
0d62e5e8
DJ		 250}
251
252static void
442ea881 253ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 254{
abf516c6 255 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 256 {
257 unsigned int newpc = pc;
442ea881 258 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 259 }
260 else
261 {
262 unsigned long newpc = pc;
442ea881 263 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 264 }
265}
266
3aee8918
PA		 267#ifndef __powerpc64__
268static int ppc_regmap_adjusted;
269#endif
270
0d62e5e8 271
5b0a002e 272/* Correct in either endianness.
0d62e5e8
DJ		 273 This instruction is "twge r2, r2", which GDB uses as a software
274 breakpoint. */
5b0a002e 275static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 276#define ppc_breakpoint_len 4
277
dd373349
AT		 278/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
279
280static const gdb_byte *
281ppc_sw_breakpoint_from_kind (int kind, int *size)
282{
283 *size = ppc_breakpoint_len;
284 return (const gdb_byte *) &ppc_breakpoint;
285}
286
0d62e5e8
DJ		 287static int
288ppc_breakpoint_at (CORE_ADDR where)
289{
5b0a002e 290 unsigned int insn;
0d62e5e8 291
52405d85 292 the_target->read_memory (where, (unsigned char *) &insn, 4);
abf516c6
UW		 293 if (insn == ppc_breakpoint)
294 return 1;
295 /* If necessary, recognize more trap instructions here. GDB only uses
296 the one. */
0b9ff2c0 297
0d62e5e8
DJ		 298 return 0;
299}
300
657f9cde
WW		 301/* Implement supports_z_point_type target-ops.
302 Returns true if type Z_TYPE breakpoint is supported.
303
304 Handling software breakpoint at server side, so tracepoints
305 and breakpoints can be inserted at the same location. */
306
307static int
308ppc_supports_z_point_type (char z_type)
309{
310 switch (z_type)
311 {
312 case Z_PACKET_SW_BP:
313 return 1;
314 case Z_PACKET_HW_BP:
315 case Z_PACKET_WRITE_WP:
316 case Z_PACKET_ACCESS_WP:
317 default:
318 return 0;
319 }
320}
321
322/* Implement insert_point target-ops.
323 Returns 0 on success, -1 on failure and 1 on unsupported. */
324
325static int
326ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
327 int size, struct raw_breakpoint *bp)
328{
329 switch (type)
330 {
331 case raw_bkpt_type_sw:
332 return insert_memory_breakpoint (bp);
333
334 case raw_bkpt_type_hw:
335 case raw_bkpt_type_write_wp:
336 case raw_bkpt_type_access_wp:
337 default:
338 /* Unsupported. */
339 return 1;
340 }
341}
342
343/* Implement remove_point target-ops.
344 Returns 0 on success, -1 on failure and 1 on unsupported. */
345
346static int
347ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
348 int size, struct raw_breakpoint *bp)
349{
350 switch (type)
351 {
352 case raw_bkpt_type_sw:
353 return remove_memory_breakpoint (bp);
354
355 case raw_bkpt_type_hw:
356 case raw_bkpt_type_write_wp:
357 case raw_bkpt_type_access_wp:
358 default:
359 /* Unsupported. */
360 return 1;
361 }
362}
363
e9d25b98
DJ		 364/* Provide only a fill function for the general register set. ps_lgetregs
365 will use this for NPTL support. */
366
442ea881 367static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 368{
369 int i;
370
371 for (i = 0; i < 32; i++)
442ea881 372 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 373
374 for (i = 64; i < 70; i++)
442ea881 375 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 376
377 for (i = 71; i < 73; i++)
442ea881 378 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 379}
380
7ca18ed6
EBM		 381/* Program Priority Register regset fill function. */
382
383static void
384ppc_fill_pprregset (struct regcache *regcache, void *buf)
385{
386 char *ppr = (char *) buf;
387
388 collect_register_by_name (regcache, "ppr", ppr);
389}
390
391/* Program Priority Register regset store function. */
392
393static void
394ppc_store_pprregset (struct regcache *regcache, const void *buf)
395{
396 const char *ppr = (const char *) buf;
397
398 supply_register_by_name (regcache, "ppr", ppr);
399}
400
401/* Data Stream Control Register regset fill function. */
402
403static void
404ppc_fill_dscrregset (struct regcache *regcache, void *buf)
405{
406 char *dscr = (char *) buf;
407
408 collect_register_by_name (regcache, "dscr", dscr);
409}
410
411/* Data Stream Control Register regset store function. */
412
413static void
414ppc_store_dscrregset (struct regcache *regcache, const void *buf)
415{
416 const char *dscr = (const char *) buf;
417
418 supply_register_by_name (regcache, "dscr", dscr);
419}
420
f2cf6173
EBM		 421/* Target Address Register regset fill function. */
422
423static void
424ppc_fill_tarregset (struct regcache *regcache, void *buf)
425{
426 char *tar = (char *) buf;
427
428 collect_register_by_name (regcache, "tar", tar);
429}
430
431/* Target Address Register regset store function. */
432
433static void
434ppc_store_tarregset (struct regcache *regcache, const void *buf)
435{
436 const char *tar = (const char *) buf;
437
438 supply_register_by_name (regcache, "tar", tar);
439}
440
232bfb86
EBM		 441/* Event-Based Branching regset store function. Unless the inferior
442 has a perf event open, ptrace can return in error when reading and
443 writing to the regset, with ENODATA. For reading, the registers
444 will correctly show as unavailable. For writing, gdbserver
445 currently only caches any register writes from P and G packets and
446 the stub always tries to write all the regsets when resuming the
447 inferior, which would result in frequent warnings. For this
448 reason, we don't define a fill function. This also means that the
449 client-side regcache will be dirty if the user tries to write to
450 the EBB registers. G packets that the client sends to write to
451 unrelated registers will also include data for EBB registers, even
452 if they are unavailable. */
453
454static void
455ppc_store_ebbregset (struct regcache *regcache, const void *buf)
456{
457 const char *regset = (const char *) buf;
458
459 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
460 .dat file is BESCR, EBBHR, EBBRR. */
461 supply_register_by_name (regcache, "ebbrr", &regset[0]);
462 supply_register_by_name (regcache, "ebbhr", &regset[8]);
463 supply_register_by_name (regcache, "bescr", &regset[16]);
464}
465
466/* Performance Monitoring Unit regset fill function. */
467
468static void
469ppc_fill_pmuregset (struct regcache *regcache, void *buf)
470{
471 char *regset = (char *) buf;
472
473 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
474 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
475 collect_register_by_name (regcache, "siar", &regset[0]);
476 collect_register_by_name (regcache, "sdar", &regset[8]);
477 collect_register_by_name (regcache, "sier", &regset[16]);
478 collect_register_by_name (regcache, "mmcr2", &regset[24]);
479 collect_register_by_name (regcache, "mmcr0", &regset[32]);
480}
481
482/* Performance Monitoring Unit regset store function. */
483
484static void
485ppc_store_pmuregset (struct regcache *regcache, const void *buf)
486{
487 const char *regset = (const char *) buf;
488
489 supply_register_by_name (regcache, "siar", &regset[0]);
490 supply_register_by_name (regcache, "sdar", &regset[8]);
491 supply_register_by_name (regcache, "sier", &regset[16]);
492 supply_register_by_name (regcache, "mmcr2", &regset[24]);
493 supply_register_by_name (regcache, "mmcr0", &regset[32]);
494}
495
8d619c01
EBM		 496/* Hardware Transactional Memory special-purpose register regset fill
497 function. */
498
499static void
500ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
501{
502 int i, base;
503 char *regset = (char *) buf;
504
505 base = find_regno (regcache->tdesc, "tfhar");
506 for (i = 0; i < 3; i++)
507 collect_register (regcache, base + i, &regset[i * 8]);
508}
509
510/* Hardware Transactional Memory special-purpose register regset store
511 function. */
512
513static void
514ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
515{
516 int i, base;
517 const char *regset = (const char *) buf;
518
519 base = find_regno (regcache->tdesc, "tfhar");
520 for (i = 0; i < 3; i++)
521 supply_register (regcache, base + i, &regset[i * 8]);
522}
523
524/* For the same reasons as the EBB regset, none of the HTM
525 checkpointed regsets have a fill function. These registers are
526 only available if the inferior is in a transaction. */
527
528/* Hardware Transactional Memory checkpointed general-purpose regset
529 store function. */
530
531static void
532ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
533{
534 int i, base, size, endian_offset;
535 const char *regset = (const char *) buf;
536
537 base = find_regno (regcache->tdesc, "cr0");
538 size = register_size (regcache->tdesc, base);
539
540 gdb_assert (size == 4 || size == 8);
541
542 for (i = 0; i < 32; i++)
543 supply_register (regcache, base + i, &regset[i * size]);
544
545 endian_offset = 0;
546
547 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
548 endian_offset = 4;
549
550 supply_register_by_name (regcache, "ccr",
551 &regset[PT_CCR * size + endian_offset]);
552
553 supply_register_by_name (regcache, "cxer",
554 &regset[PT_XER * size + endian_offset]);
555
556 supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
557 supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
558}
559
560/* Hardware Transactional Memory checkpointed floating-point regset
561 store function. */
562
563static void
564ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
565{
566 int i, base;
567 const char *regset = (const char *) buf;
568
569 base = find_regno (regcache->tdesc, "cf0");
570
571 for (i = 0; i < 32; i++)
572 supply_register (regcache, base + i, &regset[i * 8]);
573
574 supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
575}
576
577/* Hardware Transactional Memory checkpointed vector regset store
578 function. */
579
580static void
581ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
582{
583 int i, base;
584 const char *regset = (const char *) buf;
585 int vscr_offset = 0;
586
587 base = find_regno (regcache->tdesc, "cvr0");
588
589 for (i = 0; i < 32; i++)
590 supply_register (regcache, base + i, &regset[i * 16]);
591
592 if (__BYTE_ORDER == __BIG_ENDIAN)
593 vscr_offset = 12;
594
595 supply_register_by_name (regcache, "cvscr",
596 &regset[32 * 16 + vscr_offset]);
597
598 supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
599}
600
601/* Hardware Transactional Memory checkpointed vector-scalar regset
602 store function. */
603
604static void
605ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
606{
607 int i, base;
608 const char *regset = (const char *) buf;
609
610 base = find_regno (regcache->tdesc, "cvs0h");
611 for (i = 0; i < 32; i++)
612 supply_register (regcache, base + i, &regset[i * 8]);
613}
614
615/* Hardware Transactional Memory checkpointed Program Priority
616 Register regset store function. */
617
618static void
619ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
620{
621 const char *cppr = (const char *) buf;
622
623 supply_register_by_name (regcache, "cppr", cppr);
624}
625
626/* Hardware Transactional Memory checkpointed Data Stream Control
627 Register regset store function. */
628
629static void
630ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
631{
632 const char *cdscr = (const char *) buf;
633
634 supply_register_by_name (regcache, "cdscr", cdscr);
635}
636
637/* Hardware Transactional Memory checkpointed Target Address Register
638 regset store function. */
639
640static void
641ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
642{
643 const char *ctar = (const char *) buf;
644
645 supply_register_by_name (regcache, "ctar", ctar);
646}
647
677c5bb1 648static void
442ea881 649ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 650{
651 int i, base;
2bc84e8a 652 char *regset = (char *) buf;
677c5bb1 653
3aee8918 654 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 655 for (i = 0; i < 32; i++)
442ea881 656 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 657}
658
659static void
442ea881 660ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 661{
662 int i, base;
2bc84e8a 663 const char *regset = (const char *) buf;
677c5bb1 664
3aee8918 665 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 666 for (i = 0; i < 32; i++)
442ea881 667 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 668}
669
30ed0a8f 670static void
442ea881 671ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 672{
673 int i, base;
2bc84e8a 674 char *regset = (char *) buf;
1d75a658 675 int vscr_offset = 0;
30ed0a8f 676
3aee8918 677 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 678 for (i = 0; i < 32; i++)
442ea881 679 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 680
1d75a658
PFC		 681 if (__BYTE_ORDER == __BIG_ENDIAN)
682 vscr_offset = 12;
683
1d75a658
PFC		 684 collect_register_by_name (regcache, "vscr",
685 &regset[32 * 16 + vscr_offset]);
686
442ea881 687 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 688}
689
690static void
442ea881 691ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 692{
693 int i, base;
2bc84e8a 694 const char *regset = (const char *) buf;
1d75a658 695 int vscr_offset = 0;
30ed0a8f 696
3aee8918 697 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 698 for (i = 0; i < 32; i++)
442ea881 699 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 700
1d75a658
PFC		 701 if (__BYTE_ORDER == __BIG_ENDIAN)
702 vscr_offset = 12;
703
704 supply_register_by_name (regcache, "vscr",
705 &regset[32 * 16 + vscr_offset]);
442ea881 706 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 707}
708
30ed0a8f
DJ		 709struct gdb_evrregset_t
710{
711 unsigned long evr[32];
712 unsigned long long acc;
713 unsigned long spefscr;
714};
715
716static void
442ea881 717ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 718{
719 int i, ev0;
2bc84e8a 720 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 721
3aee8918 722 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 723 for (i = 0; i < 32; i++)
442ea881 724 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 725
442ea881
PA		 726 collect_register_by_name (regcache, "acc", &regset->acc);
727 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 728}
729
730static void
442ea881 731ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 732{
733 int i, ev0;
2bc84e8a 734 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 735
3aee8918 736 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 737 for (i = 0; i < 32; i++)
442ea881 738 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 739
442ea881
PA		 740 supply_register_by_name (regcache, "acc", &regset->acc);
741 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 742}
30ed0a8f 743
7d00775e
AT		 744/* Support for hardware single step. */
745
746static int
747ppc_supports_hardware_single_step (void)
748{
749 return 1;
750}
751
3aee8918 752static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 753 /* List the extra register sets before GENERAL_REGS. That way we will
754 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
755 general registers. Some kernels support these, but not the newer
756 PPC_PTRACE_GETREGS. */
8d619c01
EBM		 757 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
758 NULL, ppc_store_tm_ctarregset },
759 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
760 NULL, ppc_store_tm_cdscrregset },
761 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
762 NULL, ppc_store_tm_cpprregset },
763 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
764 NULL, ppc_store_tm_cvsxregset },
765 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
766 NULL, ppc_store_tm_cvrregset },
767 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
768 NULL, ppc_store_tm_cfprregset },
769 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
770 NULL, ppc_store_tm_cgprregset },
771 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
772 ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
232bfb86
EBM		 773 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
774 NULL, ppc_store_ebbregset },
775 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
776 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 777 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
778 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 779 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
780 ppc_fill_pprregset, ppc_store_pprregset },
781 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
782 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 783 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 784 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 785 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 786 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 787 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 788 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 789 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 790 NULL_REGSET
e9d25b98
DJ		 791};
792
3aee8918
PA		 793static struct usrregs_info ppc_usrregs_info =
794 {
795 ppc_num_regs,
796 ppc_regmap,
797 };
798
799static struct regsets_info ppc_regsets_info =
800 {
801 ppc_regsets, /* regsets */
802 0, /* num_regsets */
803 NULL, /* disabled_regsets */
804 };
805
806static struct regs_info regs_info =
807 {
808 NULL, /* regset_bitmap */
809 &ppc_usrregs_info,
810 &ppc_regsets_info
811 };
812
813static const struct regs_info *
814ppc_regs_info (void)
815{
816 return &regs_info;
817}
818
e6c5bb05
SM		 819static void
820ppc_arch_setup (void)
821{
822 const struct target_desc *tdesc;
7273b5fc 823 struct regset_info *regset;
bd64614e 824 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 825
2e077f5e 826 int tid = lwpid_of (current_thread);
bd64614e 827
2e077f5e 828 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 829
bd64614e 830 if (features.wordsize == 4)
bd64614e 831 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 832 else
833 tdesc = tdesc_powerpc_64l;
834
835 current_process ()->tdesc = tdesc;
e6c5bb05 836
bd64614e
PFC		 837 /* The value of current_process ()->tdesc needs to be set for this
838 call. */
974c89e0
AH		 839 ppc_hwcap = linux_get_hwcap (features.wordsize);
840 ppc_hwcap2 = linux_get_hwcap2 (features.wordsize);
bd64614e
PFC		 841
842 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
843
844 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
845 features.vsx = true;
846
847 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
848 features.altivec = true;
849
7ca18ed6
EBM		 850 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
851 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
852 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 853 {
854 features.ppr_dscr = true;
855 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
856 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 857 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 858 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 859 PPC_LINUX_SIZEOF_TARREGSET)
860 && ppc_check_regset (tid, NT_PPC_EBB,
861 PPC_LINUX_SIZEOF_EBBREGSET)
862 && ppc_check_regset (tid, NT_PPC_PMU,
863 PPC_LINUX_SIZEOF_PMUREGSET))
8d619c01
EBM		 864 {
865 features.isa207 = true;
866 if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
867 && ppc_check_regset (tid, NT_PPC_TM_SPR,
868 PPC_LINUX_SIZEOF_TM_SPRREGSET))
869 features.htm = true;
870 }
f2cf6173 871 }
7ca18ed6 872
bd64614e 873 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 874
875 /* On 32-bit machines, check for SPE registers.
876 Set the low target's regmap field as appropriately. */
877#ifndef __powerpc64__
878 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
879 tdesc = tdesc_powerpc_e500l;
880
881 if (!ppc_regmap_adjusted)
882 {
883 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
884 ppc_usrregs_info.regmap = ppc_regmap_e500;
885
886 /* If the FPSCR is 64-bit wide, we need to fetch the whole
887 64-bit slot and not just its second word. The PT_FPSCR
888 supplied in a 32-bit GDB compilation doesn't reflect
889 this. */
890 if (register_size (tdesc, 70) == 8)
891 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
892
893 ppc_regmap_adjusted = 1;
894 }
895#endif
bd64614e 896
e6c5bb05 897 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 898
899 for (regset = ppc_regsets; regset->size >= 0; regset++)
900 switch (regset->get_request)
901 {
902 case PTRACE_GETVRREGS:
d078308a 903 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 904 break;
905 case PTRACE_GETVSXREGS:
d078308a 906 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 907 break;
908 case PTRACE_GETEVRREGS:
909 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
910 regset->size = 32 * 4 + 8 + 4;
911 else
912 regset->size = 0;
913 break;
7ca18ed6
EBM		 914 case PTRACE_GETREGSET:
915 switch (regset->nt_type)
916 {
917 case NT_PPC_PPR:
918 regset->size = (features.ppr_dscr ?
919 PPC_LINUX_SIZEOF_PPRREGSET : 0);
920 break;
921 case NT_PPC_DSCR:
922 regset->size = (features.ppr_dscr ?
923 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
924 break;
f2cf6173
EBM		 925 case NT_PPC_TAR:
926 regset->size = (features.isa207 ?
927 PPC_LINUX_SIZEOF_TARREGSET : 0);
928 break;
232bfb86
EBM		 929 case NT_PPC_EBB:
930 regset->size = (features.isa207 ?
931 PPC_LINUX_SIZEOF_EBBREGSET : 0);
932 break;
933 case NT_PPC_PMU:
934 regset->size = (features.isa207 ?
935 PPC_LINUX_SIZEOF_PMUREGSET : 0);
936 break;
8d619c01
EBM		 937 case NT_PPC_TM_SPR:
938 regset->size = (features.htm ?
939 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
940 break;
941 case NT_PPC_TM_CGPR:
942 if (features.wordsize == 4)
943 regset->size = (features.htm ?
944 PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
945 else
946 regset->size = (features.htm ?
947 PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
948 break;
949 case NT_PPC_TM_CFPR:
950 regset->size = (features.htm ?
951 PPC_LINUX_SIZEOF_CFPRREGSET : 0);
952 break;
953 case NT_PPC_TM_CVMX:
954 regset->size = (features.htm ?
955 PPC_LINUX_SIZEOF_CVMXREGSET : 0);
956 break;
957 case NT_PPC_TM_CVSX:
958 regset->size = (features.htm ?
959 PPC_LINUX_SIZEOF_CVSXREGSET : 0);
960 break;
961 case NT_PPC_TM_CPPR:
962 regset->size = (features.htm ?
963 PPC_LINUX_SIZEOF_CPPRREGSET : 0);
964 break;
965 case NT_PPC_TM_CDSCR:
966 regset->size = (features.htm ?
967 PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
968 break;
969 case NT_PPC_TM_CTAR:
970 regset->size = (features.htm ?
971 PPC_LINUX_SIZEOF_CTARREGSET : 0);
972 break;
7ca18ed6
EBM		 973 default:
974 break;
975 }
976 break;
7273b5fc
PFC		 977 default:
978 break;
979 }
e6c5bb05
SM		 980}
981
a2174ba4
MK		 982/* Implementation of linux_target_ops method "supports_tracepoints". */
983
b04fd3be
MK		 984static int
985ppc_supports_tracepoints (void)
986{
987 return 1;
988}
989
a2174ba4
MK		 990/* Get the thread area address. This is used to recognize which
991 thread is which when tracing with the in-process agent library. We
992 don't read anything from the address, and treat it as opaque; it's
993 the address itself that we assume is unique per-thread. */
994
995static int
996ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
997{
f2907e49 998 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 999 struct thread_info *thr = get_lwp_thread (lwp);
1000 struct regcache *regcache = get_thread_regcache (thr, 1);
1001 ULONGEST tp = 0;
1002
1003#ifdef __powerpc64__
1004 if (register_size (regcache->tdesc, 0) == 8)
1005 collect_register_by_name (regcache, "r13", &tp);
1006 else
1007#endif
1008 collect_register_by_name (regcache, "r2", &tp);
1009
1010 *addr = tp;
1011
1012 return 0;
1013}
1014
1015#ifdef __powerpc64__
1016
1017/* Older glibc doesn't provide this. */
1018
1019#ifndef EF_PPC64_ABI
1020#define EF_PPC64_ABI 3
1021#endif
1022
1023/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1024 inferiors. */
1025
1026static int
1027is_elfv2_inferior (void)
1028{
1029 /* To be used as fallback if we're unable to determine the right result -
1030 assume inferior uses the same ABI as gdbserver. */
1031#if _CALL_ELF == 2
1032 const int def_res = 1;
1033#else
1034 const int def_res = 0;
1035#endif
0570503d 1036 CORE_ADDR phdr;
a2174ba4
MK		 1037 Elf64_Ehdr ehdr;
1038
0570503d
PFC		 1039 const struct target_desc *tdesc = current_process ()->tdesc;
1040 int wordsize = register_size (tdesc, 0);
1041
1042 if (!linux_get_auxv (wordsize, AT_PHDR, &phdr))
a2174ba4
MK		 1043 return def_res;
1044
1045 /* Assume ELF header is at the beginning of the page where program headers
1046 are located. If it doesn't look like one, bail. */
1047
1048 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
1049 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
1050 return def_res;
1051
1052 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
1053}
1054
1055#endif
1056
1057/* Generate a ds-form instruction in BUF and return the number of bytes written
1058
1059 0 6 11 16 30 32
1060 | OPCD | RST | RA | DS |XO| */
1061
1062__attribute__((unused)) /* Maybe unused due to conditional compilation. */
1063static int
1064gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
1065{
1066 uint32_t insn;
1067
1068 gdb_assert ((opcd & ~0x3f) == 0);
1069 gdb_assert ((rst & ~0x1f) == 0);
1070 gdb_assert ((ra & ~0x1f) == 0);
1071 gdb_assert ((xo & ~0x3) == 0);
1072
1073 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
1074 *buf = (opcd << 26) | insn;
1075 return 1;
1076}
1077
1078/* Followings are frequently used ds-form instructions. */
1079
1080#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1081#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1082#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1083#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1084
1085/* Generate a d-form instruction in BUF.
1086
1087 0 6 11 16 32
1088 | OPCD | RST | RA | D | */
1089
1090static int
1091gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
1092{
1093 uint32_t insn;
1094
1095 gdb_assert ((opcd & ~0x3f) == 0);
1096 gdb_assert ((rst & ~0x1f) == 0);
1097 gdb_assert ((ra & ~0x1f) == 0);
1098
1099 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
1100 *buf = (opcd << 26) | insn;
1101 return 1;
1102}
1103
1104/* Followings are frequently used d-form instructions. */
1105
1106#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1107#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1108#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1109#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1110#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1111#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1112#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1113#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1114#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1115
1116/* Generate a xfx-form instruction in BUF and return the number of bytes
1117 written.
1118
1119 0 6 11 21 31 32
1120 | OPCD | RST | RI | XO |/| */
1121
1122static int
1123gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1124{
1125 uint32_t insn;
1126 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1127
1128 gdb_assert ((opcd & ~0x3f) == 0);
1129 gdb_assert ((rst & ~0x1f) == 0);
1130 gdb_assert ((xo & ~0x3ff) == 0);
1131
1132 insn = (rst << 21) | (n << 11) | (xo << 1);
1133 *buf = (opcd << 26) | insn;
1134 return 1;
1135}
1136
1137/* Followings are frequently used xfx-form instructions. */
1138
1139#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1140#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1141#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1142#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1143#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1144 E & 0xf, 598)
1145#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1146
1147
1148/* Generate a x-form instruction in BUF and return the number of bytes written.
1149
1150 0 6 11 16 21 31 32
1151 | OPCD | RST | RA | RB | XO |RC| */
1152
1153static int
1154gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1155{
1156 uint32_t insn;
1157
1158 gdb_assert ((opcd & ~0x3f) == 0);
1159 gdb_assert ((rst & ~0x1f) == 0);
1160 gdb_assert ((ra & ~0x1f) == 0);
1161 gdb_assert ((rb & ~0x1f) == 0);
1162 gdb_assert ((xo & ~0x3ff) == 0);
1163 gdb_assert ((rc & ~1) == 0);
1164
1165 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1166 *buf = (opcd << 26) | insn;
1167 return 1;
1168}
1169
1170/* Followings are frequently used x-form instructions. */
1171
1172#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1173#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1174#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1175#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1176/* Assume bf = cr7. */
1177#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1178
1179
1180/* Generate a md-form instruction in BUF and return the number of bytes written.
1181
1182 0 6 11 16 21 27 30 31 32
1183 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1184
1185static int
1186gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1187 int xo, int rc)
1188{
1189 uint32_t insn;
1190 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1191 unsigned int sh0_4 = sh & 0x1f;
1192 unsigned int sh5 = (sh >> 5) & 1;
1193
1194 gdb_assert ((opcd & ~0x3f) == 0);
1195 gdb_assert ((rs & ~0x1f) == 0);
1196 gdb_assert ((ra & ~0x1f) == 0);
1197 gdb_assert ((sh & ~0x3f) == 0);
1198 gdb_assert ((mb & ~0x3f) == 0);
1199 gdb_assert ((xo & ~0x7) == 0);
1200 gdb_assert ((rc & ~0x1) == 0);
1201
1202 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1203 | (sh5 << 1) | (xo << 2) | (rc & 1);
1204 *buf = (opcd << 26) | insn;
1205 return 1;
1206}
1207
1208/* The following are frequently used md-form instructions. */
1209
1210#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1211 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1212#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1213 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1214
1215/* Generate a i-form instruction in BUF and return the number of bytes written.
1216
1217 0 6 30 31 32
1218 | OPCD | LI |AA|LK| */
1219
1220static int
1221gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1222{
1223 uint32_t insn;
1224
1225 gdb_assert ((opcd & ~0x3f) == 0);
1226
1227 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1228 *buf = (opcd << 26) | insn;
1229 return 1;
1230}
1231
1232/* The following are frequently used i-form instructions. */
1233
1234#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1235#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1236
1237/* Generate a b-form instruction in BUF and return the number of bytes written.
1238
1239 0 6 11 16 30 31 32
1240 | OPCD | BO | BI | BD |AA|LK| */
1241
1242static int
1243gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1244 int aa, int lk)
1245{
1246 uint32_t insn;
1247
1248 gdb_assert ((opcd & ~0x3f) == 0);
1249 gdb_assert ((bo & ~0x1f) == 0);
1250 gdb_assert ((bi & ~0x1f) == 0);
1251
1252 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1253 *buf = (opcd << 26) | insn;
1254 return 1;
1255}
1256
1257/* The following are frequently used b-form instructions. */
1258/* Assume bi = cr7. */
1259#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1260
1261/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1262 respectively. They are primary used for save/restore GPRs in jump-pad,
1263 not used for bytecode compiling. */
1264
1265#ifdef __powerpc64__
1266#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1267 GEN_LD (buf, rt, ra, si) : \
1268 GEN_LWZ (buf, rt, ra, si))
1269#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1270 GEN_STD (buf, rt, ra, si) : \
1271 GEN_STW (buf, rt, ra, si))
1272#else
1273#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1274#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1275#endif
1276
1277/* Generate a sequence of instructions to load IMM in the register REG.
1278 Write the instructions in BUF and return the number of bytes written. */
1279
1280static int
1281gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1282{
1283 uint32_t *p = buf;
1284
1285 if ((imm + 32768) < 65536)
1286 {
1287 /* li reg, imm[15:0] */
1288 p += GEN_LI (p, reg, imm);
1289 }
1290 else if ((imm >> 32) == 0)
1291 {
1292 /* lis reg, imm[31:16]
1293 ori reg, reg, imm[15:0]
1294 rldicl reg, reg, 0, 32 */
1295 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1296 if ((imm & 0xffff) != 0)
1297 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1298 /* Clear upper 32-bit if sign-bit is set. */
1299 if (imm & (1u << 31) && is_64)
1300 p += GEN_RLDICL (p, reg, reg, 0, 32);
1301 }
1302 else
1303 {
1304 gdb_assert (is_64);
1305 /* lis reg, <imm[63:48]>
1306 ori reg, reg, <imm[48:32]>
1307 rldicr reg, reg, 32, 31
1308 oris reg, reg, <imm[31:16]>
1309 ori reg, reg, <imm[15:0]> */
1310 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1311 if (((imm >> 32) & 0xffff) != 0)
1312 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1313 p += GEN_RLDICR (p, reg, reg, 32, 31);
1314 if (((imm >> 16) & 0xffff) != 0)
1315 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1316 if ((imm & 0xffff) != 0)
1317 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1318 }
1319
1320 return p - buf;
1321}
1322
1323/* Generate a sequence for atomically exchange at location LOCK.
1324 This code sequence clobbers r6, r7, r8. LOCK is the location for
1325 the atomic-xchg, OLD_VALUE is expected old value stored in the
1326 location, and R_NEW is a register for the new value. */
1327
1328static int
1329gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1330 int is_64)
1331{
1332 const int r_lock = 6;
1333 const int r_old = 7;
1334 const int r_tmp = 8;
1335 uint32_t *p = buf;
1336
1337 /*
1338 1: lwarx TMP, 0, LOCK
1339 cmpwi TMP, OLD
1340 bne 1b
1341 stwcx. NEW, 0, LOCK
1342 bne 1b */
1343
1344 p += gen_limm (p, r_lock, lock, is_64);
1345 p += gen_limm (p, r_old, old_value, is_64);
1346
1347 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1348 p += GEN_CMPW (p, r_tmp, r_old);
1349 p += GEN_BNE (p, -8);
1350 p += GEN_STWCX (p, r_new, 0, r_lock);
1351 p += GEN_BNE (p, -16);
1352
1353 return p - buf;
1354}
1355
1356/* Generate a sequence of instructions for calling a function
1357 at address of FN. Return the number of bytes are written in BUF. */
1358
1359static int
1360gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1361{
1362 uint32_t *p = buf;
1363
1364 /* Must be called by r12 for caller to calculate TOC address. */
1365 p += gen_limm (p, 12, fn, is_64);
1366 if (is_opd)
1367 {
1368 p += GEN_LOAD (p, 11, 12, 16, is_64);
1369 p += GEN_LOAD (p, 2, 12, 8, is_64);
1370 p += GEN_LOAD (p, 12, 12, 0, is_64);
1371 }
1372 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1373 *p++ = 0x4e800421; /* bctrl */
1374
1375 return p - buf;
1376}
1377
1378/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1379 of instruction. This function is used to adjust pc-relative instructions
1380 when copying. */
1381
1382static void
1383ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1384{
1385 uint32_t insn, op6;
1386 long rel, newrel;
1387
1388 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1389 op6 = PPC_OP6 (insn);
1390
1391 if (op6 == 18 && (insn & 2) == 0)
1392 {
1393 /* branch && AA = 0 */
1394 rel = PPC_LI (insn);
1395 newrel = (oldloc - *to) + rel;
1396
1397 /* Out of range. Cannot relocate instruction. */
1398 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1399 return;
1400
1401 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1402 }
1403 else if (op6 == 16 && (insn & 2) == 0)
1404 {
1405 /* conditional branch && AA = 0 */
1406
1407 /* If the new relocation is too big for even a 26-bit unconditional
1408 branch, there is nothing we can do. Just abort.
1409
1410 Otherwise, if it can be fit in 16-bit conditional branch, just
1411 copy the instruction and relocate the address.
1412
1413 If the it's big for conditional-branch (16-bit), try to invert the
1414 condition and jump with 26-bit branch. For example,
1415
1416 beq .Lgoto
1417 INSN1
1418
1419 =>
1420
1421 bne 1f (+8)
1422 b .Lgoto
1423 1:INSN1
1424
1425 After this transform, we are actually jump from *TO+4 instead of *TO,
1426 so check the relocation again because it will be 1-insn farther then
1427 before if *TO is after OLDLOC.
1428
1429
1430 For BDNZT (or so) is transformed from
1431
1432 bdnzt eq, .Lgoto
1433 INSN1
1434
1435 =>
1436
1437 bdz 1f (+12)
1438 bf eq, 1f (+8)
1439 b .Lgoto
1440 1:INSN1
1441
1442 See also "BO field encodings". */
1443
1444 rel = PPC_BD (insn);
1445 newrel = (oldloc - *to) + rel;
1446
1447 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1448 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1449 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1450 {
1451 newrel -= 4;
1452
1453 /* Out of range. Cannot relocate instruction. */
1454 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1455 return;
1456
1457 if ((PPC_BO (insn) & 0x14) == 0x4)
1458 insn ^= (1 << 24);
1459 else if ((PPC_BO (insn) & 0x14) == 0x10)
1460 insn ^= (1 << 22);
1461
1462 /* Jump over the unconditional branch. */
1463 insn = (insn & ~0xfffc) | 0x8;
4196ab2a 1464 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1465 *to += 4;
1466
1467 /* Build a unconditional branch and copy LK bit. */
1468 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1469 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1470 *to += 4;
1471
1472 return;
1473 }
1474 else if ((PPC_BO (insn) & 0x14) == 0)
1475 {
1476 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1477 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1478
1479 newrel -= 8;
1480
1481 /* Out of range. Cannot relocate instruction. */
1482 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1483 return;
1484
1485 /* Copy BI field. */
1486 bf_insn |= (insn & 0x1f0000);
1487
1488 /* Invert condition. */
1489 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1490 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1491
4196ab2a 1492 target_write_memory (*to, (unsigned char *) &bdnz_insn, 4);
a2174ba4 1493 *to += 4;
4196ab2a 1494 target_write_memory (*to, (unsigned char *) &bf_insn, 4);
a2174ba4
MK		 1495 *to += 4;
1496
1497 /* Build a unconditional branch and copy LK bit. */
1498 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1499 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1500 *to += 4;
1501
1502 return;
1503 }
1504 else /* (BO & 0x14) == 0x14, branch always. */
1505 {
1506 /* Out of range. Cannot relocate instruction. */
1507 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1508 return;
1509
1510 /* Build a unconditional branch and copy LK bit. */
1511 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1512 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1513 *to += 4;
1514
1515 return;
1516 }
1517 }
1518
4196ab2a 1519 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1520 *to += 4;
1521}
1522
1523/* Implement install_fast_tracepoint_jump_pad of target_ops.
1524 See target.h for details. */
1525
1526static int
1527ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1528 CORE_ADDR collector,
1529 CORE_ADDR lockaddr,
1530 ULONGEST orig_size,
1531 CORE_ADDR *jump_entry,
1532 CORE_ADDR *trampoline,
1533 ULONGEST *trampoline_size,
1534 unsigned char *jjump_pad_insn,
1535 ULONGEST *jjump_pad_insn_size,
1536 CORE_ADDR *adjusted_insn_addr,
1537 CORE_ADDR *adjusted_insn_addr_end,
1538 char *err)
1539{
1540 uint32_t buf[256];
1541 uint32_t *p = buf;
1542 int j, offset;
1543 CORE_ADDR buildaddr = *jump_entry;
1544 const CORE_ADDR entryaddr = *jump_entry;
1545 int rsz, min_frame, frame_size, tp_reg;
1546#ifdef __powerpc64__
1547 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1548 int is_64 = register_size (regcache->tdesc, 0) == 8;
1549 int is_opd = is_64 && !is_elfv2_inferior ();
1550#else
1551 int is_64 = 0, is_opd = 0;
1552#endif
1553
1554#ifdef __powerpc64__
1555 if (is_64)
1556 {
1557 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1558 rsz = 8;
1559 min_frame = 112;
1560 frame_size = (40 * rsz) + min_frame;
1561 tp_reg = 13;
1562 }
1563 else
1564 {
1565#endif
1566 rsz = 4;
1567 min_frame = 16;
1568 frame_size = (40 * rsz) + min_frame;
1569 tp_reg = 2;
1570#ifdef __powerpc64__
1571 }
1572#endif
1573
1574 /* Stack frame layout for this jump pad,
1575
1576 High thread_area (r13/r2) |
1577 tpoint - collecting_t obj
1578 PC/<tpaddr> | +36
1579 CTR | +35
1580 LR | +34
1581 XER | +33
1582 CR | +32
1583 R31 |
1584 R29 |
1585 ... |
1586 R1 | +1
1587 R0 - collected registers
1588 ... |
1589 ... |
1590 Low Back-chain -
1591
1592
1593 The code flow of this jump pad,
1594
1595 1. Adjust SP
1596 2. Save GPR and SPR
1597 3. Prepare argument
1598 4. Call gdb_collector
1599 5. Restore GPR and SPR
1600 6. Restore SP
1601 7. Build a jump for back to the program
1602 8. Copy/relocate original instruction
30baf67b 1603 9. Build a jump for replacing original instruction. */
a2174ba4
MK		 1604
1605 /* Adjust stack pointer. */
1606 if (is_64)
1607 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1608 else
1609 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1610
1611 /* Store GPRs. Save R1 later, because it had just been modified, but
1612 we want the original value. */
1613 for (j = 2; j < 32; j++)
1614 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1615 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1616 /* Set r0 to the original value of r1 before adjusting stack frame,
1617 and then save it. */
1618 p += GEN_ADDI (p, 0, 1, frame_size);
1619 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1620
1621 /* Save CR, XER, LR, and CTR. */
1622 p += GEN_MFCR (p, 3); /* mfcr r3 */
1623 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1624 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1625 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1626 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1627 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1628 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1629 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1630
1631 /* Save PC<tpaddr> */
1632 p += gen_limm (p, 3, tpaddr, is_64);
1633 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1634
1635
1636 /* Setup arguments to collector. */
1637 /* Set r4 to collected registers. */
1638 p += GEN_ADDI (p, 4, 1, min_frame);
1639 /* Set r3 to TPOINT. */
1640 p += gen_limm (p, 3, tpoint, is_64);
1641
1642 /* Prepare collecting_t object for lock. */
1643 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1644 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1645 /* Set R5 to collecting object. */
1646 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1647
1648 p += GEN_LWSYNC (p);
1649 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1650 p += GEN_LWSYNC (p);
1651
1652 /* Call to collector. */
1653 p += gen_call (p, collector, is_64, is_opd);
1654
1655 /* Simply write 0 to release the lock. */
1656 p += gen_limm (p, 3, lockaddr, is_64);
1657 p += gen_limm (p, 4, 0, is_64);
1658 p += GEN_LWSYNC (p);
1659 p += GEN_STORE (p, 4, 3, 0, is_64);
1660
1661 /* Restore stack and registers. */
1662 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1663 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1664 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1665 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1666 p += GEN_MTCR (p, 3); /* mtcr r3 */
1667 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1668 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1669 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1670
1671 /* Restore GPRs. */
1672 for (j = 2; j < 32; j++)
1673 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1674 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1675 /* Restore SP. */
1676 p += GEN_ADDI (p, 1, 1, frame_size);
1677
1678 /* Flush instructions to inferior memory. */
4196ab2a 1679 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1680
1681 /* Now, insert the original instruction to execute in the jump pad. */
1682 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1683 *adjusted_insn_addr_end = *adjusted_insn_addr;
1684 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1685
1686 /* Verify the relocation size. If should be 4 for normal copy,
1687 8 or 12 for some conditional branch. */
1688 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1689 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1690 {
1691 sprintf (err, "E.Unexpected instruction length = %d"
1692 "when relocate instruction.",
1693 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1694 return 1;
1695 }
1696
1697 buildaddr = *adjusted_insn_addr_end;
1698 p = buf;
1699 /* Finally, write a jump back to the program. */
1700 offset = (tpaddr + 4) - buildaddr;
1701 if (offset >= (1 << 25) || offset < -(1 << 25))
1702 {
1703 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1704 "(offset 0x%x > 26-bit).", offset);
1705 return 1;
1706 }
1707 /* b <tpaddr+4> */
1708 p += GEN_B (p, offset);
4196ab2a 1709 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1710 *jump_entry = buildaddr + (p - buf) * 4;
1711
1712 /* The jump pad is now built. Wire in a jump to our jump pad. This
1713 is always done last (by our caller actually), so that we can
1714 install fast tracepoints with threads running. This relies on
1715 the agent's atomic write support. */
1716 offset = entryaddr - tpaddr;
1717 if (offset >= (1 << 25) || offset < -(1 << 25))
1718 {
1719 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1720 "(offset 0x%x > 26-bit).", offset);
1721 return 1;
1722 }
1723 /* b <jentry> */
1724 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1725 *jjump_pad_insn_size = 4;
1726
1727 return 0;
1728}
1729
1730/* Returns the minimum instruction length for installing a tracepoint. */
1731
1732static int
1733ppc_get_min_fast_tracepoint_insn_len (void)
1734{
1735 return 4;
1736}
1737
14e2b6d9
MK		 1738/* Emits a given buffer into the target at current_insn_ptr. Length
1739 is in units of 32-bit words. */
1740
1741static void
1742emit_insns (uint32_t *buf, int n)
1743{
1744 n = n * sizeof (uint32_t);
4196ab2a 1745 target_write_memory (current_insn_ptr, (unsigned char *) buf, n);
14e2b6d9
MK		 1746 current_insn_ptr += n;
1747}
1748
1749#define __EMIT_ASM(NAME, INSNS) \
1750 do \
1751 { \
1752 extern uint32_t start_bcax_ ## NAME []; \
1753 extern uint32_t end_bcax_ ## NAME []; \
1754 emit_insns (start_bcax_ ## NAME, \
1755 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1756 __asm__ (".section .text.__ppcbcax\n\t" \
1757 "start_bcax_" #NAME ":\n\t" \
1758 INSNS "\n\t" \
1759 "end_bcax_" #NAME ":\n\t" \
1760 ".previous\n\t"); \
1761 } while (0)
1762
1763#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1764#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1765
1766/*
1767
1768 Bytecode execution stack frame - 32-bit
1769
1770 | LR save area (SP + 4)
1771 SP' -> +- Back chain (SP + 0)
1772 | Save r31 for access saved arguments
1773 | Save r30 for bytecode stack pointer
1774 | Save r4 for incoming argument *value
1775 | Save r3 for incoming argument regs
1776 r30 -> +- Bytecode execution stack
1777 |
1778 | 64-byte (8 doublewords) at initial.
1779 | Expand stack as needed.
1780 |
1781 +-
1782 | Some padding for minimum stack frame and 16-byte alignment.
1783 | 16 bytes.
1784 SP +- Back-chain (SP')
1785
1786 initial frame size
1787 = 16 + (4 * 4) + 64
1788 = 96
1789
1790 r30 is the stack-pointer for bytecode machine.
1791 It should point to next-empty, so we can use LDU for pop.
1792 r3 is used for cache of the high part of TOP value.
1793 It was the first argument, pointer to regs.
1794 r4 is used for cache of the low part of TOP value.
1795 It was the second argument, pointer to the result.
1796 We should set *result = TOP after leaving this function.
1797
1798 Note:
1799 * To restore stack at epilogue
1800 => sp = r31
1801 * To check stack is big enough for bytecode execution.
1802 => r30 - 8 > SP + 8
1803 * To return execution result.
1804 => 0(r4) = TOP
1805
1806 */
1807
1808/* Regardless of endian, register 3 is always high part, 4 is low part.
1809 These defines are used when the register pair is stored/loaded.
1810 Likewise, to simplify code, have a similiar define for 5:6. */
1811
1812#if __BYTE_ORDER == __LITTLE_ENDIAN
1813#define TOP_FIRST "4"
1814#define TOP_SECOND "3"
1815#define TMP_FIRST "6"
1816#define TMP_SECOND "5"
1817#else
1818#define TOP_FIRST "3"
1819#define TOP_SECOND "4"
1820#define TMP_FIRST "5"
1821#define TMP_SECOND "6"
1822#endif
1823
1824/* Emit prologue in inferior memory. See above comments. */
1825
1826static void
1827ppc_emit_prologue (void)
1828{
1829 EMIT_ASM (/* Save return address. */
1830 "mflr 0 \n"
1831 "stw 0, 4(1) \n"
1832 /* Adjust SP. 96 is the initial frame size. */
1833 "stwu 1, -96(1) \n"
1834 /* Save r30 and incoming arguments. */
1835 "stw 31, 96-4(1) \n"
1836 "stw 30, 96-8(1) \n"
1837 "stw 4, 96-12(1) \n"
1838 "stw 3, 96-16(1) \n"
1839 /* Point r31 to original r1 for access arguments. */
1840 "addi 31, 1, 96 \n"
1841 /* Set r30 to pointing stack-top. */
1842 "addi 30, 1, 64 \n"
1843 /* Initial r3/TOP to 0. */
1844 "li 3, 0 \n"
1845 "li 4, 0 \n");
1846}
1847
1848/* Emit epilogue in inferior memory. See above comments. */
1849
1850static void
1851ppc_emit_epilogue (void)
1852{
1853 EMIT_ASM (/* *result = TOP */
1854 "lwz 5, -12(31) \n"
1855 "stw " TOP_FIRST ", 0(5) \n"
1856 "stw " TOP_SECOND ", 4(5) \n"
1857 /* Restore registers. */
1858 "lwz 31, -4(31) \n"
1859 "lwz 30, -8(31) \n"
1860 /* Restore SP. */
1861 "lwz 1, 0(1) \n"
1862 /* Restore LR. */
1863 "lwz 0, 4(1) \n"
1864 /* Return 0 for no-error. */
1865 "li 3, 0 \n"
1866 "mtlr 0 \n"
1867 "blr \n");
1868}
1869
1870/* TOP = stack[--sp] + TOP */
1871
1872static void
1873ppc_emit_add (void)
1874{
1875 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1876 "lwz " TMP_SECOND ", 4(30)\n"
1877 "addc 4, 6, 4 \n"
1878 "adde 3, 5, 3 \n");
1879}
1880
1881/* TOP = stack[--sp] - TOP */
1882
1883static void
1884ppc_emit_sub (void)
1885{
1886 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1887 "lwz " TMP_SECOND ", 4(30) \n"
1888 "subfc 4, 4, 6 \n"
1889 "subfe 3, 3, 5 \n");
1890}
1891
1892/* TOP = stack[--sp] * TOP */
1893
1894static void
1895ppc_emit_mul (void)
1896{
1897 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1898 "lwz " TMP_SECOND ", 4(30) \n"
1899 "mulhwu 7, 6, 4 \n"
1900 "mullw 3, 6, 3 \n"
1901 "mullw 5, 4, 5 \n"
1902 "mullw 4, 6, 4 \n"
1903 "add 3, 5, 3 \n"
1904 "add 3, 7, 3 \n");
1905}
1906
1907/* TOP = stack[--sp] << TOP */
1908
1909static void
1910ppc_emit_lsh (void)
1911{
1912 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1913 "lwz " TMP_SECOND ", 4(30) \n"
1914 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1915 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1916 "slw 5, 5, 4\n" /* Shift high part left */
1917 "slw 4, 6, 4\n" /* Shift low part left */
1918 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1919 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1920 "or 3, 5, 3\n"
1921 "or 3, 7, 3\n"); /* Assemble high part */
1922}
1923
1924/* Top = stack[--sp] >> TOP
1925 (Arithmetic shift right) */
1926
1927static void
1928ppc_emit_rsh_signed (void)
1929{
1930 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1931 "lwz " TMP_SECOND ", 4(30) \n"
1932 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1933 "sraw 3, 5, 4\n" /* Shift high part right */
1934 "cmpwi 7, 1\n"
1935 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1936 "sraw 4, 5, 7\n" /* Shift high to low */
1937 "b 2f\n"
1938 "1:\n"
1939 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1940 "srw 4, 6, 4\n" /* Shift low part right */
1941 "slw 5, 5, 7\n" /* Shift high to low */
1942 "or 4, 4, 5\n" /* Assemble low part */
1943 "2:\n");
1944}
1945
1946/* Top = stack[--sp] >> TOP
1947 (Logical shift right) */
1948
1949static void
1950ppc_emit_rsh_unsigned (void)
1951{
1952 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1953 "lwz " TMP_SECOND ", 4(30) \n"
1954 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1955 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1956 "srw 6, 6, 4\n" /* Shift low part right */
1957 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1958 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1959 "or 6, 6, 3\n"
1960 "srw 3, 5, 4\n" /* Shift high part right */
1961 "or 4, 6, 7\n"); /* Assemble low part */
1962}
1963
1964/* Emit code for signed-extension specified by ARG. */
1965
1966static void
1967ppc_emit_ext (int arg)
1968{
1969 switch (arg)
1970 {
1971 case 8:
1972 EMIT_ASM ("extsb 4, 4\n"
1973 "srawi 3, 4, 31");
1974 break;
1975 case 16:
1976 EMIT_ASM ("extsh 4, 4\n"
1977 "srawi 3, 4, 31");
1978 break;
1979 case 32:
1980 EMIT_ASM ("srawi 3, 4, 31");
1981 break;
1982 default:
1983 emit_error = 1;
1984 }
1985}
1986
1987/* Emit code for zero-extension specified by ARG. */
1988
1989static void
1990ppc_emit_zero_ext (int arg)
1991{
1992 switch (arg)
1993 {
1994 case 8:
1995 EMIT_ASM ("clrlwi 4,4,24\n"
1996 "li 3, 0\n");
1997 break;
1998 case 16:
1999 EMIT_ASM ("clrlwi 4,4,16\n"
2000 "li 3, 0\n");
2001 break;
2002 case 32:
2003 EMIT_ASM ("li 3, 0");
2004 break;
2005 default:
2006 emit_error = 1;
2007 }
2008}
2009
2010/* TOP = !TOP
2011 i.e., TOP = (TOP == 0) ? 1 : 0; */
2012
2013static void
2014ppc_emit_log_not (void)
2015{
2016 EMIT_ASM ("or 4, 3, 4 \n"
2017 "cntlzw 4, 4 \n"
2018 "srwi 4, 4, 5 \n"
2019 "li 3, 0 \n");
2020}
2021
2022/* TOP = stack[--sp] & TOP */
2023
2024static void
2025ppc_emit_bit_and (void)
2026{
2027 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2028 "lwz " TMP_SECOND ", 4(30) \n"
2029 "and 4, 6, 4 \n"
2030 "and 3, 5, 3 \n");
2031}
2032
2033/* TOP = stack[--sp] | TOP */
2034
2035static void
2036ppc_emit_bit_or (void)
2037{
2038 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2039 "lwz " TMP_SECOND ", 4(30) \n"
2040 "or 4, 6, 4 \n"
2041 "or 3, 5, 3 \n");
2042}
2043
2044/* TOP = stack[--sp] ^ TOP */
2045
2046static void
2047ppc_emit_bit_xor (void)
2048{
2049 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2050 "lwz " TMP_SECOND ", 4(30) \n"
2051 "xor 4, 6, 4 \n"
2052 "xor 3, 5, 3 \n");
2053}
2054
2055/* TOP = ~TOP
2056 i.e., TOP = ~(TOP | TOP) */
2057
2058static void
2059ppc_emit_bit_not (void)
2060{
2061 EMIT_ASM ("nor 3, 3, 3 \n"
2062 "nor 4, 4, 4 \n");
2063}
2064
2065/* TOP = stack[--sp] == TOP */
2066
2067static void
2068ppc_emit_equal (void)
2069{
2070 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2071 "lwz " TMP_SECOND ", 4(30) \n"
2072 "xor 4, 6, 4 \n"
2073 "xor 3, 5, 3 \n"
2074 "or 4, 3, 4 \n"
2075 "cntlzw 4, 4 \n"
2076 "srwi 4, 4, 5 \n"
2077 "li 3, 0 \n");
2078}
2079
2080/* TOP = stack[--sp] < TOP
2081 (Signed comparison) */
2082
2083static void
2084ppc_emit_less_signed (void)
2085{
2086 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2087 "lwz " TMP_SECOND ", 4(30) \n"
2088 "cmplw 6, 6, 4 \n"
2089 "cmpw 7, 5, 3 \n"
2090 /* CR6 bit 0 = low less and high equal */
2091 "crand 6*4+0, 6*4+0, 7*4+2\n"
2092 /* CR7 bit 0 = (low less and high equal) or high less */
2093 "cror 7*4+0, 7*4+0, 6*4+0\n"
2094 "mfcr 4 \n"
2095 "rlwinm 4, 4, 29, 31, 31 \n"
2096 "li 3, 0 \n");
2097}
2098
2099/* TOP = stack[--sp] < TOP
2100 (Unsigned comparison) */
2101
2102static void
2103ppc_emit_less_unsigned (void)
2104{
2105 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2106 "lwz " TMP_SECOND ", 4(30) \n"
2107 "cmplw 6, 6, 4 \n"
2108 "cmplw 7, 5, 3 \n"
2109 /* CR6 bit 0 = low less and high equal */
2110 "crand 6*4+0, 6*4+0, 7*4+2\n"
2111 /* CR7 bit 0 = (low less and high equal) or high less */
2112 "cror 7*4+0, 7*4+0, 6*4+0\n"
2113 "mfcr 4 \n"
2114 "rlwinm 4, 4, 29, 31, 31 \n"
2115 "li 3, 0 \n");
2116}
2117
2118/* Access the memory address in TOP in size of SIZE.
2119 Zero-extend the read value. */
2120
2121static void
2122ppc_emit_ref (int size)
2123{
2124 switch (size)
2125 {
2126 case 1:
2127 EMIT_ASM ("lbz 4, 0(4)\n"
2128 "li 3, 0");
2129 break;
2130 case 2:
2131 EMIT_ASM ("lhz 4, 0(4)\n"
2132 "li 3, 0");
2133 break;
2134 case 4:
2135 EMIT_ASM ("lwz 4, 0(4)\n"
2136 "li 3, 0");
2137 break;
2138 case 8:
2139 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2140 EMIT_ASM ("lwz 3, 4(4)\n"
2141 "lwz 4, 0(4)");
2142 else
2143 EMIT_ASM ("lwz 3, 0(4)\n"
2144 "lwz 4, 4(4)");
2145 break;
2146 }
2147}
2148
2149/* TOP = NUM */
2150
2151static void
2152ppc_emit_const (LONGEST num)
2153{
2154 uint32_t buf[10];
2155 uint32_t *p = buf;
2156
2157 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2158 p += gen_limm (p, 4, num & 0xffffffff, 0);
2159
2160 emit_insns (buf, p - buf);
2161 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2162}
2163
2164/* Set TOP to the value of register REG by calling get_raw_reg function
2165 with two argument, collected buffer and register number. */
2166
2167static void
2168ppc_emit_reg (int reg)
2169{
2170 uint32_t buf[13];
2171 uint32_t *p = buf;
2172
2173 /* fctx->regs is passed in r3 and then saved in -16(31). */
2174 p += GEN_LWZ (p, 3, 31, -16);
2175 p += GEN_LI (p, 4, reg); /* li r4, reg */
2176 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2177
2178 emit_insns (buf, p - buf);
2179 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2180
2181 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2182 {
2183 EMIT_ASM ("mr 5, 4\n"
2184 "mr 4, 3\n"
2185 "mr 3, 5\n");
2186 }
2187}
2188
2189/* TOP = stack[--sp] */
2190
2191static void
2192ppc_emit_pop (void)
2193{
2194 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2195 "lwz " TOP_SECOND ", 4(30) \n");
2196}
2197
2198/* stack[sp++] = TOP
2199
2200 Because we may use up bytecode stack, expand 8 doublewords more
2201 if needed. */
2202
2203static void
2204ppc_emit_stack_flush (void)
2205{
2206 /* Make sure bytecode stack is big enough before push.
2207 Otherwise, expand 64-byte more. */
2208
2209 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2210 " stw " TOP_SECOND ", 4(30)\n"
2211 " addi 5, 30, -(8 + 8) \n"
2212 " cmpw 7, 5, 1 \n"
2213 " bgt 7, 1f \n"
2214 " stwu 31, -64(1) \n"
2215 "1:addi 30, 30, -8 \n");
2216}
2217
2218/* Swap TOP and stack[sp-1] */
2219
2220static void
2221ppc_emit_swap (void)
2222{
2223 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2224 "lwz " TMP_SECOND ", 12(30) \n"
2225 "stw " TOP_FIRST ", 8(30) \n"
2226 "stw " TOP_SECOND ", 12(30) \n"
2227 "mr 3, 5 \n"
2228 "mr 4, 6 \n");
2229}
2230
2231/* Discard N elements in the stack. Also used for ppc64. */
2232
2233static void
2234ppc_emit_stack_adjust (int n)
2235{
2236 uint32_t buf[6];
2237 uint32_t *p = buf;
2238
2239 n = n << 3;
2240 if ((n >> 15) != 0)
2241 {
2242 emit_error = 1;
2243 return;
2244 }
2245
2246 p += GEN_ADDI (p, 30, 30, n);
2247
2248 emit_insns (buf, p - buf);
2249 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2250}
2251
2252/* Call function FN. */
2253
2254static void
2255ppc_emit_call (CORE_ADDR fn)
2256{
2257 uint32_t buf[11];
2258 uint32_t *p = buf;
2259
2260 p += gen_call (p, fn, 0, 0);
2261
2262 emit_insns (buf, p - buf);
2263 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2264}
2265
2266/* FN's prototype is `LONGEST(*fn)(int)'.
2267 TOP = fn (arg1)
2268 */
2269
2270static void
2271ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2272{
2273 uint32_t buf[15];
2274 uint32_t *p = buf;
2275
2276 /* Setup argument. arg1 is a 16-bit value. */
2277 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2278 p += gen_call (p, fn, 0, 0);
2279
2280 emit_insns (buf, p - buf);
2281 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2282
2283 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2284 {
2285 EMIT_ASM ("mr 5, 4\n"
2286 "mr 4, 3\n"
2287 "mr 3, 5\n");
2288 }
2289}
2290
2291/* FN's prototype is `void(*fn)(int,LONGEST)'.
2292 fn (arg1, TOP)
2293
2294 TOP should be preserved/restored before/after the call. */
2295
2296static void
2297ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2298{
2299 uint32_t buf[21];
2300 uint32_t *p = buf;
2301
2302 /* Save TOP. 0(30) is next-empty. */
2303 p += GEN_STW (p, 3, 30, 0);
2304 p += GEN_STW (p, 4, 30, 4);
2305
2306 /* Setup argument. arg1 is a 16-bit value. */
2307 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2308 {
2309 p += GEN_MR (p, 5, 4);
2310 p += GEN_MR (p, 6, 3);
2311 }
2312 else
2313 {
2314 p += GEN_MR (p, 5, 3);
2315 p += GEN_MR (p, 6, 4);
2316 }
2317 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2318 p += gen_call (p, fn, 0, 0);
2319
2320 /* Restore TOP */
2321 p += GEN_LWZ (p, 3, 30, 0);
2322 p += GEN_LWZ (p, 4, 30, 4);
2323
2324 emit_insns (buf, p - buf);
2325 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2326}
2327
2328/* Note in the following goto ops:
2329
2330 When emitting goto, the target address is later relocated by
2331 write_goto_address. OFFSET_P is the offset of the branch instruction
2332 in the code sequence, and SIZE_P is how to relocate the instruction,
2333 recognized by ppc_write_goto_address. In current implementation,
2334 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2335 */
2336
2337/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2338
2339static void
2340ppc_emit_if_goto (int *offset_p, int *size_p)
2341{
2342 EMIT_ASM ("or. 3, 3, 4 \n"
2343 "lwzu " TOP_FIRST ", 8(30) \n"
2344 "lwz " TOP_SECOND ", 4(30) \n"
2345 "1:bne 0, 1b \n");
2346
2347 if (offset_p)
2348 *offset_p = 12;
2349 if (size_p)
2350 *size_p = 14;
2351}
2352
2353/* Unconditional goto. Also used for ppc64. */
2354
2355static void
2356ppc_emit_goto (int *offset_p, int *size_p)
2357{
2358 EMIT_ASM ("1:b 1b");
2359
2360 if (offset_p)
2361 *offset_p = 0;
2362 if (size_p)
2363 *size_p = 24;
2364}
2365
2366/* Goto if stack[--sp] == TOP */
2367
2368static void
2369ppc_emit_eq_goto (int *offset_p, int *size_p)
2370{
2371 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2372 "lwz " TMP_SECOND ", 4(30) \n"
2373 "xor 4, 6, 4 \n"
2374 "xor 3, 5, 3 \n"
2375 "or. 3, 3, 4 \n"
2376 "lwzu " TOP_FIRST ", 8(30) \n"
2377 "lwz " TOP_SECOND ", 4(30) \n"
2378 "1:beq 0, 1b \n");
2379
2380 if (offset_p)
2381 *offset_p = 28;
2382 if (size_p)
2383 *size_p = 14;
2384}
2385
2386/* Goto if stack[--sp] != TOP */
2387
2388static void
2389ppc_emit_ne_goto (int *offset_p, int *size_p)
2390{
2391 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2392 "lwz " TMP_SECOND ", 4(30) \n"
2393 "xor 4, 6, 4 \n"
2394 "xor 3, 5, 3 \n"
2395 "or. 3, 3, 4 \n"
2396 "lwzu " TOP_FIRST ", 8(30) \n"
2397 "lwz " TOP_SECOND ", 4(30) \n"
2398 "1:bne 0, 1b \n");
2399
2400 if (offset_p)
2401 *offset_p = 28;
2402 if (size_p)
2403 *size_p = 14;
2404}
2405
2406/* Goto if stack[--sp] < TOP */
2407
2408static void
2409ppc_emit_lt_goto (int *offset_p, int *size_p)
2410{
2411 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2412 "lwz " TMP_SECOND ", 4(30) \n"
2413 "cmplw 6, 6, 4 \n"
2414 "cmpw 7, 5, 3 \n"
2415 /* CR6 bit 0 = low less and high equal */
2416 "crand 6*4+0, 6*4+0, 7*4+2\n"
2417 /* CR7 bit 0 = (low less and high equal) or high less */
2418 "cror 7*4+0, 7*4+0, 6*4+0\n"
2419 "lwzu " TOP_FIRST ", 8(30) \n"
2420 "lwz " TOP_SECOND ", 4(30)\n"
2421 "1:blt 7, 1b \n");
2422
2423 if (offset_p)
2424 *offset_p = 32;
2425 if (size_p)
2426 *size_p = 14;
2427}
2428
2429/* Goto if stack[--sp] <= TOP */
2430
2431static void
2432ppc_emit_le_goto (int *offset_p, int *size_p)
2433{
2434 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2435 "lwz " TMP_SECOND ", 4(30) \n"
2436 "cmplw 6, 6, 4 \n"
2437 "cmpw 7, 5, 3 \n"
2438 /* CR6 bit 0 = low less/equal and high equal */
2439 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2440 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2441 "cror 7*4+0, 7*4+0, 6*4+0\n"
2442 "lwzu " TOP_FIRST ", 8(30) \n"
2443 "lwz " TOP_SECOND ", 4(30)\n"
2444 "1:blt 7, 1b \n");
2445
2446 if (offset_p)
2447 *offset_p = 32;
2448 if (size_p)
2449 *size_p = 14;
2450}
2451
2452/* Goto if stack[--sp] > TOP */
2453
2454static void
2455ppc_emit_gt_goto (int *offset_p, int *size_p)
2456{
2457 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2458 "lwz " TMP_SECOND ", 4(30) \n"
2459 "cmplw 6, 6, 4 \n"
2460 "cmpw 7, 5, 3 \n"
2461 /* CR6 bit 0 = low greater and high equal */
2462 "crand 6*4+0, 6*4+1, 7*4+2\n"
2463 /* CR7 bit 0 = (low greater and high equal) or high greater */
2464 "cror 7*4+0, 7*4+1, 6*4+0\n"
2465 "lwzu " TOP_FIRST ", 8(30) \n"
2466 "lwz " TOP_SECOND ", 4(30)\n"
2467 "1:blt 7, 1b \n");
2468
2469 if (offset_p)
2470 *offset_p = 32;
2471 if (size_p)
2472 *size_p = 14;
2473}
2474
2475/* Goto if stack[--sp] >= TOP */
2476
2477static void
2478ppc_emit_ge_goto (int *offset_p, int *size_p)
2479{
2480 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2481 "lwz " TMP_SECOND ", 4(30) \n"
2482 "cmplw 6, 6, 4 \n"
2483 "cmpw 7, 5, 3 \n"
2484 /* CR6 bit 0 = low ge and high equal */
2485 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2486 /* CR7 bit 0 = (low ge and high equal) or high greater */
2487 "cror 7*4+0, 7*4+1, 6*4+0\n"
2488 "lwzu " TOP_FIRST ", 8(30)\n"
2489 "lwz " TOP_SECOND ", 4(30)\n"
2490 "1:blt 7, 1b \n");
2491
2492 if (offset_p)
2493 *offset_p = 32;
2494 if (size_p)
2495 *size_p = 14;
2496}
2497
2498/* Relocate previous emitted branch instruction. FROM is the address
2499 of the branch instruction, TO is the goto target address, and SIZE
2500 if the value we set by *SIZE_P before. Currently, it is either
2501 24 or 14 of branch and conditional-branch instruction.
2502 Also used for ppc64. */
2503
2504static void
2505ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2506{
2507 long rel = to - from;
2508 uint32_t insn;
2509 int opcd;
2510
2511 read_inferior_memory (from, (unsigned char *) &insn, 4);
2512 opcd = (insn >> 26) & 0x3f;
2513
2514 switch (size)
2515 {
2516 case 14:
2517 if (opcd != 16
2518 || (rel >= (1 << 15) || rel < -(1 << 15)))
2519 emit_error = 1;
2520 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2521 break;
2522 case 24:
2523 if (opcd != 18
2524 || (rel >= (1 << 25) || rel < -(1 << 25)))
2525 emit_error = 1;
2526 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2527 break;
2528 default:
2529 emit_error = 1;
2530 }
2531
2532 if (!emit_error)
4196ab2a 2533 target_write_memory (from, (unsigned char *) &insn, 4);
14e2b6d9
MK		 2534}
2535
2536/* Table of emit ops for 32-bit. */
2537
2538static struct emit_ops ppc_emit_ops_impl =
2539{
2540 ppc_emit_prologue,
2541 ppc_emit_epilogue,
2542 ppc_emit_add,
2543 ppc_emit_sub,
2544 ppc_emit_mul,
2545 ppc_emit_lsh,
2546 ppc_emit_rsh_signed,
2547 ppc_emit_rsh_unsigned,
2548 ppc_emit_ext,
2549 ppc_emit_log_not,
2550 ppc_emit_bit_and,
2551 ppc_emit_bit_or,
2552 ppc_emit_bit_xor,
2553 ppc_emit_bit_not,
2554 ppc_emit_equal,
2555 ppc_emit_less_signed,
2556 ppc_emit_less_unsigned,
2557 ppc_emit_ref,
2558 ppc_emit_if_goto,
2559 ppc_emit_goto,
2560 ppc_write_goto_address,
2561 ppc_emit_const,
2562 ppc_emit_call,
2563 ppc_emit_reg,
2564 ppc_emit_pop,
2565 ppc_emit_stack_flush,
2566 ppc_emit_zero_ext,
2567 ppc_emit_swap,
2568 ppc_emit_stack_adjust,
2569 ppc_emit_int_call_1,
2570 ppc_emit_void_call_2,
2571 ppc_emit_eq_goto,
2572 ppc_emit_ne_goto,
2573 ppc_emit_lt_goto,
2574 ppc_emit_le_goto,
2575 ppc_emit_gt_goto,
2576 ppc_emit_ge_goto
2577};
2578
2579#ifdef __powerpc64__
2580
2581/*
2582
2583 Bytecode execution stack frame - 64-bit
2584
2585 | LR save area (SP + 16)
2586 | CR save area (SP + 8)
2587 SP' -> +- Back chain (SP + 0)
2588 | Save r31 for access saved arguments
2589 | Save r30 for bytecode stack pointer
2590 | Save r4 for incoming argument *value
2591 | Save r3 for incoming argument regs
2592 r30 -> +- Bytecode execution stack
2593 |
2594 | 64-byte (8 doublewords) at initial.
2595 | Expand stack as needed.
2596 |
2597 +-
2598 | Some padding for minimum stack frame.
2599 | 112 for ELFv1.
2600 SP +- Back-chain (SP')
2601
2602 initial frame size
2603 = 112 + (4 * 8) + 64
2604 = 208
2605
2606 r30 is the stack-pointer for bytecode machine.
2607 It should point to next-empty, so we can use LDU for pop.
2608 r3 is used for cache of TOP value.
2609 It was the first argument, pointer to regs.
2610 r4 is the second argument, pointer to the result.
2611 We should set *result = TOP after leaving this function.
2612
2613 Note:
2614 * To restore stack at epilogue
2615 => sp = r31
2616 * To check stack is big enough for bytecode execution.
2617 => r30 - 8 > SP + 112
2618 * To return execution result.
2619 => 0(r4) = TOP
2620
2621 */
2622
2623/* Emit prologue in inferior memory. See above comments. */
2624
2625static void
2626ppc64v1_emit_prologue (void)
2627{
2628 /* On ELFv1, function pointers really point to function descriptor,
2629 so emit one here. We don't care about contents of words 1 and 2,
2630 so let them just overlap out code. */
2631 uint64_t opd = current_insn_ptr + 8;
2632 uint32_t buf[2];
2633
2634 /* Mind the strict aliasing rules. */
2635 memcpy (buf, &opd, sizeof buf);
2636 emit_insns(buf, 2);
2637 EMIT_ASM (/* Save return address. */
2638 "mflr 0 \n"
2639 "std 0, 16(1) \n"
2640 /* Save r30 and incoming arguments. */
2641 "std 31, -8(1) \n"
2642 "std 30, -16(1) \n"
2643 "std 4, -24(1) \n"
2644 "std 3, -32(1) \n"
2645 /* Point r31 to current r1 for access arguments. */
2646 "mr 31, 1 \n"
2647 /* Adjust SP. 208 is the initial frame size. */
2648 "stdu 1, -208(1) \n"
2649 /* Set r30 to pointing stack-top. */
2650 "addi 30, 1, 168 \n"
2651 /* Initial r3/TOP to 0. */
2652 "li 3, 0 \n");
2653}
2654
2655/* Emit prologue in inferior memory. See above comments. */
2656
2657static void
2658ppc64v2_emit_prologue (void)
2659{
2660 EMIT_ASM (/* Save return address. */
2661 "mflr 0 \n"
2662 "std 0, 16(1) \n"
2663 /* Save r30 and incoming arguments. */
2664 "std 31, -8(1) \n"
2665 "std 30, -16(1) \n"
2666 "std 4, -24(1) \n"
2667 "std 3, -32(1) \n"
2668 /* Point r31 to current r1 for access arguments. */
2669 "mr 31, 1 \n"
2670 /* Adjust SP. 208 is the initial frame size. */
2671 "stdu 1, -208(1) \n"
2672 /* Set r30 to pointing stack-top. */
2673 "addi 30, 1, 168 \n"
2674 /* Initial r3/TOP to 0. */
2675 "li 3, 0 \n");
2676}
2677
2678/* Emit epilogue in inferior memory. See above comments. */
2679
2680static void
2681ppc64_emit_epilogue (void)
2682{
2683 EMIT_ASM (/* Restore SP. */
2684 "ld 1, 0(1) \n"
2685 /* *result = TOP */
2686 "ld 4, -24(1) \n"
2687 "std 3, 0(4) \n"
2688 /* Restore registers. */
2689 "ld 31, -8(1) \n"
2690 "ld 30, -16(1) \n"
2691 /* Restore LR. */
2692 "ld 0, 16(1) \n"
2693 /* Return 0 for no-error. */
2694 "li 3, 0 \n"
2695 "mtlr 0 \n"
2696 "blr \n");
2697}
2698
2699/* TOP = stack[--sp] + TOP */
2700
2701static void
2702ppc64_emit_add (void)
2703{
2704 EMIT_ASM ("ldu 4, 8(30) \n"
2705 "add 3, 4, 3 \n");
2706}
2707
2708/* TOP = stack[--sp] - TOP */
2709
2710static void
2711ppc64_emit_sub (void)
2712{
2713 EMIT_ASM ("ldu 4, 8(30) \n"
2714 "sub 3, 4, 3 \n");
2715}
2716
2717/* TOP = stack[--sp] * TOP */
2718
2719static void
2720ppc64_emit_mul (void)
2721{
2722 EMIT_ASM ("ldu 4, 8(30) \n"
2723 "mulld 3, 4, 3 \n");
2724}
2725
2726/* TOP = stack[--sp] << TOP */
2727
2728static void
2729ppc64_emit_lsh (void)
2730{
2731 EMIT_ASM ("ldu 4, 8(30) \n"
2732 "sld 3, 4, 3 \n");
2733}
2734
2735/* Top = stack[--sp] >> TOP
2736 (Arithmetic shift right) */
2737
2738static void
2739ppc64_emit_rsh_signed (void)
2740{
2741 EMIT_ASM ("ldu 4, 8(30) \n"
2742 "srad 3, 4, 3 \n");
2743}
2744
2745/* Top = stack[--sp] >> TOP
2746 (Logical shift right) */
2747
2748static void
2749ppc64_emit_rsh_unsigned (void)
2750{
2751 EMIT_ASM ("ldu 4, 8(30) \n"
2752 "srd 3, 4, 3 \n");
2753}
2754
2755/* Emit code for signed-extension specified by ARG. */
2756
2757static void
2758ppc64_emit_ext (int arg)
2759{
2760 switch (arg)
2761 {
2762 case 8:
2763 EMIT_ASM ("extsb 3, 3");
2764 break;
2765 case 16:
2766 EMIT_ASM ("extsh 3, 3");
2767 break;
2768 case 32:
2769 EMIT_ASM ("extsw 3, 3");
2770 break;
2771 default:
2772 emit_error = 1;
2773 }
2774}
2775
2776/* Emit code for zero-extension specified by ARG. */
2777
2778static void
2779ppc64_emit_zero_ext (int arg)
2780{
2781 switch (arg)
2782 {
2783 case 8:
2784 EMIT_ASM ("rldicl 3,3,0,56");
2785 break;
2786 case 16:
2787 EMIT_ASM ("rldicl 3,3,0,48");
2788 break;
2789 case 32:
2790 EMIT_ASM ("rldicl 3,3,0,32");
2791 break;
2792 default:
2793 emit_error = 1;
2794 }
2795}
2796
2797/* TOP = !TOP
2798 i.e., TOP = (TOP == 0) ? 1 : 0; */
2799
2800static void
2801ppc64_emit_log_not (void)
2802{
2803 EMIT_ASM ("cntlzd 3, 3 \n"
2804 "srdi 3, 3, 6 \n");
2805}
2806
2807/* TOP = stack[--sp] & TOP */
2808
2809static void
2810ppc64_emit_bit_and (void)
2811{
2812 EMIT_ASM ("ldu 4, 8(30) \n"
2813 "and 3, 4, 3 \n");
2814}
2815
2816/* TOP = stack[--sp] | TOP */
2817
2818static void
2819ppc64_emit_bit_or (void)
2820{
2821 EMIT_ASM ("ldu 4, 8(30) \n"
2822 "or 3, 4, 3 \n");
2823}
2824
2825/* TOP = stack[--sp] ^ TOP */
2826
2827static void
2828ppc64_emit_bit_xor (void)
2829{
2830 EMIT_ASM ("ldu 4, 8(30) \n"
2831 "xor 3, 4, 3 \n");
2832}
2833
2834/* TOP = ~TOP
2835 i.e., TOP = ~(TOP | TOP) */
2836
2837static void
2838ppc64_emit_bit_not (void)
2839{
2840 EMIT_ASM ("nor 3, 3, 3 \n");
2841}
2842
2843/* TOP = stack[--sp] == TOP */
2844
2845static void
2846ppc64_emit_equal (void)
2847{
2848 EMIT_ASM ("ldu 4, 8(30) \n"
2849 "xor 3, 3, 4 \n"
2850 "cntlzd 3, 3 \n"
2851 "srdi 3, 3, 6 \n");
2852}
2853
2854/* TOP = stack[--sp] < TOP
2855 (Signed comparison) */
2856
2857static void
2858ppc64_emit_less_signed (void)
2859{
2860 EMIT_ASM ("ldu 4, 8(30) \n"
2861 "cmpd 7, 4, 3 \n"
2862 "mfcr 3 \n"
2863 "rlwinm 3, 3, 29, 31, 31 \n");
2864}
2865
2866/* TOP = stack[--sp] < TOP
2867 (Unsigned comparison) */
2868
2869static void
2870ppc64_emit_less_unsigned (void)
2871{
2872 EMIT_ASM ("ldu 4, 8(30) \n"
2873 "cmpld 7, 4, 3 \n"
2874 "mfcr 3 \n"
2875 "rlwinm 3, 3, 29, 31, 31 \n");
2876}
2877
2878/* Access the memory address in TOP in size of SIZE.
2879 Zero-extend the read value. */
2880
2881static void
2882ppc64_emit_ref (int size)
2883{
2884 switch (size)
2885 {
2886 case 1:
2887 EMIT_ASM ("lbz 3, 0(3)");
2888 break;
2889 case 2:
2890 EMIT_ASM ("lhz 3, 0(3)");
2891 break;
2892 case 4:
2893 EMIT_ASM ("lwz 3, 0(3)");
2894 break;
2895 case 8:
2896 EMIT_ASM ("ld 3, 0(3)");
2897 break;
2898 }
2899}
2900
2901/* TOP = NUM */
2902
2903static void
2904ppc64_emit_const (LONGEST num)
2905{
2906 uint32_t buf[5];
2907 uint32_t *p = buf;
2908
2909 p += gen_limm (p, 3, num, 1);
2910
2911 emit_insns (buf, p - buf);
2912 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2913}
2914
2915/* Set TOP to the value of register REG by calling get_raw_reg function
2916 with two argument, collected buffer and register number. */
2917
2918static void
2919ppc64v1_emit_reg (int reg)
2920{
2921 uint32_t buf[15];
2922 uint32_t *p = buf;
2923
2924 /* fctx->regs is passed in r3 and then saved in 176(1). */
2925 p += GEN_LD (p, 3, 31, -32);
2926 p += GEN_LI (p, 4, reg);
2927 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2928 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2929 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2930
2931 emit_insns (buf, p - buf);
2932 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2933}
2934
2935/* Likewise, for ELFv2. */
2936
2937static void
2938ppc64v2_emit_reg (int reg)
2939{
2940 uint32_t buf[12];
2941 uint32_t *p = buf;
2942
2943 /* fctx->regs is passed in r3 and then saved in 176(1). */
2944 p += GEN_LD (p, 3, 31, -32);
2945 p += GEN_LI (p, 4, reg);
2946 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2947 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2948 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2949
2950 emit_insns (buf, p - buf);
2951 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2952}
2953
2954/* TOP = stack[--sp] */
2955
2956static void
2957ppc64_emit_pop (void)
2958{
2959 EMIT_ASM ("ldu 3, 8(30)");
2960}
2961
2962/* stack[sp++] = TOP
2963
2964 Because we may use up bytecode stack, expand 8 doublewords more
2965 if needed. */
2966
2967static void
2968ppc64_emit_stack_flush (void)
2969{
2970 /* Make sure bytecode stack is big enough before push.
2971 Otherwise, expand 64-byte more. */
2972
2973 EMIT_ASM (" std 3, 0(30) \n"
2974 " addi 4, 30, -(112 + 8) \n"
2975 " cmpd 7, 4, 1 \n"
2976 " bgt 7, 1f \n"
2977 " stdu 31, -64(1) \n"
2978 "1:addi 30, 30, -8 \n");
2979}
2980
2981/* Swap TOP and stack[sp-1] */
2982
2983static void
2984ppc64_emit_swap (void)
2985{
2986 EMIT_ASM ("ld 4, 8(30) \n"
2987 "std 3, 8(30) \n"
2988 "mr 3, 4 \n");
2989}
2990
2991/* Call function FN - ELFv1. */
2992
2993static void
2994ppc64v1_emit_call (CORE_ADDR fn)
2995{
2996 uint32_t buf[13];
2997 uint32_t *p = buf;
2998
2999 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3000 p += gen_call (p, fn, 1, 1);
3001 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3002
3003 emit_insns (buf, p - buf);
3004 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3005}
3006
3007/* Call function FN - ELFv2. */
3008
3009static void
3010ppc64v2_emit_call (CORE_ADDR fn)
3011{
3012 uint32_t buf[10];
3013 uint32_t *p = buf;
3014
3015 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3016 p += gen_call (p, fn, 1, 0);
3017 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3018
3019 emit_insns (buf, p - buf);
3020 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3021}
3022
3023/* FN's prototype is `LONGEST(*fn)(int)'.
3024 TOP = fn (arg1)
3025 */
3026
3027static void
3028ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
3029{
3030 uint32_t buf[13];
3031 uint32_t *p = buf;
3032
3033 /* Setup argument. arg1 is a 16-bit value. */
3034 p += gen_limm (p, 3, arg1, 1);
3035 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3036 p += gen_call (p, fn, 1, 1);
3037 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3038
3039 emit_insns (buf, p - buf);
3040 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3041}
3042
3043/* Likewise for ELFv2. */
3044
3045static void
3046ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
3047{
3048 uint32_t buf[10];
3049 uint32_t *p = buf;
3050
3051 /* Setup argument. arg1 is a 16-bit value. */
3052 p += gen_limm (p, 3, arg1, 1);
3053 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3054 p += gen_call (p, fn, 1, 0);
3055 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3056
3057 emit_insns (buf, p - buf);
3058 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3059}
3060
3061/* FN's prototype is `void(*fn)(int,LONGEST)'.
3062 fn (arg1, TOP)
3063
3064 TOP should be preserved/restored before/after the call. */
3065
3066static void
3067ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
3068{
3069 uint32_t buf[17];
3070 uint32_t *p = buf;
3071
3072 /* Save TOP. 0(30) is next-empty. */
3073 p += GEN_STD (p, 3, 30, 0);
3074
3075 /* Setup argument. arg1 is a 16-bit value. */
3076 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3077 p += gen_limm (p, 3, arg1, 1);
3078 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3079 p += gen_call (p, fn, 1, 1);
3080 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3081
3082 /* Restore TOP */
3083 p += GEN_LD (p, 3, 30, 0);
3084
3085 emit_insns (buf, p - buf);
3086 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3087}
3088
3089/* Likewise for ELFv2. */
3090
3091static void
3092ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
3093{
3094 uint32_t buf[14];
3095 uint32_t *p = buf;
3096
3097 /* Save TOP. 0(30) is next-empty. */
3098 p += GEN_STD (p, 3, 30, 0);
3099
3100 /* Setup argument. arg1 is a 16-bit value. */
3101 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3102 p += gen_limm (p, 3, arg1, 1);
3103 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3104 p += gen_call (p, fn, 1, 0);
3105 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3106
3107 /* Restore TOP */
3108 p += GEN_LD (p, 3, 30, 0);
3109
3110 emit_insns (buf, p - buf);
3111 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3112}
3113
3114/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3115
3116static void
3117ppc64_emit_if_goto (int *offset_p, int *size_p)
3118{
3119 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3120 "ldu 3, 8(30) \n"
3121 "1:bne 7, 1b \n");
3122
3123 if (offset_p)
3124 *offset_p = 8;
3125 if (size_p)
3126 *size_p = 14;
3127}
3128
3129/* Goto if stack[--sp] == TOP */
3130
3131static void
3132ppc64_emit_eq_goto (int *offset_p, int *size_p)
3133{
3134 EMIT_ASM ("ldu 4, 8(30) \n"
3135 "cmpd 7, 4, 3 \n"
3136 "ldu 3, 8(30) \n"
3137 "1:beq 7, 1b \n");
3138
3139 if (offset_p)
3140 *offset_p = 12;
3141 if (size_p)
3142 *size_p = 14;
3143}
3144
3145/* Goto if stack[--sp] != TOP */
3146
3147static void
3148ppc64_emit_ne_goto (int *offset_p, int *size_p)
3149{
3150 EMIT_ASM ("ldu 4, 8(30) \n"
3151 "cmpd 7, 4, 3 \n"
3152 "ldu 3, 8(30) \n"
3153 "1:bne 7, 1b \n");
3154
3155 if (offset_p)
3156 *offset_p = 12;
3157 if (size_p)
3158 *size_p = 14;
3159}
3160
3161/* Goto if stack[--sp] < TOP */
3162
3163static void
3164ppc64_emit_lt_goto (int *offset_p, int *size_p)
3165{
3166 EMIT_ASM ("ldu 4, 8(30) \n"
3167 "cmpd 7, 4, 3 \n"
3168 "ldu 3, 8(30) \n"
3169 "1:blt 7, 1b \n");
3170
3171 if (offset_p)
3172 *offset_p = 12;
3173 if (size_p)
3174 *size_p = 14;
3175}
3176
3177/* Goto if stack[--sp] <= TOP */
3178
3179static void
3180ppc64_emit_le_goto (int *offset_p, int *size_p)
3181{
3182 EMIT_ASM ("ldu 4, 8(30) \n"
3183 "cmpd 7, 4, 3 \n"
3184 "ldu 3, 8(30) \n"
3185 "1:ble 7, 1b \n");
3186
3187 if (offset_p)
3188 *offset_p = 12;
3189 if (size_p)
3190 *size_p = 14;
3191}
3192
3193/* Goto if stack[--sp] > TOP */
3194
3195static void
3196ppc64_emit_gt_goto (int *offset_p, int *size_p)
3197{
3198 EMIT_ASM ("ldu 4, 8(30) \n"
3199 "cmpd 7, 4, 3 \n"
3200 "ldu 3, 8(30) \n"
3201 "1:bgt 7, 1b \n");
3202
3203 if (offset_p)
3204 *offset_p = 12;
3205 if (size_p)
3206 *size_p = 14;
3207}
3208
3209/* Goto if stack[--sp] >= TOP */
3210
3211static void
3212ppc64_emit_ge_goto (int *offset_p, int *size_p)
3213{
3214 EMIT_ASM ("ldu 4, 8(30) \n"
3215 "cmpd 7, 4, 3 \n"
3216 "ldu 3, 8(30) \n"
3217 "1:bge 7, 1b \n");
3218
3219 if (offset_p)
3220 *offset_p = 12;
3221 if (size_p)
3222 *size_p = 14;
3223}
3224
3225/* Table of emit ops for 64-bit ELFv1. */
3226
3227static struct emit_ops ppc64v1_emit_ops_impl =
3228{
3229 ppc64v1_emit_prologue,
3230 ppc64_emit_epilogue,
3231 ppc64_emit_add,
3232 ppc64_emit_sub,
3233 ppc64_emit_mul,
3234 ppc64_emit_lsh,
3235 ppc64_emit_rsh_signed,
3236 ppc64_emit_rsh_unsigned,
3237 ppc64_emit_ext,
3238 ppc64_emit_log_not,
3239 ppc64_emit_bit_and,
3240 ppc64_emit_bit_or,
3241 ppc64_emit_bit_xor,
3242 ppc64_emit_bit_not,
3243 ppc64_emit_equal,
3244 ppc64_emit_less_signed,
3245 ppc64_emit_less_unsigned,
3246 ppc64_emit_ref,
3247 ppc64_emit_if_goto,
3248 ppc_emit_goto,
3249 ppc_write_goto_address,
3250 ppc64_emit_const,
3251 ppc64v1_emit_call,
3252 ppc64v1_emit_reg,
3253 ppc64_emit_pop,
3254 ppc64_emit_stack_flush,
3255 ppc64_emit_zero_ext,
3256 ppc64_emit_swap,
3257 ppc_emit_stack_adjust,
3258 ppc64v1_emit_int_call_1,
3259 ppc64v1_emit_void_call_2,
3260 ppc64_emit_eq_goto,
3261 ppc64_emit_ne_goto,
3262 ppc64_emit_lt_goto,
3263 ppc64_emit_le_goto,
3264 ppc64_emit_gt_goto,
3265 ppc64_emit_ge_goto
3266};
3267
3268/* Table of emit ops for 64-bit ELFv2. */
3269
3270static struct emit_ops ppc64v2_emit_ops_impl =
3271{
3272 ppc64v2_emit_prologue,
3273 ppc64_emit_epilogue,
3274 ppc64_emit_add,
3275 ppc64_emit_sub,
3276 ppc64_emit_mul,
3277 ppc64_emit_lsh,
3278 ppc64_emit_rsh_signed,
3279 ppc64_emit_rsh_unsigned,
3280 ppc64_emit_ext,
3281 ppc64_emit_log_not,
3282 ppc64_emit_bit_and,
3283 ppc64_emit_bit_or,
3284 ppc64_emit_bit_xor,
3285 ppc64_emit_bit_not,
3286 ppc64_emit_equal,
3287 ppc64_emit_less_signed,
3288 ppc64_emit_less_unsigned,
3289 ppc64_emit_ref,
3290 ppc64_emit_if_goto,
3291 ppc_emit_goto,
3292 ppc_write_goto_address,
3293 ppc64_emit_const,
3294 ppc64v2_emit_call,
3295 ppc64v2_emit_reg,
3296 ppc64_emit_pop,
3297 ppc64_emit_stack_flush,
3298 ppc64_emit_zero_ext,
3299 ppc64_emit_swap,
3300 ppc_emit_stack_adjust,
3301 ppc64v2_emit_int_call_1,
3302 ppc64v2_emit_void_call_2,
3303 ppc64_emit_eq_goto,
3304 ppc64_emit_ne_goto,
3305 ppc64_emit_lt_goto,
3306 ppc64_emit_le_goto,
3307 ppc64_emit_gt_goto,
3308 ppc64_emit_ge_goto
3309};
3310
3311#endif
3312
3313/* Implementation of linux_target_ops method "emit_ops". */
3314
3315static struct emit_ops *
3316ppc_emit_ops (void)
3317{
3318#ifdef __powerpc64__
3319 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3320
3321 if (register_size (regcache->tdesc, 0) == 8)
3322 {
3323 if (is_elfv2_inferior ())
3324 return &ppc64v2_emit_ops_impl;
3325 else
3326 return &ppc64v1_emit_ops_impl;
3327 }
3328#endif
3329 return &ppc_emit_ops_impl;
3330}
3331
a2174ba4
MK		 3332/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3333
3334static int
3335ppc_get_ipa_tdesc_idx (void)
3336{
3337 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3338 const struct target_desc *tdesc = regcache->tdesc;
3339
3340#ifdef __powerpc64__
3341 if (tdesc == tdesc_powerpc_64l)
3342 return PPC_TDESC_BASE;
3343 if (tdesc == tdesc_powerpc_altivec64l)
3344 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3345 if (tdesc == tdesc_powerpc_vsx64l)
3346 return PPC_TDESC_VSX;
3347 if (tdesc == tdesc_powerpc_isa205_64l)
3348 return PPC_TDESC_ISA205;
3349 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3350 return PPC_TDESC_ISA205_ALTIVEC;
3351 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3352 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3353 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3354 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3355 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3356 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3357 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
3358 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3359#endif
3360
3361 if (tdesc == tdesc_powerpc_32l)
3362 return PPC_TDESC_BASE;
3363 if (tdesc == tdesc_powerpc_altivec32l)
3364 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3365 if (tdesc == tdesc_powerpc_vsx32l)
3366 return PPC_TDESC_VSX;
3367 if (tdesc == tdesc_powerpc_isa205_32l)
3368 return PPC_TDESC_ISA205;
3369 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3370 return PPC_TDESC_ISA205_ALTIVEC;
3371 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3372 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3373 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3374 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3375 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3376 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3377 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
3378 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3379 if (tdesc == tdesc_powerpc_e500l)
3380 return PPC_TDESC_E500;
3381
3382 return 0;
3383}
3384
2ec06d2e 3385struct linux_target_ops the_low_target = {
6fe305f7 3386 ppc_arch_setup,
3aee8918 3387 ppc_regs_info,
2ec06d2e
DJ		 3388 ppc_cannot_fetch_register,
3389 ppc_cannot_store_register,
c14dfd32 3390 NULL, /* fetch_register */
0d62e5e8
DJ		 3391 ppc_get_pc,
3392 ppc_set_pc,
dd373349
AT		 3393 NULL, /* breakpoint_kind_from_pc */
3394 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3395 NULL,
3396 0,
3397 ppc_breakpoint_at,
657f9cde
WW		 3398 ppc_supports_z_point_type,
3399 ppc_insert_point,
3400 ppc_remove_point,
5b0a002e
UW		 3401 NULL,
3402 NULL,
3403 ppc_collect_ptrace_register,
3404 ppc_supply_ptrace_register,
7d00775e
AT		 3405 NULL, /* siginfo_fixup */
3406 NULL, /* new_process */
04ec7890 3407 NULL, /* delete_process */
7d00775e 3408 NULL, /* new_thread */
466eecee 3409 NULL, /* delete_thread */
7d00775e
AT		 3410 NULL, /* new_fork */
3411 NULL, /* prepare_to_resume */
3412 NULL, /* process_qsupported */
b04fd3be 3413 ppc_supports_tracepoints,
a2174ba4
MK		 3414 ppc_get_thread_area,
3415 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3416 ppc_emit_ops,
a2174ba4 3417 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3418 NULL, /* supports_range_stepping */
3419 NULL, /* breakpoint_kind_from_current_state */
3420 ppc_supports_hardware_single_step,
a2174ba4
MK		 3421 NULL, /* get_syscall_trapinfo */
3422 ppc_get_ipa_tdesc_idx,
2ec06d2e 3423};
3aee8918 3424
ef0478f6
TBA		 3425/* The linux target ops object. */
3426
3427linux_process_target *the_linux_target = &the_ppc_target;
3428
3aee8918
PA		 3429void
3430initialize_low_arch (void)
3431{
3432 /* Initialize the Linux target descriptions. */
3433
3434 init_registers_powerpc_32l ();
3435 init_registers_powerpc_altivec32l ();
3aee8918
PA		 3436 init_registers_powerpc_vsx32l ();
3437 init_registers_powerpc_isa205_32l ();
3438 init_registers_powerpc_isa205_altivec32l ();
3439 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3440 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3441 init_registers_powerpc_isa207_vsx32l ();
8d619c01 3442 init_registers_powerpc_isa207_htm_vsx32l ();
3aee8918 3443 init_registers_powerpc_e500l ();
a2174ba4 3444#if __powerpc64__
3aee8918
PA		 3445 init_registers_powerpc_64l ();
3446 init_registers_powerpc_altivec64l ();
3aee8918
PA		 3447 init_registers_powerpc_vsx64l ();
3448 init_registers_powerpc_isa205_64l ();
3449 init_registers_powerpc_isa205_altivec64l ();
3450 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3451 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3452 init_registers_powerpc_isa207_vsx64l ();
8d619c01 3453 init_registers_powerpc_isa207_htm_vsx64l ();
a2174ba4 3454#endif
3aee8918
PA		 3455
3456 initialize_regsets_info (&ppc_regsets_info);
3457}
GDB Binutils - Deliverables
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