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[AArch64] Add ARMv8.3 combined pointer authentication load instructions
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
3f06e550
SN		 12016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
4 (enum aarch64_insn_class): Add ldst_imm10.
5
c84364ec
SN		 62016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
7
8 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
9
1924ff75
SN		 102016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
11
12 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
13 (AARCH64_ARCH_V8_3): Define.
14 (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
15
d46a2165
TP		 162016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
17
18 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
19 (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
20 (ARM_ARCH_V8M_MAIN_DSP): Likewise.
21
5a736821
GM		 222016-11-03 Graham Markall <graham.markall@embecosm.com>
23
24 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
25
bdfe53e3
AB		 262016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
27
28 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
29 fields.
30 (struct arc_long_opcode): Delete.
31 (struct arc_operand): Change types for insert and extract
32 handlers.
33
2e272202
GM		 342016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
35
36 * opcode/arc.h: Make macros 64-bit safe.
37
06fe285f
GM		 382016-11-03 Graham Markall <graham.markall@embecosm.com>
39
40 * opcode/arc.h (arc_opcode_len): Declare.
41 (ARC_SHORT): Delete.
42
e23eba97
NC		 432016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
44 Andrew Waterman <andrew@sifive.com>
45
46 Add support for RISC-V architecture.
47 * dis-asm.h: Add prototypes for print_insn_riscv and
48 print_riscv_disassembler_options.
49 * elf/riscv.h: New file.
50 * opcode/riscv-opc.h: New file.
51 * opcode/riscv.h: New file.
52
6d913794
NC		 532016-10-17 Nick Clifton <nickc@redhat.com>
54
55 * elf/common.h (DT_SYMTAB_SHNDX): Define.
56 (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
57 (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
58 (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
59 (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
60 (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
61 (ELFOSABI_OPENVOS): Define.
62 (GRP_MASKOS, GRP_MASKPROC): Define.
63
b4f6af8e
PA		 642016-10-14 Pedro Alves <palves@redhat.com>
65
66 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
67 OVERRIDE): Define as empty.
68 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
69 __final.
70 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
71 empty.
72
d118ee37
PA		 732016-10-14 Pedro Alves <palves@redhat.com>
74
75 * ansidecl.h (GCC_FINAL): Delete.
76 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
77
e5b06ef0
CZ		 782016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
79
80 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
81
a5721ba2
AM		 822016-09-29 Alan Modra <amodra@gmail.com>
83
84 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
85
2b848ebd
CZ		 862016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
87
88 * opcode/arc.h (insn_class_t): Add two new classes.
89
005d79fd
AM		 902016-09-26 Alan Modra <amodra@gmail.com>
91
92 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
93
bb7eff52
RS		 942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
95
96 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
97
c0890d26
RS		 982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
99
100 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
101 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
102 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
103 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
104
116b6019
RS		 1052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
106
107 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
108 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
109 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
110 aarch64_insn_classes.
111
047cd301
RS		 1122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
113
114 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
115 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
116 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
117
165d4950
RS		 1182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
119
120 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
121 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
122 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
123
e950b345
RS		 1242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
125
126 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
127 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
128 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
129 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
130 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
131 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
132 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
133 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
134 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
135 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
136 (aarch64_sve_dupm_mov_immediate_p): Declare.
137
98907a70
RS		 1382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
139
140 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
141 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
142 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
143 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
144 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
145
4df068de
RS		 1462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
147
148 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
149 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
150 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
151 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
152 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
153 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
154 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
155 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
156 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
157 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
158 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
159 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
160 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
161 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
162 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
163 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
164 Likewise.
165
2442d846
RS		 1662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
167
168 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
169 aarch64_opnd.
170 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
171 (aarch64_opnd_info): Make shifter.amount an int64_t and
172 rearrange the fields.
173
245d2e3f
RS		 1742016-09-21 Richard Sandiford <richard.sandiford@arm.com>
175
176 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
177 (AARCH64_OPND_SVE_PRFOP): Likewise.
178 (aarch64_sve_pattern_array): Declare.
179 (aarch64_sve_prfop_array): Likewise.
180
d50c751e
RS		 1812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
182
183 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
184 (AARCH64_OPND_QLF_P_M): Likewise.
185
f11ad6bc
RS		 1862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
187
188 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
189 aarch64_operand_class.
190 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
191 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
192 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
193 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
194 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
195 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
196 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
197 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
198
0c608d6b
RS		 1992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
200
201 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
202 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
203
4989adac
RS		 2042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
205
206 * opcode/aarch64.h (F_STRICT): New flag.
207
27e5a270
RE		 2082016-09-07 Richard Earnshaw <rearnsha@arm.com>
209
210 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
211
a87aa054
CM		 2122016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
213 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
214 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
215 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
216 relocation.
217
4ba2ef8f
TP		 2182016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
219
220 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
221 (ARM_SET_SYM_CMSE_SPCL): Likewise.
222
dfdaec14
AJ		 2232016-08-01 Andrew Jenner <andrew@codesourcery.com>
224
225 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
226
fa3fcee7
NC		 2272016-07-29 Aldy Hernandez <aldyh@redhat.com>
228
229 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
230
db18dbab
GM		 2312016-07-27 Graham Markall <graham.markall@embecosm.com>
232
233 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
234 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
235 ARC_NUM_ADDRTYPES.
236 * opcode/arc.h: Add BMU to insn_class_t enum.
237 * opcode/arc.h: Add PMU to insn_class_t enum.
238
37fd5ef3
CZ		 2392016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
240
241 * dis-asm.h: Declare print_arc_disassembler_options.
242
76359541
TP		 2432016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
244
245 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
246 out_implib_bfd fields.
247
fa1c0170
CZ		 2482016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
249
250 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
251
f0728ee3
AV		 2522016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
253
254 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
255 (SHF_ARM_PURECODE): ... this.
256
93d8990c
SN		 2572016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
258
259 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
260 (AARCH64_CPU_HAS_ANY_FEATURES): New.
261 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
262 (AARCH64_OPCODE_HAS_FEATURE): Remove.
263
534dbe46
MW		 2642016-06-30 Matthew Wahab <matthew.wahab@arm.com>
265
266 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
267 of enabled FPU features.
268
042c94de
TS		 2692016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
270
271 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
272 SPARC_OPCODE_ARCH_MAX into the enum.
273
dab26bf4
RS		 2742016-06-28 Richard Sandiford <richard.sandiford@arm.com>
275
276 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
277
c9775dde
MR		 2782016-06-28 Maciej W. Rozycki <macro@imgtec.com>
279
280 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
281
7c2c4aa1
TS		 2822016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
283
284 * elf/xtensa.h (xtensa_make_property_section): New prototype.
285
b00f86d0
JB		 2862016-06-24 John Baldwin <jhb@FreeBSD.org>
287
288 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
289 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
290 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
291 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
292
ce440d63
GM		 2932016-06-23 Graham Markall <graham.markall@embecosm.com>
294
295 * opcode/arc.h: Make insn_class_t alphabetical again.
296
6b477896
TS		 2972016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
298
299 * elf/dlx.h: Wrap in extern C.
300 * elf/xtensa.h: Likewise.
301 * opcode/arc.h: Likewise.
302
6edaf4d7
TS		 3032016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
304
305 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
306 tilegx_pipeline.
307
bdd582db
GM		 3082016-06-21 Graham Markall <graham.markall@embecosm.com>
309
310 * opcode/arc.h: Add nps400 extension and instruction
311 subclass.
312 Remove ARC_OPCODE_NPS400
313 * elf/arc.h: Remove E_ARC_MACH_NPS400
314
4f26fb3a
JM		 3152016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
316
317 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
318 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
319 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
320 SPARC_OPCODE_ARCH_V9M.
321
99a54ef6
JB		 3222016-06-14 John Baldwin <jhb@FreeBSD.org>
323
324 * opcode/msp430-decode.h (MSP430_Size): Remove.
325 (Msp430_Opcode_Decoded): Change type of size to int.
326
0eaf2e1b
AM		 3272016-06-11 Alan Modra <amodra@gmail.com>
328
329 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
330
337c570c
JM		 3312016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
332
333 * opcode/sparc.h: Add missing documentation for hyperprivileged
334 registers in rd (%) and rs1 ($).
335
14b57c7c
AM		 3362016-06-07 Alan Modra <amodra@gmail.com>
337
338 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
339 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
340 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
341 PPC_APUINFO_VLE: Define.
342
4d1464f2
MW		 3432016-06-07 Matthew Wahab <matthew.wahab@arm.com>
344
345 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
346 entries.
347 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
348
4eb6f892
AB		 3492016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
350
351 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
352 (struct arc_long_opcode): New structure.
353 (arc_long_opcodes): Declare.
354 (arc_num_long_opcodes): Declare.
355
1fe0971e
TS		 3562016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
357
358 * elf/mips.h: Add extern "C".
359 * elf/sh.h: Likewise.
360 * opcode/d10v.h: Likewise.
361 * opcode/d30v.h: Likewise.
362 * opcode/ia64.h: Likewise.
363 * opcode/mips.h: Likewise.
364 * opcode/ppc.h: Likewise.
365 * opcode/sparc.h: Likewise.
366 * opcode/tic6x.h: Likewise.
367 * opcode/v850.h: Likewise.
368
1a72702b
AM		 3692016-05-28 Alan Modra <amodra@gmail.com>
370
371 * bfdlink.h (struct bfd_link_callbacks): Update comments.
372 Return void from multiple_definition, multiple_common,
373 add_to_set, constructor, warning, undefined_symbol,
374 reloc_overflow, reloc_dangerous and unattached_reloc.
375
94740f9c
TS		 3762016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
377
378 * opcode/metag.h: wrap declarations in extern "C".
379
d9eca1df
CZ		 3802016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
381
382 * opcode/arc.h (insn_subclass_t): Add COND.
383 (flag_class_t): Add F_CLASS_EXTEND.
384
c810e0b8
CZ		 3852016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
386
387 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
388 insn_class.
389 (struct arc_flag_class): Renamed attribute class to flag_class.
390
3d207518
TS		 3912016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
392
393 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
394 plain symbol.
395
5ff087ac
TT		 3962016-04-29 Tom Tromey <tom@tromey.com>
397
398 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
399 DW_LANG_Rust_old>: New constants.
400
8f4f9071
MF		 4012016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
402
403 * elf/mips.h (AFL_ASE_DSPR3): New macro.
404 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
405 * opcode/mips.h (ASE_DSPR3): New macro.
406
39d911fc
TP		 4072016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
408 Nick Clifton <nickc@redhat.com>
409
410 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
411 enumerator.
412 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
413 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
414 (ARM_SYM_BRANCH_TYPE): Replace by ...
415 (ARM_GET_SYM_BRANCH_TYPE): This and ...
416 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
417 BFD_ASSERT is defined or not.
418
15afaa63
TP		 4192016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
420
421 * elf/arm.h (Tag_DSP_extension): Define.
422
d942732e
TP		 4232016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
424
425 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
426
16a1fa25
TP		 4272016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
428
429 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
430 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
431 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
432 for the high core bits.
433
945e0f82
CZ		 4342016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
435
436 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
437 (ARC_SYNTAX_NOP): Likewsie.
438 (ARC_OP1_MUST_BE_IMM): Update defined value.
439 (ARC_OP1_IMM_IMPLIED): Likewise.
440 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
441
4bd13cde
NC		 4422016-04-28 Nick Clifton <nickc@redhat.com>
443
444 PR target/19722
445 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
446
a6a4679f
AM		 4472016-04-27 Alan Modra <amodra@gmail.com>
448
449 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
450 undef. Formatting.
451
4f3b23b3
NC		 4522016-04-21 Nick Clifton <nickc@redhat.com>
453
454 * bfdlink.h: Add prototype for bfd_link_check_relocs.
455
d9689752
L		 4562016-04-20 H.J. Lu <hongjiu.lu@intel.com>
457
458 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
459
52176c67
AB		 4602016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
461
462 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
463
537aefaf
AB		 4642016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
465
466 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
467
c8f785f2
AB		 4682016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
469
470 * opcode/arc.h (insn_class_t): Add NET and ACL class.
471
4b0c052e
AB		 4722016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
473
474 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
475 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
476
f36e33da
CZ		 4772016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
478
479 * opcode/arc.h (flag_class_t): Update.
480 (ARC_OPCODE_NONE): Define.
481 (ARC_OPCODE_ARCALL): Likewise.
482 (ARC_OPCODE_ARCFPX): Likewise.
483 (ARC_REGISTER_READONLY): Likewise.
484 (ARC_REGISTER_WRITEONLY): Likewise.
485 (ARC_REGISTER_NOSHORT_CUT): Likewise.
486 (arc_aux_reg): Add cpu.
487
b99747ae
CZ		 4882016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
489
490 * opcode/arc.h (arc_num_opcodes): Remove.
491 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
492 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
493 (ARC_SUFFIX_FLAG): Define.
494 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
495 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
496 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
497 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
498 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
499 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
500 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
501 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
502 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
503 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
504
5052016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
506
507 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
508 (ARC_FPUDA): Define.
509 (arc_aux_reg): Add new field.
510
5112016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 512
513 * opcode/arc-func.h (replace_bits24): Changed.
514 (replace_bits24_be): Created.
515
f2dd8838
CZ		 5162016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
517
b99747ae
CZ		 518 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
519 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
520 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
521 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
522 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
523 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
524 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
525 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
526 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
527 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
528 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
529 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
530 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
531 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 532
b9bb4a93
TS		 5332016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
534
535 * opcode/i960.h: Add const qualifiers.
536 * opcode/tic4x.h (struct tic4x_inst): Likewise.
537
e23e8ebe
AB		 5382016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
539
540 * opcodes/arc.h (insn_class_t): Add BITOP type.
541
1ae8ab47
AB		 5422016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
543
544 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
545 new classes instead.
546
8699fc3e
AB		 5472016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
548
549 * elf/arc.h (E_ARC_MACH_NPS400): Define.
550 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
551
a9522a21
AB		 5522016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
553
554 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
555
c0334580
AB		 5562016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
557
558 * elf/arc.h (EF_ARC_MACH): Delete.
559 (EF_ARC_MACH_MSK): Remove out of date comment.
560
24740d83
AB		 5612016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
562
563 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
564
4c10bbaa
L		 5652016-03-15 H.J. Lu <hongjiu.lu@intel.com>
566
567 PR ld/19807
568 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
569
72f3b6aa
CZ		 5702016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
571 Andrew Burgess <andrew.burgess@embecosm.com>
572
573 * elf/arc-reloc.def: Add a call to ME within the formula for each
574 relocation that requires middle-endian correction.
575
f86f5863
TS		 5762016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
577
578 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
579 * opcode/h8300.h (struct h8_opcode): Likewise.
580 * opcode/hppa.h (struct pa_opcode): Likewise.
581 * opcode/msp430.h: Likewise.
582 * opcode/spu.h (struct spu_opcode): Likewise.
583 * opcode/tic30.h (struct _register): Likewise.
584 * opcode/tic4x.h (struct tic4x_register): Likewise.
585 (struct tic4x_cond): Likewise.
586 (struct tic4x_indirect): Likewise.
587 (struct tic4x_inst): Likewise.
588 * opcode/visium.h (struct reg_entry): Likewise.
589
643afb90
MW		 5902016-03-04 Matthew Wahab <matthew.wahab@arm.com>
591
592 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
593 (ARM_CPU_HAS_FEATURE): Add comment.
594
3f1f41f5
L		 5952016-03-03 Than McIntosh <thanm@google.com>
596
597 * plugin-api.h: Add new hooks to the plugin transfer vector to
598 to support querying section alignment and section size.
599 (ld_plugin_get_input_section_alignment): New hook.
600 (ld_plugin_get_input_section_size): New hook.
601 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
602 and LDPT_GET_INPUT_SECTION_SIZE.
603 (ld_plugin_tv): Add tv_get_input_section_alignment and
604 tv_get_input_section_size.
605
9b738e36 6062016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 607
608 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
609
11e5f1ec
L		 6102016-02-26 H.J. Lu <hongjiu.lu@intel.com>
611
612 PR ld/19645
613 * bfdlink.h (bfd_link_elf_stt_common): New enum.
614 (bfd_link_info): Add elf_stt_common.
615
aec6b87e
L		 6162016-02-26 H.J. Lu <hongjiu.lu@intel.com>
617
618 PR ld/19636
619 PR ld/19704
620 PR ld/19719
621 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
622
b8ec4e87
JW		 6232016-02-19 Matthew Wahab <matthew.wahab@arm.com>
624 Jiong Wang <jiong.wang@arm.com>
625
626 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
627
4670103e
CZ		 6282016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
629 Janek van Oirschot <jvanoirs@synopsys.com>
630
b99747ae
CZ		 631 * opcode/arc.h (arc_opcode arc_relax_opcodes)
632 (arc_num_relax_opcodes): Declare.
4670103e 633
609332f1
NC		 6342016-02-09 Nick Clifton <nickc@redhat.com>
635
636 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
637 * opcode/nds32.h (nds32_r45map): Likewise.
638 (nds32_r54map): Likewise.
639 * opcode/visium.h (gen_reg_table): Likewise.
640 (fp_reg_table, cc_table, opcode_table): Likewise.
641
24f5f69a
AM		 6422016-02-09 Alan Modra <amodra@gmail.com>
643
644 PR 16583
645 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
646
c1d9289f
NC		 6472016-02-04 Nick Clifton <nickc@redhat.com>
648
649 PR target/19561
650 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
651 (RRUX): Synthesise using case 2 rather than 7.
652
f4ddf30f
JB		 6532016-01-19 John Baldwin <jhb@FreeBSD.org>
654
655 * elf/common.h (NT_FREEBSD_THRMISC): Define.
656 (NT_FREEBSD_PROCSTAT_PROC): Define.
657 (NT_FREEBSD_PROCSTAT_FILES): Define.
658 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
659 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
660 (NT_FREEBSD_PROCSTAT_UMASK): Define.
661 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
662 (NT_FREEBSD_PROCSTAT_OSREL): Define.
663 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
664 (NT_FREEBSD_PROCSTAT_AUXV): Define.
665
34e967a5
MC		 6662016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
667 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
668
669 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
670 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
671 (ARC_TLS_LE_32): Fixed formula.
672 (ARC_TLS_GD_LD): Use new special function.
673 * opcode/arc-func.h: Changed all the replacement
674 functions to clear the patching bits before doing an or it with the value
675 argument.
676
9ae678af
NC		 6772016-01-18 Nick Clifton <nickc@redhat.com>
678
679 PR ld/19440
680 * coff/internal.h (internal_syment): Use int to hold section
681 number.
682 (N_UNDEF): Cast to int not short.
683 (N_ABS): Likewise.
684 (N_DEBUG): Likewise.
685 (N_TV): Likewise.
686 (P_TV): Likewise.
687
4849dfd8
NC		 6882016-01-11 Nick Clifton <nickc@redhat.com>
689
690 Import this change from GCC mainline:
691
692 2016-01-07 Mike Frysinger <vapier@gentoo.org>
693
694 * longlong.h: Change !__SHMEDIA__ to
695 (!defined (__SHMEDIA__) || !__SHMEDIA__).
696 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
697
b31e4803
MR		 6982016-01-06 Maciej W. Rozycki <macro@imgtec.com>
699
700 * opcode/mips.h: Add a summary of MIPS16 operand codes.
701
b36c1ccb
MF		 7022016-01-05 Mike Frysinger <vapier@gentoo.org>
703
704 * libiberty.h (dupargv): Change arg to char * const *.
705 (writeargv, countargv): Likewise.
706
6f2750fe
AM		 7072016-01-01 Alan Modra <amodra@gmail.com>
708
709 Update year range in copyright notice of all files.
710
3499769a
AM		 711For older changes see ChangeLog-0415, aout/ChangeLog-9115,
712cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
713mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
714som/ChangeLog-1015, and vms/ChangeLog-1015
715\f
716Copyright (C) 2016 Free Software Foundation, Inc.
717
718Copying and distribution of this file, with or without modification,
719are permitted in any medium without royalty provided the copyright
720notice and this notice are preserved.
721
722Local Variables:
723mode: change-log
724left-margin: 8
725fill-column: 74
726version-control: never
727End:
GDB Binutils - Deliverables
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