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[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
c2c4ff8d
SN		 12016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
4 AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
5 (enum aarch64_op): Add OP_FCMLA_ELEM.
6
3f06e550
SN		 72016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
8
9 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
10 (enum aarch64_insn_class): Add ldst_imm10.
11
c84364ec
SN		 122016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
13
14 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
15
1924ff75
SN		 162016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
17
18 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
19 (AARCH64_ARCH_V8_3): Define.
20 (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
21
d46a2165
TP		 222016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
23
24 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
25 (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
26 (ARM_ARCH_V8M_MAIN_DSP): Likewise.
27
5a736821
GM		 282016-11-03 Graham Markall <graham.markall@embecosm.com>
29
30 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
31
bdfe53e3
AB		 322016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
33
34 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
35 fields.
36 (struct arc_long_opcode): Delete.
37 (struct arc_operand): Change types for insert and extract
38 handlers.
39
2e272202
GM		 402016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
41
42 * opcode/arc.h: Make macros 64-bit safe.
43
06fe285f
GM		 442016-11-03 Graham Markall <graham.markall@embecosm.com>
45
46 * opcode/arc.h (arc_opcode_len): Declare.
47 (ARC_SHORT): Delete.
48
e23eba97
NC		 492016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
50 Andrew Waterman <andrew@sifive.com>
51
52 Add support for RISC-V architecture.
53 * dis-asm.h: Add prototypes for print_insn_riscv and
54 print_riscv_disassembler_options.
55 * elf/riscv.h: New file.
56 * opcode/riscv-opc.h: New file.
57 * opcode/riscv.h: New file.
58
6d913794
NC		 592016-10-17 Nick Clifton <nickc@redhat.com>
60
61 * elf/common.h (DT_SYMTAB_SHNDX): Define.
62 (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
63 (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
64 (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
65 (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
66 (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
67 (ELFOSABI_OPENVOS): Define.
68 (GRP_MASKOS, GRP_MASKPROC): Define.
69
b4f6af8e
PA		 702016-10-14 Pedro Alves <palves@redhat.com>
71
72 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
73 OVERRIDE): Define as empty.
74 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
75 __final.
76 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
77 empty.
78
d118ee37
PA		 792016-10-14 Pedro Alves <palves@redhat.com>
80
81 * ansidecl.h (GCC_FINAL): Delete.
82 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
83
e5b06ef0
CZ		 842016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
85
86 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
87
a5721ba2
AM		 882016-09-29 Alan Modra <amodra@gmail.com>
89
90 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
91
2b848ebd
CZ		 922016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
93
94 * opcode/arc.h (insn_class_t): Add two new classes.
95
005d79fd
AM		 962016-09-26 Alan Modra <amodra@gmail.com>
97
98 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
99
bb7eff52
RS		 1002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
101
102 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
103
c0890d26
RS		 1042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
105
106 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
107 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
108 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
109 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
110
116b6019
RS		 1112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
112
113 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
114 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
115 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
116 aarch64_insn_classes.
117
047cd301
RS		 1182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
119
120 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
121 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
122 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
123
165d4950
RS		 1242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
125
126 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
127 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
128 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
129
e950b345
RS		 1302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
131
132 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
133 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
134 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
135 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
136 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
137 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
138 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
139 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
140 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
141 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
142 (aarch64_sve_dupm_mov_immediate_p): Declare.
143
98907a70
RS		 1442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
145
146 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
147 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
148 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
149 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
150 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
151
4df068de
RS		 1522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
153
154 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
155 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
156 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
157 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
158 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
159 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
160 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
161 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
162 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
163 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
164 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
165 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
166 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
167 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
168 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
169 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
170 Likewise.
171
2442d846
RS		 1722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
173
174 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
175 aarch64_opnd.
176 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
177 (aarch64_opnd_info): Make shifter.amount an int64_t and
178 rearrange the fields.
179
245d2e3f
RS		 1802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
181
182 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
183 (AARCH64_OPND_SVE_PRFOP): Likewise.
184 (aarch64_sve_pattern_array): Declare.
185 (aarch64_sve_prfop_array): Likewise.
186
d50c751e
RS		 1872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
188
189 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
190 (AARCH64_OPND_QLF_P_M): Likewise.
191
f11ad6bc
RS		 1922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
193
194 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
195 aarch64_operand_class.
196 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
197 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
198 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
199 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
200 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
201 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
202 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
203 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
204
0c608d6b
RS		 2052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
206
207 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
208 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
209
4989adac
RS		 2102016-09-21 Richard Sandiford <richard.sandiford@arm.com>
211
212 * opcode/aarch64.h (F_STRICT): New flag.
213
27e5a270
RE		 2142016-09-07 Richard Earnshaw <rearnsha@arm.com>
215
216 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
217
a87aa054
CM		 2182016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
219 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
220 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
221 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
222 relocation.
223
4ba2ef8f
TP		 2242016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
225
226 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
227 (ARM_SET_SYM_CMSE_SPCL): Likewise.
228
dfdaec14
AJ		 2292016-08-01 Andrew Jenner <andrew@codesourcery.com>
230
231 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
232
fa3fcee7
NC		 2332016-07-29 Aldy Hernandez <aldyh@redhat.com>
234
235 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
236
db18dbab
GM		 2372016-07-27 Graham Markall <graham.markall@embecosm.com>
238
239 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
240 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
241 ARC_NUM_ADDRTYPES.
242 * opcode/arc.h: Add BMU to insn_class_t enum.
243 * opcode/arc.h: Add PMU to insn_class_t enum.
244
37fd5ef3
CZ		 2452016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
246
247 * dis-asm.h: Declare print_arc_disassembler_options.
248
76359541
TP		 2492016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
250
251 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
252 out_implib_bfd fields.
253
fa1c0170
CZ		 2542016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
255
256 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
257
f0728ee3
AV		 2582016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
259
260 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
261 (SHF_ARM_PURECODE): ... this.
262
93d8990c
SN		 2632016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
264
265 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
266 (AARCH64_CPU_HAS_ANY_FEATURES): New.
267 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
268 (AARCH64_OPCODE_HAS_FEATURE): Remove.
269
534dbe46
MW		 2702016-06-30 Matthew Wahab <matthew.wahab@arm.com>
271
272 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
273 of enabled FPU features.
274
042c94de
TS		 2752016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
276
277 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
278 SPARC_OPCODE_ARCH_MAX into the enum.
279
dab26bf4
RS		 2802016-06-28 Richard Sandiford <richard.sandiford@arm.com>
281
282 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
283
c9775dde
MR		 2842016-06-28 Maciej W. Rozycki <macro@imgtec.com>
285
286 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
287
7c2c4aa1
TS		 2882016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
289
290 * elf/xtensa.h (xtensa_make_property_section): New prototype.
291
b00f86d0
JB		 2922016-06-24 John Baldwin <jhb@FreeBSD.org>
293
294 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
295 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
296 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
297 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
298
ce440d63
GM		 2992016-06-23 Graham Markall <graham.markall@embecosm.com>
300
301 * opcode/arc.h: Make insn_class_t alphabetical again.
302
6b477896
TS		 3032016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
304
305 * elf/dlx.h: Wrap in extern C.
306 * elf/xtensa.h: Likewise.
307 * opcode/arc.h: Likewise.
308
6edaf4d7
TS		 3092016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
310
311 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
312 tilegx_pipeline.
313
bdd582db
GM		 3142016-06-21 Graham Markall <graham.markall@embecosm.com>
315
316 * opcode/arc.h: Add nps400 extension and instruction
317 subclass.
318 Remove ARC_OPCODE_NPS400
319 * elf/arc.h: Remove E_ARC_MACH_NPS400
320
4f26fb3a
JM		 3212016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
322
323 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
324 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
325 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
326 SPARC_OPCODE_ARCH_V9M.
327
99a54ef6
JB		 3282016-06-14 John Baldwin <jhb@FreeBSD.org>
329
330 * opcode/msp430-decode.h (MSP430_Size): Remove.
331 (Msp430_Opcode_Decoded): Change type of size to int.
332
0eaf2e1b
AM		 3332016-06-11 Alan Modra <amodra@gmail.com>
334
335 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
336
337c570c
JM		 3372016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
338
339 * opcode/sparc.h: Add missing documentation for hyperprivileged
340 registers in rd (%) and rs1 ($).
341
14b57c7c
AM		 3422016-06-07 Alan Modra <amodra@gmail.com>
343
344 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
345 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
346 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
347 PPC_APUINFO_VLE: Define.
348
4d1464f2
MW		 3492016-06-07 Matthew Wahab <matthew.wahab@arm.com>
350
351 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
352 entries.
353 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
354
4eb6f892
AB		 3552016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
356
357 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
358 (struct arc_long_opcode): New structure.
359 (arc_long_opcodes): Declare.
360 (arc_num_long_opcodes): Declare.
361
1fe0971e
TS		 3622016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
363
364 * elf/mips.h: Add extern "C".
365 * elf/sh.h: Likewise.
366 * opcode/d10v.h: Likewise.
367 * opcode/d30v.h: Likewise.
368 * opcode/ia64.h: Likewise.
369 * opcode/mips.h: Likewise.
370 * opcode/ppc.h: Likewise.
371 * opcode/sparc.h: Likewise.
372 * opcode/tic6x.h: Likewise.
373 * opcode/v850.h: Likewise.
374
1a72702b
AM		 3752016-05-28 Alan Modra <amodra@gmail.com>
376
377 * bfdlink.h (struct bfd_link_callbacks): Update comments.
378 Return void from multiple_definition, multiple_common,
379 add_to_set, constructor, warning, undefined_symbol,
380 reloc_overflow, reloc_dangerous and unattached_reloc.
381
94740f9c
TS		 3822016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
383
384 * opcode/metag.h: wrap declarations in extern "C".
385
d9eca1df
CZ		 3862016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
387
388 * opcode/arc.h (insn_subclass_t): Add COND.
389 (flag_class_t): Add F_CLASS_EXTEND.
390
c810e0b8
CZ		 3912016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
392
393 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
394 insn_class.
395 (struct arc_flag_class): Renamed attribute class to flag_class.
396
3d207518
TS		 3972016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
398
399 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
400 plain symbol.
401
5ff087ac
TT		 4022016-04-29 Tom Tromey <tom@tromey.com>
403
404 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
405 DW_LANG_Rust_old>: New constants.
406
8f4f9071
MF		 4072016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
408
409 * elf/mips.h (AFL_ASE_DSPR3): New macro.
410 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
411 * opcode/mips.h (ASE_DSPR3): New macro.
412
39d911fc
TP		 4132016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
414 Nick Clifton <nickc@redhat.com>
415
416 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
417 enumerator.
418 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
419 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
420 (ARM_SYM_BRANCH_TYPE): Replace by ...
421 (ARM_GET_SYM_BRANCH_TYPE): This and ...
422 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
423 BFD_ASSERT is defined or not.
424
15afaa63
TP		 4252016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
426
427 * elf/arm.h (Tag_DSP_extension): Define.
428
d942732e
TP		 4292016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
430
431 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
432
16a1fa25
TP		 4332016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
434
435 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
436 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
437 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
438 for the high core bits.
439
945e0f82
CZ		 4402016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
441
442 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
443 (ARC_SYNTAX_NOP): Likewsie.
444 (ARC_OP1_MUST_BE_IMM): Update defined value.
445 (ARC_OP1_IMM_IMPLIED): Likewise.
446 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
447
4bd13cde
NC		 4482016-04-28 Nick Clifton <nickc@redhat.com>
449
450 PR target/19722
451 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
452
a6a4679f
AM		 4532016-04-27 Alan Modra <amodra@gmail.com>
454
455 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
456 undef. Formatting.
457
4f3b23b3
NC		 4582016-04-21 Nick Clifton <nickc@redhat.com>
459
460 * bfdlink.h: Add prototype for bfd_link_check_relocs.
461
d9689752
L		 4622016-04-20 H.J. Lu <hongjiu.lu@intel.com>
463
464 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
465
52176c67
AB		 4662016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
467
468 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
469
537aefaf
AB		 4702016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
471
472 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
473
c8f785f2
AB		 4742016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
475
476 * opcode/arc.h (insn_class_t): Add NET and ACL class.
477
4b0c052e
AB		 4782016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
479
480 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
481 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
482
f36e33da
CZ		 4832016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
484
485 * opcode/arc.h (flag_class_t): Update.
486 (ARC_OPCODE_NONE): Define.
487 (ARC_OPCODE_ARCALL): Likewise.
488 (ARC_OPCODE_ARCFPX): Likewise.
489 (ARC_REGISTER_READONLY): Likewise.
490 (ARC_REGISTER_WRITEONLY): Likewise.
491 (ARC_REGISTER_NOSHORT_CUT): Likewise.
492 (arc_aux_reg): Add cpu.
493
b99747ae
CZ		 4942016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
495
496 * opcode/arc.h (arc_num_opcodes): Remove.
497 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
498 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
499 (ARC_SUFFIX_FLAG): Define.
500 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
501 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
502 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
503 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
504 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
505 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
506 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
507 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
508 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
509 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
510
5112016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
512
513 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
514 (ARC_FPUDA): Define.
515 (arc_aux_reg): Add new field.
516
5172016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 518
519 * opcode/arc-func.h (replace_bits24): Changed.
520 (replace_bits24_be): Created.
521
f2dd8838
CZ		 5222016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
523
b99747ae
CZ		 524 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
525 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
526 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
527 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
528 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
529 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
530 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
531 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
532 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
533 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
534 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
535 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
536 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
537 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 538
b9bb4a93
TS		 5392016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
540
541 * opcode/i960.h: Add const qualifiers.
542 * opcode/tic4x.h (struct tic4x_inst): Likewise.
543
e23e8ebe
AB		 5442016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
545
546 * opcodes/arc.h (insn_class_t): Add BITOP type.
547
1ae8ab47
AB		 5482016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
549
550 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
551 new classes instead.
552
8699fc3e
AB		 5532016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
554
555 * elf/arc.h (E_ARC_MACH_NPS400): Define.
556 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
557
a9522a21
AB		 5582016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
559
560 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
561
c0334580
AB		 5622016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
563
564 * elf/arc.h (EF_ARC_MACH): Delete.
565 (EF_ARC_MACH_MSK): Remove out of date comment.
566
24740d83
AB		 5672016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
568
569 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
570
4c10bbaa
L		 5712016-03-15 H.J. Lu <hongjiu.lu@intel.com>
572
573 PR ld/19807
574 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
575
72f3b6aa
CZ		 5762016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
577 Andrew Burgess <andrew.burgess@embecosm.com>
578
579 * elf/arc-reloc.def: Add a call to ME within the formula for each
580 relocation that requires middle-endian correction.
581
f86f5863
TS		 5822016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
583
584 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
585 * opcode/h8300.h (struct h8_opcode): Likewise.
586 * opcode/hppa.h (struct pa_opcode): Likewise.
587 * opcode/msp430.h: Likewise.
588 * opcode/spu.h (struct spu_opcode): Likewise.
589 * opcode/tic30.h (struct _register): Likewise.
590 * opcode/tic4x.h (struct tic4x_register): Likewise.
591 (struct tic4x_cond): Likewise.
592 (struct tic4x_indirect): Likewise.
593 (struct tic4x_inst): Likewise.
594 * opcode/visium.h (struct reg_entry): Likewise.
595
643afb90
MW		 5962016-03-04 Matthew Wahab <matthew.wahab@arm.com>
597
598 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
599 (ARM_CPU_HAS_FEATURE): Add comment.
600
3f1f41f5
L		 6012016-03-03 Than McIntosh <thanm@google.com>
602
603 * plugin-api.h: Add new hooks to the plugin transfer vector to
604 to support querying section alignment and section size.
605 (ld_plugin_get_input_section_alignment): New hook.
606 (ld_plugin_get_input_section_size): New hook.
607 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
608 and LDPT_GET_INPUT_SECTION_SIZE.
609 (ld_plugin_tv): Add tv_get_input_section_alignment and
610 tv_get_input_section_size.
611
9b738e36 6122016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 613
614 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
615
11e5f1ec
L		 6162016-02-26 H.J. Lu <hongjiu.lu@intel.com>
617
618 PR ld/19645
619 * bfdlink.h (bfd_link_elf_stt_common): New enum.
620 (bfd_link_info): Add elf_stt_common.
621
aec6b87e
L		 6222016-02-26 H.J. Lu <hongjiu.lu@intel.com>
623
624 PR ld/19636
625 PR ld/19704
626 PR ld/19719
627 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
628
b8ec4e87
JW		 6292016-02-19 Matthew Wahab <matthew.wahab@arm.com>
630 Jiong Wang <jiong.wang@arm.com>
631
632 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
633
4670103e
CZ		 6342016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
635 Janek van Oirschot <jvanoirs@synopsys.com>
636
b99747ae
CZ		 637 * opcode/arc.h (arc_opcode arc_relax_opcodes)
638 (arc_num_relax_opcodes): Declare.
4670103e 639
609332f1
NC		 6402016-02-09 Nick Clifton <nickc@redhat.com>
641
642 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
643 * opcode/nds32.h (nds32_r45map): Likewise.
644 (nds32_r54map): Likewise.
645 * opcode/visium.h (gen_reg_table): Likewise.
646 (fp_reg_table, cc_table, opcode_table): Likewise.
647
24f5f69a
AM		 6482016-02-09 Alan Modra <amodra@gmail.com>
649
650 PR 16583
651 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
652
c1d9289f
NC		 6532016-02-04 Nick Clifton <nickc@redhat.com>
654
655 PR target/19561
656 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
657 (RRUX): Synthesise using case 2 rather than 7.
658
f4ddf30f
JB		 6592016-01-19 John Baldwin <jhb@FreeBSD.org>
660
661 * elf/common.h (NT_FREEBSD_THRMISC): Define.
662 (NT_FREEBSD_PROCSTAT_PROC): Define.
663 (NT_FREEBSD_PROCSTAT_FILES): Define.
664 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
665 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
666 (NT_FREEBSD_PROCSTAT_UMASK): Define.
667 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
668 (NT_FREEBSD_PROCSTAT_OSREL): Define.
669 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
670 (NT_FREEBSD_PROCSTAT_AUXV): Define.
671
34e967a5
MC		 6722016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
673 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
674
675 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
676 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
677 (ARC_TLS_LE_32): Fixed formula.
678 (ARC_TLS_GD_LD): Use new special function.
679 * opcode/arc-func.h: Changed all the replacement
680 functions to clear the patching bits before doing an or it with the value
681 argument.
682
9ae678af
NC		 6832016-01-18 Nick Clifton <nickc@redhat.com>
684
685 PR ld/19440
686 * coff/internal.h (internal_syment): Use int to hold section
687 number.
688 (N_UNDEF): Cast to int not short.
689 (N_ABS): Likewise.
690 (N_DEBUG): Likewise.
691 (N_TV): Likewise.
692 (P_TV): Likewise.
693
4849dfd8
NC		 6942016-01-11 Nick Clifton <nickc@redhat.com>
695
696 Import this change from GCC mainline:
697
698 2016-01-07 Mike Frysinger <vapier@gentoo.org>
699
700 * longlong.h: Change !__SHMEDIA__ to
701 (!defined (__SHMEDIA__) || !__SHMEDIA__).
702 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
703
b31e4803
MR		 7042016-01-06 Maciej W. Rozycki <macro@imgtec.com>
705
706 * opcode/mips.h: Add a summary of MIPS16 operand codes.
707
b36c1ccb
MF		 7082016-01-05 Mike Frysinger <vapier@gentoo.org>
709
710 * libiberty.h (dupargv): Change arg to char * const *.
711 (writeargv, countargv): Likewise.
712
6f2750fe
AM		 7132016-01-01 Alan Modra <amodra@gmail.com>
714
715 Update year range in copyright notice of all files.
716
3499769a
AM		 717For older changes see ChangeLog-0415, aout/ChangeLog-9115,
718cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
719mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
720som/ChangeLog-1015, and vms/ChangeLog-1015
721\f
722Copyright (C) 2016 Free Software Foundation, Inc.
723
724Copying and distribution of this file, with or without modification,
725are permitted in any medium without royalty provided the copyright
726notice and this notice are preserved.
727
728Local Variables:
729mode: change-log
730left-margin: 8
731fill-column: 74
732version-control: never
733End:
GDB Binutils - Deliverables
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