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[AArch64] Add ARMv8.3 PACGA instruction
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
c84364ec
SN		 12016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
4
1924ff75
SN		 52016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
6
7 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
8 (AARCH64_ARCH_V8_3): Define.
9 (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
10
d46a2165
TP		 112016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
12
13 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
14 (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
15 (ARM_ARCH_V8M_MAIN_DSP): Likewise.
16
5a736821
GM		 172016-11-03 Graham Markall <graham.markall@embecosm.com>
18
19 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
20
bdfe53e3
AB		 212016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
22
23 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
24 fields.
25 (struct arc_long_opcode): Delete.
26 (struct arc_operand): Change types for insert and extract
27 handlers.
28
2e272202
GM		 292016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
30
31 * opcode/arc.h: Make macros 64-bit safe.
32
06fe285f
GM		 332016-11-03 Graham Markall <graham.markall@embecosm.com>
34
35 * opcode/arc.h (arc_opcode_len): Declare.
36 (ARC_SHORT): Delete.
37
e23eba97
NC		 382016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
39 Andrew Waterman <andrew@sifive.com>
40
41 Add support for RISC-V architecture.
42 * dis-asm.h: Add prototypes for print_insn_riscv and
43 print_riscv_disassembler_options.
44 * elf/riscv.h: New file.
45 * opcode/riscv-opc.h: New file.
46 * opcode/riscv.h: New file.
47
6d913794
NC		 482016-10-17 Nick Clifton <nickc@redhat.com>
49
50 * elf/common.h (DT_SYMTAB_SHNDX): Define.
51 (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
52 (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
53 (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
54 (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
55 (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
56 (ELFOSABI_OPENVOS): Define.
57 (GRP_MASKOS, GRP_MASKPROC): Define.
58
b4f6af8e
PA		 592016-10-14 Pedro Alves <palves@redhat.com>
60
61 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
62 OVERRIDE): Define as empty.
63 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
64 __final.
65 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
66 empty.
67
d118ee37
PA		 682016-10-14 Pedro Alves <palves@redhat.com>
69
70 * ansidecl.h (GCC_FINAL): Delete.
71 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
72
e5b06ef0
CZ		 732016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
74
75 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
76
a5721ba2
AM		 772016-09-29 Alan Modra <amodra@gmail.com>
78
79 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
80
2b848ebd
CZ		 812016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
82
83 * opcode/arc.h (insn_class_t): Add two new classes.
84
005d79fd
AM		 852016-09-26 Alan Modra <amodra@gmail.com>
86
87 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
88
bb7eff52
RS		 892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
90
91 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
92
c0890d26
RS		 932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
94
95 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
96 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
97 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
98 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
99
116b6019
RS		 1002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
101
102 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
103 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
104 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
105 aarch64_insn_classes.
106
047cd301
RS		 1072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
108
109 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
110 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
111 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
112
165d4950
RS		 1132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
114
115 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
116 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
117 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
118
e950b345
RS		 1192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
120
121 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
122 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
123 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
124 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
125 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
126 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
127 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
128 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
129 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
130 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
131 (aarch64_sve_dupm_mov_immediate_p): Declare.
132
98907a70
RS		 1332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
134
135 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
136 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
137 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
138 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
139 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
140
4df068de
RS		 1412016-09-21 Richard Sandiford <richard.sandiford@arm.com>
142
143 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
144 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
145 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
146 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
147 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
148 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
149 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
150 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
151 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
152 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
153 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
154 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
155 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
156 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
157 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
158 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
159 Likewise.
160
2442d846
RS		 1612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
162
163 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
164 aarch64_opnd.
165 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
166 (aarch64_opnd_info): Make shifter.amount an int64_t and
167 rearrange the fields.
168
245d2e3f
RS		 1692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
170
171 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
172 (AARCH64_OPND_SVE_PRFOP): Likewise.
173 (aarch64_sve_pattern_array): Declare.
174 (aarch64_sve_prfop_array): Likewise.
175
d50c751e
RS		 1762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
177
178 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
179 (AARCH64_OPND_QLF_P_M): Likewise.
180
f11ad6bc
RS		 1812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
182
183 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
184 aarch64_operand_class.
185 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
186 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
187 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
188 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
189 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
190 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
191 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
192 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
193
0c608d6b
RS		 1942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
195
196 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
197 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
198
4989adac
RS		 1992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
200
201 * opcode/aarch64.h (F_STRICT): New flag.
202
27e5a270
RE		 2032016-09-07 Richard Earnshaw <rearnsha@arm.com>
204
205 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
206
a87aa054
CM		 2072016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
208 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
209 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
210 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
211 relocation.
212
4ba2ef8f
TP		 2132016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
214
215 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
216 (ARM_SET_SYM_CMSE_SPCL): Likewise.
217
dfdaec14
AJ		 2182016-08-01 Andrew Jenner <andrew@codesourcery.com>
219
220 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
221
fa3fcee7
NC		 2222016-07-29 Aldy Hernandez <aldyh@redhat.com>
223
224 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
225
db18dbab
GM		 2262016-07-27 Graham Markall <graham.markall@embecosm.com>
227
228 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
229 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
230 ARC_NUM_ADDRTYPES.
231 * opcode/arc.h: Add BMU to insn_class_t enum.
232 * opcode/arc.h: Add PMU to insn_class_t enum.
233
37fd5ef3
CZ		 2342016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
235
236 * dis-asm.h: Declare print_arc_disassembler_options.
237
76359541
TP		 2382016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
239
240 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
241 out_implib_bfd fields.
242
fa1c0170
CZ		 2432016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
244
245 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
246
f0728ee3
AV		 2472016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
248
249 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
250 (SHF_ARM_PURECODE): ... this.
251
93d8990c
SN		 2522016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
253
254 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
255 (AARCH64_CPU_HAS_ANY_FEATURES): New.
256 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
257 (AARCH64_OPCODE_HAS_FEATURE): Remove.
258
534dbe46
MW		 2592016-06-30 Matthew Wahab <matthew.wahab@arm.com>
260
261 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
262 of enabled FPU features.
263
042c94de
TS		 2642016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
265
266 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
267 SPARC_OPCODE_ARCH_MAX into the enum.
268
dab26bf4
RS		 2692016-06-28 Richard Sandiford <richard.sandiford@arm.com>
270
271 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
272
c9775dde
MR		 2732016-06-28 Maciej W. Rozycki <macro@imgtec.com>
274
275 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
276
7c2c4aa1
TS		 2772016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
278
279 * elf/xtensa.h (xtensa_make_property_section): New prototype.
280
b00f86d0
JB		 2812016-06-24 John Baldwin <jhb@FreeBSD.org>
282
283 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
284 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
285 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
286 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
287
ce440d63
GM		 2882016-06-23 Graham Markall <graham.markall@embecosm.com>
289
290 * opcode/arc.h: Make insn_class_t alphabetical again.
291
6b477896
TS		 2922016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
293
294 * elf/dlx.h: Wrap in extern C.
295 * elf/xtensa.h: Likewise.
296 * opcode/arc.h: Likewise.
297
6edaf4d7
TS		 2982016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
299
300 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
301 tilegx_pipeline.
302
bdd582db
GM		 3032016-06-21 Graham Markall <graham.markall@embecosm.com>
304
305 * opcode/arc.h: Add nps400 extension and instruction
306 subclass.
307 Remove ARC_OPCODE_NPS400
308 * elf/arc.h: Remove E_ARC_MACH_NPS400
309
4f26fb3a
JM		 3102016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
311
312 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
313 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
314 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
315 SPARC_OPCODE_ARCH_V9M.
316
99a54ef6
JB		 3172016-06-14 John Baldwin <jhb@FreeBSD.org>
318
319 * opcode/msp430-decode.h (MSP430_Size): Remove.
320 (Msp430_Opcode_Decoded): Change type of size to int.
321
0eaf2e1b
AM		 3222016-06-11 Alan Modra <amodra@gmail.com>
323
324 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
325
337c570c
JM		 3262016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
327
328 * opcode/sparc.h: Add missing documentation for hyperprivileged
329 registers in rd (%) and rs1 ($).
330
14b57c7c
AM		 3312016-06-07 Alan Modra <amodra@gmail.com>
332
333 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
334 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
335 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
336 PPC_APUINFO_VLE: Define.
337
4d1464f2
MW		 3382016-06-07 Matthew Wahab <matthew.wahab@arm.com>
339
340 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
341 entries.
342 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
343
4eb6f892
AB		 3442016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
345
346 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
347 (struct arc_long_opcode): New structure.
348 (arc_long_opcodes): Declare.
349 (arc_num_long_opcodes): Declare.
350
1fe0971e
TS		 3512016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
352
353 * elf/mips.h: Add extern "C".
354 * elf/sh.h: Likewise.
355 * opcode/d10v.h: Likewise.
356 * opcode/d30v.h: Likewise.
357 * opcode/ia64.h: Likewise.
358 * opcode/mips.h: Likewise.
359 * opcode/ppc.h: Likewise.
360 * opcode/sparc.h: Likewise.
361 * opcode/tic6x.h: Likewise.
362 * opcode/v850.h: Likewise.
363
1a72702b
AM		 3642016-05-28 Alan Modra <amodra@gmail.com>
365
366 * bfdlink.h (struct bfd_link_callbacks): Update comments.
367 Return void from multiple_definition, multiple_common,
368 add_to_set, constructor, warning, undefined_symbol,
369 reloc_overflow, reloc_dangerous and unattached_reloc.
370
94740f9c
TS		 3712016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
372
373 * opcode/metag.h: wrap declarations in extern "C".
374
d9eca1df
CZ		 3752016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
376
377 * opcode/arc.h (insn_subclass_t): Add COND.
378 (flag_class_t): Add F_CLASS_EXTEND.
379
c810e0b8
CZ		 3802016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
381
382 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
383 insn_class.
384 (struct arc_flag_class): Renamed attribute class to flag_class.
385
3d207518
TS		 3862016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
387
388 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
389 plain symbol.
390
5ff087ac
TT		 3912016-04-29 Tom Tromey <tom@tromey.com>
392
393 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
394 DW_LANG_Rust_old>: New constants.
395
8f4f9071
MF		 3962016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
397
398 * elf/mips.h (AFL_ASE_DSPR3): New macro.
399 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
400 * opcode/mips.h (ASE_DSPR3): New macro.
401
39d911fc
TP		 4022016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
403 Nick Clifton <nickc@redhat.com>
404
405 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
406 enumerator.
407 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
408 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
409 (ARM_SYM_BRANCH_TYPE): Replace by ...
410 (ARM_GET_SYM_BRANCH_TYPE): This and ...
411 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
412 BFD_ASSERT is defined or not.
413
15afaa63
TP		 4142016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
415
416 * elf/arm.h (Tag_DSP_extension): Define.
417
d942732e
TP		 4182016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
419
420 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
421
16a1fa25
TP		 4222016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
423
424 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
425 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
426 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
427 for the high core bits.
428
945e0f82
CZ		 4292016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
430
431 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
432 (ARC_SYNTAX_NOP): Likewsie.
433 (ARC_OP1_MUST_BE_IMM): Update defined value.
434 (ARC_OP1_IMM_IMPLIED): Likewise.
435 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
436
4bd13cde
NC		 4372016-04-28 Nick Clifton <nickc@redhat.com>
438
439 PR target/19722
440 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
441
a6a4679f
AM		 4422016-04-27 Alan Modra <amodra@gmail.com>
443
444 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
445 undef. Formatting.
446
4f3b23b3
NC		 4472016-04-21 Nick Clifton <nickc@redhat.com>
448
449 * bfdlink.h: Add prototype for bfd_link_check_relocs.
450
d9689752
L		 4512016-04-20 H.J. Lu <hongjiu.lu@intel.com>
452
453 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
454
52176c67
AB		 4552016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
456
457 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
458
537aefaf
AB		 4592016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
460
461 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
462
c8f785f2
AB		 4632016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
464
465 * opcode/arc.h (insn_class_t): Add NET and ACL class.
466
4b0c052e
AB		 4672016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
468
469 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
470 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
471
f36e33da
CZ		 4722016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
473
474 * opcode/arc.h (flag_class_t): Update.
475 (ARC_OPCODE_NONE): Define.
476 (ARC_OPCODE_ARCALL): Likewise.
477 (ARC_OPCODE_ARCFPX): Likewise.
478 (ARC_REGISTER_READONLY): Likewise.
479 (ARC_REGISTER_WRITEONLY): Likewise.
480 (ARC_REGISTER_NOSHORT_CUT): Likewise.
481 (arc_aux_reg): Add cpu.
482
b99747ae
CZ		 4832016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
484
485 * opcode/arc.h (arc_num_opcodes): Remove.
486 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
487 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
488 (ARC_SUFFIX_FLAG): Define.
489 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
490 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
491 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
492 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
493 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
494 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
495 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
496 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
497 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
498 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
499
5002016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
501
502 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
503 (ARC_FPUDA): Define.
504 (arc_aux_reg): Add new field.
505
5062016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 507
508 * opcode/arc-func.h (replace_bits24): Changed.
509 (replace_bits24_be): Created.
510
f2dd8838
CZ		 5112016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
512
b99747ae
CZ		 513 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
514 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
515 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
516 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
517 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
518 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
519 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
520 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
521 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
522 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
523 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
524 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
525 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
526 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 527
b9bb4a93
TS		 5282016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
529
530 * opcode/i960.h: Add const qualifiers.
531 * opcode/tic4x.h (struct tic4x_inst): Likewise.
532
e23e8ebe
AB		 5332016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
534
535 * opcodes/arc.h (insn_class_t): Add BITOP type.
536
1ae8ab47
AB		 5372016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
538
539 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
540 new classes instead.
541
8699fc3e
AB		 5422016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
543
544 * elf/arc.h (E_ARC_MACH_NPS400): Define.
545 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
546
a9522a21
AB		 5472016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
548
549 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
550
c0334580
AB		 5512016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
552
553 * elf/arc.h (EF_ARC_MACH): Delete.
554 (EF_ARC_MACH_MSK): Remove out of date comment.
555
24740d83
AB		 5562016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
557
558 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
559
4c10bbaa
L		 5602016-03-15 H.J. Lu <hongjiu.lu@intel.com>
561
562 PR ld/19807
563 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
564
72f3b6aa
CZ		 5652016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
566 Andrew Burgess <andrew.burgess@embecosm.com>
567
568 * elf/arc-reloc.def: Add a call to ME within the formula for each
569 relocation that requires middle-endian correction.
570
f86f5863
TS		 5712016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
572
573 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
574 * opcode/h8300.h (struct h8_opcode): Likewise.
575 * opcode/hppa.h (struct pa_opcode): Likewise.
576 * opcode/msp430.h: Likewise.
577 * opcode/spu.h (struct spu_opcode): Likewise.
578 * opcode/tic30.h (struct _register): Likewise.
579 * opcode/tic4x.h (struct tic4x_register): Likewise.
580 (struct tic4x_cond): Likewise.
581 (struct tic4x_indirect): Likewise.
582 (struct tic4x_inst): Likewise.
583 * opcode/visium.h (struct reg_entry): Likewise.
584
643afb90
MW		 5852016-03-04 Matthew Wahab <matthew.wahab@arm.com>
586
587 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
588 (ARM_CPU_HAS_FEATURE): Add comment.
589
3f1f41f5
L		 5902016-03-03 Than McIntosh <thanm@google.com>
591
592 * plugin-api.h: Add new hooks to the plugin transfer vector to
593 to support querying section alignment and section size.
594 (ld_plugin_get_input_section_alignment): New hook.
595 (ld_plugin_get_input_section_size): New hook.
596 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
597 and LDPT_GET_INPUT_SECTION_SIZE.
598 (ld_plugin_tv): Add tv_get_input_section_alignment and
599 tv_get_input_section_size.
600
9b738e36 6012016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 602
603 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
604
11e5f1ec
L		 6052016-02-26 H.J. Lu <hongjiu.lu@intel.com>
606
607 PR ld/19645
608 * bfdlink.h (bfd_link_elf_stt_common): New enum.
609 (bfd_link_info): Add elf_stt_common.
610
aec6b87e
L		 6112016-02-26 H.J. Lu <hongjiu.lu@intel.com>
612
613 PR ld/19636
614 PR ld/19704
615 PR ld/19719
616 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
617
b8ec4e87
JW		 6182016-02-19 Matthew Wahab <matthew.wahab@arm.com>
619 Jiong Wang <jiong.wang@arm.com>
620
621 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
622
4670103e
CZ		 6232016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
624 Janek van Oirschot <jvanoirs@synopsys.com>
625
b99747ae
CZ		 626 * opcode/arc.h (arc_opcode arc_relax_opcodes)
627 (arc_num_relax_opcodes): Declare.
4670103e 628
609332f1
NC		 6292016-02-09 Nick Clifton <nickc@redhat.com>
630
631 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
632 * opcode/nds32.h (nds32_r45map): Likewise.
633 (nds32_r54map): Likewise.
634 * opcode/visium.h (gen_reg_table): Likewise.
635 (fp_reg_table, cc_table, opcode_table): Likewise.
636
24f5f69a
AM		 6372016-02-09 Alan Modra <amodra@gmail.com>
638
639 PR 16583
640 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
641
c1d9289f
NC		 6422016-02-04 Nick Clifton <nickc@redhat.com>
643
644 PR target/19561
645 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
646 (RRUX): Synthesise using case 2 rather than 7.
647
f4ddf30f
JB		 6482016-01-19 John Baldwin <jhb@FreeBSD.org>
649
650 * elf/common.h (NT_FREEBSD_THRMISC): Define.
651 (NT_FREEBSD_PROCSTAT_PROC): Define.
652 (NT_FREEBSD_PROCSTAT_FILES): Define.
653 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
654 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
655 (NT_FREEBSD_PROCSTAT_UMASK): Define.
656 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
657 (NT_FREEBSD_PROCSTAT_OSREL): Define.
658 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
659 (NT_FREEBSD_PROCSTAT_AUXV): Define.
660
34e967a5
MC		 6612016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
662 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
663
664 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
665 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
666 (ARC_TLS_LE_32): Fixed formula.
667 (ARC_TLS_GD_LD): Use new special function.
668 * opcode/arc-func.h: Changed all the replacement
669 functions to clear the patching bits before doing an or it with the value
670 argument.
671
9ae678af
NC		 6722016-01-18 Nick Clifton <nickc@redhat.com>
673
674 PR ld/19440
675 * coff/internal.h (internal_syment): Use int to hold section
676 number.
677 (N_UNDEF): Cast to int not short.
678 (N_ABS): Likewise.
679 (N_DEBUG): Likewise.
680 (N_TV): Likewise.
681 (P_TV): Likewise.
682
4849dfd8
NC		 6832016-01-11 Nick Clifton <nickc@redhat.com>
684
685 Import this change from GCC mainline:
686
687 2016-01-07 Mike Frysinger <vapier@gentoo.org>
688
689 * longlong.h: Change !__SHMEDIA__ to
690 (!defined (__SHMEDIA__) || !__SHMEDIA__).
691 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
692
b31e4803
MR		 6932016-01-06 Maciej W. Rozycki <macro@imgtec.com>
694
695 * opcode/mips.h: Add a summary of MIPS16 operand codes.
696
b36c1ccb
MF		 6972016-01-05 Mike Frysinger <vapier@gentoo.org>
698
699 * libiberty.h (dupargv): Change arg to char * const *.
700 (writeargv, countargv): Likewise.
701
6f2750fe
AM		 7022016-01-01 Alan Modra <amodra@gmail.com>
703
704 Update year range in copyright notice of all files.
705
3499769a
AM		 706For older changes see ChangeLog-0415, aout/ChangeLog-9115,
707cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
708mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
709som/ChangeLog-1015, and vms/ChangeLog-1015
710\f
711Copyright (C) 2016 Free Software Foundation, Inc.
712
713Copying and distribution of this file, with or without modification,
714are permitted in any medium without royalty provided the copyright
715notice and this notice are preserved.
716
717Local Variables:
718mode: change-log
719left-margin: 8
720fill-column: 74
721version-control: never
722End:
GDB Binutils - Deliverables
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