[deliverable/linux.git] / include / asm-ia64 / sn / tioca_provider.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H

#include <asm/sn/tioca.h>

/*
 * WAR enables
 * Defines for individual WARs. Each is a bitmask of applicable
 * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
 * (3 << 1) == (rev A or rev B), etc
 */

#define TIOCA_WAR_ENABLED(pv, tioca_common) \
	((1 << tioca_common->ca_rev) & pv)

  /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
#define PV907908 (1 << 1)
  /* ATI config space problems after BIOS execution starts */
#define PV908234 (1 << 1)
  /* CA:AGPDMA write request data mismatch with ABC1CL merge */
#define PV895469 (1 << 1)
  /* TIO:CA TLB invalidate of written GART entries possibly not occuring in CA*/
#define PV910244 (1 << 1)

struct tioca_dmamap{
	struct list_head	cad_list;	/* headed by ca_list */

	dma_addr_t		cad_dma_addr;	/* Linux dma handle */
	uint			cad_gart_entry; /* start entry in ca_gart_pagemap */
	uint			cad_gart_size;	/* #entries for this map */
};

/*
 * Kernel only fields.  Prom may look at this stuff for debugging only.
 * Access this structure through the ca_kernel_private ptr.
 */

struct tioca_common ;

struct tioca_kernel {
	struct tioca_common	*ca_common;	/* tioca this belongs to */
	struct list_head	ca_list;	/* list of all ca's */
	struct list_head	ca_dmamaps;
	spinlock_t		ca_lock;	/* Kernel lock */
	cnodeid_t		ca_closest_node;
	struct list_head	*ca_devices;	/* bus->devices */

	/*
	 * General GART stuff
	 */
	uint64_t	ca_ap_size;		/* size of aperature in bytes */
	uint32_t	ca_gart_entries;	/* # uint64_t entries in gart */
	uint32_t	ca_ap_pagesize; 	/* aperature page size in bytes */
	uint64_t	ca_ap_bus_base; 	/* bus address of CA aperature */
	uint64_t	ca_gart_size;		/* gart size in bytes */
	uint64_t	*ca_gart;		/* gart table vaddr */
	uint64_t	ca_gart_coretalk_addr;	/* gart coretalk addr */
	uint8_t		ca_gart_iscoherent;	/* used in tioca_tlbflush */

	/* PCI GART convenience values */
	uint64_t	ca_pciap_base;		/* pci aperature bus base address */
	uint64_t	ca_pciap_size;		/* pci aperature size (bytes) */
	uint64_t	ca_pcigart_base;	/* gfx GART bus base address */
	uint64_t	*ca_pcigart;		/* gfx GART vm address */
	uint32_t	ca_pcigart_entries;
	uint32_t	ca_pcigart_start;	/* PCI start index in ca_gart */
	void		*ca_pcigart_pagemap;

	/* AGP GART convenience values */
	uint64_t	ca_gfxap_base;		/* gfx aperature bus base address */
	uint64_t	ca_gfxap_size;		/* gfx aperature size (bytes) */
	uint64_t	ca_gfxgart_base;	/* gfx GART bus base address */
	uint64_t	*ca_gfxgart;		/* gfx GART vm address */
	uint32_t	ca_gfxgart_entries;
	uint32_t	ca_gfxgart_start;	/* agpgart start index in ca_gart */
};

/*
 * Common tioca info shared between kernel and prom
 *
 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
 * TO THE PROM VERSION.
 */

struct tioca_common {
	struct pcibus_bussoft	ca_common;	/* common pciio header */

	uint32_t		ca_rev;
	uint32_t		ca_closest_nasid;

	uint64_t		ca_prom_private;
	uint64_t		ca_kernel_private;
};

/**
 * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
 * @paddr: page address to convert
 *
 * Convert a system [coretalk] address to a GART entry.  GART entries are
 * formed using the following:
 *
 *     data = ( (1<<63) |  ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) | 
 * (REMAP_SYS_ADDR) ) >> 12 )
 *
 * DATA written to 1 GART TABLE Entry in system memory is remapped system
 * addr for 1 page 
 *
 * The data is for coretalk address format right shifted 12 bits with a
 * valid bit.
 *
 *	GART_TABLE_ENTRY [ 25:0 ]  -- REMAP_SYS_ADDRESS[37:12].
 *	GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
 *	GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
 *	GART_TABLE_ENTRY [ 63 ]    -- Valid Bit 
 */
static inline u64
tioca_paddr_to_gart(unsigned long paddr)
{
	/*
	 * We are assuming right now that paddr already has the correct
	 * format since the address from xtalk_dmaXXX should already have
	 * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
	 */

	return ((paddr) >> 12) | (1UL << 63);
}

/**
 * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
 * @page_addr: system page address to map
 */

static inline unsigned long
tioca_physpage_to_gart(uint64_t page_addr)
{
	uint64_t coretalk_addr;

	coretalk_addr = PHYS_TO_TIODMA(page_addr);
	if (!coretalk_addr) {
		return 0;
	}

	return tioca_paddr_to_gart(coretalk_addr);
}

/**
 * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
 * @tioca_kernel: CA context 
 *
 * Invalidate tlb entries for a given CA GART.  Main complexity is to account
 * for revA bug.
 */
static inline void
tioca_tlbflush(struct tioca_kernel *tioca_kernel)
{
	volatile uint64_t tmp;
	volatile struct tioca *ca_base;
	struct tioca_common *tioca_common;

	tioca_common = tioca_kernel->ca_common;
	ca_base = (struct tioca *)tioca_common->ca_common.bs_base;

	/*
	 * Explicit flushes not needed if GART is in cached mode
	 */
	if (tioca_kernel->ca_gart_iscoherent) {
		if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
			/*
			 * PV910244:  RevA CA needs explicit flushes.
			 * Need to put GART into uncached mode before
			 * flushing otherwise the explicit flush is ignored.
			 *
			 * Alternate WAR would be to leave GART cached and
			 * touch every CL aligned GART entry.
			 */

			ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
			ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
			ca_base->ca_control2 |=
			    (0x2ull << CA_GART_MEM_PARAM_SHFT);
			tmp = ca_base->ca_control2;
		}

		return;
	}

	/*
	 * Gart in uncached mode ... need an explicit flush.
	 */

	ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
	tmp = ca_base->ca_control2;
}

extern uint32_t	tioca_gart_found;
extern struct list_head tioca_list;
extern int tioca_init_provider(void);
extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
Commit	Line	Data
9c90bdde MM	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
	7	*/
	8
	9	#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
	10	#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
	11
	12	#include <asm/sn/tioca.h>
	13
	14	/*
	15	* WAR enables
	16	* Defines for individual WARs. Each is a bitmask of applicable
	17	* part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
	18	* (3 << 1) == (rev A or rev B), etc
	19	*/
	20
	21	#define TIOCA_WAR_ENABLED(pv, tioca_common) \
	22	((1 << tioca_common->ca_rev) & pv)
	23
	24	/* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
	25	#define PV907908 (1 << 1)
	26	/* ATI config space problems after BIOS execution starts */
	27	#define PV908234 (1 << 1)
	28	/* CA:AGPDMA write request data mismatch with ABC1CL merge */
	29	#define PV895469 (1 << 1)
	30	/* TIO:CA TLB invalidate of written GART entries possibly not occuring in CA*/
	31	#define PV910244 (1 << 1)
	32
	33	struct tioca_dmamap{
	34	struct list_head cad_list; /* headed by ca_list */
	35
	36	dma_addr_t cad_dma_addr; /* Linux dma handle */
	37	uint cad_gart_entry; /* start entry in ca_gart_pagemap */
	38	uint cad_gart_size; /* #entries for this map */
	39	};
	40
	41	/*
	42	* Kernel only fields. Prom may look at this stuff for debugging only.
	43	* Access this structure through the ca_kernel_private ptr.
	44	*/
	45
	46	struct tioca_common ;
	47
	48	struct tioca_kernel {
	49	struct tioca_common ca_common; / tioca this belongs to */
	50	struct list_head ca_list; /* list of all ca's */
	51	struct list_head ca_dmamaps;
	52	spinlock_t ca_lock; /* Kernel lock */
	53	cnodeid_t ca_closest_node;
	54	struct list_head ca_devices; / bus->devices */
	55
	56	/*
	57	* General GART stuff
	58	*/
	59	uint64_t ca_ap_size; /* size of aperature in bytes */
	60	uint32_t ca_gart_entries; /* # uint64_t entries in gart */
	61	uint32_t ca_ap_pagesize; /* aperature page size in bytes */
	62	uint64_t ca_ap_bus_base; /* bus address of CA aperature */
	63	uint64_t ca_gart_size; /* gart size in bytes */
	64	uint64_t ca_gart; / gart table vaddr */
65	uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */
66	uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */
67
68	/* PCI GART convenience values */
69	uint64_t ca_pciap_base; /* pci aperature bus base address */
70	uint64_t ca_pciap_size; /* pci aperature size (bytes) */
71	uint64_t ca_pcigart_base; /* gfx GART bus base address */
72	uint64_t ca_pcigart; / gfx GART vm address */
73	uint32_t ca_pcigart_entries;
74	uint32_t ca_pcigart_start; /* PCI start index in ca_gart */
75	void *ca_pcigart_pagemap;
76
77	/* AGP GART convenience values */
78	uint64_t ca_gfxap_base; /* gfx aperature bus base address */
79	uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */
80	uint64_t ca_gfxgart_base; /* gfx GART bus base address */
81	uint64_t ca_gfxgart; / gfx GART vm address */
82	uint32_t ca_gfxgart_entries;
83	uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */
84	};
85
86	/*
87	* Common tioca info shared between kernel and prom
88	*
89	* DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
90	* TO THE PROM VERSION.
91	*/
92
93	struct tioca_common {
94	struct pcibus_bussoft ca_common; /* common pciio header */
95
96	uint32_t ca_rev;
97	uint32_t ca_closest_nasid;
98
99	uint64_t ca_prom_private;
100	uint64_t ca_kernel_private;
101	};
102
103	/**
104	* tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
105	* @paddr: page address to convert
106	*
107	* Convert a system [coretalk] address to a GART entry. GART entries are
108	* formed using the following:
109	*
110	* data = ( (1<<63) \| ( (REMAP_NODE_ID << 40) \| (MD_CHIPLET_ID << 38) \|
111	* (REMAP_SYS_ADDR) ) >> 12 )
112	*
113	* DATA written to 1 GART TABLE Entry in system memory is remapped system
114	* addr for 1 page
115	*
116	* The data is for coretalk address format right shifted 12 bits with a
117	* valid bit.
118	*
119	* GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
120	* GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
121	* GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
122	* GART_TABLE_ENTRY [ 63 ] -- Valid Bit
123	*/
124	static inline u64
125	tioca_paddr_to_gart(unsigned long paddr)
126	{
127	/*
128	* We are assuming right now that paddr already has the correct
129	* format since the address from xtalk_dmaXXX should already have
130	* NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
131	*/
132
133	return ((paddr) >> 12) \| (1UL << 63);
134	}
135
136	/**
137	* tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
138	* @page_addr: system page address to map
139	*/
140
141	static inline unsigned long
142	tioca_physpage_to_gart(uint64_t page_addr)
143	{
144	uint64_t coretalk_addr;
145
146	coretalk_addr = PHYS_TO_TIODMA(page_addr);
147	if (!coretalk_addr) {
148	return 0;
149	}
150
151	return tioca_paddr_to_gart(coretalk_addr);
152	}
153
154	/**
155	* tioca_tlbflush - invalidate cached SGI CA GART TLB entries
156	* @tioca_kernel: CA context
157	*
158	* Invalidate tlb entries for a given CA GART. Main complexity is to account
159	* for revA bug.
160	*/
161	static inline void
162	tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163	{
164	volatile uint64_t tmp;
165	volatile struct tioca *ca_base;
166	struct tioca_common *tioca_common;
167
168	tioca_common = tioca_kernel->ca_common;
169	ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
170
171	/*
172	* Explicit flushes not needed if GART is in cached mode
173	*/
174	if (tioca_kernel->ca_gart_iscoherent) {
175	if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
176	/*
177	* PV910244: RevA CA needs explicit flushes.
178	* Need to put GART into uncached mode before
179	* flushing otherwise the explicit flush is ignored.
180	*
181	* Alternate WAR would be to leave GART cached and
182	* touch every CL aligned GART entry.
183	*/
184
185	ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
186	ca_base->ca_control2 \|= CA_GART_FLUSH_TLB;
187	ca_base->ca_control2 \|=
188	(0x2ull << CA_GART_MEM_PARAM_SHFT);
189	tmp = ca_base->ca_control2;
190	}
191
192	return;
193	}
194
195	/*
196	* Gart in uncached mode ... need an explicit flush.
197	*/
198
199	ca_base->ca_control2 \|= CA_GART_FLUSH_TLB;
200	tmp = ca_base->ca_control2;
201	}
202
203	extern uint32_t tioca_gart_found;
92a582ed	204	extern struct list_head tioca_list;
9c90bdde MM	205	extern int tioca_init_provider(void);
	206	extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
	207	#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */