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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/pgtable.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com) | |
7 | * Ulrich Weigand (weigand@de.ibm.com) | |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
9 | * | |
10 | * Derived from "include/asm-i386/pgtable.h" | |
11 | */ | |
12 | ||
13 | #ifndef _ASM_S390_PGTABLE_H | |
14 | #define _ASM_S390_PGTABLE_H | |
15 | ||
1da177e4 LT |
16 | /* |
17 | * The Linux memory management assumes a three-level page table setup. For | |
18 | * s390 31 bit we "fold" the mid level into the top-level page table, so | |
19 | * that we physically have the same two-level page table as the s390 mmu | |
20 | * expects in 31 bit mode. For s390 64 bit we use three of the five levels | |
21 | * the hardware provides (region first and region second tables are not | |
22 | * used). | |
23 | * | |
24 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
25 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
26 | * into the pgd entry) | |
27 | * | |
28 | * This file contains the functions and defines necessary to modify and use | |
29 | * the S390 page table tree. | |
30 | */ | |
31 | #ifndef __ASSEMBLY__ | |
2dcea57a | 32 | #include <linux/mm_types.h> |
5b7baf05 | 33 | #include <asm/bitops.h> |
1da177e4 LT |
34 | #include <asm/bug.h> |
35 | #include <asm/processor.h> | |
1da177e4 | 36 | |
1da177e4 LT |
37 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
38 | extern void paging_init(void); | |
2b67fc46 | 39 | extern void vmem_map_init(void); |
1da177e4 LT |
40 | |
41 | /* | |
42 | * The S390 doesn't have any external MMU info: the kernel page | |
43 | * tables contain all the necessary information. | |
44 | */ | |
45 | #define update_mmu_cache(vma, address, pte) do { } while (0) | |
46 | ||
47 | /* | |
48 | * ZERO_PAGE is a global shared page that is always zero: used | |
49 | * for zero-mapped memory areas etc.. | |
50 | */ | |
51 | extern char empty_zero_page[PAGE_SIZE]; | |
52 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | |
53 | #endif /* !__ASSEMBLY__ */ | |
54 | ||
55 | /* | |
56 | * PMD_SHIFT determines the size of the area a second-level page | |
57 | * table can map | |
58 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
59 | */ | |
60 | #ifndef __s390x__ | |
146e4b3c MS |
61 | # define PMD_SHIFT 20 |
62 | # define PUD_SHIFT 20 | |
63 | # define PGDIR_SHIFT 20 | |
1da177e4 | 64 | #else /* __s390x__ */ |
146e4b3c | 65 | # define PMD_SHIFT 20 |
190a1d72 | 66 | # define PUD_SHIFT 31 |
5a216a20 | 67 | # define PGDIR_SHIFT 42 |
1da177e4 LT |
68 | #endif /* __s390x__ */ |
69 | ||
70 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
71 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
72 | #define PUD_SIZE (1UL << PUD_SHIFT) |
73 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
74 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
75 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
76 | |
77 | /* | |
78 | * entries per page directory level: the S390 is two-level, so | |
79 | * we don't really have any PMD directory physically. | |
80 | * for S390 segment-table entries are combined to one PGD | |
81 | * that leads to 1024 pte per pgd | |
82 | */ | |
146e4b3c | 83 | #define PTRS_PER_PTE 256 |
1da177e4 | 84 | #ifndef __s390x__ |
146e4b3c | 85 | #define PTRS_PER_PMD 1 |
5a216a20 | 86 | #define PTRS_PER_PUD 1 |
1da177e4 | 87 | #else /* __s390x__ */ |
146e4b3c | 88 | #define PTRS_PER_PMD 2048 |
5a216a20 | 89 | #define PTRS_PER_PUD 2048 |
1da177e4 | 90 | #endif /* __s390x__ */ |
146e4b3c | 91 | #define PTRS_PER_PGD 2048 |
1da177e4 | 92 | |
d455a369 HD |
93 | #define FIRST_USER_ADDRESS 0 |
94 | ||
1da177e4 LT |
95 | #define pte_ERROR(e) \ |
96 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
97 | #define pmd_ERROR(e) \ | |
98 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
99 | #define pud_ERROR(e) \ |
100 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
101 | #define pgd_ERROR(e) \ |
102 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
103 | ||
104 | #ifndef __ASSEMBLY__ | |
105 | /* | |
5fd9c6e2 CB |
106 | * The vmalloc area will always be on the topmost area of the kernel |
107 | * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc, | |
108 | * which should be enough for any sane case. | |
109 | * By putting vmalloc at the top, we maximise the gap between physical | |
110 | * memory and vmalloc to catch misplaced memory accesses. As a side | |
111 | * effect, this also makes sure that 64 bit module code cannot be used | |
112 | * as system call address. | |
8b62bc96 | 113 | */ |
1da177e4 | 114 | #ifndef __s390x__ |
5fd9c6e2 CB |
115 | #define VMALLOC_START 0x78000000UL |
116 | #define VMALLOC_END 0x7e000000UL | |
0189103c | 117 | #define VMEM_MAP_END 0x80000000UL |
1da177e4 | 118 | #else /* __s390x__ */ |
5fd9c6e2 CB |
119 | #define VMALLOC_START 0x3e000000000UL |
120 | #define VMALLOC_END 0x3e040000000UL | |
0189103c | 121 | #define VMEM_MAP_END 0x40000000000UL |
1da177e4 LT |
122 | #endif /* __s390x__ */ |
123 | ||
0189103c HC |
124 | /* |
125 | * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1 | |
126 | * mapping. This needs to be calculated at compile time since the size of the | |
127 | * VMEM_MAP is static but the size of struct page can change. | |
128 | */ | |
522d8dc0 MS |
129 | #define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page)) |
130 | #define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES) | |
131 | #define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1)) | |
5fd9c6e2 | 132 | #define VMEM_MAP ((struct page *) VMALLOC_END) |
5fd9c6e2 | 133 | |
1da177e4 LT |
134 | /* |
135 | * A 31 bit pagetable entry of S390 has following format: | |
136 | * | PFRA | | OS | | |
137 | * 0 0IP0 | |
138 | * 00000000001111111111222222222233 | |
139 | * 01234567890123456789012345678901 | |
140 | * | |
141 | * I Page-Invalid Bit: Page is not available for address-translation | |
142 | * P Page-Protection Bit: Store access not possible for page | |
143 | * | |
144 | * A 31 bit segmenttable entry of S390 has following format: | |
145 | * | P-table origin | |PTL | |
146 | * 0 IC | |
147 | * 00000000001111111111222222222233 | |
148 | * 01234567890123456789012345678901 | |
149 | * | |
150 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
151 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
152 | * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) | |
153 | * | |
154 | * The 31 bit segmenttable origin of S390 has following format: | |
155 | * | |
156 | * |S-table origin | | STL | | |
157 | * X **GPS | |
158 | * 00000000001111111111222222222233 | |
159 | * 01234567890123456789012345678901 | |
160 | * | |
161 | * X Space-Switch event: | |
162 | * G Segment-Invalid Bit: * | |
163 | * P Private-Space Bit: Segment is not private (PoP 3-30) | |
164 | * S Storage-Alteration: | |
165 | * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) | |
166 | * | |
167 | * A 64 bit pagetable entry of S390 has following format: | |
168 | * | PFRA |0IP0| OS | | |
169 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
170 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
171 | * | |
172 | * I Page-Invalid Bit: Page is not available for address-translation | |
173 | * P Page-Protection Bit: Store access not possible for page | |
174 | * | |
175 | * A 64 bit segmenttable entry of S390 has following format: | |
176 | * | P-table origin | TT | |
177 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
178 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
179 | * | |
180 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
181 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
182 | * P Page-Protection Bit: Store access not possible for page | |
183 | * TT Type 00 | |
184 | * | |
185 | * A 64 bit region table entry of S390 has following format: | |
186 | * | S-table origin | TF TTTL | |
187 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
188 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
189 | * | |
190 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
191 | * TT Type 01 | |
192 | * TF | |
190a1d72 | 193 | * TL Table length |
1da177e4 LT |
194 | * |
195 | * The 64 bit regiontable origin of S390 has following format: | |
196 | * | region table origon | DTTL | |
197 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
198 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
199 | * | |
200 | * X Space-Switch event: | |
201 | * G Segment-Invalid Bit: | |
202 | * P Private-Space Bit: | |
203 | * S Storage-Alteration: | |
204 | * R Real space | |
205 | * TL Table-Length: | |
206 | * | |
207 | * A storage key has the following format: | |
208 | * | ACC |F|R|C|0| | |
209 | * 0 3 4 5 6 7 | |
210 | * ACC: access key | |
211 | * F : fetch protection bit | |
212 | * R : referenced bit | |
213 | * C : changed bit | |
214 | */ | |
215 | ||
216 | /* Hardware bits in the page table entry */ | |
83377484 MS |
217 | #define _PAGE_RO 0x200 /* HW read-only bit */ |
218 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
3610cce8 MS |
219 | |
220 | /* Software bits in the page table entry */ | |
83377484 MS |
221 | #define _PAGE_SWT 0x001 /* SW pte type bit t */ |
222 | #define _PAGE_SWX 0x002 /* SW pte type bit x */ | |
1da177e4 | 223 | |
83377484 | 224 | /* Six different types of pages. */ |
9282ed92 GS |
225 | #define _PAGE_TYPE_EMPTY 0x400 |
226 | #define _PAGE_TYPE_NONE 0x401 | |
83377484 MS |
227 | #define _PAGE_TYPE_SWAP 0x403 |
228 | #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ | |
9282ed92 GS |
229 | #define _PAGE_TYPE_RO 0x200 |
230 | #define _PAGE_TYPE_RW 0x000 | |
c1821c2e GS |
231 | #define _PAGE_TYPE_EX_RO 0x202 |
232 | #define _PAGE_TYPE_EX_RW 0x002 | |
1da177e4 | 233 | |
83377484 MS |
234 | /* |
235 | * PTE type bits are rather complicated. handle_pte_fault uses pte_present, | |
236 | * pte_none and pte_file to find out the pte type WITHOUT holding the page | |
237 | * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to | |
238 | * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs | |
239 | * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. | |
240 | * This change is done while holding the lock, but the intermediate step | |
241 | * of a previously valid pte with the hw invalid bit set can be observed by | |
242 | * handle_pte_fault. That makes it necessary that all valid pte types with | |
243 | * the hw invalid bit set must be distinguishable from the four pte types | |
244 | * empty, none, swap and file. | |
245 | * | |
246 | * irxt ipte irxt | |
247 | * _PAGE_TYPE_EMPTY 1000 -> 1000 | |
248 | * _PAGE_TYPE_NONE 1001 -> 1001 | |
249 | * _PAGE_TYPE_SWAP 1011 -> 1011 | |
250 | * _PAGE_TYPE_FILE 11?1 -> 11?1 | |
251 | * _PAGE_TYPE_RO 0100 -> 1100 | |
252 | * _PAGE_TYPE_RW 0000 -> 1000 | |
c1821c2e GS |
253 | * _PAGE_TYPE_EX_RO 0110 -> 1110 |
254 | * _PAGE_TYPE_EX_RW 0010 -> 1010 | |
83377484 | 255 | * |
c1821c2e | 256 | * pte_none is true for bits combinations 1000, 1010, 1100, 1110 |
83377484 MS |
257 | * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 |
258 | * pte_file is true for bits combinations 1101, 1111 | |
c1821c2e | 259 | * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. |
83377484 MS |
260 | */ |
261 | ||
5b7baf05 CB |
262 | /* Page status table bits for virtualization */ |
263 | #define RCP_PCL_BIT 55 | |
264 | #define RCP_HR_BIT 54 | |
265 | #define RCP_HC_BIT 53 | |
266 | #define RCP_GR_BIT 50 | |
267 | #define RCP_GC_BIT 49 | |
268 | ||
1da177e4 LT |
269 | #ifndef __s390x__ |
270 | ||
3610cce8 MS |
271 | /* Bits in the segment table address-space-control-element */ |
272 | #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ | |
273 | #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ | |
274 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
275 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
276 | #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ | |
1da177e4 | 277 | |
3610cce8 MS |
278 | /* Bits in the segment table entry */ |
279 | #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ | |
280 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
281 | #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ | |
282 | #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ | |
1da177e4 | 283 | |
3610cce8 MS |
284 | #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) |
285 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
1da177e4 LT |
286 | |
287 | #else /* __s390x__ */ | |
288 | ||
3610cce8 MS |
289 | /* Bits in the segment/region table address-space-control-element */ |
290 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
291 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
292 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
293 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
294 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
295 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
296 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
297 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
298 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
299 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
300 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
301 | ||
302 | /* Bits in the region table entry */ | |
303 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
304 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ | |
305 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
306 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
307 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
308 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
309 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
310 | ||
311 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
312 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) | |
313 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) | |
314 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) | |
315 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) | |
316 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) | |
317 | ||
1da177e4 | 318 | /* Bits in the segment table entry */ |
3610cce8 MS |
319 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
320 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
321 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
1da177e4 | 322 | |
3610cce8 MS |
323 | #define _SEGMENT_ENTRY (0) |
324 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
325 | ||
326 | #endif /* __s390x__ */ | |
1da177e4 LT |
327 | |
328 | /* | |
3610cce8 MS |
329 | * A user page table pointer has the space-switch-event bit, the |
330 | * private-space-control bit and the storage-alteration-event-control | |
331 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 332 | */ |
3610cce8 MS |
333 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
334 | _ASCE_ALT_EVENT) | |
1da177e4 | 335 | |
3610cce8 | 336 | /* Bits int the storage key */ |
1da177e4 LT |
337 | #define _PAGE_CHANGED 0x02 /* HW changed bit */ |
338 | #define _PAGE_REFERENCED 0x04 /* HW referenced bit */ | |
339 | ||
1da177e4 | 340 | /* |
9282ed92 | 341 | * Page protection definitions. |
1da177e4 | 342 | */ |
9282ed92 GS |
343 | #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) |
344 | #define PAGE_RO __pgprot(_PAGE_TYPE_RO) | |
345 | #define PAGE_RW __pgprot(_PAGE_TYPE_RW) | |
c1821c2e GS |
346 | #define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO) |
347 | #define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW) | |
9282ed92 GS |
348 | |
349 | #define PAGE_KERNEL PAGE_RW | |
350 | #define PAGE_COPY PAGE_RO | |
1da177e4 LT |
351 | |
352 | /* | |
c1821c2e GS |
353 | * Dependent on the EXEC_PROTECT option s390 can do execute protection. |
354 | * Write permission always implies read permission. In theory with a | |
355 | * primary/secondary page table execute only can be implemented but | |
356 | * it would cost an additional bit in the pte to distinguish all the | |
357 | * different pte types. To avoid that execute permission currently | |
358 | * implies read permission as well. | |
1da177e4 LT |
359 | */ |
360 | /*xwr*/ | |
9282ed92 GS |
361 | #define __P000 PAGE_NONE |
362 | #define __P001 PAGE_RO | |
363 | #define __P010 PAGE_RO | |
364 | #define __P011 PAGE_RO | |
c1821c2e GS |
365 | #define __P100 PAGE_EX_RO |
366 | #define __P101 PAGE_EX_RO | |
367 | #define __P110 PAGE_EX_RO | |
368 | #define __P111 PAGE_EX_RO | |
9282ed92 GS |
369 | |
370 | #define __S000 PAGE_NONE | |
371 | #define __S001 PAGE_RO | |
372 | #define __S010 PAGE_RW | |
373 | #define __S011 PAGE_RW | |
c1821c2e GS |
374 | #define __S100 PAGE_EX_RO |
375 | #define __S101 PAGE_EX_RO | |
376 | #define __S110 PAGE_EX_RW | |
377 | #define __S111 PAGE_EX_RW | |
378 | ||
379 | #ifndef __s390x__ | |
3610cce8 | 380 | # define PxD_SHADOW_SHIFT 1 |
c1821c2e | 381 | #else /* __s390x__ */ |
3610cce8 | 382 | # define PxD_SHADOW_SHIFT 2 |
c1821c2e GS |
383 | #endif /* __s390x__ */ |
384 | ||
3610cce8 | 385 | static inline void *get_shadow_table(void *table) |
c1821c2e | 386 | { |
3610cce8 MS |
387 | unsigned long addr, offset; |
388 | struct page *page; | |
389 | ||
390 | addr = (unsigned long) table; | |
391 | offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1); | |
392 | page = virt_to_page((void *)(addr ^ offset)); | |
393 | return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL); | |
c1821c2e | 394 | } |
1da177e4 LT |
395 | |
396 | /* | |
397 | * Certain architectures need to do special things when PTEs | |
398 | * within a page table are directly modified. Thus, the following | |
399 | * hook is made available. | |
400 | */ | |
ba8a9229 | 401 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
146e4b3c | 402 | pte_t *ptep, pte_t entry) |
1da177e4 | 403 | { |
146e4b3c MS |
404 | *ptep = entry; |
405 | if (mm->context.noexec) { | |
406 | if (!(pte_val(entry) & _PAGE_INVALID) && | |
407 | (pte_val(entry) & _PAGE_SWX)) | |
408 | pte_val(entry) |= _PAGE_RO; | |
c1821c2e | 409 | else |
146e4b3c MS |
410 | pte_val(entry) = _PAGE_TYPE_EMPTY; |
411 | ptep[PTRS_PER_PTE] = entry; | |
c1821c2e | 412 | } |
1da177e4 | 413 | } |
1da177e4 LT |
414 | |
415 | /* | |
416 | * pgd/pmd/pte query functions | |
417 | */ | |
418 | #ifndef __s390x__ | |
419 | ||
4448aaf0 AB |
420 | static inline int pgd_present(pgd_t pgd) { return 1; } |
421 | static inline int pgd_none(pgd_t pgd) { return 0; } | |
422 | static inline int pgd_bad(pgd_t pgd) { return 0; } | |
1da177e4 | 423 | |
190a1d72 MS |
424 | static inline int pud_present(pud_t pud) { return 1; } |
425 | static inline int pud_none(pud_t pud) { return 0; } | |
426 | static inline int pud_bad(pud_t pud) { return 0; } | |
427 | ||
1da177e4 LT |
428 | #else /* __s390x__ */ |
429 | ||
5a216a20 MS |
430 | static inline int pgd_present(pgd_t pgd) |
431 | { | |
6252d702 MS |
432 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
433 | return 1; | |
5a216a20 MS |
434 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
435 | } | |
436 | ||
437 | static inline int pgd_none(pgd_t pgd) | |
438 | { | |
6252d702 MS |
439 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
440 | return 0; | |
5a216a20 MS |
441 | return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; |
442 | } | |
443 | ||
444 | static inline int pgd_bad(pgd_t pgd) | |
445 | { | |
6252d702 MS |
446 | /* |
447 | * With dynamic page table levels the pgd can be a region table | |
448 | * entry or a segment table entry. Check for the bit that are | |
449 | * invalid for either table entry. | |
450 | */ | |
5a216a20 | 451 | unsigned long mask = |
6252d702 | 452 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
453 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
454 | return (pgd_val(pgd) & mask) != 0; | |
455 | } | |
190a1d72 MS |
456 | |
457 | static inline int pud_present(pud_t pud) | |
1da177e4 | 458 | { |
6252d702 MS |
459 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
460 | return 1; | |
0d017923 | 461 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
462 | } |
463 | ||
190a1d72 | 464 | static inline int pud_none(pud_t pud) |
1da177e4 | 465 | { |
6252d702 MS |
466 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
467 | return 0; | |
0d017923 | 468 | return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; |
1da177e4 LT |
469 | } |
470 | ||
190a1d72 | 471 | static inline int pud_bad(pud_t pud) |
1da177e4 | 472 | { |
6252d702 MS |
473 | /* |
474 | * With dynamic page table levels the pud can be a region table | |
475 | * entry or a segment table entry. Check for the bit that are | |
476 | * invalid for either table entry. | |
477 | */ | |
5a216a20 | 478 | unsigned long mask = |
6252d702 | 479 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
480 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
481 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
482 | } |
483 | ||
3610cce8 MS |
484 | #endif /* __s390x__ */ |
485 | ||
4448aaf0 | 486 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 487 | { |
0d017923 | 488 | return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
489 | } |
490 | ||
4448aaf0 | 491 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 492 | { |
0d017923 | 493 | return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL; |
1da177e4 LT |
494 | } |
495 | ||
4448aaf0 | 496 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 497 | { |
3610cce8 MS |
498 | unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; |
499 | return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; | |
1da177e4 LT |
500 | } |
501 | ||
4448aaf0 | 502 | static inline int pte_none(pte_t pte) |
1da177e4 | 503 | { |
83377484 | 504 | return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); |
1da177e4 LT |
505 | } |
506 | ||
4448aaf0 | 507 | static inline int pte_present(pte_t pte) |
1da177e4 | 508 | { |
83377484 MS |
509 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; |
510 | return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || | |
511 | (!(pte_val(pte) & _PAGE_INVALID) && | |
512 | !(pte_val(pte) & _PAGE_SWT)); | |
1da177e4 LT |
513 | } |
514 | ||
4448aaf0 | 515 | static inline int pte_file(pte_t pte) |
1da177e4 | 516 | { |
83377484 MS |
517 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; |
518 | return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; | |
1da177e4 LT |
519 | } |
520 | ||
ba8a9229 MS |
521 | #define __HAVE_ARCH_PTE_SAME |
522 | #define pte_same(a,b) (pte_val(a) == pte_val(b)) | |
1da177e4 | 523 | |
5b7baf05 CB |
524 | static inline void rcp_lock(pte_t *ptep) |
525 | { | |
526 | #ifdef CONFIG_PGSTE | |
527 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
528 | preempt_disable(); | |
529 | while (test_and_set_bit(RCP_PCL_BIT, pgste)) | |
530 | ; | |
531 | #endif | |
532 | } | |
533 | ||
534 | static inline void rcp_unlock(pte_t *ptep) | |
535 | { | |
536 | #ifdef CONFIG_PGSTE | |
537 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
538 | clear_bit(RCP_PCL_BIT, pgste); | |
539 | preempt_enable(); | |
540 | #endif | |
541 | } | |
542 | ||
543 | /* forward declaration for SetPageUptodate in page-flags.h*/ | |
544 | static inline void page_clear_dirty(struct page *page); | |
545 | #include <linux/page-flags.h> | |
546 | ||
547 | static inline void ptep_rcp_copy(pte_t *ptep) | |
548 | { | |
549 | #ifdef CONFIG_PGSTE | |
550 | struct page *page = virt_to_page(pte_val(*ptep)); | |
551 | unsigned int skey; | |
552 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
553 | ||
554 | skey = page_get_storage_key(page_to_phys(page)); | |
555 | if (skey & _PAGE_CHANGED) | |
c71799c1 | 556 | set_bit_simple(RCP_GC_BIT, pgste); |
5b7baf05 | 557 | if (skey & _PAGE_REFERENCED) |
c71799c1 HC |
558 | set_bit_simple(RCP_GR_BIT, pgste); |
559 | if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) | |
5b7baf05 | 560 | SetPageDirty(page); |
c71799c1 | 561 | if (test_and_clear_bit_simple(RCP_HR_BIT, pgste)) |
5b7baf05 CB |
562 | SetPageReferenced(page); |
563 | #endif | |
564 | } | |
565 | ||
1da177e4 LT |
566 | /* |
567 | * query functions pte_write/pte_dirty/pte_young only work if | |
568 | * pte_present() is true. Undefined behaviour if not.. | |
569 | */ | |
4448aaf0 | 570 | static inline int pte_write(pte_t pte) |
1da177e4 LT |
571 | { |
572 | return (pte_val(pte) & _PAGE_RO) == 0; | |
573 | } | |
574 | ||
4448aaf0 | 575 | static inline int pte_dirty(pte_t pte) |
1da177e4 LT |
576 | { |
577 | /* A pte is neither clean nor dirty on s/390. The dirty bit | |
578 | * is in the storage key. See page_test_and_clear_dirty for | |
579 | * details. | |
580 | */ | |
581 | return 0; | |
582 | } | |
583 | ||
4448aaf0 | 584 | static inline int pte_young(pte_t pte) |
1da177e4 LT |
585 | { |
586 | /* A pte is neither young nor old on s/390. The young bit | |
587 | * is in the storage key. See page_test_and_clear_young for | |
588 | * details. | |
589 | */ | |
590 | return 0; | |
591 | } | |
592 | ||
1da177e4 LT |
593 | /* |
594 | * pgd/pmd/pte modification functions | |
595 | */ | |
596 | ||
597 | #ifndef __s390x__ | |
598 | ||
190a1d72 MS |
599 | #define pgd_clear(pgd) do { } while (0) |
600 | #define pud_clear(pud) do { } while (0) | |
1da177e4 | 601 | |
1da177e4 LT |
602 | #else /* __s390x__ */ |
603 | ||
5a216a20 MS |
604 | static inline void pgd_clear_kernel(pgd_t * pgd) |
605 | { | |
6252d702 MS |
606 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
607 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
608 | } |
609 | ||
610 | static inline void pgd_clear(pgd_t * pgd) | |
611 | { | |
612 | pgd_t *shadow = get_shadow_table(pgd); | |
613 | ||
614 | pgd_clear_kernel(pgd); | |
615 | if (shadow) | |
616 | pgd_clear_kernel(shadow); | |
617 | } | |
190a1d72 MS |
618 | |
619 | static inline void pud_clear_kernel(pud_t *pud) | |
1da177e4 | 620 | { |
6252d702 MS |
621 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
622 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
623 | } |
624 | ||
6252d702 | 625 | static inline void pud_clear(pud_t *pud) |
c1821c2e | 626 | { |
190a1d72 | 627 | pud_t *shadow = get_shadow_table(pud); |
c1821c2e | 628 | |
190a1d72 MS |
629 | pud_clear_kernel(pud); |
630 | if (shadow) | |
631 | pud_clear_kernel(shadow); | |
c1821c2e GS |
632 | } |
633 | ||
146e4b3c MS |
634 | #endif /* __s390x__ */ |
635 | ||
c1821c2e | 636 | static inline void pmd_clear_kernel(pmd_t * pmdp) |
1da177e4 | 637 | { |
3610cce8 | 638 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
639 | } |
640 | ||
146e4b3c | 641 | static inline void pmd_clear(pmd_t *pmd) |
c1821c2e | 642 | { |
146e4b3c | 643 | pmd_t *shadow = get_shadow_table(pmd); |
c1821c2e | 644 | |
146e4b3c MS |
645 | pmd_clear_kernel(pmd); |
646 | if (shadow) | |
647 | pmd_clear_kernel(shadow); | |
c1821c2e GS |
648 | } |
649 | ||
4448aaf0 | 650 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 651 | { |
5b7baf05 CB |
652 | if (mm->context.pgstes) |
653 | ptep_rcp_copy(ptep); | |
9282ed92 | 654 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
146e4b3c MS |
655 | if (mm->context.noexec) |
656 | pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY; | |
1da177e4 LT |
657 | } |
658 | ||
659 | /* | |
660 | * The following pte modification functions only work if | |
661 | * pte_present() is true. Undefined behaviour if not.. | |
662 | */ | |
4448aaf0 | 663 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 LT |
664 | { |
665 | pte_val(pte) &= PAGE_MASK; | |
666 | pte_val(pte) |= pgprot_val(newprot); | |
667 | return pte; | |
668 | } | |
669 | ||
4448aaf0 | 670 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 671 | { |
9282ed92 | 672 | /* Do not clobber _PAGE_TYPE_NONE pages! */ |
1da177e4 LT |
673 | if (!(pte_val(pte) & _PAGE_INVALID)) |
674 | pte_val(pte) |= _PAGE_RO; | |
675 | return pte; | |
676 | } | |
677 | ||
4448aaf0 | 678 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 LT |
679 | { |
680 | pte_val(pte) &= ~_PAGE_RO; | |
681 | return pte; | |
682 | } | |
683 | ||
4448aaf0 | 684 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 LT |
685 | { |
686 | /* The only user of pte_mkclean is the fork() code. | |
687 | We must *not* clear the *physical* page dirty bit | |
688 | just because fork() wants to clear the dirty bit in | |
689 | *one* of the page's mappings. So we just do nothing. */ | |
690 | return pte; | |
691 | } | |
692 | ||
4448aaf0 | 693 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 LT |
694 | { |
695 | /* We do not explicitly set the dirty bit because the | |
696 | * sske instruction is slow. It is faster to let the | |
697 | * next instruction set the dirty bit. | |
698 | */ | |
699 | return pte; | |
700 | } | |
701 | ||
4448aaf0 | 702 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 LT |
703 | { |
704 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
705 | * There is no point in clearing the real referenced bit. | |
706 | */ | |
707 | return pte; | |
708 | } | |
709 | ||
4448aaf0 | 710 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 LT |
711 | { |
712 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
713 | * There is no point in setting the real referenced bit. | |
714 | */ | |
715 | return pte; | |
716 | } | |
717 | ||
ba8a9229 MS |
718 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
719 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
720 | unsigned long addr, pte_t *ptep) | |
1da177e4 | 721 | { |
5b7baf05 CB |
722 | #ifdef CONFIG_PGSTE |
723 | unsigned long physpage; | |
724 | int young; | |
725 | unsigned long *pgste; | |
726 | ||
727 | if (!vma->vm_mm->context.pgstes) | |
728 | return 0; | |
729 | physpage = pte_val(*ptep) & PAGE_MASK; | |
730 | pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
731 | ||
732 | young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0); | |
733 | rcp_lock(ptep); | |
734 | if (young) | |
c71799c1 HC |
735 | set_bit_simple(RCP_GR_BIT, pgste); |
736 | young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste); | |
5b7baf05 CB |
737 | rcp_unlock(ptep); |
738 | return young; | |
739 | #endif | |
1da177e4 LT |
740 | return 0; |
741 | } | |
742 | ||
ba8a9229 MS |
743 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
744 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
745 | unsigned long address, pte_t *ptep) | |
1da177e4 | 746 | { |
5b7baf05 CB |
747 | /* No need to flush TLB |
748 | * On s390 reference bits are in storage key and never in TLB | |
749 | * With virtualization we handle the reference bit, without we | |
750 | * we can simply return */ | |
751 | #ifdef CONFIG_PGSTE | |
752 | return ptep_test_and_clear_young(vma, address, ptep); | |
753 | #endif | |
ba8a9229 | 754 | return 0; |
1da177e4 LT |
755 | } |
756 | ||
9282ed92 | 757 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 758 | { |
9282ed92 | 759 | if (!(pte_val(*ptep) & _PAGE_INVALID)) { |
1da177e4 | 760 | #ifndef __s390x__ |
146e4b3c | 761 | /* pto must point to the start of the segment table */ |
1da177e4 | 762 | pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); |
9282ed92 GS |
763 | #else |
764 | /* ipte in zarch mode can do the math */ | |
765 | pte_t *pto = ptep; | |
766 | #endif | |
94c12cc7 MS |
767 | asm volatile( |
768 | " ipte %2,%3" | |
769 | : "=m" (*ptep) : "m" (*ptep), | |
770 | "a" (pto), "a" (address)); | |
1da177e4 | 771 | } |
9282ed92 GS |
772 | } |
773 | ||
146e4b3c MS |
774 | static inline void ptep_invalidate(struct mm_struct *mm, |
775 | unsigned long address, pte_t *ptep) | |
9282ed92 | 776 | { |
5b7baf05 CB |
777 | if (mm->context.pgstes) { |
778 | rcp_lock(ptep); | |
779 | __ptep_ipte(address, ptep); | |
780 | ptep_rcp_copy(ptep); | |
781 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; | |
782 | rcp_unlock(ptep); | |
783 | return; | |
784 | } | |
9282ed92 | 785 | __ptep_ipte(address, ptep); |
5b7baf05 CB |
786 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
787 | if (mm->context.noexec) { | |
146e4b3c | 788 | __ptep_ipte(address, ptep + PTRS_PER_PTE); |
5b7baf05 CB |
789 | pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY; |
790 | } | |
f0e47c22 MS |
791 | } |
792 | ||
ba8a9229 MS |
793 | /* |
794 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
795 | * both clear the TLB for the unmapped pte. The reason is that | |
796 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
797 | * to modify an active pte. The sequence is | |
798 | * 1) ptep_get_and_clear | |
799 | * 2) set_pte_at | |
800 | * 3) flush_tlb_range | |
801 | * On s390 the tlb needs to get flushed with the modification of the pte | |
802 | * if the pte is active. The only way how this can be implemented is to | |
803 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
804 | * is a nop. | |
805 | */ | |
806 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
807 | #define ptep_get_and_clear(__mm, __address, __ptep) \ | |
808 | ({ \ | |
809 | pte_t __pte = *(__ptep); \ | |
810 | if (atomic_read(&(__mm)->mm_users) > 1 || \ | |
811 | (__mm) != current->active_mm) \ | |
146e4b3c | 812 | ptep_invalidate(__mm, __address, __ptep); \ |
ba8a9229 MS |
813 | else \ |
814 | pte_clear((__mm), (__address), (__ptep)); \ | |
815 | __pte; \ | |
816 | }) | |
817 | ||
818 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
819 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
820 | unsigned long address, pte_t *ptep) | |
821 | { | |
822 | pte_t pte = *ptep; | |
146e4b3c | 823 | ptep_invalidate(vma->vm_mm, address, ptep); |
1da177e4 LT |
824 | return pte; |
825 | } | |
826 | ||
ba8a9229 MS |
827 | /* |
828 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
829 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
830 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
831 | * cannot be accessed while the batched unmap is running. In this case | |
832 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
833 | */ | |
834 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
835 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
836 | unsigned long addr, | |
837 | pte_t *ptep, int full) | |
1da177e4 | 838 | { |
ba8a9229 MS |
839 | pte_t pte = *ptep; |
840 | ||
841 | if (full) | |
842 | pte_clear(mm, addr, ptep); | |
843 | else | |
146e4b3c | 844 | ptep_invalidate(mm, addr, ptep); |
ba8a9229 | 845 | return pte; |
1da177e4 LT |
846 | } |
847 | ||
ba8a9229 MS |
848 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
849 | #define ptep_set_wrprotect(__mm, __addr, __ptep) \ | |
850 | ({ \ | |
851 | pte_t __pte = *(__ptep); \ | |
852 | if (pte_write(__pte)) { \ | |
853 | if (atomic_read(&(__mm)->mm_users) > 1 || \ | |
854 | (__mm) != current->active_mm) \ | |
146e4b3c | 855 | ptep_invalidate(__mm, __addr, __ptep); \ |
ba8a9229 MS |
856 | set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \ |
857 | } \ | |
858 | }) | |
859 | ||
860 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
f0e47c22 MS |
861 | #define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \ |
862 | ({ \ | |
863 | int __changed = !pte_same(*(__ptep), __entry); \ | |
864 | if (__changed) { \ | |
146e4b3c | 865 | ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \ |
f0e47c22 MS |
866 | set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \ |
867 | } \ | |
868 | __changed; \ | |
8dab5241 | 869 | }) |
1da177e4 LT |
870 | |
871 | /* | |
872 | * Test and clear dirty bit in storage key. | |
873 | * We can't clear the changed bit atomically. This is a potential | |
874 | * race against modification of the referenced bit. This function | |
875 | * should therefore only be called if it is not mapped in any | |
876 | * address space. | |
877 | */ | |
ba8a9229 | 878 | #define __HAVE_ARCH_PAGE_TEST_DIRTY |
6c210482 | 879 | static inline int page_test_dirty(struct page *page) |
2dcea57a | 880 | { |
6c210482 MS |
881 | return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0; |
882 | } | |
2dcea57a | 883 | |
ba8a9229 | 884 | #define __HAVE_ARCH_PAGE_CLEAR_DIRTY |
6c210482 MS |
885 | static inline void page_clear_dirty(struct page *page) |
886 | { | |
887 | page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY); | |
2dcea57a | 888 | } |
1da177e4 LT |
889 | |
890 | /* | |
891 | * Test and clear referenced bit in storage key. | |
892 | */ | |
ba8a9229 | 893 | #define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG |
2dcea57a HC |
894 | static inline int page_test_and_clear_young(struct page *page) |
895 | { | |
0b2b6e1d | 896 | unsigned long physpage = page_to_phys(page); |
2dcea57a HC |
897 | int ccode; |
898 | ||
0b2b6e1d HC |
899 | asm volatile( |
900 | " rrbe 0,%1\n" | |
901 | " ipm %0\n" | |
902 | " srl %0,28\n" | |
2dcea57a HC |
903 | : "=d" (ccode) : "a" (physpage) : "cc" ); |
904 | return ccode & 2; | |
905 | } | |
1da177e4 LT |
906 | |
907 | /* | |
908 | * Conversion functions: convert a page and protection to a page entry, | |
909 | * and a page entry and page directory to the page they refer to. | |
910 | */ | |
911 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
912 | { | |
913 | pte_t __pte; | |
914 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
915 | return __pte; | |
916 | } | |
917 | ||
2dcea57a HC |
918 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
919 | { | |
0b2b6e1d | 920 | unsigned long physpage = page_to_phys(page); |
1da177e4 | 921 | |
2dcea57a HC |
922 | return mk_pte_phys(physpage, pgprot); |
923 | } | |
924 | ||
190a1d72 MS |
925 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
926 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
927 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
928 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 929 | |
190a1d72 MS |
930 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
931 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 932 | |
190a1d72 | 933 | #ifndef __s390x__ |
1da177e4 | 934 | |
190a1d72 MS |
935 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
936 | #define pud_deref(pmd) ({ BUG(); 0UL; }) | |
937 | #define pgd_deref(pmd) ({ BUG(); 0UL; }) | |
46a82b2d | 938 | |
190a1d72 MS |
939 | #define pud_offset(pgd, address) ((pud_t *) pgd) |
940 | #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) | |
1da177e4 | 941 | |
190a1d72 | 942 | #else /* __s390x__ */ |
1da177e4 | 943 | |
190a1d72 MS |
944 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
945 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 946 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 947 | |
5a216a20 MS |
948 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
949 | { | |
6252d702 MS |
950 | pud_t *pud = (pud_t *) pgd; |
951 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
952 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
953 | return pud + pud_index(address); |
954 | } | |
1da177e4 | 955 | |
190a1d72 | 956 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 957 | { |
6252d702 MS |
958 | pmd_t *pmd = (pmd_t *) pud; |
959 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
960 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 961 | return pmd + pmd_index(address); |
1da177e4 LT |
962 | } |
963 | ||
190a1d72 | 964 | #endif /* __s390x__ */ |
1da177e4 | 965 | |
190a1d72 MS |
966 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
967 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
968 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 969 | |
190a1d72 | 970 | #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) |
1da177e4 | 971 | |
190a1d72 MS |
972 | /* Find an entry in the lowest level page table.. */ |
973 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
974 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 LT |
975 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
976 | #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address) | |
977 | #define pte_unmap(pte) do { } while (0) | |
978 | #define pte_unmap_nested(pte) do { } while (0) | |
979 | ||
980 | /* | |
981 | * 31 bit swap entry format: | |
982 | * A page-table entry has some bits we have to treat in a special way. | |
983 | * Bits 0, 20 and bit 23 have to be zero, otherwise an specification | |
984 | * exception will occur instead of a page translation exception. The | |
985 | * specifiation exception has the bad habit not to store necessary | |
986 | * information in the lowcore. | |
987 | * Bit 21 and bit 22 are the page invalid bit and the page protection | |
988 | * bit. We set both to indicate a swapped page. | |
989 | * Bit 30 and 31 are used to distinguish the different page types. For | |
990 | * a swapped page these bits need to be zero. | |
991 | * This leaves the bits 1-19 and bits 24-29 to store type and offset. | |
992 | * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 | |
993 | * plus 24 for the offset. | |
994 | * 0| offset |0110|o|type |00| | |
995 | * 0 0000000001111111111 2222 2 22222 33 | |
996 | * 0 1234567890123456789 0123 4 56789 01 | |
997 | * | |
998 | * 64 bit swap entry format: | |
999 | * A page-table entry has some bits we have to treat in a special way. | |
1000 | * Bits 52 and bit 55 have to be zero, otherwise an specification | |
1001 | * exception will occur instead of a page translation exception. The | |
1002 | * specifiation exception has the bad habit not to store necessary | |
1003 | * information in the lowcore. | |
1004 | * Bit 53 and bit 54 are the page invalid bit and the page protection | |
1005 | * bit. We set both to indicate a swapped page. | |
1006 | * Bit 62 and 63 are used to distinguish the different page types. For | |
1007 | * a swapped page these bits need to be zero. | |
1008 | * This leaves the bits 0-51 and bits 56-61 to store type and offset. | |
1009 | * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 | |
1010 | * plus 56 for the offset. | |
1011 | * | offset |0110|o|type |00| | |
1012 | * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 | |
1013 | * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 | |
1014 | */ | |
1015 | #ifndef __s390x__ | |
1016 | #define __SWP_OFFSET_MASK (~0UL >> 12) | |
1017 | #else | |
1018 | #define __SWP_OFFSET_MASK (~0UL >> 11) | |
1019 | #endif | |
4448aaf0 | 1020 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1021 | { |
1022 | pte_t pte; | |
1023 | offset &= __SWP_OFFSET_MASK; | |
9282ed92 | 1024 | pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | |
1da177e4 LT |
1025 | ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); |
1026 | return pte; | |
1027 | } | |
1028 | ||
1029 | #define __swp_type(entry) (((entry).val >> 2) & 0x1f) | |
1030 | #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) | |
1031 | #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) | |
1032 | ||
1033 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1034 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1035 | ||
1036 | #ifndef __s390x__ | |
1037 | # define PTE_FILE_MAX_BITS 26 | |
1038 | #else /* __s390x__ */ | |
1039 | # define PTE_FILE_MAX_BITS 59 | |
1040 | #endif /* __s390x__ */ | |
1041 | ||
1042 | #define pte_to_pgoff(__pte) \ | |
1043 | ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) | |
1044 | ||
1045 | #define pgoff_to_pte(__off) \ | |
1046 | ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ | |
9282ed92 | 1047 | | _PAGE_TYPE_FILE }) |
1da177e4 LT |
1048 | |
1049 | #endif /* !__ASSEMBLY__ */ | |
1050 | ||
1051 | #define kern_addr_valid(addr) (1) | |
1052 | ||
f4eb07c1 HC |
1053 | extern int add_shared_memory(unsigned long start, unsigned long size); |
1054 | extern int remove_shared_memory(unsigned long start, unsigned long size); | |
402b0862 | 1055 | extern int s390_enable_sie(void); |
f4eb07c1 | 1056 | |
1da177e4 LT |
1057 | /* |
1058 | * No page table caches to initialise | |
1059 | */ | |
1060 | #define pgtable_cache_init() do { } while (0) | |
1061 | ||
f4eb07c1 HC |
1062 | #define __HAVE_ARCH_MEMMAP_INIT |
1063 | extern void memmap_init(unsigned long, int, unsigned long, unsigned long); | |
1064 | ||
1da177e4 LT |
1065 | #include <asm-generic/pgtable.h> |
1066 | ||
1067 | #endif /* _S390_PAGE_H */ |