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[S390] cio: Make ccw_dev_id_is_equal() more robust.
[deliverable/linux.git] / include / asm-s390 / pgtable.h
CommitLineData
1da177e4
LT		 1/*
2 * include/asm-s390/pgtable.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Ulrich Weigand (weigand@de.ibm.com)
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
9 *
10 * Derived from "include/asm-i386/pgtable.h"
11 */
12
13#ifndef _ASM_S390_PGTABLE_H
14#define _ASM_S390_PGTABLE_H
15
16#include <asm-generic/4level-fixup.h>
17
18/*
19 * The Linux memory management assumes a three-level page table setup. For
20 * s390 31 bit we "fold" the mid level into the top-level page table, so
21 * that we physically have the same two-level page table as the s390 mmu
22 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
23 * the hardware provides (region first and region second tables are not
24 * used).
25 *
26 * The "pgd_xxx()" functions are trivial for a folded two-level
27 * setup: the pgd is never bad, and a pmd always exists (as it's folded
28 * into the pgd entry)
29 *
30 * This file contains the functions and defines necessary to modify and use
31 * the S390 page table tree.
32 */
33#ifndef __ASSEMBLY__
2dcea57a 34#include <linux/mm_types.h>
1da177e4
LT		 35#include <asm/bug.h>
36#include <asm/processor.h>
1da177e4
LT		 37
38struct vm_area_struct; /* forward declaration (include/linux/mm.h) */
8c65b4a6 39struct mm_struct;
1da177e4
LT		 40
41extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
42extern void paging_init(void);
43
44/*
45 * The S390 doesn't have any external MMU info: the kernel page
46 * tables contain all the necessary information.
47 */
48#define update_mmu_cache(vma, address, pte) do { } while (0)
49
50/*
51 * ZERO_PAGE is a global shared page that is always zero: used
52 * for zero-mapped memory areas etc..
53 */
54extern char empty_zero_page[PAGE_SIZE];
55#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
56#endif /* !__ASSEMBLY__ */
57
58/*
59 * PMD_SHIFT determines the size of the area a second-level page
60 * table can map
61 * PGDIR_SHIFT determines what a third-level page table entry can map
62 */
63#ifndef __s390x__
64# define PMD_SHIFT 22
65# define PGDIR_SHIFT 22
66#else /* __s390x__ */
67# define PMD_SHIFT 21
68# define PGDIR_SHIFT 31
69#endif /* __s390x__ */
70
71#define PMD_SIZE (1UL << PMD_SHIFT)
72#define PMD_MASK (~(PMD_SIZE-1))
73#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
74#define PGDIR_MASK (~(PGDIR_SIZE-1))
75
76/*
77 * entries per page directory level: the S390 is two-level, so
78 * we don't really have any PMD directory physically.
79 * for S390 segment-table entries are combined to one PGD
80 * that leads to 1024 pte per pgd
81 */
82#ifndef __s390x__
83# define PTRS_PER_PTE 1024
84# define PTRS_PER_PMD 1
85# define PTRS_PER_PGD 512
86#else /* __s390x__ */
87# define PTRS_PER_PTE 512
88# define PTRS_PER_PMD 1024
89# define PTRS_PER_PGD 2048
90#endif /* __s390x__ */
91
d455a369
HD		 92#define FIRST_USER_ADDRESS 0
93
1da177e4
LT		 94#define pte_ERROR(e) \
95 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
96#define pmd_ERROR(e) \
97 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
98#define pgd_ERROR(e) \
99 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
100
101#ifndef __ASSEMBLY__
102/*
103 * Just any arbitrary offset to the start of the vmalloc VM area: the
104 * current 8MB value just means that there will be a 8MB "hole" after the
105 * physical memory until the kernel virtual memory starts. That means that
106 * any out-of-bounds memory accesses will hopefully be caught.
107 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
108 * area for the same reason. ;)
109 */
110#define VMALLOC_OFFSET (8*1024*1024)
111#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) \
112 & ~(VMALLOC_OFFSET-1))
113#ifndef __s390x__
114# define VMALLOC_END (0x7fffffffL)
115#else /* __s390x__ */
116# define VMALLOC_END (0x40000000000L)
117#endif /* __s390x__ */
118
119
120/*
121 * A 31 bit pagetable entry of S390 has following format:
122 * | PFRA | | OS |
123 * 0 0IP0
124 * 00000000001111111111222222222233
125 * 01234567890123456789012345678901
126 *
127 * I Page-Invalid Bit: Page is not available for address-translation
128 * P Page-Protection Bit: Store access not possible for page
129 *
130 * A 31 bit segmenttable entry of S390 has following format:
131 * | P-table origin | |PTL
132 * 0 IC
133 * 00000000001111111111222222222233
134 * 01234567890123456789012345678901
135 *
136 * I Segment-Invalid Bit: Segment is not available for address-translation
137 * C Common-Segment Bit: Segment is not private (PoP 3-30)
138 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
139 *
140 * The 31 bit segmenttable origin of S390 has following format:
141 *
142 * |S-table origin | | STL |
143 * X **GPS
144 * 00000000001111111111222222222233
145 * 01234567890123456789012345678901
146 *
147 * X Space-Switch event:
148 * G Segment-Invalid Bit: *
149 * P Private-Space Bit: Segment is not private (PoP 3-30)
150 * S Storage-Alteration:
151 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
152 *
153 * A 64 bit pagetable entry of S390 has following format:
154 * | PFRA |0IP0| OS |
155 * 0000000000111111111122222222223333333333444444444455555555556666
156 * 0123456789012345678901234567890123456789012345678901234567890123
157 *
158 * I Page-Invalid Bit: Page is not available for address-translation
159 * P Page-Protection Bit: Store access not possible for page
160 *
161 * A 64 bit segmenttable entry of S390 has following format:
162 * | P-table origin | TT
163 * 0000000000111111111122222222223333333333444444444455555555556666
164 * 0123456789012345678901234567890123456789012345678901234567890123
165 *
166 * I Segment-Invalid Bit: Segment is not available for address-translation
167 * C Common-Segment Bit: Segment is not private (PoP 3-30)
168 * P Page-Protection Bit: Store access not possible for page
169 * TT Type 00
170 *
171 * A 64 bit region table entry of S390 has following format:
172 * | S-table origin | TF TTTL
173 * 0000000000111111111122222222223333333333444444444455555555556666
174 * 0123456789012345678901234567890123456789012345678901234567890123
175 *
176 * I Segment-Invalid Bit: Segment is not available for address-translation
177 * TT Type 01
178 * TF
179 * TL Table lenght
180 *
181 * The 64 bit regiontable origin of S390 has following format:
182 * | region table origon | DTTL
183 * 0000000000111111111122222222223333333333444444444455555555556666
184 * 0123456789012345678901234567890123456789012345678901234567890123
185 *
186 * X Space-Switch event:
187 * G Segment-Invalid Bit:
188 * P Private-Space Bit:
189 * S Storage-Alteration:
190 * R Real space
191 * TL Table-Length:
192 *
193 * A storage key has the following format:
194 * | ACC |F|R|C|0|
195 * 0 3 4 5 6 7
196 * ACC: access key
197 * F : fetch protection bit
198 * R : referenced bit
199 * C : changed bit
200 */
201
202/* Hardware bits in the page table entry */
83377484
MS		 203#define _PAGE_RO 0x200 /* HW read-only bit */
204#define _PAGE_INVALID 0x400 /* HW invalid bit */
205#define _PAGE_SWT 0x001 /* SW pte type bit t */
206#define _PAGE_SWX 0x002 /* SW pte type bit x */
1da177e4 207
83377484 208/* Six different types of pages. */
9282ed92
GS		 209#define _PAGE_TYPE_EMPTY 0x400
210#define _PAGE_TYPE_NONE 0x401
83377484
MS		 211#define _PAGE_TYPE_SWAP 0x403
212#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
9282ed92
GS		 213#define _PAGE_TYPE_RO 0x200
214#define _PAGE_TYPE_RW 0x000
1da177e4 215
83377484
MS		 216/*
217 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
218 * pte_none and pte_file to find out the pte type WITHOUT holding the page
219 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
220 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
221 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
222 * This change is done while holding the lock, but the intermediate step
223 * of a previously valid pte with the hw invalid bit set can be observed by
224 * handle_pte_fault. That makes it necessary that all valid pte types with
225 * the hw invalid bit set must be distinguishable from the four pte types
226 * empty, none, swap and file.
227 *
228 * irxt ipte irxt
229 * _PAGE_TYPE_EMPTY 1000 -> 1000
230 * _PAGE_TYPE_NONE 1001 -> 1001
231 * _PAGE_TYPE_SWAP 1011 -> 1011
232 * _PAGE_TYPE_FILE 11?1 -> 11?1
233 * _PAGE_TYPE_RO 0100 -> 1100
234 * _PAGE_TYPE_RW 0000 -> 1000
235 *
236 * pte_none is true for bits combinations 1000, 1100
237 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
238 * pte_file is true for bits combinations 1101, 1111
239 * swap pte is 1011 and 0001, 0011, 0101, 0111, 1010 and 1110 are invalid.
240 */
241
1da177e4
LT		 242#ifndef __s390x__
243
244/* Bits in the segment table entry */
245#define _PAGE_TABLE_LEN 0xf /* only full page-tables */
246#define _PAGE_TABLE_COM 0x10 /* common page-table */
247#define _PAGE_TABLE_INV 0x20 /* invalid page-table */
248#define _SEG_PRESENT 0x001 /* Software (overlap with PTL) */
249
250/* Bits int the storage key */
251#define _PAGE_CHANGED 0x02 /* HW changed bit */
252#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
253
254#define _USER_SEG_TABLE_LEN 0x7f /* user-segment-table up to 2 GB */
255#define _KERNEL_SEG_TABLE_LEN 0x7f /* kernel-segment-table up to 2 GB */
256
257/*
258 * User and Kernel pagetables are identical
259 */
260#define _PAGE_TABLE _PAGE_TABLE_LEN
261#define _KERNPG_TABLE _PAGE_TABLE_LEN
262
263/*
264 * The Kernel segment-tables includes the User segment-table
265 */
266
267#define _SEGMENT_TABLE (_USER_SEG_TABLE_LEN|0x80000000|0x100)
268#define _KERNSEG_TABLE _KERNEL_SEG_TABLE_LEN
269
270#define USER_STD_MASK 0x00000080UL
271
272#else /* __s390x__ */
273
274/* Bits in the segment table entry */
275#define _PMD_ENTRY_INV 0x20 /* invalid segment table entry */
276#define _PMD_ENTRY 0x00
277
278/* Bits in the region third table entry */
279#define _PGD_ENTRY_INV 0x20 /* invalid region table entry */
280#define _PGD_ENTRY 0x07
281
282/*
283 * User and kernel page directory
284 */
285#define _REGION_THIRD 0x4
286#define _REGION_THIRD_LEN 0x3
287#define _REGION_TABLE (_REGION_THIRD|_REGION_THIRD_LEN|0x40|0x100)
288#define _KERN_REGION_TABLE (_REGION_THIRD|_REGION_THIRD_LEN)
289
290#define USER_STD_MASK 0x0000000000000080UL
291
292/* Bits in the storage key */
293#define _PAGE_CHANGED 0x02 /* HW changed bit */
294#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
295
296#endif /* __s390x__ */
297
298/*
9282ed92 299 * Page protection definitions.
1da177e4 300 */
9282ed92
GS		 301#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
302#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
303#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
304
305#define PAGE_KERNEL PAGE_RW
306#define PAGE_COPY PAGE_RO
1da177e4
LT		 307
308/*
309 * The S390 can't do page protection for execute, and considers that the
310 * same are read. Also, write permissions imply read permissions. This is
311 * the closest we can get..
312 */
313 /*xwr*/
9282ed92
GS		 314#define __P000 PAGE_NONE
315#define __P001 PAGE_RO
316#define __P010 PAGE_RO
317#define __P011 PAGE_RO
318#define __P100 PAGE_RO
319#define __P101 PAGE_RO
320#define __P110 PAGE_RO
321#define __P111 PAGE_RO
322
323#define __S000 PAGE_NONE
324#define __S001 PAGE_RO
325#define __S010 PAGE_RW
326#define __S011 PAGE_RW
327#define __S100 PAGE_RO
328#define __S101 PAGE_RO
329#define __S110 PAGE_RW
330#define __S111 PAGE_RW
1da177e4
LT		 331
332/*
333 * Certain architectures need to do special things when PTEs
334 * within a page table are directly modified. Thus, the following
335 * hook is made available.
336 */
4448aaf0 337static inline void set_pte(pte_t *pteptr, pte_t pteval)
1da177e4
LT		 338{
339 *pteptr = pteval;
340}
341#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
342
343/*
344 * pgd/pmd/pte query functions
345 */
346#ifndef __s390x__
347
4448aaf0
AB		 348static inline int pgd_present(pgd_t pgd) { return 1; }
349static inline int pgd_none(pgd_t pgd) { return 0; }
350static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 351
4448aaf0
AB		 352static inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _SEG_PRESENT; }
353static inline int pmd_none(pmd_t pmd) { return pmd_val(pmd) & _PAGE_TABLE_INV; }
354static inline int pmd_bad(pmd_t pmd)
1da177e4
LT		 355{
356 return (pmd_val(pmd) & (~PAGE_MASK & ~_PAGE_TABLE_INV)) != _PAGE_TABLE;
357}
358
359#else /* __s390x__ */
360
4448aaf0 361static inline int pgd_present(pgd_t pgd)
1da177e4
LT		 362{
363 return (pgd_val(pgd) & ~PAGE_MASK) == _PGD_ENTRY;
364}
365
4448aaf0 366static inline int pgd_none(pgd_t pgd)
1da177e4
LT		 367{
368 return pgd_val(pgd) & _PGD_ENTRY_INV;
369}
370
4448aaf0 371static inline int pgd_bad(pgd_t pgd)
1da177e4
LT		 372{
373 return (pgd_val(pgd) & (~PAGE_MASK & ~_PGD_ENTRY_INV)) != _PGD_ENTRY;
374}
375
4448aaf0 376static inline int pmd_present(pmd_t pmd)
1da177e4
LT		 377{
378 return (pmd_val(pmd) & ~PAGE_MASK) == _PMD_ENTRY;
379}
380
4448aaf0 381static inline int pmd_none(pmd_t pmd)
1da177e4
LT		 382{
383 return pmd_val(pmd) & _PMD_ENTRY_INV;
384}
385
4448aaf0 386static inline int pmd_bad(pmd_t pmd)
1da177e4
LT		 387{
388 return (pmd_val(pmd) & (~PAGE_MASK & ~_PMD_ENTRY_INV)) != _PMD_ENTRY;
389}
390
391#endif /* __s390x__ */
392
4448aaf0 393static inline int pte_none(pte_t pte)
1da177e4 394{
83377484 395 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
1da177e4
LT		 396}
397
4448aaf0 398static inline int pte_present(pte_t pte)
1da177e4 399{
83377484
MS		 400 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
401 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
402 (!(pte_val(pte) & _PAGE_INVALID) &&
403 !(pte_val(pte) & _PAGE_SWT));
1da177e4
LT		 404}
405
4448aaf0 406static inline int pte_file(pte_t pte)
1da177e4 407{
83377484
MS		 408 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
409 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
1da177e4
LT		 410}
411
412#define pte_same(a,b) (pte_val(a) == pte_val(b))
413
414/*
415 * query functions pte_write/pte_dirty/pte_young only work if
416 * pte_present() is true. Undefined behaviour if not..
417 */
4448aaf0 418static inline int pte_write(pte_t pte)
1da177e4
LT		 419{
420 return (pte_val(pte) & _PAGE_RO) == 0;
421}
422
4448aaf0 423static inline int pte_dirty(pte_t pte)
1da177e4
LT		 424{
425 /* A pte is neither clean nor dirty on s/390. The dirty bit
426 * is in the storage key. See page_test_and_clear_dirty for
427 * details.
428 */
429 return 0;
430}
431
4448aaf0 432static inline int pte_young(pte_t pte)
1da177e4
LT		 433{
434 /* A pte is neither young nor old on s/390. The young bit
435 * is in the storage key. See page_test_and_clear_young for
436 * details.
437 */
438 return 0;
439}
440
4448aaf0 441static inline int pte_read(pte_t pte)
1da177e4
LT		 442{
443 /* All pages are readable since we don't use the fetch
444 * protection bit in the storage key.
445 */
446 return 1;
447}
448
449/*
450 * pgd/pmd/pte modification functions
451 */
452
453#ifndef __s390x__
454
4448aaf0 455static inline void pgd_clear(pgd_t * pgdp) { }
1da177e4 456
4448aaf0 457static inline void pmd_clear(pmd_t * pmdp)
1da177e4
LT		 458{
459 pmd_val(pmdp[0]) = _PAGE_TABLE_INV;
460 pmd_val(pmdp[1]) = _PAGE_TABLE_INV;
461 pmd_val(pmdp[2]) = _PAGE_TABLE_INV;
462 pmd_val(pmdp[3]) = _PAGE_TABLE_INV;
463}
464
465#else /* __s390x__ */
466
4448aaf0 467static inline void pgd_clear(pgd_t * pgdp)
1da177e4
LT		 468{
469 pgd_val(*pgdp) = _PGD_ENTRY_INV | _PGD_ENTRY;
470}
471
4448aaf0 472static inline void pmd_clear(pmd_t * pmdp)
1da177e4
LT		 473{
474 pmd_val(*pmdp) = _PMD_ENTRY_INV | _PMD_ENTRY;
475 pmd_val1(*pmdp) = _PMD_ENTRY_INV | _PMD_ENTRY;
476}
477
478#endif /* __s390x__ */
479
4448aaf0 480static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 481{
9282ed92 482 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1da177e4
LT		 483}
484
485/*
486 * The following pte modification functions only work if
487 * pte_present() is true. Undefined behaviour if not..
488 */
4448aaf0 489static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4
LT		 490{
491 pte_val(pte) &= PAGE_MASK;
492 pte_val(pte) |= pgprot_val(newprot);
493 return pte;
494}
495
4448aaf0 496static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 497{
9282ed92 498 /* Do not clobber _PAGE_TYPE_NONE pages! */
1da177e4
LT		 499 if (!(pte_val(pte) & _PAGE_INVALID))
500 pte_val(pte) |= _PAGE_RO;
501 return pte;
502}
503
4448aaf0 504static inline pte_t pte_mkwrite(pte_t pte)
1da177e4
LT		 505{
506 pte_val(pte) &= ~_PAGE_RO;
507 return pte;
508}
509
4448aaf0 510static inline pte_t pte_mkclean(pte_t pte)
1da177e4
LT		 511{
512 /* The only user of pte_mkclean is the fork() code.
513 We must *not* clear the *physical* page dirty bit
514 just because fork() wants to clear the dirty bit in
515 *one* of the page's mappings. So we just do nothing. */
516 return pte;
517}
518
4448aaf0 519static inline pte_t pte_mkdirty(pte_t pte)
1da177e4
LT		 520{
521 /* We do not explicitly set the dirty bit because the
522 * sske instruction is slow. It is faster to let the
523 * next instruction set the dirty bit.
524 */
525 return pte;
526}
527
4448aaf0 528static inline pte_t pte_mkold(pte_t pte)
1da177e4
LT		 529{
530 /* S/390 doesn't keep its dirty/referenced bit in the pte.
531 * There is no point in clearing the real referenced bit.
532 */
533 return pte;
534}
535
4448aaf0 536static inline pte_t pte_mkyoung(pte_t pte)
1da177e4
LT		 537{
538 /* S/390 doesn't keep its dirty/referenced bit in the pte.
539 * There is no point in setting the real referenced bit.
540 */
541 return pte;
542}
543
544static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
545{
546 return 0;
547}
548
549static inline int
550ptep_clear_flush_young(struct vm_area_struct *vma,
551 unsigned long address, pte_t *ptep)
552{
553 /* No need to flush TLB; bits are in storage key */
554 return ptep_test_and_clear_young(vma, address, ptep);
555}
556
557static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
558{
559 return 0;
560}
561
562static inline int
563ptep_clear_flush_dirty(struct vm_area_struct *vma,
564 unsigned long address, pte_t *ptep)
565{
566 /* No need to flush TLB; bits are in storage key */
567 return ptep_test_and_clear_dirty(vma, address, ptep);
568}
569
570static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
571{
572 pte_t pte = *ptep;
573 pte_clear(mm, addr, ptep);
574 return pte;
575}
576
9282ed92 577static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 578{
9282ed92 579 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
1da177e4 580#ifndef __s390x__
1da177e4
LT		 581 /* S390 has 1mb segments, we are emulating 4MB segments */
582 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS		 583#else
584 /* ipte in zarch mode can do the math */
585 pte_t *pto = ptep;
586#endif
94c12cc7
MS		 587 asm volatile(
588 " ipte %2,%3"
589 : "=m" (*ptep) : "m" (*ptep),
590 "a" (pto), "a" (address));
1da177e4 591 }
9282ed92
GS		 592 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
593}
594
595static inline pte_t
596ptep_clear_flush(struct vm_area_struct *vma,
597 unsigned long address, pte_t *ptep)
598{
599 pte_t pte = *ptep;
600
601 __ptep_ipte(address, ptep);
1da177e4
LT		 602 return pte;
603}
604
605static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
606{
607 pte_t old_pte = *ptep;
608 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
609}
610
611static inline void
612ptep_establish(struct vm_area_struct *vma,
613 unsigned long address, pte_t *ptep,
614 pte_t entry)
615{
616 ptep_clear_flush(vma, address, ptep);
617 set_pte(ptep, entry);
618}
619
620#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
621 ptep_establish(__vma, __address, __ptep, __entry)
622
623/*
624 * Test and clear dirty bit in storage key.
625 * We can't clear the changed bit atomically. This is a potential
626 * race against modification of the referenced bit. This function
627 * should therefore only be called if it is not mapped in any
628 * address space.
629 */
2dcea57a
HC		 630static inline int page_test_and_clear_dirty(struct page *page)
631{
0b2b6e1d 632 unsigned long physpage = page_to_phys(page);
2dcea57a
HC		 633 int skey = page_get_storage_key(physpage);
634
635 if (skey & _PAGE_CHANGED)
636 page_set_storage_key(physpage, skey & ~_PAGE_CHANGED);
637 return skey & _PAGE_CHANGED;
638}
1da177e4
LT		 639
640/*
641 * Test and clear referenced bit in storage key.
642 */
2dcea57a
HC		 643static inline int page_test_and_clear_young(struct page *page)
644{
0b2b6e1d 645 unsigned long physpage = page_to_phys(page);
2dcea57a
HC		 646 int ccode;
647
0b2b6e1d
HC		 648 asm volatile(
649 " rrbe 0,%1\n"
650 " ipm %0\n"
651 " srl %0,28\n"
2dcea57a
HC		 652 : "=d" (ccode) : "a" (physpage) : "cc" );
653 return ccode & 2;
654}
1da177e4
LT		 655
656/*
657 * Conversion functions: convert a page and protection to a page entry,
658 * and a page entry and page directory to the page they refer to.
659 */
660static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
661{
662 pte_t __pte;
663 pte_val(__pte) = physpage + pgprot_val(pgprot);
664 return __pte;
665}
666
2dcea57a
HC		 667static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
668{
0b2b6e1d 669 unsigned long physpage = page_to_phys(page);
1da177e4 670
2dcea57a
HC		 671 return mk_pte_phys(physpage, pgprot);
672}
673
674static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
675{
676 unsigned long physpage = __pa((pfn) << PAGE_SHIFT);
677
678 return mk_pte_phys(physpage, pgprot);
679}
1da177e4 680
1da177e4
LT		 681#ifdef __s390x__
682
2dcea57a
HC		 683static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
684{
685 unsigned long physpage = __pa((pfn) << PAGE_SHIFT);
686
687 return __pmd(physpage + pgprot_val(pgprot));
688}
1da177e4
LT		 689
690#endif /* __s390x__ */
691
692#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
693#define pte_page(x) pfn_to_page(pte_pfn(x))
694
46a82b2d 695#define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK)
1da177e4 696
0b2b6e1d 697#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 698
46a82b2d
DM		 699#define pgd_page_vaddr(pgd) (pgd_val(pgd) & PAGE_MASK)
700
0b2b6e1d 701#define pgd_page(pgd) pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT)
1da177e4
LT		 702
703/* to find an entry in a page-table-directory */
704#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
705#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
706
707/* to find an entry in a kernel page-table-directory */
708#define pgd_offset_k(address) pgd_offset(&init_mm, address)
709
710#ifndef __s390x__
711
712/* Find an entry in the second-level page table.. */
4448aaf0 713static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
1da177e4
LT		 714{
715 return (pmd_t *) dir;
716}
717
718#else /* __s390x__ */
719
720/* Find an entry in the second-level page table.. */
721#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
722#define pmd_offset(dir,addr) \
46a82b2d 723 ((pmd_t *) pgd_page_vaddr(*(dir)) + pmd_index(addr))
1da177e4
LT		 724
725#endif /* __s390x__ */
726
727/* Find an entry in the third-level page table.. */
728#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
729#define pte_offset_kernel(pmd, address) \
46a82b2d 730 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
1da177e4
LT		 731#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
732#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
733#define pte_unmap(pte) do { } while (0)
734#define pte_unmap_nested(pte) do { } while (0)
735
736/*
737 * 31 bit swap entry format:
738 * A page-table entry has some bits we have to treat in a special way.
739 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
740 * exception will occur instead of a page translation exception. The
741 * specifiation exception has the bad habit not to store necessary
742 * information in the lowcore.
743 * Bit 21 and bit 22 are the page invalid bit and the page protection
744 * bit. We set both to indicate a swapped page.
745 * Bit 30 and 31 are used to distinguish the different page types. For
746 * a swapped page these bits need to be zero.
747 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
748 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
749 * plus 24 for the offset.
750 * 0| offset |0110|o|type |00|
751 * 0 0000000001111111111 2222 2 22222 33
752 * 0 1234567890123456789 0123 4 56789 01
753 *
754 * 64 bit swap entry format:
755 * A page-table entry has some bits we have to treat in a special way.
756 * Bits 52 and bit 55 have to be zero, otherwise an specification
757 * exception will occur instead of a page translation exception. The
758 * specifiation exception has the bad habit not to store necessary
759 * information in the lowcore.
760 * Bit 53 and bit 54 are the page invalid bit and the page protection
761 * bit. We set both to indicate a swapped page.
762 * Bit 62 and 63 are used to distinguish the different page types. For
763 * a swapped page these bits need to be zero.
764 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
765 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
766 * plus 56 for the offset.
767 * | offset |0110|o|type |00|
768 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
769 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
770 */
771#ifndef __s390x__
772#define __SWP_OFFSET_MASK (~0UL >> 12)
773#else
774#define __SWP_OFFSET_MASK (~0UL >> 11)
775#endif
4448aaf0 776static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 777{
778 pte_t pte;
779 offset &= __SWP_OFFSET_MASK;
9282ed92 780 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1da177e4
LT		 781 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
782 return pte;
783}
784
785#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
786#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
787#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
788
789#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
790#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
791
792#ifndef __s390x__
793# define PTE_FILE_MAX_BITS 26
794#else /* __s390x__ */
795# define PTE_FILE_MAX_BITS 59
796#endif /* __s390x__ */
797
798#define pte_to_pgoff(__pte) \
799 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
800
801#define pgoff_to_pte(__off) \
802 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
9282ed92 803 | _PAGE_TYPE_FILE })
1da177e4
LT		 804
805#endif /* !__ASSEMBLY__ */
806
807#define kern_addr_valid(addr) (1)
808
809/*
810 * No page table caches to initialise
811 */
812#define pgtable_cache_init() do { } while (0)
813
814#define __HAVE_ARCH_PTEP_ESTABLISH
815#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
816#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
817#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
818#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
819#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
820#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
821#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
822#define __HAVE_ARCH_PTEP_SET_WRPROTECT
823#define __HAVE_ARCH_PTE_SAME
824#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
825#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
826#include <asm-generic/pgtable.h>
827
828#endif /* _S390_PAGE_H */
829
Linux kernel - Deliverables
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