[deliverable/linux.git] / include / asm-x86 / cpufeature.h

/*
 * Defines x86 CPU feature bits
 */
#ifndef _ASM_X86_CPUFEATURE_H
#define _ASM_X86_CPUFEATURE_H

#include <asm/required-features.h>

#define NCAPINTS	8	/* N 32-bit words worth of info */

/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
#define X86_FEATURE_FPU		(0*32+ 0) /* Onboard FPU */
#define X86_FEATURE_VME		(0*32+ 1) /* Virtual Mode Extensions */
#define X86_FEATURE_DE		(0*32+ 2) /* Debugging Extensions */
#define X86_FEATURE_PSE		(0*32+ 3) /* Page Size Extensions */
#define X86_FEATURE_TSC		(0*32+ 4) /* Time Stamp Counter */
#define X86_FEATURE_MSR		(0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
#define X86_FEATURE_PAE		(0*32+ 6) /* Physical Address Extensions */
#define X86_FEATURE_MCE		(0*32+ 7) /* Machine Check Architecture */
#define X86_FEATURE_CX8		(0*32+ 8) /* CMPXCHG8 instruction */
#define X86_FEATURE_APIC	(0*32+ 9) /* Onboard APIC */
#define X86_FEATURE_SEP		(0*32+11) /* SYSENTER/SYSEXIT */
#define X86_FEATURE_MTRR	(0*32+12) /* Memory Type Range Registers */
#define X86_FEATURE_PGE		(0*32+13) /* Page Global Enable */
#define X86_FEATURE_MCA		(0*32+14) /* Machine Check Architecture */
#define X86_FEATURE_CMOV	(0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
#define X86_FEATURE_PAT		(0*32+16) /* Page Attribute Table */
#define X86_FEATURE_PSE36	(0*32+17) /* 36-bit PSEs */
#define X86_FEATURE_PN		(0*32+18) /* Processor serial number */
#define X86_FEATURE_CLFLSH	(0*32+19) /* Supports the CLFLUSH instruction */
#define X86_FEATURE_DS		(0*32+21) /* Debug Store */
#define X86_FEATURE_ACPI	(0*32+22) /* ACPI via MSR */
#define X86_FEATURE_MMX		(0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR	(0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
					  /* of FPU context), and CR4.OSFXSR available */
#define X86_FEATURE_XMM		(0*32+25) /* Streaming SIMD Extensions */
#define X86_FEATURE_XMM2	(0*32+26) /* Streaming SIMD Extensions-2 */
#define X86_FEATURE_SELFSNOOP	(0*32+27) /* CPU self snoop */
#define X86_FEATURE_HT		(0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC		(0*32+29) /* Automatic clock control */
#define X86_FEATURE_IA64	(0*32+30) /* IA-64 processor */

/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
#define X86_FEATURE_SYSCALL	(1*32+11) /* SYSCALL/SYSRET */
#define X86_FEATURE_MP		(1*32+19) /* MP Capable. */
#define X86_FEATURE_NX		(1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT	(1*32+22) /* AMD MMX extensions */
#define X86_FEATURE_RDTSCP	(1*32+27) /* RDTSCP */
#define X86_FEATURE_LM		(1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT	(1*32+30) /* AMD 3DNow! extensions */
#define X86_FEATURE_3DNOW	(1*32+31) /* 3DNow! */

/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
#define X86_FEATURE_RECOVERY	(2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN	(2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI	(2*32+ 3) /* LongRun table interface */

/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
#define X86_FEATURE_CXMMX	(3*32+ 0) /* Cyrix MMX extensions */
#define X86_FEATURE_K6_MTRR	(3*32+ 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR	(3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR	(3*32+ 3) /* Centaur MCRs (= MTRRs) */
/* cpu types for specific tunings: */
#define X86_FEATURE_K8		(3*32+ 4) /* Opteron, Athlon64 */
#define X86_FEATURE_K7		(3*32+ 5) /* Athlon */
#define X86_FEATURE_P3		(3*32+ 6) /* P3 */
#define X86_FEATURE_P4		(3*32+ 7) /* P4 */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS	(3*32+12)  /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS		(3*32+13)  /* Branch Trace Store */
/* 14 free */
/* 15 free */
#define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well on this CPU */
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
#define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
#define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
#define X86_FEATURE_CID		(4*32+10) /* Context ID */
#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE	(5*32+ 2) /* on-CPU RNG present (xstore insn) */
#define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* on-CPU RNG enabled */
#define X86_FEATURE_XCRYPT	(5*32+ 6) /* on-CPU crypto (xcrypt insn) */
#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* on-CPU crypto enabled */
#define X86_FEATURE_ACE2	(5*32+ 8) /* Advanced Cryptography Engine v2 */
#define X86_FEATURE_ACE2_EN	(5*32+ 9) /* ACE v2 enabled */
#define X86_FEATURE_PHE		(5*32+ 10) /* PadLock Hash Engine */
#define X86_FEATURE_PHE_EN	(5*32+ 11) /* PHE enabled */
#define X86_FEATURE_PMM		(5*32+ 12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN	(5*32+ 13) /* PMM enabled */

/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */

/*
 * Auxiliary flags: Linux defined - For features scattered in various
 * CPUID levels like 0x6, 0xA etc
 */
#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */

#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

#include <linux/bitops.h>

extern const char * const x86_cap_flags[NCAPINTS*32];
extern const char * const x86_power_flags[32];

#define cpu_has(c, bit)							\
	(__builtin_constant_p(bit) &&					\
	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\
	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\
	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\
	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\
	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\
	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\
	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\
	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )	\
	  ? 1 :								\
	 test_bit(bit, (unsigned long *)((c)->x86_capability)))
#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)

#define set_cpu_cap(c, bit)	set_bit(bit, (unsigned long *)((c)->x86_capability))
#define clear_cpu_cap(c, bit)	clear_bit(bit, (unsigned long *)((c)->x86_capability))
#define setup_clear_cpu_cap(bit) do { \
	clear_cpu_cap(&boot_cpu_data, bit);	\
	set_bit(bit, cleared_cpu_caps); 	\
} while (0)
#define setup_force_cpu_cap(bit) do { \
	set_cpu_cap(&boot_cpu_data, bit);	\
	clear_bit(bit, cleared_cpu_caps); 	\
} while (0)

#define cpu_has_fpu		boot_cpu_has(X86_FEATURE_FPU)
#define cpu_has_vme		boot_cpu_has(X86_FEATURE_VME)
#define cpu_has_de		boot_cpu_has(X86_FEATURE_DE)
#define cpu_has_pse		boot_cpu_has(X86_FEATURE_PSE)
#define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
#define cpu_has_pae		boot_cpu_has(X86_FEATURE_PAE)
#define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
#define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
#define cpu_has_sep		boot_cpu_has(X86_FEATURE_SEP)
#define cpu_has_mtrr		boot_cpu_has(X86_FEATURE_MTRR)
#define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
#define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)
#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)
#define cpu_has_centaur_mcr	boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
#define cpu_has_xstore		boot_cpu_has(X86_FEATURE_XSTORE)
#define cpu_has_xstore_enabled	boot_cpu_has(X86_FEATURE_XSTORE_EN)
#define cpu_has_xcrypt		boot_cpu_has(X86_FEATURE_XCRYPT)
#define cpu_has_xcrypt_enabled	boot_cpu_has(X86_FEATURE_XCRYPT_EN)
#define cpu_has_ace2		boot_cpu_has(X86_FEATURE_ACE2)
#define cpu_has_ace2_enabled	boot_cpu_has(X86_FEATURE_ACE2_EN)
#define cpu_has_phe		boot_cpu_has(X86_FEATURE_PHE)
#define cpu_has_phe_enabled	boot_cpu_has(X86_FEATURE_PHE_EN)
#define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)
#define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)
#define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)
#define cpu_has_pebs		boot_cpu_has(X86_FEATURE_PEBS)
#define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
#define cpu_has_bts		boot_cpu_has(X86_FEATURE_BTS)

#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
# define cpu_has_invlpg		1
#else
# define cpu_has_invlpg		(boot_cpu_data.x86 > 3)
#endif

#ifdef CONFIG_X86_64

#undef  cpu_has_vme
#define cpu_has_vme		0

#undef  cpu_has_pae
#define cpu_has_pae		___BUG___

#undef  cpu_has_mp
#define cpu_has_mp		1

#undef  cpu_has_k6_mtrr
#define cpu_has_k6_mtrr		0

#undef  cpu_has_cyrix_arr
#define cpu_has_cyrix_arr	0

#undef  cpu_has_centaur_mcr
#define cpu_has_centaur_mcr	0

#endif /* CONFIG_X86_64 */

#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */

#endif /* _ASM_X86_CPUFEATURE_H */
Commit	Line	Data
7b11fb51 PA	1	/*
	2	* Defines x86 CPU feature bits
	3	*/
	4	#ifndef _ASM_X86_CPUFEATURE_H
	5	#define _ASM_X86_CPUFEATURE_H
	6
7b11fb51 PA	7	#include <asm/required-features.h>
	8
	9	#define NCAPINTS 8 /* N 32-bit words worth of info */
	10
	11	/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
	12	#define X86_FEATURE_FPU (032+ 0) / Onboard FPU */
	13	#define X86_FEATURE_VME (032+ 1) / Virtual Mode Extensions */
	14	#define X86_FEATURE_DE (032+ 2) / Debugging Extensions */
	15	#define X86_FEATURE_PSE (032+ 3) / Page Size Extensions */
	16	#define X86_FEATURE_TSC (032+ 4) / Time Stamp Counter */
	17	#define X86_FEATURE_MSR (032+ 5) / Model-Specific Registers, RDMSR, WRMSR */
	18	#define X86_FEATURE_PAE (032+ 6) / Physical Address Extensions */
	19	#define X86_FEATURE_MCE (032+ 7) / Machine Check Architecture */
	20	#define X86_FEATURE_CX8 (032+ 8) / CMPXCHG8 instruction */
	21	#define X86_FEATURE_APIC (032+ 9) / Onboard APIC */
	22	#define X86_FEATURE_SEP (032+11) / SYSENTER/SYSEXIT */
	23	#define X86_FEATURE_MTRR (032+12) / Memory Type Range Registers */
	24	#define X86_FEATURE_PGE (032+13) / Page Global Enable */
	25	#define X86_FEATURE_MCA (032+14) / Machine Check Architecture */
	26	#define X86_FEATURE_CMOV (032+15) / CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
	27	#define X86_FEATURE_PAT (032+16) / Page Attribute Table */
	28	#define X86_FEATURE_PSE36 (032+17) / 36-bit PSEs */
	29	#define X86_FEATURE_PN (032+18) / Processor serial number */
	30	#define X86_FEATURE_CLFLSH (032+19) / Supports the CLFLUSH instruction */
	31	#define X86_FEATURE_DS (032+21) / Debug Store */
	32	#define X86_FEATURE_ACPI (032+22) / ACPI via MSR */
	33	#define X86_FEATURE_MMX (032+23) / Multimedia Extensions */
	34	#define X86_FEATURE_FXSR (032+24) / FXSAVE and FXRSTOR instructions (fast save and restore */
	35	/* of FPU context), and CR4.OSFXSR available */
	36	#define X86_FEATURE_XMM (032+25) / Streaming SIMD Extensions */
	37	#define X86_FEATURE_XMM2 (032+26) / Streaming SIMD Extensions-2 */
	38	#define X86_FEATURE_SELFSNOOP (032+27) / CPU self snoop */
	39	#define X86_FEATURE_HT (032+28) / Hyper-Threading */
	40	#define X86_FEATURE_ACC (032+29) / Automatic clock control */
	41	#define X86_FEATURE_IA64 (032+30) / IA-64 processor */
	42
	43	/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
	44	/* Don't duplicate feature flags which are redundant with Intel! */
	45	#define X86_FEATURE_SYSCALL (132+11) / SYSCALL/SYSRET */
	46	#define X86_FEATURE_MP (132+19) / MP Capable. */
	47	#define X86_FEATURE_NX (132+20) / Execute Disable */
	48	#define X86_FEATURE_MMXEXT (132+22) / AMD MMX extensions */
	49	#define X86_FEATURE_RDTSCP (132+27) / RDTSCP */
	50	#define X86_FEATURE_LM (132+29) / Long Mode (x86-64) */
	51	#define X86_FEATURE_3DNOWEXT (132+30) / AMD 3DNow! extensions */
	52	#define X86_FEATURE_3DNOW (132+31) / 3DNow! */
	53
	54	/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
	55	#define X86_FEATURE_RECOVERY (232+ 0) / CPU in recovery mode */
	56	#define X86_FEATURE_LONGRUN (232+ 1) / Longrun power control */
	57	#define X86_FEATURE_LRTI (232+ 3) / LongRun table interface */
	58
	59	/* Other features, Linux-defined mapping, word 3 */
	60	/* This range is used for feature bits which conflict or are synthesized */
	61	#define X86_FEATURE_CXMMX (332+ 0) / Cyrix MMX extensions */
	62	#define X86_FEATURE_K6_MTRR (332+ 1) / AMD K6 nonstandard MTRRs */
	63	#define X86_FEATURE_CYRIX_ARR (332+ 2) / Cyrix ARRs (= MTRRs) */
	64	#define X86_FEATURE_CENTAUR_MCR (332+ 3) / Centaur MCRs (= MTRRs) */
	65	/* cpu types for specific tunings: */
	66	#define X86_FEATURE_K8 (332+ 4) / Opteron, Athlon64 */
	67	#define X86_FEATURE_K7 (332+ 5) / Athlon */
	68	#define X86_FEATURE_P3 (332+ 6) / P3 */
	69	#define X86_FEATURE_P4 (332+ 7) / P4 */
	70	#define X86_FEATURE_CONSTANT_TSC (332+ 8) / TSC ticks at a constant rate */
71	#define X86_FEATURE_UP (332+ 9) / smp kernel running on up */
72	#define X86_FEATURE_FXSAVE_LEAK (332+10) / FXSAVE leaks FOP/FIP/FOP */
73	#define X86_FEATURE_ARCH_PERFMON (332+11) / Intel Architectural PerfMon */
74	#define X86_FEATURE_PEBS (332+12) / Precise-Event Based Sampling */
75	#define X86_FEATURE_BTS (332+13) / Branch Trace Store */
76	/* 14 free */
68071a96	77	/* 15 free */
7b11fb51	78	#define X86_FEATURE_REP_GOOD (332+16) / rep microcode works well on this CPU */
de421863	79	#define X86_FEATURE_MFENCE_RDTSC (332+17) / Mfence synchronizes RDTSC */
707fa8ed	80	#define X86_FEATURE_LFENCE_RDTSC (332+18) / Lfence synchronizes RDTSC */
7b11fb51 PA	81
	82	/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
	83	#define X86_FEATURE_XMM3 (432+ 0) / Streaming SIMD Extensions-3 */
	84	#define X86_FEATURE_MWAIT (432+ 3) / Monitor/Mwait support */
	85	#define X86_FEATURE_DSCPL (432+ 4) / CPL Qualified Debug Store */
	86	#define X86_FEATURE_EST (432+ 7) / Enhanced SpeedStep */
	87	#define X86_FEATURE_TM2 (432+ 8) / Thermal Monitor 2 */
	88	#define X86_FEATURE_CID (432+10) / Context ID */
	89	#define X86_FEATURE_CX16 (432+13) / CMPXCHG16B */
	90	#define X86_FEATURE_XTPR (432+14) / Send Task Priority Messages */
	91	#define X86_FEATURE_DCA (432+18) / Direct Cache Access */
	92
	93	/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
	94	#define X86_FEATURE_XSTORE (532+ 2) / on-CPU RNG present (xstore insn) */
	95	#define X86_FEATURE_XSTORE_EN (532+ 3) / on-CPU RNG enabled */
	96	#define X86_FEATURE_XCRYPT (532+ 6) / on-CPU crypto (xcrypt insn) */
	97	#define X86_FEATURE_XCRYPT_EN (532+ 7) / on-CPU crypto enabled */
	98	#define X86_FEATURE_ACE2 (532+ 8) / Advanced Cryptography Engine v2 */
	99	#define X86_FEATURE_ACE2_EN (532+ 9) / ACE v2 enabled */
	100	#define X86_FEATURE_PHE (532+ 10) / PadLock Hash Engine */
	101	#define X86_FEATURE_PHE_EN (532+ 11) / PHE enabled */
	102	#define X86_FEATURE_PMM (532+ 12) / PadLock Montgomery Multiplier */
	103	#define X86_FEATURE_PMM_EN (532+ 13) / PMM enabled */
	104
	105	/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
	106	#define X86_FEATURE_LAHF_LM (632+ 0) / LAHF/SAHF in long mode */
	107	#define X86_FEATURE_CMP_LEGACY (632+ 1) / If yes HyperThreading not valid */
	108
	109	/*
	110	* Auxiliary flags: Linux defined - For features scattered in various
	111	* CPUID levels like 0x6, 0xA etc
	112	*/
	113	#define X86_FEATURE_IDA (732+ 0) / Intel Dynamic Acceleration */
	114
fa1408e4 PA	115	#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
	116
	117	#include <linux/bitops.h>
	118
	119	extern const char * const x86_cap_flags[NCAPINTS*32];
	120	extern const char * const x86_power_flags[32];
	121
7b11fb51 PA	122	#define cpu_has(c, bit) \
	123	(__builtin_constant_p(bit) && \
	124	( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) \|\| \
	125	(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) \|\| \
	126	(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) \|\| \
	127	(((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) \|\| \
	128	(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) \|\| \
	129	(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) \|\| \
	130	(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) \|\| \
	131	(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
	132	? 1 : \
53756d37	133	test_bit(bit, (unsigned long *)((c)->x86_capability)))
7b11fb51 PA	134	#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
7b11fb51 PA	135
53756d37 JF	136	#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
53756d37 JF	137	#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
7d851c8d AK	138	#define setup_clear_cpu_cap(bit) do { \
	139	clear_cpu_cap(&boot_cpu_data, bit); \
	140	set_bit(bit, cleared_cpu_caps); \
	141	} while (0)
404ee5b1 AK	142	#define setup_force_cpu_cap(bit) do { \
	143	set_cpu_cap(&boot_cpu_data, bit); \
	144	clear_bit(bit, cleared_cpu_caps); \
	145	} while (0)
53756d37	146
7b11fb51 PA	147	#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
	148	#define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
	149	#define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
	150	#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
	151	#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
	152	#define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
	153	#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
	154	#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
	155	#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
	156	#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
	157	#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
	158	#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
	159	#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
	160	#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
	161	#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
	162	#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
	163	#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
	164	#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
	165	#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
	166	#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
	167	#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
	168	#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
	169	#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
	170	#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
	171	#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
	172	#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
	173	#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
	174	#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
	175	#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
	176	#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
	177	#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
	178	#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
	179	#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
	180	#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
	181	#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
	182
0b9c99b6 TG	183	#if defined(CONFIG_X86_INVLPG) \|\| defined(CONFIG_X86_64)
	184	# define cpu_has_invlpg 1
	185	#else
	186	# define cpu_has_invlpg (boot_cpu_data.x86 > 3)
	187	#endif
	188
7b11fb51 PA	189	#ifdef CONFIG_X86_64
	190
	191	#undef cpu_has_vme
	192	#define cpu_has_vme 0
	193
	194	#undef cpu_has_pae
	195	#define cpu_has_pae ___BUG___
	196
	197	#undef cpu_has_mp
	198	#define cpu_has_mp 1
	199
	200	#undef cpu_has_k6_mtrr
	201	#define cpu_has_k6_mtrr 0
	202
	203	#undef cpu_has_cyrix_arr
	204	#define cpu_has_cyrix_arr 0
	205
	206	#undef cpu_has_centaur_mcr
	207	#define cpu_has_centaur_mcr 0
	208
	209	#endif /* CONFIG_X86_64 */
	210
fa1408e4 PA	211	#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
fa1408e4 PA	212
7b11fb51	213	#endif /* _ASM_X86_CPUFEATURE_H */