[deliverable/linux.git] / include / linux / amba / clcd.h

/*
 * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
 *
 * David A Rusling
 *
 * Copyright (C) 2001 ARM Limited
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */
#include <linux/fb.h>

/*
 * CLCD Controller Internal Register addresses
 */
#define CLCD_TIM0		0x00000000
#define CLCD_TIM1 		0x00000004
#define CLCD_TIM2 		0x00000008
#define CLCD_TIM3 		0x0000000c
#define CLCD_UBAS 		0x00000010
#define CLCD_LBAS 		0x00000014

#define CLCD_PL110_IENB		0x00000018
#define CLCD_PL110_CNTL		0x0000001c
#define CLCD_PL110_STAT		0x00000020
#define CLCD_PL110_INTR 	0x00000024
#define CLCD_PL110_UCUR		0x00000028
#define CLCD_PL110_LCUR		0x0000002C

#define CLCD_PL111_CNTL		0x00000018
#define CLCD_PL111_IENB		0x0000001c
#define CLCD_PL111_RIS		0x00000020
#define CLCD_PL111_MIS		0x00000024
#define CLCD_PL111_ICR		0x00000028
#define CLCD_PL111_UCUR		0x0000002c
#define CLCD_PL111_LCUR		0x00000030

#define CLCD_PALL 		0x00000200
#define CLCD_PALETTE		0x00000200

#define TIM2_CLKSEL		(1 << 5)
#define TIM2_IVS		(1 << 11)
#define TIM2_IHS		(1 << 12)
#define TIM2_IPC		(1 << 13)
#define TIM2_IOE		(1 << 14)
#define TIM2_BCD		(1 << 26)

#define CNTL_LCDEN		(1 << 0)
#define CNTL_LCDBPP1		(0 << 1)
#define CNTL_LCDBPP2		(1 << 1)
#define CNTL_LCDBPP4		(2 << 1)
#define CNTL_LCDBPP8		(3 << 1)
#define CNTL_LCDBPP16		(4 << 1)
#define CNTL_LCDBPP16_565	(6 << 1)
#define CNTL_LCDBPP16_444	(7 << 1)
#define CNTL_LCDBPP24		(5 << 1)
#define CNTL_LCDBW		(1 << 4)
#define CNTL_LCDTFT		(1 << 5)
#define CNTL_LCDMONO8		(1 << 6)
#define CNTL_LCDDUAL		(1 << 7)
#define CNTL_BGR		(1 << 8)
#define CNTL_BEBO		(1 << 9)
#define CNTL_BEPO		(1 << 10)
#define CNTL_LCDPWR		(1 << 11)
#define CNTL_LCDVCOMP(x)	((x) << 12)
#define CNTL_LDMAFIFOTIME	(1 << 15)
#define CNTL_WATERMARK		(1 << 16)

/* ST Microelectronics variant bits */
#define CNTL_ST_1XBPP_444	0x0
#define CNTL_ST_1XBPP_5551	(1 << 17)
#define CNTL_ST_1XBPP_565	(1 << 18)
#define CNTL_ST_CDWID_12	0x0
#define CNTL_ST_CDWID_16	(1 << 19)
#define CNTL_ST_CDWID_18	(1 << 20)
#define CNTL_ST_CDWID_24	((1 << 19)|(1 << 20))
#define CNTL_ST_CEAEN		(1 << 21)
#define CNTL_ST_LCDBPP24_PACKED	(6 << 1)

enum {
	/* individual formats */
	CLCD_CAP_RGB444		= (1 << 0),
	CLCD_CAP_RGB5551	= (1 << 1),
	CLCD_CAP_RGB565		= (1 << 2),
	CLCD_CAP_RGB888		= (1 << 3),
	CLCD_CAP_BGR444		= (1 << 4),
	CLCD_CAP_BGR5551	= (1 << 5),
	CLCD_CAP_BGR565		= (1 << 6),
	CLCD_CAP_BGR888		= (1 << 7),

	/* connection layouts */
	CLCD_CAP_444		= CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
	CLCD_CAP_5551		= CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
	CLCD_CAP_565		= CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
	CLCD_CAP_888		= CLCD_CAP_RGB888 | CLCD_CAP_BGR888,

	/* red/blue ordering */
	CLCD_CAP_RGB		= CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
				  CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
	CLCD_CAP_BGR		= CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
				  CLCD_CAP_BGR565 | CLCD_CAP_BGR888,

	CLCD_CAP_ALL		= CLCD_CAP_BGR | CLCD_CAP_RGB,
};

struct backlight_device;

struct clcd_panel {
	struct fb_videomode	mode;
	signed short		width;	/* width in mm */
	signed short		height;	/* height in mm */
	u32			tim2;
	u32			tim3;
	u32			cntl;
	u32			caps;
	unsigned int		bpp:8,
				fixedtimings:1,
				grayscale:1;
	unsigned int		connector;
	struct backlight_device	*backlight;
	/*
	 * If the B/R lines are switched between the CLCD
	 * and the panel we need to know this and not try to
	 * compensate with the BGR bit in the control register.
	 */
	bool			bgr_connection;
};

struct clcd_regs {
	u32			tim0;
	u32			tim1;
	u32			tim2;
	u32			tim3;
	u32			cntl;
	unsigned long		pixclock;
};

struct clcd_fb;

/*
 * the board-type specific routines
 */
struct clcd_board {
	const char *name;

	/*
	 * Optional.  Hardware capability flags.
	 */
	u32	caps;

	/*
	 * Optional.  Check whether the var structure is acceptable
	 * for this display.
	 */
	int	(*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);

	/*
	 * Compulsory.  Decode fb->fb.var into regs->*.  In the case of
	 * fixed timing, set regs->* to the register values required.
	 */
	void	(*decode)(struct clcd_fb *fb, struct clcd_regs *regs);

	/*
	 * Optional.  Disable any extra display hardware.
	 */
	void	(*disable)(struct clcd_fb *);

	/*
	 * Optional.  Enable any extra display hardware.
	 */
	void	(*enable)(struct clcd_fb *);

	/*
	 * Setup platform specific parts of CLCD driver
	 */
	int	(*setup)(struct clcd_fb *);

	/*
	 * mmap the framebuffer memory
	 */
	int	(*mmap)(struct clcd_fb *, struct vm_area_struct *);

	/*
	 * Remove platform specific parts of CLCD driver
	 */
	void	(*remove)(struct clcd_fb *);
};

struct amba_device;
struct clk;

/**
 * struct clcd_vendor_data - holds hardware (IP-block) vendor-specific
 * variant information
 *
 * @clock_timregs: the CLCD needs to be clocked when accessing the
 * timer registers, or the hardware will hang.
 * @packed_24_bit_pixels: this variant supports 24bit packed pixel data,
 * so that RGB accesses 3 bytes at a time, not just on even 32bit
 * boundaries, packing the pixel data in memory. ST Microelectronics
 * have this.
 * @st_bitmux_control: ST Microelectronics have implemented output
 * bit line multiplexing into the CLCD control register. This indicates
 * that we need to use this.
 * @init_board: custom board init function for this variant
 * @init_panel: custom panel init function for this variant
 */
struct clcd_vendor_data {
	bool	clock_timregs;
	bool	packed_24_bit_pixels;
	bool	st_bitmux_control;
	int	(*init_board)(struct amba_device *adev,
			      struct clcd_board *board);
	int	(*init_panel)(struct clcd_fb *fb,
			      struct device_node *panel);
};

/* this data structure describes each frame buffer device we find */
struct clcd_fb {
	struct fb_info		fb;
	struct amba_device	*dev;
	struct clk		*clk;
	struct clcd_vendor_data	*vendor;
	struct clcd_panel	*panel;
	struct clcd_board	*board;
	void			*board_data;
	void __iomem		*regs;
	u16			off_ienb;
	u16			off_cntl;
	u32			clcd_cntl;
	u32			cmap[16];
	bool			clk_enabled;
};

static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val, cpl;

	/*
	 * Program the CLCD controller registers and start the CLCD
	 */
	val = ((var->xres / 16) - 1) << 2;
	val |= (var->hsync_len - 1) << 8;
	val |= (var->right_margin - 1) << 16;
	val |= (var->left_margin - 1) << 24;
	regs->tim0 = val;

	val = var->yres;
	if (fb->panel->cntl & CNTL_LCDDUAL)
		val /= 2;
	val -= 1;
	val |= (var->vsync_len - 1) << 10;
	val |= var->lower_margin << 16;
	val |= var->upper_margin << 24;
	regs->tim1 = val;

	val = fb->panel->tim2;
	val |= var->sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
	val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;

	cpl = var->xres_virtual;
	if (fb->panel->cntl & CNTL_LCDTFT)	  /* TFT */
		/* / 1 */;
	else if (!var->grayscale)		  /* STN color */
		cpl = cpl * 8 / 3;
	else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
		cpl /= 8;
	else					  /* STN monochrome, 4bit */
		cpl /= 4;

	regs->tim2 = val | ((cpl - 1) << 16);

	regs->tim3 = fb->panel->tim3;

	val = fb->panel->cntl;
	if (var->grayscale)
		val |= CNTL_LCDBW;

	if (fb->panel->caps && fb->board->caps && var->bits_per_pixel >= 16) {
		/*
		 * if board and panel supply capabilities, we can support
		 * changing BGR/RGB depending on supplied parameters. Here
		 * we switch to what the framebuffer is providing if need
		 * be, so if the framebuffer is BGR but the display connection
		 * is RGB (first case) we switch it around. Vice versa mutatis
		 * mutandis if the framebuffer is RGB but the display connection
		 * is BGR, we flip it around.
		 */
		if (var->red.offset == 0)
			val &= ~CNTL_BGR;
		else
			val |= CNTL_BGR;
		if (fb->panel->bgr_connection)
			val ^= CNTL_BGR;
	}

	switch (var->bits_per_pixel) {
	case 1:
		val |= CNTL_LCDBPP1;
		break;
	case 2:
		val |= CNTL_LCDBPP2;
		break;
	case 4:
		val |= CNTL_LCDBPP4;
		break;
	case 8:
		val |= CNTL_LCDBPP8;
		break;
	case 16:
		/*
		 * PL110 cannot choose between 5551 and 565 modes in its
		 * control register.  It is possible to use 565 with
		 * custom external wiring.
		 */
		if (amba_part(fb->dev) == 0x110 ||
		    var->green.length == 5)
			val |= CNTL_LCDBPP16;
		else if (var->green.length == 6)
			val |= CNTL_LCDBPP16_565;
		else
			val |= CNTL_LCDBPP16_444;
		break;
	case 24:
		/* Modified variant supporting 24 bit packed pixels */
		val |= CNTL_ST_LCDBPP24_PACKED;
		break;
	case 32:
		val |= CNTL_LCDBPP24;
		break;
	}

	regs->cntl = val;
	regs->pixclock = var->pixclock;
}

static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
{
	var->xres_virtual = var->xres = (var->xres + 15) & ~15;
	var->yres_virtual = var->yres = (var->yres + 1) & ~1;

#define CHECK(e,l,h) (var->e < l || var->e > h)
	if (CHECK(right_margin, (5+1), 256) ||	/* back porch */
	    CHECK(left_margin, (5+1), 256) ||	/* front porch */
	    CHECK(hsync_len, (5+1), 256) ||
	    var->xres > 4096 ||
	    var->lower_margin > 255 ||		/* back porch */
	    var->upper_margin > 255 ||		/* front porch */
	    var->vsync_len > 32 ||
	    var->yres > 1024)
		return -EINVAL;
#undef CHECK

	/* single panel mode: PCD = max(PCD, 1) */
	/* dual panel mode: PCD = max(PCD, 5) */

	/*
	 * You can't change the grayscale setting, and
	 * we can only do non-interlaced video.
	 */
	if (var->grayscale != fb->fb.var.grayscale ||
	    (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
		return -EINVAL;

#define CHECK(e) (var->e != fb->fb.var.e)
	if (fb->panel->fixedtimings &&
	    (CHECK(xres)		||
	     CHECK(yres)		||
	     CHECK(bits_per_pixel)	||
	     CHECK(pixclock)		||
	     CHECK(left_margin)		||
	     CHECK(right_margin)	||
	     CHECK(upper_margin)	||
	     CHECK(lower_margin)	||
	     CHECK(hsync_len)		||
	     CHECK(vsync_len)		||
	     CHECK(sync)))
		return -EINVAL;
#undef CHECK

	var->nonstd = 0;
	var->accel_flags = 0;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
	3	*
	4	* David A Rusling
	5	*
	6	* Copyright (C) 2001 ARM Limited
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file COPYING in the main directory of this archive
	10	* for more details.
	11	*/
1da177e4 LT	12	#include <linux/fb.h>
	13
	14	/*
	15	* CLCD Controller Internal Register addresses
	16	*/
	17	#define CLCD_TIM0 0x00000000
	18	#define CLCD_TIM1 0x00000004
	19	#define CLCD_TIM2 0x00000008
	20	#define CLCD_TIM3 0x0000000c
	21	#define CLCD_UBAS 0x00000010
	22	#define CLCD_LBAS 0x00000014
	23
3f17522c RK	24	#define CLCD_PL110_IENB 0x00000018
	25	#define CLCD_PL110_CNTL 0x0000001c
	26	#define CLCD_PL110_STAT 0x00000020
	27	#define CLCD_PL110_INTR 0x00000024
	28	#define CLCD_PL110_UCUR 0x00000028
	29	#define CLCD_PL110_LCUR 0x0000002C
	30
	31	#define CLCD_PL111_CNTL 0x00000018
	32	#define CLCD_PL111_IENB 0x0000001c
	33	#define CLCD_PL111_RIS 0x00000020
	34	#define CLCD_PL111_MIS 0x00000024
	35	#define CLCD_PL111_ICR 0x00000028
	36	#define CLCD_PL111_UCUR 0x0000002c
	37	#define CLCD_PL111_LCUR 0x00000030
	38
1da177e4 LT	39	#define CLCD_PALL 0x00000200
	40	#define CLCD_PALETTE 0x00000200
	41
	42	#define TIM2_CLKSEL (1 << 5)
	43	#define TIM2_IVS (1 << 11)
	44	#define TIM2_IHS (1 << 12)
	45	#define TIM2_IPC (1 << 13)
	46	#define TIM2_IOE (1 << 14)
	47	#define TIM2_BCD (1 << 26)
	48
	49	#define CNTL_LCDEN (1 << 0)
	50	#define CNTL_LCDBPP1 (0 << 1)
	51	#define CNTL_LCDBPP2 (1 << 1)
	52	#define CNTL_LCDBPP4 (2 << 1)
	53	#define CNTL_LCDBPP8 (3 << 1)
	54	#define CNTL_LCDBPP16 (4 << 1)
243f196d	55	#define CNTL_LCDBPP16_565 (6 << 1)
7b4e9ced	56	#define CNTL_LCDBPP16_444 (7 << 1)
1da177e4 LT	57	#define CNTL_LCDBPP24 (5 << 1)
	58	#define CNTL_LCDBW (1 << 4)
	59	#define CNTL_LCDTFT (1 << 5)
	60	#define CNTL_LCDMONO8 (1 << 6)
	61	#define CNTL_LCDDUAL (1 << 7)
	62	#define CNTL_BGR (1 << 8)
	63	#define CNTL_BEBO (1 << 9)
	64	#define CNTL_BEPO (1 << 10)
	65	#define CNTL_LCDPWR (1 << 11)
	66	#define CNTL_LCDVCOMP(x) ((x) << 12)
	67	#define CNTL_LDMAFIFOTIME (1 << 15)
	68	#define CNTL_WATERMARK (1 << 16)
	69
046ad6cd LW	70	/* ST Microelectronics variant bits */
	71	#define CNTL_ST_1XBPP_444 0x0
	72	#define CNTL_ST_1XBPP_5551 (1 << 17)
	73	#define CNTL_ST_1XBPP_565 (1 << 18)
	74	#define CNTL_ST_CDWID_12 0x0
	75	#define CNTL_ST_CDWID_16 (1 << 19)
	76	#define CNTL_ST_CDWID_18 (1 << 20)
	77	#define CNTL_ST_CDWID_24 ((1 << 19)\|(1 << 20))
	78	#define CNTL_ST_CEAEN (1 << 21)
	79	#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
	80
7b4e9ced RK	81	enum {
	82	/* individual formats */
	83	CLCD_CAP_RGB444 = (1 << 0),
	84	CLCD_CAP_RGB5551 = (1 << 1),
	85	CLCD_CAP_RGB565 = (1 << 2),
	86	CLCD_CAP_RGB888 = (1 << 3),
	87	CLCD_CAP_BGR444 = (1 << 4),
	88	CLCD_CAP_BGR5551 = (1 << 5),
	89	CLCD_CAP_BGR565 = (1 << 6),
	90	CLCD_CAP_BGR888 = (1 << 7),
	91
	92	/* connection layouts */
	93	CLCD_CAP_444 = CLCD_CAP_RGB444 \| CLCD_CAP_BGR444,
	94	CLCD_CAP_5551 = CLCD_CAP_RGB5551 \| CLCD_CAP_BGR5551,
	95	CLCD_CAP_565 = CLCD_CAP_RGB565 \| CLCD_CAP_BGR565,
	96	CLCD_CAP_888 = CLCD_CAP_RGB888 \| CLCD_CAP_BGR888,
	97
	98	/* red/blue ordering */
	99	CLCD_CAP_RGB = CLCD_CAP_RGB444 \| CLCD_CAP_RGB5551 \|
	100	CLCD_CAP_RGB565 \| CLCD_CAP_RGB888,
	101	CLCD_CAP_BGR = CLCD_CAP_BGR444 \| CLCD_CAP_BGR5551 \|
	102	CLCD_CAP_BGR565 \| CLCD_CAP_BGR888,
	103
	104	CLCD_CAP_ALL = CLCD_CAP_BGR \| CLCD_CAP_RGB,
	105	};
	106
c38162be LW	107	struct backlight_device;
c38162be LW	108
1da177e4 LT	109	struct clcd_panel {
	110	struct fb_videomode mode;
	111	signed short width; /* width in mm */
	112	signed short height; /* height in mm */
	113	u32 tim2;
	114	u32 tim3;
	115	u32 cntl;
7b4e9ced	116	u32 caps;
1da177e4 LT	117	unsigned int bpp:8,
	118	fixedtimings:1,
	119	grayscale:1;
	120	unsigned int connector;
c38162be	121	struct backlight_device *backlight;
03d14c36 LW	122	/*
	123	* If the B/R lines are switched between the CLCD
	124	* and the panel we need to know this and not try to
	125	* compensate with the BGR bit in the control register.
	126	*/
	127	bool bgr_connection;
1da177e4 LT	128	};
	129
	130	struct clcd_regs {
	131	u32 tim0;
	132	u32 tim1;
	133	u32 tim2;
	134	u32 tim3;
	135	u32 cntl;
	136	unsigned long pixclock;
	137	};
	138
	139	struct clcd_fb;
	140
	141	/*
	142	* the board-type specific routines
	143	*/
	144	struct clcd_board {
	145	const char *name;
	146
7b4e9ced RK	147	/*
	148	* Optional. Hardware capability flags.
	149	*/
	150	u32 caps;
	151
1da177e4 LT	152	/*
	153	* Optional. Check whether the var structure is acceptable
	154	* for this display.
	155	*/
	156	int (check)(struct clcd_fb fb, struct fb_var_screeninfo *var);
	157
	158	/*
25985edc	159	* Compulsory. Decode fb->fb.var into regs->*. In the case of
1da177e4 LT	160	* fixed timing, set regs->* to the register values required.
	161	*/
	162	void (decode)(struct clcd_fb fb, struct clcd_regs *regs);
	163
	164	/*
	165	* Optional. Disable any extra display hardware.
	166	*/
	167	void (disable)(struct clcd_fb );
	168
	169	/*
	170	* Optional. Enable any extra display hardware.
	171	*/
	172	void (enable)(struct clcd_fb );
	173
	174	/*
	175	* Setup platform specific parts of CLCD driver
	176	*/
	177	int (setup)(struct clcd_fb );
	178
	179	/*
	180	* mmap the framebuffer memory
	181	*/
	182	int (mmap)(struct clcd_fb , struct vm_area_struct *);
	183
	184	/*
	185	* Remove platform specific parts of CLCD driver
	186	*/
	187	void (remove)(struct clcd_fb );
	188	};
	189
	190	struct amba_device;
	191	struct clk;
	192
046ad6cd LW	193	/**
	194	* struct clcd_vendor_data - holds hardware (IP-block) vendor-specific
	195	* variant information
	196	*
	197	* @clock_timregs: the CLCD needs to be clocked when accessing the
	198	* timer registers, or the hardware will hang.
	199	* @packed_24_bit_pixels: this variant supports 24bit packed pixel data,
	200	* so that RGB accesses 3 bytes at a time, not just on even 32bit
	201	* boundaries, packing the pixel data in memory. ST Microelectronics
	202	* have this.
	203	* @st_bitmux_control: ST Microelectronics have implemented output
	204	* bit line multiplexing into the CLCD control register. This indicates
	205	* that we need to use this.
	206	* @init_board: custom board init function for this variant
	207	* @init_panel: custom panel init function for this variant
	208	*/
	209	struct clcd_vendor_data {
	210	bool clock_timregs;
	211	bool packed_24_bit_pixels;
	212	bool st_bitmux_control;
	213	int (init_board)(struct amba_device adev,
	214	struct clcd_board *board);
	215	int (init_panel)(struct clcd_fb fb,
	216	struct device_node *panel);
	217	};
	218
1da177e4 LT	219	/* this data structure describes each frame buffer device we find */
	220	struct clcd_fb {
	221	struct fb_info fb;
	222	struct amba_device *dev;
	223	struct clk *clk;
046ad6cd	224	struct clcd_vendor_data *vendor;
1da177e4 LT	225	struct clcd_panel *panel;
	226	struct clcd_board *board;
	227	void *board_data;
	228	void __iomem *regs;
3f17522c RK	229	u16 off_ienb;
3f17522c RK	230	u16 off_cntl;
1da177e4 LT	231	u32 clcd_cntl;
1da177e4 LT	232	u32 cmap[16];
99c796df	233	bool clk_enabled;
1da177e4 LT	234	};
	235
	236	static inline void clcdfb_decode(struct clcd_fb fb, struct clcd_regs regs)
	237	{
7b4e9ced	238	struct fb_var_screeninfo *var = &fb->fb.var;
c4d12b98	239	u32 val, cpl;
1da177e4 LT	240
	241	/*
	242	* Program the CLCD controller registers and start the CLCD
	243	*/
7b4e9ced RK	244	val = ((var->xres / 16) - 1) << 2;
	245	val \|= (var->hsync_len - 1) << 8;
	246	val \|= (var->right_margin - 1) << 16;
	247	val \|= (var->left_margin - 1) << 24;
1da177e4 LT	248	regs->tim0 = val;
1da177e4 LT	249
7b4e9ced	250	val = var->yres;
c4d12b98 RK	251	if (fb->panel->cntl & CNTL_LCDDUAL)
	252	val /= 2;
	253	val -= 1;
7b4e9ced RK	254	val \|= (var->vsync_len - 1) << 10;
	255	val \|= var->lower_margin << 16;
	256	val \|= var->upper_margin << 24;
1da177e4 LT	257	regs->tim1 = val;
	258
	259	val = fb->panel->tim2;
7b4e9ced RK	260	val \|= var->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
7b4e9ced RK	261	val \|= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
1da177e4	262
7b4e9ced	263	cpl = var->xres_virtual;
c4d12b98 RK	264	if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
c4d12b98 RK	265	/* / 1 */;
7b4e9ced	266	else if (!var->grayscale) /* STN color */
c4d12b98 RK	267	cpl = cpl * 8 / 3;
	268	else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
	269	cpl /= 8;
	270	else /* STN monochrome, 4bit */
	271	cpl /= 4;
	272
	273	regs->tim2 = val \| ((cpl - 1) << 16);
1da177e4 LT	274
	275	regs->tim3 = fb->panel->tim3;
	276
	277	val = fb->panel->cntl;
7b4e9ced	278	if (var->grayscale)
1da177e4 LT	279	val \|= CNTL_LCDBW;
1da177e4 LT	280
03d14c36	281	if (fb->panel->caps && fb->board->caps && var->bits_per_pixel >= 16) {
7b4e9ced RK	282	/*
7b4e9ced RK	283	* if board and panel supply capabilities, we can support
03d14c36 LW	284	* changing BGR/RGB depending on supplied parameters. Here
	285	* we switch to what the framebuffer is providing if need
	286	* be, so if the framebuffer is BGR but the display connection
	287	* is RGB (first case) we switch it around. Vice versa mutatis
	288	* mutandis if the framebuffer is RGB but the display connection
	289	* is BGR, we flip it around.
7b4e9ced RK	290	*/
	291	if (var->red.offset == 0)
	292	val &= ~CNTL_BGR;
	293	else
	294	val \|= CNTL_BGR;
03d14c36 LW	295	if (fb->panel->bgr_connection)
03d14c36 LW	296	val ^= CNTL_BGR;
7b4e9ced RK	297	}
	298
	299	switch (var->bits_per_pixel) {
1da177e4 LT	300	case 1:
	301	val \|= CNTL_LCDBPP1;
	302	break;
	303	case 2:
	304	val \|= CNTL_LCDBPP2;
	305	break;
	306	case 4:
	307	val \|= CNTL_LCDBPP4;
	308	break;
	309	case 8:
	310	val \|= CNTL_LCDBPP8;
	311	break;
	312	case 16:
243f196d	313	/*
9c49e4ab RK	314	* PL110 cannot choose between 5551 and 565 modes in its
	315	* control register. It is possible to use 565 with
	316	* custom external wiring.
243f196d	317	*/
9c49e4ab	318	if (amba_part(fb->dev) == 0x110 \|\|
7b4e9ced	319	var->green.length == 5)
243f196d	320	val \|= CNTL_LCDBPP16;
7b4e9ced	321	else if (var->green.length == 6)
243f196d	322	val \|= CNTL_LCDBPP16_565;
7b4e9ced RK	323	else
7b4e9ced RK	324	val \|= CNTL_LCDBPP16_444;
1da177e4	325	break;
046ad6cd LW	326	case 24:
	327	/* Modified variant supporting 24 bit packed pixels */
	328	val \|= CNTL_ST_LCDBPP24_PACKED;
	329	break;
82235e91	330	case 32:
1da177e4 LT	331	val \|= CNTL_LCDBPP24;
	332	break;
	333	}
	334
	335	regs->cntl = val;
7b4e9ced	336	regs->pixclock = var->pixclock;
1da177e4 LT	337	}
	338
	339	static inline int clcdfb_check(struct clcd_fb fb, struct fb_var_screeninfo var)
	340	{
0f7ad450	341	var->xres_virtual = var->xres = (var->xres + 15) & ~15;
c4d12b98	342	var->yres_virtual = var->yres = (var->yres + 1) & ~1;
1da177e4 LT	343
	344	#define CHECK(e,l,h) (var->e < l \|\| var->e > h)
	345	if (CHECK(right_margin, (5+1), 256) \|\| /* back porch */
	346	CHECK(left_margin, (5+1), 256) \|\| /* front porch */
	347	CHECK(hsync_len, (5+1), 256) \|\|
	348	var->xres > 4096 \|\|
	349	var->lower_margin > 255 \|\| /* back porch */
	350	var->upper_margin > 255 \|\| /* front porch */
	351	var->vsync_len > 32 \|\|
	352	var->yres > 1024)
	353	return -EINVAL;
	354	#undef CHECK
	355
	356	/* single panel mode: PCD = max(PCD, 1) */
	357	/* dual panel mode: PCD = max(PCD, 5) */
	358
	359	/*
	360	* You can't change the grayscale setting, and
	361	* we can only do non-interlaced video.
	362	*/
	363	if (var->grayscale != fb->fb.var.grayscale \|\|
	364	(var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
	365	return -EINVAL;
	366
	367	#define CHECK(e) (var->e != fb->fb.var.e)
	368	if (fb->panel->fixedtimings &&
	369	(CHECK(xres) \|\|
	370	CHECK(yres) \|\|
	371	CHECK(bits_per_pixel) \|\|
	372	CHECK(pixclock) \|\|
	373	CHECK(left_margin) \|\|
	374	CHECK(right_margin) \|\|
	375	CHECK(upper_margin) \|\|
	376	CHECK(lower_margin) \|\|
	377	CHECK(hsync_len) \|\|
	378	CHECK(vsync_len) \|\|
	379	CHECK(sync)))
	380	return -EINVAL;
	381	#undef CHECK
	382
	383	var->nonstd = 0;
	384	var->accel_flags = 0;
	385
	386	return 0;
	387	}