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cfb61a41 CC |
1 | /* |
2 | * Functions and registers to access AXP20X power management chip. | |
3 | * | |
4 | * Copyright (C) 2013, Carlo Caione <carlo@caione.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __LINUX_MFD_AXP20X_H | |
12 | #define __LINUX_MFD_AXP20X_H | |
13 | ||
69fb4dca HG |
14 | #include <linux/regmap.h> |
15 | ||
cfb61a41 | 16 | enum { |
d8d79f8f MS |
17 | AXP152_ID = 0, |
18 | AXP202_ID, | |
cfb61a41 | 19 | AXP209_ID, |
f05be589 | 20 | AXP221_ID, |
af7e9069 JP |
21 | AXP288_ID, |
22 | NR_AXP20X_VARIANTS, | |
cfb61a41 CC |
23 | }; |
24 | ||
25 | #define AXP20X_DATACACHE(m) (0x04 + (m)) | |
26 | ||
27 | /* Power supply */ | |
d8d79f8f MS |
28 | #define AXP152_PWR_OP_MODE 0x01 |
29 | #define AXP152_LDO3456_DC1234_CTRL 0x12 | |
30 | #define AXP152_ALDO_OP_MODE 0x13 | |
31 | #define AXP152_LDO0_CTRL 0x15 | |
32 | #define AXP152_DCDC2_V_OUT 0x23 | |
33 | #define AXP152_DCDC2_V_SCAL 0x25 | |
34 | #define AXP152_DCDC1_V_OUT 0x26 | |
35 | #define AXP152_DCDC3_V_OUT 0x27 | |
36 | #define AXP152_ALDO12_V_OUT 0x28 | |
37 | #define AXP152_DLDO1_V_OUT 0x29 | |
38 | #define AXP152_DLDO2_V_OUT 0x2a | |
39 | #define AXP152_DCDC4_V_OUT 0x2b | |
40 | #define AXP152_V_OFF 0x31 | |
41 | #define AXP152_OFF_CTRL 0x32 | |
42 | #define AXP152_PEK_KEY 0x36 | |
43 | #define AXP152_DCDC_FREQ 0x37 | |
44 | #define AXP152_DCDC_MODE 0x80 | |
45 | ||
cfb61a41 CC |
46 | #define AXP20X_PWR_INPUT_STATUS 0x00 |
47 | #define AXP20X_PWR_OP_MODE 0x01 | |
48 | #define AXP20X_USB_OTG_STATUS 0x02 | |
49 | #define AXP20X_PWR_OUT_CTRL 0x12 | |
50 | #define AXP20X_DCDC2_V_OUT 0x23 | |
51 | #define AXP20X_DCDC2_LDO3_V_SCAL 0x25 | |
52 | #define AXP20X_DCDC3_V_OUT 0x27 | |
53 | #define AXP20X_LDO24_V_OUT 0x28 | |
54 | #define AXP20X_LDO3_V_OUT 0x29 | |
55 | #define AXP20X_VBUS_IPSOUT_MGMT 0x30 | |
56 | #define AXP20X_V_OFF 0x31 | |
57 | #define AXP20X_OFF_CTRL 0x32 | |
58 | #define AXP20X_CHRG_CTRL1 0x33 | |
59 | #define AXP20X_CHRG_CTRL2 0x34 | |
60 | #define AXP20X_CHRG_BAK_CTRL 0x35 | |
61 | #define AXP20X_PEK_KEY 0x36 | |
62 | #define AXP20X_DCDC_FREQ 0x37 | |
63 | #define AXP20X_V_LTF_CHRG 0x38 | |
64 | #define AXP20X_V_HTF_CHRG 0x39 | |
65 | #define AXP20X_APS_WARN_L1 0x3a | |
66 | #define AXP20X_APS_WARN_L2 0x3b | |
67 | #define AXP20X_V_LTF_DISCHRG 0x3c | |
68 | #define AXP20X_V_HTF_DISCHRG 0x3d | |
69 | ||
f05be589 BB |
70 | #define AXP22X_PWR_OUT_CTRL1 0x10 |
71 | #define AXP22X_PWR_OUT_CTRL2 0x12 | |
72 | #define AXP22X_PWR_OUT_CTRL3 0x13 | |
73 | #define AXP22X_DLDO1_V_OUT 0x15 | |
74 | #define AXP22X_DLDO2_V_OUT 0x16 | |
75 | #define AXP22X_DLDO3_V_OUT 0x17 | |
76 | #define AXP22X_DLDO4_V_OUT 0x18 | |
77 | #define AXP22X_ELDO1_V_OUT 0x19 | |
78 | #define AXP22X_ELDO2_V_OUT 0x1a | |
79 | #define AXP22X_ELDO3_V_OUT 0x1b | |
80 | #define AXP22X_DC5LDO_V_OUT 0x1c | |
81 | #define AXP22X_DCDC1_V_OUT 0x21 | |
82 | #define AXP22X_DCDC2_V_OUT 0x22 | |
83 | #define AXP22X_DCDC3_V_OUT 0x23 | |
84 | #define AXP22X_DCDC4_V_OUT 0x24 | |
85 | #define AXP22X_DCDC5_V_OUT 0x25 | |
86 | #define AXP22X_DCDC23_V_RAMP_CTRL 0x27 | |
87 | #define AXP22X_ALDO1_V_OUT 0x28 | |
88 | #define AXP22X_ALDO2_V_OUT 0x29 | |
89 | #define AXP22X_ALDO3_V_OUT 0x2a | |
90 | #define AXP22X_CHRG_CTRL3 0x35 | |
91 | ||
cfb61a41 | 92 | /* Interrupt */ |
d8d79f8f MS |
93 | #define AXP152_IRQ1_EN 0x40 |
94 | #define AXP152_IRQ2_EN 0x41 | |
95 | #define AXP152_IRQ3_EN 0x42 | |
96 | #define AXP152_IRQ1_STATE 0x48 | |
97 | #define AXP152_IRQ2_STATE 0x49 | |
98 | #define AXP152_IRQ3_STATE 0x4a | |
99 | ||
cfb61a41 CC |
100 | #define AXP20X_IRQ1_EN 0x40 |
101 | #define AXP20X_IRQ2_EN 0x41 | |
102 | #define AXP20X_IRQ3_EN 0x42 | |
103 | #define AXP20X_IRQ4_EN 0x43 | |
104 | #define AXP20X_IRQ5_EN 0x44 | |
af7e9069 | 105 | #define AXP20X_IRQ6_EN 0x45 |
cfb61a41 CC |
106 | #define AXP20X_IRQ1_STATE 0x48 |
107 | #define AXP20X_IRQ2_STATE 0x49 | |
108 | #define AXP20X_IRQ3_STATE 0x4a | |
109 | #define AXP20X_IRQ4_STATE 0x4b | |
110 | #define AXP20X_IRQ5_STATE 0x4c | |
af7e9069 | 111 | #define AXP20X_IRQ6_STATE 0x4d |
cfb61a41 CC |
112 | |
113 | /* ADC */ | |
114 | #define AXP20X_ACIN_V_ADC_H 0x56 | |
115 | #define AXP20X_ACIN_V_ADC_L 0x57 | |
116 | #define AXP20X_ACIN_I_ADC_H 0x58 | |
117 | #define AXP20X_ACIN_I_ADC_L 0x59 | |
118 | #define AXP20X_VBUS_V_ADC_H 0x5a | |
119 | #define AXP20X_VBUS_V_ADC_L 0x5b | |
120 | #define AXP20X_VBUS_I_ADC_H 0x5c | |
121 | #define AXP20X_VBUS_I_ADC_L 0x5d | |
122 | #define AXP20X_TEMP_ADC_H 0x5e | |
123 | #define AXP20X_TEMP_ADC_L 0x5f | |
124 | #define AXP20X_TS_IN_H 0x62 | |
125 | #define AXP20X_TS_IN_L 0x63 | |
126 | #define AXP20X_GPIO0_V_ADC_H 0x64 | |
127 | #define AXP20X_GPIO0_V_ADC_L 0x65 | |
128 | #define AXP20X_GPIO1_V_ADC_H 0x66 | |
129 | #define AXP20X_GPIO1_V_ADC_L 0x67 | |
130 | #define AXP20X_PWR_BATT_H 0x70 | |
131 | #define AXP20X_PWR_BATT_M 0x71 | |
132 | #define AXP20X_PWR_BATT_L 0x72 | |
133 | #define AXP20X_BATT_V_H 0x78 | |
134 | #define AXP20X_BATT_V_L 0x79 | |
135 | #define AXP20X_BATT_CHRG_I_H 0x7a | |
136 | #define AXP20X_BATT_CHRG_I_L 0x7b | |
137 | #define AXP20X_BATT_DISCHRG_I_H 0x7c | |
138 | #define AXP20X_BATT_DISCHRG_I_L 0x7d | |
139 | #define AXP20X_IPSOUT_V_HIGH_H 0x7e | |
140 | #define AXP20X_IPSOUT_V_HIGH_L 0x7f | |
141 | ||
142 | /* Power supply */ | |
143 | #define AXP20X_DCDC_MODE 0x80 | |
144 | #define AXP20X_ADC_EN1 0x82 | |
145 | #define AXP20X_ADC_EN2 0x83 | |
146 | #define AXP20X_ADC_RATE 0x84 | |
147 | #define AXP20X_GPIO10_IN_RANGE 0x85 | |
148 | #define AXP20X_GPIO1_ADC_IRQ_RIS 0x86 | |
149 | #define AXP20X_GPIO1_ADC_IRQ_FAL 0x87 | |
150 | #define AXP20X_TIMER_CTRL 0x8a | |
151 | #define AXP20X_VBUS_MON 0x8b | |
152 | #define AXP20X_OVER_TMP 0x8f | |
153 | ||
f05be589 BB |
154 | #define AXP22X_PWREN_CTRL1 0x8c |
155 | #define AXP22X_PWREN_CTRL2 0x8d | |
156 | ||
cfb61a41 | 157 | /* GPIO */ |
d8d79f8f MS |
158 | #define AXP152_GPIO0_CTRL 0x90 |
159 | #define AXP152_GPIO1_CTRL 0x91 | |
160 | #define AXP152_GPIO2_CTRL 0x92 | |
161 | #define AXP152_GPIO3_CTRL 0x93 | |
162 | #define AXP152_LDOGPIO2_V_OUT 0x96 | |
163 | #define AXP152_GPIO_INPUT 0x97 | |
164 | #define AXP152_PWM0_FREQ_X 0x98 | |
165 | #define AXP152_PWM0_FREQ_Y 0x99 | |
166 | #define AXP152_PWM0_DUTY_CYCLE 0x9a | |
167 | #define AXP152_PWM1_FREQ_X 0x9b | |
168 | #define AXP152_PWM1_FREQ_Y 0x9c | |
169 | #define AXP152_PWM1_DUTY_CYCLE 0x9d | |
170 | ||
cfb61a41 CC |
171 | #define AXP20X_GPIO0_CTRL 0x90 |
172 | #define AXP20X_LDO5_V_OUT 0x91 | |
173 | #define AXP20X_GPIO1_CTRL 0x92 | |
174 | #define AXP20X_GPIO2_CTRL 0x93 | |
175 | #define AXP20X_GPIO20_SS 0x94 | |
176 | #define AXP20X_GPIO3_CTRL 0x95 | |
177 | ||
f05be589 BB |
178 | #define AXP22X_LDO_IO0_V_OUT 0x91 |
179 | #define AXP22X_LDO_IO1_V_OUT 0x93 | |
180 | #define AXP22X_GPIO_STATE 0x94 | |
181 | #define AXP22X_GPIO_PULL_DOWN 0x95 | |
182 | ||
cfb61a41 CC |
183 | /* Battery */ |
184 | #define AXP20X_CHRG_CC_31_24 0xb0 | |
185 | #define AXP20X_CHRG_CC_23_16 0xb1 | |
186 | #define AXP20X_CHRG_CC_15_8 0xb2 | |
187 | #define AXP20X_CHRG_CC_7_0 0xb3 | |
188 | #define AXP20X_DISCHRG_CC_31_24 0xb4 | |
189 | #define AXP20X_DISCHRG_CC_23_16 0xb5 | |
190 | #define AXP20X_DISCHRG_CC_15_8 0xb6 | |
191 | #define AXP20X_DISCHRG_CC_7_0 0xb7 | |
192 | #define AXP20X_CC_CTRL 0xb8 | |
193 | #define AXP20X_FG_RES 0xb9 | |
194 | ||
553ed4b5 BP |
195 | /* OCV */ |
196 | #define AXP20X_RDC_H 0xba | |
197 | #define AXP20X_RDC_L 0xbb | |
198 | #define AXP20X_OCV(m) (0xc0 + (m)) | |
199 | #define AXP20X_OCV_MAX 0xf | |
200 | ||
f05be589 BB |
201 | /* AXP22X specific registers */ |
202 | #define AXP22X_BATLOW_THRES1 0xe6 | |
203 | ||
af7e9069 JP |
204 | /* AXP288 specific registers */ |
205 | #define AXP288_PMIC_ADC_H 0x56 | |
206 | #define AXP288_PMIC_ADC_L 0x57 | |
207 | #define AXP288_ADC_TS_PIN_CTRL 0x84 | |
af7e9069 | 208 | #define AXP288_PMIC_ADC_EN 0x84 |
af7e9069 | 209 | |
774e0b41 TB |
210 | /* Fuel Gauge */ |
211 | #define AXP288_FG_RDC1_REG 0xba | |
212 | #define AXP288_FG_RDC0_REG 0xbb | |
213 | #define AXP288_FG_OCVH_REG 0xbc | |
214 | #define AXP288_FG_OCVL_REG 0xbd | |
215 | #define AXP288_FG_OCV_CURVE_REG 0xc0 | |
216 | #define AXP288_FG_DES_CAP1_REG 0xe0 | |
217 | #define AXP288_FG_DES_CAP0_REG 0xe1 | |
218 | #define AXP288_FG_CC_MTR1_REG 0xe2 | |
219 | #define AXP288_FG_CC_MTR0_REG 0xe3 | |
220 | #define AXP288_FG_OCV_CAP_REG 0xe4 | |
221 | #define AXP288_FG_CC_CAP_REG 0xe5 | |
222 | #define AXP288_FG_LOW_CAP_REG 0xe6 | |
223 | #define AXP288_FG_TUNE0 0xe8 | |
224 | #define AXP288_FG_TUNE1 0xe9 | |
225 | #define AXP288_FG_TUNE2 0xea | |
226 | #define AXP288_FG_TUNE3 0xeb | |
227 | #define AXP288_FG_TUNE4 0xec | |
228 | #define AXP288_FG_TUNE5 0xed | |
af7e9069 | 229 | |
cfb61a41 CC |
230 | /* Regulators IDs */ |
231 | enum { | |
232 | AXP20X_LDO1 = 0, | |
233 | AXP20X_LDO2, | |
234 | AXP20X_LDO3, | |
235 | AXP20X_LDO4, | |
236 | AXP20X_LDO5, | |
237 | AXP20X_DCDC2, | |
238 | AXP20X_DCDC3, | |
239 | AXP20X_REG_ID_MAX, | |
240 | }; | |
241 | ||
f05be589 BB |
242 | enum { |
243 | AXP22X_DCDC1 = 0, | |
244 | AXP22X_DCDC2, | |
245 | AXP22X_DCDC3, | |
246 | AXP22X_DCDC4, | |
247 | AXP22X_DCDC5, | |
248 | AXP22X_DC1SW, | |
249 | AXP22X_DC5LDO, | |
250 | AXP22X_ALDO1, | |
251 | AXP22X_ALDO2, | |
252 | AXP22X_ALDO3, | |
253 | AXP22X_ELDO1, | |
254 | AXP22X_ELDO2, | |
255 | AXP22X_ELDO3, | |
256 | AXP22X_DLDO1, | |
257 | AXP22X_DLDO2, | |
258 | AXP22X_DLDO3, | |
259 | AXP22X_DLDO4, | |
260 | AXP22X_RTC_LDO, | |
261 | AXP22X_LDO_IO0, | |
262 | AXP22X_LDO_IO1, | |
263 | AXP22X_REG_ID_MAX, | |
264 | }; | |
265 | ||
cfb61a41 | 266 | /* IRQs */ |
d8d79f8f MS |
267 | enum { |
268 | AXP152_IRQ_LDO0IN_CONNECT = 1, | |
269 | AXP152_IRQ_LDO0IN_REMOVAL, | |
270 | AXP152_IRQ_ALDO0IN_CONNECT, | |
271 | AXP152_IRQ_ALDO0IN_REMOVAL, | |
272 | AXP152_IRQ_DCDC1_V_LOW, | |
273 | AXP152_IRQ_DCDC2_V_LOW, | |
274 | AXP152_IRQ_DCDC3_V_LOW, | |
275 | AXP152_IRQ_DCDC4_V_LOW, | |
276 | AXP152_IRQ_PEK_SHORT, | |
277 | AXP152_IRQ_PEK_LONG, | |
278 | AXP152_IRQ_TIMER, | |
279 | AXP152_IRQ_PEK_RIS_EDGE, | |
280 | AXP152_IRQ_PEK_FAL_EDGE, | |
281 | AXP152_IRQ_GPIO3_INPUT, | |
282 | AXP152_IRQ_GPIO2_INPUT, | |
283 | AXP152_IRQ_GPIO1_INPUT, | |
284 | AXP152_IRQ_GPIO0_INPUT, | |
285 | }; | |
286 | ||
cfb61a41 CC |
287 | enum { |
288 | AXP20X_IRQ_ACIN_OVER_V = 1, | |
289 | AXP20X_IRQ_ACIN_PLUGIN, | |
290 | AXP20X_IRQ_ACIN_REMOVAL, | |
291 | AXP20X_IRQ_VBUS_OVER_V, | |
292 | AXP20X_IRQ_VBUS_PLUGIN, | |
293 | AXP20X_IRQ_VBUS_REMOVAL, | |
294 | AXP20X_IRQ_VBUS_V_LOW, | |
295 | AXP20X_IRQ_BATT_PLUGIN, | |
296 | AXP20X_IRQ_BATT_REMOVAL, | |
297 | AXP20X_IRQ_BATT_ENT_ACT_MODE, | |
298 | AXP20X_IRQ_BATT_EXIT_ACT_MODE, | |
299 | AXP20X_IRQ_CHARG, | |
300 | AXP20X_IRQ_CHARG_DONE, | |
301 | AXP20X_IRQ_BATT_TEMP_HIGH, | |
302 | AXP20X_IRQ_BATT_TEMP_LOW, | |
303 | AXP20X_IRQ_DIE_TEMP_HIGH, | |
304 | AXP20X_IRQ_CHARG_I_LOW, | |
305 | AXP20X_IRQ_DCDC1_V_LONG, | |
306 | AXP20X_IRQ_DCDC2_V_LONG, | |
307 | AXP20X_IRQ_DCDC3_V_LONG, | |
308 | AXP20X_IRQ_PEK_SHORT = 22, | |
309 | AXP20X_IRQ_PEK_LONG, | |
310 | AXP20X_IRQ_N_OE_PWR_ON, | |
311 | AXP20X_IRQ_N_OE_PWR_OFF, | |
312 | AXP20X_IRQ_VBUS_VALID, | |
313 | AXP20X_IRQ_VBUS_NOT_VALID, | |
314 | AXP20X_IRQ_VBUS_SESS_VALID, | |
315 | AXP20X_IRQ_VBUS_SESS_END, | |
316 | AXP20X_IRQ_LOW_PWR_LVL1, | |
317 | AXP20X_IRQ_LOW_PWR_LVL2, | |
318 | AXP20X_IRQ_TIMER, | |
319 | AXP20X_IRQ_PEK_RIS_EDGE, | |
320 | AXP20X_IRQ_PEK_FAL_EDGE, | |
321 | AXP20X_IRQ_GPIO3_INPUT, | |
322 | AXP20X_IRQ_GPIO2_INPUT, | |
323 | AXP20X_IRQ_GPIO1_INPUT, | |
324 | AXP20X_IRQ_GPIO0_INPUT, | |
325 | }; | |
326 | ||
f05be589 BB |
327 | enum axp22x_irqs { |
328 | AXP22X_IRQ_ACIN_OVER_V = 1, | |
329 | AXP22X_IRQ_ACIN_PLUGIN, | |
330 | AXP22X_IRQ_ACIN_REMOVAL, | |
331 | AXP22X_IRQ_VBUS_OVER_V, | |
332 | AXP22X_IRQ_VBUS_PLUGIN, | |
333 | AXP22X_IRQ_VBUS_REMOVAL, | |
334 | AXP22X_IRQ_VBUS_V_LOW, | |
335 | AXP22X_IRQ_BATT_PLUGIN, | |
336 | AXP22X_IRQ_BATT_REMOVAL, | |
337 | AXP22X_IRQ_BATT_ENT_ACT_MODE, | |
338 | AXP22X_IRQ_BATT_EXIT_ACT_MODE, | |
339 | AXP22X_IRQ_CHARG, | |
340 | AXP22X_IRQ_CHARG_DONE, | |
341 | AXP22X_IRQ_BATT_TEMP_HIGH, | |
342 | AXP22X_IRQ_BATT_TEMP_LOW, | |
343 | AXP22X_IRQ_DIE_TEMP_HIGH, | |
344 | AXP22X_IRQ_PEK_SHORT, | |
345 | AXP22X_IRQ_PEK_LONG, | |
346 | AXP22X_IRQ_LOW_PWR_LVL1, | |
347 | AXP22X_IRQ_LOW_PWR_LVL2, | |
348 | AXP22X_IRQ_TIMER, | |
349 | AXP22X_IRQ_PEK_RIS_EDGE, | |
350 | AXP22X_IRQ_PEK_FAL_EDGE, | |
351 | AXP22X_IRQ_GPIO1_INPUT, | |
352 | AXP22X_IRQ_GPIO0_INPUT, | |
353 | }; | |
354 | ||
af7e9069 JP |
355 | enum axp288_irqs { |
356 | AXP288_IRQ_VBUS_FALL = 2, | |
357 | AXP288_IRQ_VBUS_RISE, | |
358 | AXP288_IRQ_OV, | |
359 | AXP288_IRQ_FALLING_ALT, | |
360 | AXP288_IRQ_RISING_ALT, | |
361 | AXP288_IRQ_OV_ALT, | |
362 | AXP288_IRQ_DONE = 10, | |
363 | AXP288_IRQ_CHARGING, | |
364 | AXP288_IRQ_SAFE_QUIT, | |
365 | AXP288_IRQ_SAFE_ENTER, | |
366 | AXP288_IRQ_ABSENT, | |
367 | AXP288_IRQ_APPEND, | |
368 | AXP288_IRQ_QWBTU, | |
369 | AXP288_IRQ_WBTU, | |
370 | AXP288_IRQ_QWBTO, | |
371 | AXP288_IRQ_WBTO, | |
372 | AXP288_IRQ_QCBTU, | |
373 | AXP288_IRQ_CBTU, | |
374 | AXP288_IRQ_QCBTO, | |
375 | AXP288_IRQ_CBTO, | |
376 | AXP288_IRQ_WL2, | |
377 | AXP288_IRQ_WL1, | |
378 | AXP288_IRQ_GPADC, | |
379 | AXP288_IRQ_OT = 31, | |
380 | AXP288_IRQ_GPIO0, | |
381 | AXP288_IRQ_GPIO1, | |
382 | AXP288_IRQ_POKO, | |
383 | AXP288_IRQ_POKL, | |
384 | AXP288_IRQ_POKS, | |
385 | AXP288_IRQ_POKN, | |
386 | AXP288_IRQ_POKP, | |
387 | AXP288_IRQ_TIMER, | |
388 | AXP288_IRQ_MV_CHNG, | |
389 | AXP288_IRQ_BC_USB_CHNG, | |
390 | }; | |
391 | ||
392 | #define AXP288_TS_ADC_H 0x58 | |
393 | #define AXP288_TS_ADC_L 0x59 | |
394 | #define AXP288_GP_ADC_H 0x5a | |
395 | #define AXP288_GP_ADC_L 0x5b | |
396 | ||
cfb61a41 CC |
397 | struct axp20x_dev { |
398 | struct device *dev; | |
4fd41151 | 399 | int irq; |
cfb61a41 CC |
400 | struct regmap *regmap; |
401 | struct regmap_irq_chip_data *regmap_irqc; | |
402 | long variant; | |
af7e9069 JP |
403 | int nr_cells; |
404 | struct mfd_cell *cells; | |
405 | const struct regmap_config *regmap_cfg; | |
406 | const struct regmap_irq_chip *regmap_irq_chip; | |
cfb61a41 CC |
407 | }; |
408 | ||
774e0b41 TB |
409 | #define BATTID_LEN 64 |
410 | #define OCV_CURVE_SIZE 32 | |
411 | #define MAX_THERM_CURVE_SIZE 25 | |
412 | #define PD_DEF_MIN_TEMP 0 | |
413 | #define PD_DEF_MAX_TEMP 55 | |
414 | ||
415 | struct axp20x_fg_pdata { | |
416 | char battid[BATTID_LEN + 1]; | |
417 | int design_cap; | |
418 | int min_volt; | |
419 | int max_volt; | |
420 | int max_temp; | |
421 | int min_temp; | |
422 | int cap1; | |
423 | int cap0; | |
424 | int rdc1; | |
425 | int rdc0; | |
426 | int ocv_curve[OCV_CURVE_SIZE]; | |
427 | int tcsz; | |
428 | int thermistor_curve[MAX_THERM_CURVE_SIZE][2]; | |
429 | }; | |
430 | ||
843735b7 RP |
431 | struct axp20x_chrg_pdata { |
432 | int max_cc; | |
433 | int max_cv; | |
434 | int def_cc; | |
435 | int def_cv; | |
436 | }; | |
437 | ||
f0312378 RP |
438 | struct axp288_extcon_pdata { |
439 | /* GPIO pin control to switch D+/D- lines b/w PMIC and SOC */ | |
440 | struct gpio_desc *gpio_mux_cntl; | |
441 | }; | |
442 | ||
69fb4dca HG |
443 | /* generic helper function for reading 9-16 bit wide regs */ |
444 | static inline int axp20x_read_variable_width(struct regmap *regmap, | |
445 | unsigned int reg, unsigned int width) | |
446 | { | |
447 | unsigned int reg_val, result; | |
448 | int err; | |
449 | ||
450 | err = regmap_read(regmap, reg, ®_val); | |
451 | if (err) | |
452 | return err; | |
453 | ||
454 | result = reg_val << (width - 8); | |
455 | ||
456 | err = regmap_read(regmap, reg + 1, ®_val); | |
457 | if (err) | |
458 | return err; | |
459 | ||
460 | result |= reg_val; | |
461 | ||
462 | return result; | |
463 | } | |
464 | ||
4fd41151 CYT |
465 | /** |
466 | * axp20x_match_device(): Setup axp20x variant related fields | |
467 | * | |
468 | * @axp20x: axp20x device to setup (.dev field must be set) | |
469 | * @dev: device associated with this axp20x device | |
470 | * | |
471 | * This lets the axp20x core configure the mfd cells and register maps | |
472 | * for later use. | |
473 | */ | |
474 | int axp20x_match_device(struct axp20x_dev *axp20x); | |
475 | ||
476 | /** | |
477 | * axp20x_device_probe(): Probe a configured axp20x device | |
478 | * | |
479 | * @axp20x: axp20x device to probe (must be configured) | |
480 | * | |
481 | * This function lets the axp20x core register the axp20x mfd devices | |
482 | * and irqchip. The axp20x device passed in must be fully configured | |
483 | * with axp20x_match_device, its irq set, and regmap created. | |
484 | */ | |
485 | int axp20x_device_probe(struct axp20x_dev *axp20x); | |
486 | ||
487 | /** | |
488 | * axp20x_device_probe(): Remove a axp20x device | |
489 | * | |
490 | * @axp20x: axp20x device to remove | |
491 | * | |
492 | * This tells the axp20x core to remove the associated mfd devices | |
493 | */ | |
494 | int axp20x_device_remove(struct axp20x_dev *axp20x); | |
495 | ||
cfb61a41 | 496 | #endif /* __LINUX_MFD_AXP20X_H */ |