projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ada68c31 AS |
1 | /* |
| 2 | * Copyright (c) 2016, Mellanox Technologies. All rights reserved. | |
| 3 | * | |
| 4 | * This software is available to you under a choice of one of two | |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU | |
| 6 | * General Public License (GPL) Version 2, available from the file | |
| 7 | * COPYING in the main directory of this source tree, or the | |
| 8 | * OpenIB.org BSD license below: | |
| 9 | * | |
| 10 | * Redistribution and use in source and binary forms, with or | |
| 11 | * without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistributions of source code must retain the above | |
| 15 | * copyright notice, this list of conditions and the following | |
| 16 | * disclaimer. | |
| 17 | * | |
| 18 | * - Redistributions in binary form must reproduce the above | |
| 19 | * copyright notice, this list of conditions and the following | |
| 20 | * disclaimer in the documentation and/or other materials | |
| 21 | * provided with the distribution. | |
| 22 | * | |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
| 30 | * SOFTWARE. | |
| 31 | */ | |
| 32 | ||
| 33 | #ifndef __MLX5_PORT_H__ | |
| 34 | #define __MLX5_PORT_H__ | |
| 35 | ||
| 36 | #include <linux/mlx5/driver.h> | |
| 37 | ||
| da54d24e GP |
38 | enum mlx5_beacon_duration { |
| 39 | MLX5_BEACON_DURATION_OFF = 0x0, | |
| 40 | MLX5_BEACON_DURATION_INF = 0xffff, | |
| 41 | }; | |
| 42 | ||
| bb64143e GP |
43 | enum mlx5_module_id { |
| 44 | MLX5_MODULE_ID_SFP = 0x3, | |
| 45 | MLX5_MODULE_ID_QSFP = 0xC, | |
| 46 | MLX5_MODULE_ID_QSFP_PLUS = 0xD, | |
| 47 | MLX5_MODULE_ID_QSFP28 = 0x11, | |
| 48 | }; | |
| 49 | ||
| 52244d96 GP |
50 | enum mlx5_an_status { |
| 51 | MLX5_AN_UNAVAILABLE = 0, | |
| 52 | MLX5_AN_COMPLETE = 1, | |
| 53 | MLX5_AN_FAILED = 2, | |
| 54 | MLX5_AN_LINK_UP = 3, | |
| 55 | MLX5_AN_LINK_DOWN = 4, | |
| 56 | }; | |
| 57 | ||
| bb64143e GP |
58 | #define MLX5_EEPROM_MAX_BYTES 32 |
| 59 | #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff | |
| 60 | #define MLX5_I2C_ADDR_LOW 0x50 | |
| 61 | #define MLX5_I2C_ADDR_HIGH 0x51 | |
| 62 | #define MLX5_EEPROM_PAGE_LENGTH 256 | |
| 63 | ||
| 8cca30a7 NO |
64 | enum mlx5e_link_mode { |
| 65 | MLX5E_1000BASE_CX_SGMII = 0, | |
| 66 | MLX5E_1000BASE_KX = 1, | |
| 67 | MLX5E_10GBASE_CX4 = 2, | |
| 68 | MLX5E_10GBASE_KX4 = 3, | |
| 69 | MLX5E_10GBASE_KR = 4, | |
| 70 | MLX5E_20GBASE_KR2 = 5, | |
| 71 | MLX5E_40GBASE_CR4 = 6, | |
| 72 | MLX5E_40GBASE_KR4 = 7, | |
| 73 | MLX5E_56GBASE_R4 = 8, | |
| 74 | MLX5E_10GBASE_CR = 12, | |
| 75 | MLX5E_10GBASE_SR = 13, | |
| 76 | MLX5E_10GBASE_ER = 14, | |
| 77 | MLX5E_40GBASE_SR4 = 15, | |
| 78 | MLX5E_40GBASE_LR4 = 16, | |
| 79 | MLX5E_50GBASE_SR2 = 18, | |
| 80 | MLX5E_100GBASE_CR4 = 20, | |
| 81 | MLX5E_100GBASE_SR4 = 21, | |
| 82 | MLX5E_100GBASE_KR4 = 22, | |
| 83 | MLX5E_100GBASE_LR4 = 23, | |
| 84 | MLX5E_100BASE_TX = 24, | |
| 85 | MLX5E_1000BASE_T = 25, | |
| 86 | MLX5E_10GBASE_T = 26, | |
| 87 | MLX5E_25GBASE_CR = 27, | |
| 88 | MLX5E_25GBASE_KR = 28, | |
| 89 | MLX5E_25GBASE_SR = 29, | |
| 90 | MLX5E_50GBASE_CR2 = 30, | |
| 91 | MLX5E_50GBASE_KR2 = 31, | |
| 92 | MLX5E_LINK_MODES_NUMBER, | |
| 93 | }; | |
| 94 | ||
| 95 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
| 96 | ||
| ada68c31 AS |
97 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); |
| 98 | int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, | |
| 99 | int ptys_size, int proto_mask, u8 local_port); | |
| 100 | int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, | |
| 101 | u32 *proto_cap, int proto_mask); | |
| 102 | int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, | |
| 103 | u32 *proto_admin, int proto_mask); | |
| 104 | int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, | |
| 105 | u8 *link_width_oper, u8 local_port); | |
| d5beb7f2 NO |
106 | int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev, |
| 107 | u8 *proto_oper, u8 local_port); | |
| 108 | int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev, | |
| 109 | u32 *proto_oper, u8 local_port); | |
| 52244d96 GP |
110 | int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable, |
| 111 | u32 proto_admin, int proto_mask); | |
| 667daeda | 112 | void mlx5_toggle_port_link(struct mlx5_core_dev *dev); |
| ada68c31 AS |
113 | int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, |
| 114 | enum mlx5_port_status status); | |
| 115 | int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, | |
| 116 | enum mlx5_port_status *status); | |
| da54d24e | 117 | int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration); |
| 52244d96 GP |
118 | void mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, |
| 119 | u8 *an_status, | |
| 120 | u8 *an_disable_cap, u8 *an_disable_admin); | |
| ada68c31 | 121 | |
| 046339ea SM |
122 | int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port); |
| 123 | void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port); | |
| 124 | void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, | |
| ada68c31 AS |
125 | u8 port); |
| 126 | ||
| 127 | int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, | |
| 128 | u8 *vl_hw_cap, u8 local_port); | |
| 129 | ||
| 130 | int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); | |
| 131 | int mlx5_query_port_pause(struct mlx5_core_dev *dev, | |
| 132 | u32 *rx_pause, u32 *tx_pause); | |
| 133 | ||
| ad909eb0 AS |
134 | int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); |
| 135 | int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, | |
| 136 | u8 *pfc_en_rx); | |
| 137 | ||
| 4f3961ee SM |
138 | int mlx5_max_tc(struct mlx5_core_dev *mdev); |
| 139 | ||
| 140 | int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc); | |
| 141 | int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group); | |
| 142 | int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw); | |
| d8880795 TT |
143 | int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, |
| 144 | u8 *max_bw_value, | |
| 145 | u8 *max_bw_unit); | |
| 146 | int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, | |
| 147 | u8 *max_bw_value, | |
| 148 | u8 *max_bw_unit); | |
| 928cfe87 TT |
149 | int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); |
| 150 | int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); | |
| 4f3961ee | 151 | |
| 94cb1ebb EBE |
152 | int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable); |
| 153 | void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, | |
| 154 | bool *enabled); | |
| bb64143e GP |
155 | int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, |
| 156 | u16 offset, u16 size, u8 *data); | |
| 94cb1ebb | 157 | |
| ada68c31 | 158 | #endif /* __MLX5_PORT_H__ */ |