[deliverable/linux.git] / include / linux / msi.h

#ifndef LINUX_MSI_H
#define LINUX_MSI_H

#include <linux/kobject.h>
#include <linux/list.h>

struct msi_msg {
	u32	address_lo;	/* low 32 bits of msi message address */
	u32	address_hi;	/* high 32 bits of msi message address */
	u32	data;		/* 16 bits of msi message data */
};

extern int pci_msi_ignore_mask;
/* Helper functions */
struct irq_data;
struct msi_desc;
struct pci_dev;
struct platform_msi_priv_data;
void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);

typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc,
				    struct msi_msg *msg);

/**
 * platform_msi_desc - Platform device specific msi descriptor data
 * @msi_priv_data:	Pointer to platform private data
 * @msi_index:		The index of the MSI descriptor for multi MSI
 */
struct platform_msi_desc {
	struct platform_msi_priv_data	*msi_priv_data;
	u16				msi_index;
};

/**
 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
 * @msi_index:		The index of the MSI descriptor
 */
struct fsl_mc_msi_desc {
	u16				msi_index;
};

/**
 * struct msi_desc - Descriptor structure for MSI based interrupts
 * @list:	List head for management
 * @irq:	The base interrupt number
 * @nvec_used:	The number of vectors used
 * @dev:	Pointer to the device which uses this descriptor
 * @msg:	The last set MSI message cached for reuse
 *
 * @masked:	[PCI MSI/X] Mask bits
 * @is_msix:	[PCI MSI/X] True if MSI-X
 * @multiple:	[PCI MSI/X] log2 num of messages allocated
 * @multi_cap:	[PCI MSI/X] log2 num of messages supported
 * @maskbit:	[PCI MSI/X] Mask-Pending bit supported?
 * @is_64:	[PCI MSI/X] Address size: 0=32bit 1=64bit
 * @entry_nr:	[PCI MSI/X] Entry which is described by this descriptor
 * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
 * @mask_pos:	[PCI MSI]   Mask register position
 * @mask_base:	[PCI MSI-X] Mask register base address
 * @platform:	[platform]  Platform device specific msi descriptor data
 */
struct msi_desc {
	/* Shared device/bus type independent data */
	struct list_head		list;
	unsigned int			irq;
	unsigned int			nvec_used;
	struct device			*dev;
	struct msi_msg			msg;

	union {
		/* PCI MSI/X specific data */
		struct {
			u32 masked;
			struct {
				__u8	is_msix		: 1;
				__u8	multiple	: 3;
				__u8	multi_cap	: 3;
				__u8	maskbit		: 1;
				__u8	is_64		: 1;
				__u16	entry_nr;
				unsigned default_irq;
			} msi_attrib;
			union {
				u8	mask_pos;
				void __iomem *mask_base;
			};
		};

		/*
		 * Non PCI variants add their data structure here. New
		 * entries need to use a named structure. We want
		 * proper name spaces for this. The PCI part is
		 * anonymous for now as it would require an immediate
		 * tree wide cleanup.
		 */
		struct platform_msi_desc platform;
		struct fsl_mc_msi_desc fsl_mc;
	};
};

/* Helpers to hide struct msi_desc implementation details */
#define msi_desc_to_dev(desc)		((desc)->dev)
#define dev_to_msi_list(dev)		(&(dev)->msi_list)
#define first_msi_entry(dev)		\
	list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
#define for_each_msi_entry(desc, dev)	\
	list_for_each_entry((desc), dev_to_msi_list((dev)), list)

#ifdef CONFIG_PCI_MSI
#define first_pci_msi_entry(pdev)	first_msi_entry(&(pdev)->dev)
#define for_each_pci_msi_entry(desc, pdev)	\
	for_each_msi_entry((desc), &(pdev)->dev)

struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc);
void *msi_desc_to_pci_sysdata(struct msi_desc *desc);
#else /* CONFIG_PCI_MSI */
static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
{
	return NULL;
}
#endif /* CONFIG_PCI_MSI */

struct msi_desc *alloc_msi_entry(struct device *dev);
void free_msi_entry(struct msi_desc *entry);
void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);

u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
void pci_msi_mask_irq(struct irq_data *data);
void pci_msi_unmask_irq(struct irq_data *data);

/* Conversion helpers. Should be removed after merging */
static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
{
	__pci_write_msi_msg(entry, msg);
}
static inline void write_msi_msg(int irq, struct msi_msg *msg)
{
	pci_write_msi_msg(irq, msg);
}
static inline void mask_msi_irq(struct irq_data *data)
{
	pci_msi_mask_irq(data);
}
static inline void unmask_msi_irq(struct irq_data *data)
{
	pci_msi_unmask_irq(data);
}

/*
 * The arch hooks to setup up msi irqs. Those functions are
 * implemented as weak symbols so that they /can/ be overriden by
 * architecture specific code if needed.
 */
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
void arch_teardown_msi_irq(unsigned int irq);
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
void arch_teardown_msi_irqs(struct pci_dev *dev);
void arch_restore_msi_irqs(struct pci_dev *dev);

void default_teardown_msi_irqs(struct pci_dev *dev);
void default_restore_msi_irqs(struct pci_dev *dev);

struct msi_controller {
	struct module *owner;
	struct device *dev;
	struct device_node *of_node;
	struct list_head list;

	int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev,
			 struct msi_desc *desc);
	int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev,
			  int nvec, int type);
	void (*teardown_irq)(struct msi_controller *chip, unsigned int irq);
};

#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN

#include <linux/irqhandler.h>
#include <asm/msi.h>

struct irq_domain;
struct irq_domain_ops;
struct irq_chip;
struct device_node;
struct fwnode_handle;
struct msi_domain_info;

/**
 * struct msi_domain_ops - MSI interrupt domain callbacks
 * @get_hwirq:		Retrieve the resulting hw irq number
 * @msi_init:		Domain specific init function for MSI interrupts
 * @msi_free:		Domain specific function to free a MSI interrupts
 * @msi_check:		Callback for verification of the domain/info/dev data
 * @msi_prepare:	Prepare the allocation of the interrupts in the domain
 * @msi_finish:		Optional callback to finalize the allocation
 * @set_desc:		Set the msi descriptor for an interrupt
 * @handle_error:	Optional error handler if the allocation fails
 *
 * @get_hwirq, @msi_init and @msi_free are callbacks used by
 * msi_create_irq_domain() and related interfaces
 *
 * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
 * are callbacks used by msi_domain_alloc_irqs() and related
 * interfaces which are based on msi_desc.
 */
struct msi_domain_ops {
	irq_hw_number_t	(*get_hwirq)(struct msi_domain_info *info,
				     msi_alloc_info_t *arg);
	int		(*msi_init)(struct irq_domain *domain,
				    struct msi_domain_info *info,
				    unsigned int virq, irq_hw_number_t hwirq,
				    msi_alloc_info_t *arg);
	void		(*msi_free)(struct irq_domain *domain,
				    struct msi_domain_info *info,
				    unsigned int virq);
	int		(*msi_check)(struct irq_domain *domain,
				     struct msi_domain_info *info,
				     struct device *dev);
	int		(*msi_prepare)(struct irq_domain *domain,
				       struct device *dev, int nvec,
				       msi_alloc_info_t *arg);
	void		(*msi_finish)(msi_alloc_info_t *arg, int retval);
	void		(*set_desc)(msi_alloc_info_t *arg,
				    struct msi_desc *desc);
	int		(*handle_error)(struct irq_domain *domain,
					struct msi_desc *desc, int error);
};

/**
 * struct msi_domain_info - MSI interrupt domain data
 * @flags:		Flags to decribe features and capabilities
 * @ops:		The callback data structure
 * @chip:		Optional: associated interrupt chip
 * @chip_data:		Optional: associated interrupt chip data
 * @handler:		Optional: associated interrupt flow handler
 * @handler_data:	Optional: associated interrupt flow handler data
 * @handler_name:	Optional: associated interrupt flow handler name
 * @data:		Optional: domain specific data
 */
struct msi_domain_info {
	u32			flags;
	struct msi_domain_ops	*ops;
	struct irq_chip		*chip;
	void			*chip_data;
	irq_flow_handler_t	handler;
	void			*handler_data;
	const char		*handler_name;
	void			*data;
};

/* Flags for msi_domain_info */
enum {
	/*
	 * Init non implemented ops callbacks with default MSI domain
	 * callbacks.
	 */
	MSI_FLAG_USE_DEF_DOM_OPS	= (1 << 0),
	/*
	 * Init non implemented chip callbacks with default MSI chip
	 * callbacks.
	 */
	MSI_FLAG_USE_DEF_CHIP_OPS	= (1 << 1),
	/* Build identity map between hwirq and irq */
	MSI_FLAG_IDENTITY_MAP		= (1 << 2),
	/* Support multiple PCI MSI interrupts */
	MSI_FLAG_MULTI_PCI_MSI		= (1 << 3),
	/* Support PCI MSIX interrupts */
	MSI_FLAG_PCI_MSIX		= (1 << 4),
};

int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask,
			    bool force);

struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
					 struct msi_domain_info *info,
					 struct irq_domain *parent);
int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
			  int nvec);
void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev);
struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain);

struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode,
						  struct msi_domain_info *info,
						  struct irq_domain *parent);
int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
				   irq_write_msi_msg_t write_msi_msg);
void platform_msi_domain_free_irqs(struct device *dev);

/* When an MSI domain is used as an intermediate domain */
int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
			    int nvec, msi_alloc_info_t *args);
int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
			     int virq, int nvec, msi_alloc_info_t *args);
struct irq_domain *
platform_msi_create_device_domain(struct device *dev,
				  unsigned int nvec,
				  irq_write_msi_msg_t write_msi_msg,
				  const struct irq_domain_ops *ops,
				  void *host_data);
int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
			      unsigned int nr_irqs);
void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
			      unsigned int nvec);
void *platform_msi_get_host_data(struct irq_domain *domain);
#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */

#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg);
struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
					     struct msi_domain_info *info,
					     struct irq_domain *parent);
int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
			      int nvec, int type);
void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev);
struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
		 struct msi_domain_info *info, struct irq_domain *parent);

irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
					  struct msi_desc *desc);
int pci_msi_domain_check_cap(struct irq_domain *domain,
			     struct msi_domain_info *info, struct device *dev);
u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev);
struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev);
#else
static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
{
	return NULL;
}
#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */

#endif /* LINUX_MSI_H */
Commit	Line	Data
3b7d1921 EB	1	#ifndef LINUX_MSI_H
	2	#define LINUX_MSI_H
	3
b50cac55	4	#include <linux/kobject.h>
4aa9bc95 ME	5	#include <linux/list.h>
4aa9bc95 ME	6
3b7d1921 EB	7	struct msi_msg {
	8	u32 address_lo; /* low 32 bits of msi message address */
	9	u32 address_hi; /* high 32 bits of msi message address */
	10	u32 data; /* 16 bits of msi message data */
	11	};
	12
38737d82	13	extern int pci_msi_ignore_mask;
c54c1879	14	/* Helper functions */
1c9db525	15	struct irq_data;
39431acb	16	struct msi_desc;
25a98bd4	17	struct pci_dev;
c09fcc4b	18	struct platform_msi_priv_data;
2366d06e	19	void __get_cached_msi_msg(struct msi_desc entry, struct msi_msg msg);
2366d06e	20	void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
891d4a48	21
c09fcc4b MZ	22	typedef void (irq_write_msi_msg_t)(struct msi_desc desc,
	23	struct msi_msg *msg);
	24
	25	/**
	26	* platform_msi_desc - Platform device specific msi descriptor data
	27	* @msi_priv_data: Pointer to platform private data
	28	* @msi_index: The index of the MSI descriptor for multi MSI
	29	*/
	30	struct platform_msi_desc {
	31	struct platform_msi_priv_data *msi_priv_data;
	32	u16 msi_index;
	33	};
	34
550308e4 GR	35	/**
	36	* fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
	37	* @msi_index: The index of the MSI descriptor
	38	*/
	39	struct fsl_mc_msi_desc {
	40	u16 msi_index;
	41	};
	42
fc88419c JL	43	/**
	44	* struct msi_desc - Descriptor structure for MSI based interrupts
	45	* @list: List head for management
	46	* @irq: The base interrupt number
	47	* @nvec_used: The number of vectors used
	48	* @dev: Pointer to the device which uses this descriptor
	49	* @msg: The last set MSI message cached for reuse
	50	*
	51	* @masked: [PCI MSI/X] Mask bits
	52	* @is_msix: [PCI MSI/X] True if MSI-X
	53	* @multiple: [PCI MSI/X] log2 num of messages allocated
	54	* @multi_cap: [PCI MSI/X] log2 num of messages supported
	55	* @maskbit: [PCI MSI/X] Mask-Pending bit supported?
	56	* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
	57	* @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
	58	* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
	59	* @mask_pos: [PCI MSI] Mask register position
	60	* @mask_base: [PCI MSI-X] Mask register base address
c09fcc4b	61	* @platform: [platform] Platform device specific msi descriptor data
fc88419c	62	*/
3b7d1921	63	struct msi_desc {
fc88419c JL	64	/* Shared device/bus type independent data */
	65	struct list_head list;
	66	unsigned int irq;
	67	unsigned int nvec_used;
	68	struct device *dev;
	69	struct msi_msg msg;
3b7d1921	70
264d9caa	71	union {
fc88419c JL	72	/* PCI MSI/X specific data */
	73	struct {
	74	u32 masked;
	75	struct {
	76	__u8 is_msix : 1;
	77	__u8 multiple : 3;
	78	__u8 multi_cap : 3;
	79	__u8 maskbit : 1;
	80	__u8 is_64 : 1;
	81	__u16 entry_nr;
	82	unsigned default_irq;
	83	} msi_attrib;
	84	union {
	85	u8 mask_pos;
	86	void __iomem *mask_base;
	87	};
	88	};
3b7d1921	89
fc88419c JL	90	/*
	91	* Non PCI variants add their data structure here. New
	92	* entries need to use a named structure. We want
	93	* proper name spaces for this. The PCI part is
	94	* anonymous for now as it would require an immediate
	95	* tree wide cleanup.
	96	*/
c09fcc4b	97	struct platform_msi_desc platform;
550308e4	98	struct fsl_mc_msi_desc fsl_mc;
fc88419c	99	};
3b7d1921 EB	100	};
3b7d1921 EB	101
d31eb342	102	/* Helpers to hide struct msi_desc implementation details */
25a98bd4	103	#define msi_desc_to_dev(desc) ((desc)->dev)
4a7cc831	104	#define dev_to_msi_list(dev) (&(dev)->msi_list)
d31eb342 JL	105	#define first_msi_entry(dev) \
	106	list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list)
	107	#define for_each_msi_entry(desc, dev) \
	108	list_for_each_entry((desc), dev_to_msi_list((dev)), list)
	109
	110	#ifdef CONFIG_PCI_MSI
	111	#define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
	112	#define for_each_pci_msi_entry(desc, pdev) \
	113	for_each_msi_entry((desc), &(pdev)->dev)
	114
25a98bd4	115	struct pci_dev msi_desc_to_pci_dev(struct msi_desc desc);
c179c9b9 JL	116	void msi_desc_to_pci_sysdata(struct msi_desc desc);
	117	#else /* CONFIG_PCI_MSI */
	118	static inline void msi_desc_to_pci_sysdata(struct msi_desc desc)
	119	{
	120	return NULL;
	121	}
d31eb342 JL	122	#endif /* CONFIG_PCI_MSI */
d31eb342 JL	123
aa48b6f7 JL	124	struct msi_desc alloc_msi_entry(struct device dev);
aa48b6f7 JL	125	void free_msi_entry(struct msi_desc *entry);
891d4a48	126	void __pci_read_msi_msg(struct msi_desc entry, struct msi_msg msg);
83a18912 JL	127	void __pci_write_msi_msg(struct msi_desc entry, struct msi_msg msg);
	128	void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg);
	129
23ed8d57 TG	130	u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag);
	131	u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
	132	void pci_msi_mask_irq(struct irq_data *data);
	133	void pci_msi_unmask_irq(struct irq_data *data);
	134
83a18912 JL	135	/* Conversion helpers. Should be removed after merging */
	136	static inline void __write_msi_msg(struct msi_desc entry, struct msi_msg msg)
	137	{
	138	__pci_write_msi_msg(entry, msg);
	139	}
	140	static inline void write_msi_msg(int irq, struct msi_msg *msg)
	141	{
	142	pci_write_msi_msg(irq, msg);
	143	}
23ed8d57 TG	144	static inline void mask_msi_irq(struct irq_data *data)
	145	{
	146	pci_msi_mask_irq(data);
	147	}
	148	static inline void unmask_msi_irq(struct irq_data *data)
	149	{
	150	pci_msi_unmask_irq(data);
	151	}
891d4a48	152
3b7d1921	153	/*
4287d824 TP	154	* The arch hooks to setup up msi irqs. Those functions are
	155	* implemented as weak symbols so that they /can/ be overriden by
	156	* architecture specific code if needed.
3b7d1921	157	*/
f7feaca7	158	int arch_setup_msi_irq(struct pci_dev dev, struct msi_desc desc);
3b7d1921	159	void arch_teardown_msi_irq(unsigned int irq);
2366d06e BH	160	int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
2366d06e BH	161	void arch_teardown_msi_irqs(struct pci_dev *dev);
ac8344c4	162	void arch_restore_msi_irqs(struct pci_dev *dev);
4287d824 TP	163
4287d824 TP	164	void default_teardown_msi_irqs(struct pci_dev *dev);
ac8344c4	165	void default_restore_msi_irqs(struct pci_dev *dev);
3b7d1921	166
c2791b80	167	struct msi_controller {
0cbdcfcf TR	168	struct module *owner;
0cbdcfcf TR	169	struct device *dev;
0d5a6db3 TP	170	struct device_node *of_node;
0d5a6db3 TP	171	struct list_head list;
0cbdcfcf	172
c2791b80	173	int (setup_irq)(struct msi_controller chip, struct pci_dev *dev,
0cbdcfcf	174	struct msi_desc *desc);
339e5b44 LS	175	int (setup_irqs)(struct msi_controller chip, struct pci_dev *dev,
339e5b44 LS	176	int nvec, int type);
c2791b80	177	void (teardown_irq)(struct msi_controller chip, unsigned int irq);
0cbdcfcf TR	178	};
0cbdcfcf TR	179
f3cf8bb0	180	#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
d9109698	181
aeeb5965	182	#include <linux/irqhandler.h>
d9109698 JL	183	#include <asm/msi.h>
d9109698 JL	184
f3cf8bb0	185	struct irq_domain;
552c494a	186	struct irq_domain_ops;
f3cf8bb0 JL	187	struct irq_chip;
f3cf8bb0 JL	188	struct device_node;
be5436c8	189	struct fwnode_handle;
f3cf8bb0 JL	190	struct msi_domain_info;
	191
	192	/**
	193	* struct msi_domain_ops - MSI interrupt domain callbacks
	194	* @get_hwirq: Retrieve the resulting hw irq number
	195	* @msi_init: Domain specific init function for MSI interrupts
	196	* @msi_free: Domain specific function to free a MSI interrupts
d9109698 JL	197	* @msi_check: Callback for verification of the domain/info/dev data
d9109698 JL	198	* @msi_prepare: Prepare the allocation of the interrupts in the domain
1d1e8cdc	199	* @msi_finish: Optional callback to finalize the allocation
d9109698 JL	200	* @set_desc: Set the msi descriptor for an interrupt
	201	* @handle_error: Optional error handler if the allocation fails
	202	*
	203	* @get_hwirq, @msi_init and @msi_free are callbacks used by
	204	* msi_create_irq_domain() and related interfaces
	205	*
	206	* @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
1d1e8cdc	207	* are callbacks used by msi_domain_alloc_irqs() and related
d9109698	208	* interfaces which are based on msi_desc.
f3cf8bb0 JL	209	*/
f3cf8bb0 JL	210	struct msi_domain_ops {
aeeb5965 JL	211	irq_hw_number_t (get_hwirq)(struct msi_domain_info info,
aeeb5965 JL	212	msi_alloc_info_t *arg);
f3cf8bb0 JL	213	int (msi_init)(struct irq_domain domain,
	214	struct msi_domain_info *info,
	215	unsigned int virq, irq_hw_number_t hwirq,
aeeb5965	216	msi_alloc_info_t *arg);
f3cf8bb0 JL	217	void (msi_free)(struct irq_domain domain,
	218	struct msi_domain_info *info,
	219	unsigned int virq);
d9109698 JL	220	int (msi_check)(struct irq_domain domain,
	221	struct msi_domain_info *info,
	222	struct device *dev);
	223	int (msi_prepare)(struct irq_domain domain,
	224	struct device *dev, int nvec,
	225	msi_alloc_info_t *arg);
	226	void (msi_finish)(msi_alloc_info_t arg, int retval);
	227	void (set_desc)(msi_alloc_info_t arg,
	228	struct msi_desc *desc);
	229	int (handle_error)(struct irq_domain domain,
	230	struct msi_desc *desc, int error);
f3cf8bb0 JL	231	};
	232
	233	/**
	234	* struct msi_domain_info - MSI interrupt domain data
aeeb5965 JL	235	* @flags: Flags to decribe features and capabilities
	236	* @ops: The callback data structure
	237	* @chip: Optional: associated interrupt chip
	238	* @chip_data: Optional: associated interrupt chip data
	239	* @handler: Optional: associated interrupt flow handler
	240	* @handler_data: Optional: associated interrupt flow handler data
	241	* @handler_name: Optional: associated interrupt flow handler name
	242	* @data: Optional: domain specific data
f3cf8bb0 JL	243	*/
f3cf8bb0 JL	244	struct msi_domain_info {
aeeb5965	245	u32 flags;
f3cf8bb0 JL	246	struct msi_domain_ops *ops;
f3cf8bb0 JL	247	struct irq_chip *chip;
aeeb5965 JL	248	void *chip_data;
	249	irq_flow_handler_t handler;
	250	void *handler_data;
	251	const char *handler_name;
f3cf8bb0 JL	252	void *data;
	253	};
	254
aeeb5965 JL	255	/* Flags for msi_domain_info */
	256	enum {
	257	/*
	258	* Init non implemented ops callbacks with default MSI domain
	259	* callbacks.
	260	*/
	261	MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0),
	262	/*
	263	* Init non implemented chip callbacks with default MSI chip
	264	* callbacks.
	265	*/
	266	MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1),
	267	/* Build identity map between hwirq and irq */
	268	MSI_FLAG_IDENTITY_MAP = (1 << 2),
	269	/* Support multiple PCI MSI interrupts */
	270	MSI_FLAG_MULTI_PCI_MSI = (1 << 3),
	271	/* Support PCI MSIX interrupts */
	272	MSI_FLAG_PCI_MSIX = (1 << 4),
	273	};
	274
f3cf8bb0 JL	275	int msi_domain_set_affinity(struct irq_data data, const struct cpumask mask,
	276	bool force);
	277
be5436c8	278	struct irq_domain msi_create_irq_domain(struct fwnode_handle fwnode,
f3cf8bb0 JL	279	struct msi_domain_info *info,
f3cf8bb0 JL	280	struct irq_domain *parent);
d9109698 JL	281	int msi_domain_alloc_irqs(struct irq_domain domain, struct device dev,
	282	int nvec);
	283	void msi_domain_free_irqs(struct irq_domain domain, struct device dev);
f3cf8bb0 JL	284	struct msi_domain_info msi_get_domain_info(struct irq_domain domain);
f3cf8bb0 JL	285
be5436c8	286	struct irq_domain platform_msi_create_irq_domain(struct fwnode_handle fwnode,
c09fcc4b MZ	287	struct msi_domain_info *info,
	288	struct irq_domain *parent);
	289	int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
	290	irq_write_msi_msg_t write_msi_msg);
	291	void platform_msi_domain_free_irqs(struct device *dev);
b2eba39b MZ	292
	293	/* When an MSI domain is used as an intermediate domain */
	294	int msi_domain_prepare_irqs(struct irq_domain domain, struct device dev,
	295	int nvec, msi_alloc_info_t *args);
2145ac93 MZ	296	int msi_domain_populate_irqs(struct irq_domain domain, struct device dev,
2145ac93 MZ	297	int virq, int nvec, msi_alloc_info_t *args);
552c494a MZ	298	struct irq_domain *
	299	platform_msi_create_device_domain(struct device *dev,
	300	unsigned int nvec,
	301	irq_write_msi_msg_t write_msi_msg,
	302	const struct irq_domain_ops *ops,
	303	void *host_data);
	304	int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
	305	unsigned int nr_irqs);
	306	void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
	307	unsigned int nvec);
	308	void platform_msi_get_host_data(struct irq_domain domain);
f3cf8bb0 JL	309	#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
f3cf8bb0 JL	310
3878eaef JL	311	#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
3878eaef JL	312	void pci_msi_domain_write_msg(struct irq_data irq_data, struct msi_msg msg);
be5436c8	313	struct irq_domain pci_msi_create_irq_domain(struct fwnode_handle fwnode,
3878eaef JL	314	struct msi_domain_info *info,
	315	struct irq_domain *parent);
	316	int pci_msi_domain_alloc_irqs(struct irq_domain domain, struct pci_dev dev,
	317	int nvec, int type);
	318	void pci_msi_domain_free_irqs(struct irq_domain domain, struct pci_dev dev);
be5436c8	319	struct irq_domain pci_msi_create_default_irq_domain(struct fwnode_handle fwnode,
8e047ada JL	320	struct msi_domain_info info, struct irq_domain parent);
8e047ada JL	321
3878eaef JL	322	irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
	323	struct msi_desc *desc);
	324	int pci_msi_domain_check_cap(struct irq_domain *domain,
	325	struct msi_domain_info info, struct device dev);
b6eec9b7	326	u32 pci_msi_domain_get_msi_rid(struct irq_domain domain, struct pci_dev pdev);
54fa97ee MZ	327	struct irq_domain pci_msi_get_device_domain(struct pci_dev pdev);
	328	#else
	329	static inline struct irq_domain pci_msi_get_device_domain(struct pci_dev pdev)
	330	{
	331	return NULL;
	332	}
3878eaef JL	333	#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
3878eaef JL	334
3b7d1921	335	#endif /* LINUX_MSI_H */