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PCI: allow P2P bridge windows starting at PCI bus address zero
[deliverable/linux.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
f46753c5 20#include <linux/pci_regs.h> /* The pci register defines */
1da177e4 21
1da177e4
LT		 22/*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
05cca6e5 30#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
1da177e4
LT		 31#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32#define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34/* Ioctls for /proc/bus/pci/X/Y nodes. */
35#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41#ifdef __KERNEL__
42
778382e0
DW		 43#include <linux/mod_devicetable.h>
44
1da177e4 45#include <linux/types.h>
98db6f19 46#include <linux/init.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
f46753c5 51#include <linux/kobject.h>
60063497 52#include <linux/atomic.h>
1da177e4 53#include <linux/device.h>
1388cc96 54#include <linux/io.h>
74bb1bcc 55#include <linux/irqreturn.h>
1da177e4 56
7e7a43c3
AB		 57/* Include the ID list */
58#include <linux/pci_ids.h>
59
f46753c5
AC		 60/* pci_slot represents a physical slot */
61struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67};
68
0ad772ec
AC		 69static inline const char *pci_slot_name(const struct pci_slot *slot)
70{
71 return kobject_name(&slot->kobj);
72}
73
1da177e4
LT		 74/* File state for mmap()s on /proc/bus/pci/X/Y */
75enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78};
79
80/* This defines the direction arg to the DMA mapping routines. */
81#define PCI_DMA_BIDIRECTIONAL 0
82#define PCI_DMA_TODEVICE 1
83#define PCI_DMA_FROMDEVICE 2
84#define PCI_DMA_NONE 3
85
fde09c6d
YZ		 86/*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
d1b054da
YZ		 97 /* device specific resources */
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
fde09c6d
YZ		 103 /* resources assigned to buses behind the bridge */
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
cda57bf9 114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 115};
1da177e4
LT		 116
117typedef int __bitwise pci_power_t;
118
4352dfd5
GKH		 119#define PCI_D0 ((pci_power_t __force) 0)
120#define PCI_D1 ((pci_power_t __force) 1)
121#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 122#define PCI_D3hot ((pci_power_t __force) 3)
123#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 124#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 125#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 126
00240c38
AS		 127/* Remember to update this when the list above changes! */
128extern const char *pci_power_names[];
129
130static inline const char *pci_power_name(pci_power_t state)
131{
132 return pci_power_names[1 + (int) state];
133}
134
aa8c6c93
RW		 135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50
138
392a1ce7 139/** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143typedef unsigned int __bitwise pci_channel_state_t;
144
145enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154};
155
f7bdd12d
BK		 156typedef unsigned int __bitwise pcie_reset_state_t;
157
158enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167};
168
ba698ad4
DM		 169typedef unsigned short __bitwise pci_dev_flags_t;
170enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
979b1791
AC		 175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
6777829c
GR		 177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
ba698ad4
DM		 179};
180
e1d3a908
SA		 181enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184};
185
6e325a62
MT		 186typedef unsigned short __bitwise pci_bus_flags_t;
187enum pci_bus_flags {
d556ad4b
PO		 188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 190};
191
536c8cb4
MW		 192/* Based on the PCI Hotplug Spec, but some values are made up by us */
193enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
536c8cb4
MW		 210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 215 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 216 PCI_SPEED_UNKNOWN = 0xff,
217};
218
24a4742f 219struct pci_cap_saved_data {
41017f0c 220 char cap_nr;
24a4742f 221 unsigned int size;
41017f0c
SL		 222 u32 data[0];
223};
224
24a4742f
AW		 225struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228};
229
7d715a6c 230struct pcie_link_state;
ee69439c 231struct pci_vpd;
d1b054da 232struct pci_sriov;
302b4215 233struct pci_ats;
ee69439c 234
1da177e4
LT		 235/*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238struct pci_dev {
1da177e4
LT		 239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 245 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 253 u8 revision; /* PCI revision, low byte of class word */
1da177e4 254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
0efea000 255 u8 pcie_cap; /* PCI-E capability offset */
b03e7495
JM		 256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
1da177e4 258 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 259 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
4d57cdfa
FT		 268 struct device_dma_parameters dma_parms;
269
1da177e4
LT		 270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
337001b6
RW		 273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
c7f48656 277 unsigned int pme_interrupt:1;
379021d5 278 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
253d2e54
JP		 282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
e80bb09d 284 unsigned int wakeup_prepared:1;
1ae861e6 285 unsigned int d3_delay; /* D3->D0 transition time in ms */
1da177e4 286
7d715a6c
SL		 287#ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
289#endif
290
392a1ce7 291 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 292 struct device dev; /* Generic device interface */
293
1da177e4
LT		 294 int cfg_size; /* Size of configuration space */
295
296 /*
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
299 */
300 unsigned int irq;
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302
303 /* These fields are used by common fixups */
304 unsigned int transparent:1; /* Transparent PCI bridge */
305 unsigned int multifunction:1;/* Part of multi-function device */
306 /* keep track of device state */
8a1bc901 307 unsigned int is_added:1;
1da177e4 308 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 309 unsigned int no_msi:1; /* device may not use msi */
fb51ccbf 310 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 311 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 312 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
99dc804d
SL		 313 unsigned int msi_enabled:1;
314 unsigned int msix_enabled:1;
58c3a727 315 unsigned int ari_enabled:1; /* ARI forwarding */
9ac7849e 316 unsigned int is_managed:1;
6d3be84a
KK		 317 unsigned int is_pcie:1; /* Obsolete. Will be removed.
318 Use pci_is_pcie() instead */
260d703a 319 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 320 unsigned int state_saved:1;
d1b054da 321 unsigned int is_physfn:1;
dd7cc44d 322 unsigned int is_virtfn:1;
711d5779 323 unsigned int reset_fn:1;
28760489 324 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 325 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1;
ba698ad4 327 pci_dev_flags_t dev_flags;
bae94d02 328 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 329
1da177e4 330 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 331 struct hlist_head saved_cap_space;
1da177e4
LT		 332 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
333 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
334 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 335 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 336#ifdef CONFIG_PCI_MSI
4aa9bc95 337 struct list_head msi_list;
da8d1c8b 338 struct kset *msi_kset;
ded86d8d 339#endif
94e61088 340 struct pci_vpd *vpd;
466b3ddf 341#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 342 union {
343 struct pci_sriov *sriov; /* SR-IOV capability related */
344 struct pci_dev *physfn; /* the PF this VF is associated with */
345 };
302b4215 346 struct pci_ats *ats; /* Address Translation Service */
d1b054da 347#endif
1da177e4
LT		 348};
349
dda56549
Y		 350static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
351{
352#ifdef CONFIG_PCI_IOV
353 if (dev->is_virtfn)
354 dev = dev->physfn;
355#endif
356
357 return dev;
358}
359
65891215
ME		 360extern struct pci_dev *alloc_pci_dev(void);
361
1da177e4
LT		 362#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
363#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
364#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
365
a7369f1f
LV		 366static inline int pci_channel_offline(struct pci_dev *pdev)
367{
368 return (pdev->error_state != pci_channel_io_normal);
369}
370
0efd5aab
BH		 371struct pci_host_bridge_window {
372 struct list_head list;
373 struct resource *res; /* host bridge aperture (CPU address) */
374 resource_size_t offset; /* bus address + offset = CPU address */
375};
41017f0c 376
5a21d70d 377struct pci_host_bridge {
7b543663 378 struct device dev;
5a21d70d 379 struct pci_bus *bus; /* root bus */
0efd5aab 380 struct list_head windows; /* pci_host_bridge_windows */
4fa2649a
YL		 381 void (*release_fn)(struct pci_host_bridge *);
382 void *release_data;
5a21d70d 383};
41017f0c 384
7b543663 385#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
4fa2649a
YL		 386void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
387 void (*release_fn)(struct pci_host_bridge *),
388 void *release_data);
7b543663 389
2fe2abf8
BH		 390/*
391 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
392 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
393 * buses below host bridges or subtractive decode bridges) go in the list.
394 * Use pci_bus_for_each_resource() to iterate through all the resources.
395 */
396
397/*
398 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
399 * and there's no way to program the bridge with the details of the window.
400 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
401 * decode bit set, because they are explicit and can be programmed with _SRS.
402 */
403#define PCI_SUBTRACTIVE_DECODE 0x1
404
405struct pci_bus_resource {
406 struct list_head list;
407 struct resource *res;
408 unsigned int flags;
409};
4352dfd5
GKH		 410
411#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 412
413struct pci_bus {
414 struct list_head node; /* node in list of buses */
415 struct pci_bus *parent; /* parent bus this bridge is on */
416 struct list_head children; /* list of child buses */
417 struct list_head devices; /* list of devices on this bus */
418 struct pci_dev *self; /* bridge device as seen by parent */
f46753c5 419 struct list_head slots; /* list of slots on this bus */
2fe2abf8
BH		 420 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
421 struct list_head resources; /* address space routed to this bus */
1da177e4
LT		 422
423 struct pci_ops *ops; /* configuration access functions */
424 void *sysdata; /* hook for sys-specific extension */
425 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
426
427 unsigned char number; /* bus number */
428 unsigned char primary; /* number of primary bridge */
429 unsigned char secondary; /* number of secondary bridge */
430 unsigned char subordinate; /* max number of subordinate buses */
3749c51a
MW		 431 unsigned char max_bus_speed; /* enum pci_bus_speed */
432 unsigned char cur_bus_speed; /* enum pci_bus_speed */
1da177e4
LT		 433
434 char name[48];
435
436 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 437 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4 438 struct device *bridge;
fd7d1ced 439 struct device dev;
1da177e4
LT		 440 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
441 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 442 unsigned int is_added:1;
1da177e4
LT		 443};
444
445#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
fd7d1ced 446#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 447
79af72d7
KK		 448/*
449 * Returns true if the pci bus is root (behind host-pci bridge),
450 * false otherwise
451 */
452static inline bool pci_is_root_bus(struct pci_bus *pbus)
453{
454 return !(pbus->parent);
455}
456
16cf0ebc
RW		 457#ifdef CONFIG_PCI_MSI
458static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
459{
460 return pci_dev->msi_enabled || pci_dev->msix_enabled;
461}
462#else
463static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
464#endif
465
1da177e4
LT		 466/*
467 * Error values that may be returned by PCI functions.
468 */
469#define PCIBIOS_SUCCESSFUL 0x00
470#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
471#define PCIBIOS_BAD_VENDOR_ID 0x83
472#define PCIBIOS_DEVICE_NOT_FOUND 0x86
473#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
474#define PCIBIOS_SET_FAILED 0x88
475#define PCIBIOS_BUFFER_TOO_SMALL 0x89
476
477/* Low-level architecture-dependent routines */
478
479struct pci_ops {
480 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
481 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
482};
483
b6ce068a
MW		 484/*
485 * ACPI needs to be able to access PCI config space before we've done a
486 * PCI bus scan and created pci_bus structures.
487 */
488extern int raw_pci_read(unsigned int domain, unsigned int bus,
489 unsigned int devfn, int reg, int len, u32 *val);
490extern int raw_pci_write(unsigned int domain, unsigned int bus,
491 unsigned int devfn, int reg, int len, u32 val);
1da177e4
LT		 492
493struct pci_bus_region {
c40a22e0
BH		 494 resource_size_t start;
495 resource_size_t end;
1da177e4
LT		 496};
497
498struct pci_dynids {
499 spinlock_t lock; /* protects list, index */
500 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 501};
502
392a1ce7 503/* ---------------------------------------------------------------- */
504/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
579082df 505 * a set of callbacks in struct pci_error_handlers, then that device driver
392a1ce7 506 * will be notified of PCI bus errors, and will be driven to recovery
507 * when an error occurs.
508 */
509
510typedef unsigned int __bitwise pci_ers_result_t;
511
512enum pci_ers_result {
513 /* no result/none/not supported in device driver */
514 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
515
516 /* Device driver can recover without slot reset */
517 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
518
519 /* Device driver wants slot to be reset. */
520 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
521
522 /* Device has completely failed, is unrecoverable */
523 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
524
525 /* Device driver is fully recovered and operational */
526 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
527};
528
529/* PCI bus error event callbacks */
05cca6e5 530struct pci_error_handlers {
392a1ce7 531 /* PCI bus error detected on this device */
532 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 533 enum pci_channel_state error);
392a1ce7 534
535 /* MMIO has been re-enabled, but not DMA */
536 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
537
538 /* PCI Express link has been reset */
539 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
540
541 /* PCI slot has been reset */
542 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
543
544 /* Device driver may resume normal operations */
545 void (*resume)(struct pci_dev *dev);
546};
547
548/* ---------------------------------------------------------------- */
549
1da177e4
LT		 550struct module;
551struct pci_driver {
552 struct list_head node;
42b21932 553 const char *name;
1da177e4
LT		 554 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
555 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
556 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
557 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 558 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
559 int (*resume_early) (struct pci_dev *dev);
1da177e4 560 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 561 void (*shutdown) (struct pci_dev *dev);
392a1ce7 562 struct pci_error_handlers *err_handler;
1da177e4
LT		 563 struct device_driver driver;
564 struct pci_dynids dynids;
565};
566
05cca6e5 567#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 568
90a1ba0c 569/**
9f9351bb 570 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 571 * @_table: device table name
572 *
573 * This macro is used to create a struct pci_device_id array (a device table)
574 * in a generic manner.
575 */
9f9351bb 576#define DEFINE_PCI_DEVICE_TABLE(_table) \
90a1ba0c
JB		 577 const struct pci_device_id _table[] __devinitconst
578
1da177e4
LT		 579/**
580 * PCI_DEVICE - macro used to describe a specific pci device
581 * @vend: the 16 bit PCI Vendor ID
582 * @dev: the 16 bit PCI Device ID
583 *
584 * This macro is used to create a struct pci_device_id that matches a
585 * specific device. The subvendor and subdevice fields will be set to
586 * PCI_ANY_ID.
587 */
588#define PCI_DEVICE(vend,dev) \
589 .vendor = (vend), .device = (dev), \
590 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
591
592/**
593 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
594 * @dev_class: the class, subclass, prog-if triple for this device
595 * @dev_class_mask: the class mask for this device
596 *
597 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 598 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 599 * fields will be set to PCI_ANY_ID.
600 */
601#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
602 .class = (dev_class), .class_mask = (dev_class_mask), \
603 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
604 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
605
1597cacb
AC		 606/**
607 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c322b28a
ZY		 608 * @vendor: the vendor name
609 * @device: the 16 bit PCI Device ID
1597cacb
AC		 610 *
611 * This macro is used to create a struct pci_device_id that matches a
612 * specific PCI device. The subvendor, and subdevice fields will be set
613 * to PCI_ANY_ID. The macro allows the next field to follow as the device
614 * private data.
615 */
616
617#define PCI_VDEVICE(vendor, device) \
618 PCI_VENDOR_ID_##vendor, (device), \
619 PCI_ANY_ID, PCI_ANY_ID, 0, 0
620
1da177e4
LT		 621/* these external functions are only available when PCI support is enabled */
622#ifdef CONFIG_PCI
623
b03e7495
JM		 624extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
625
626enum pcie_bus_config_types {
5f39e670 627 PCIE_BUS_TUNE_OFF,
b03e7495 628 PCIE_BUS_SAFE,
5f39e670 629 PCIE_BUS_PERFORMANCE,
b03e7495
JM		 630 PCIE_BUS_PEER2PEER,
631};
632
633extern enum pcie_bus_config_types pcie_bus_config;
634
1da177e4
LT		 635extern struct bus_type pci_bus_type;
636
637/* Do NOT directly access these two variables, unless you are arch specific pci
638 * code, or pci core code. */
639extern struct list_head pci_root_buses; /* list of all known PCI buses */
ed4aaadb
ZY		 640/* Some device drivers need know if pci is initiated */
641extern int no_pci_devices(void);
1da177e4
LT		 642
643void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 644int __must_check pcibios_enable_device(struct pci_dev *, int mask);
05cca6e5 645char *pcibios_setup(char *str);
1da177e4
LT		 646
647/* Used only when drivers/pci/setup.c is used */
3b7a17fc 648resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 649 resource_size_t,
e31dd6e4 650 resource_size_t);
1da177e4
LT		 651void pcibios_update_irq(struct pci_dev *, int irq);
652
2d1c8618
BH		 653/* Weak but can be overriden by arch */
654void pci_fixup_cardbus(struct pci_bus *);
655
1da177e4
LT		 656/* Generic PCI functions used internally */
657
36a66cd6
BH		 658void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
659 struct resource *res);
660void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
661 struct pci_bus_region *region);
d1fd4fb6 662void pcibios_scan_specific_bus(int busn);
1da177e4 663extern struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 664void pci_bus_add_devices(const struct pci_bus *bus);
05cca6e5
GKH		 665struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
666 struct pci_ops *ops, void *sysdata);
de4b2f76 667struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 668struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
669 struct pci_ops *ops, void *sysdata,
670 struct list_head *resources);
a2ebb827
BH		 671struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
672 struct pci_ops *ops, void *sysdata,
673 struct list_head *resources);
05cca6e5
GKH		 674struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
675 int busnr);
3749c51a 676void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 677struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 678 const char *name,
679 struct hotplug_slot *hotplug);
f46753c5 680void pci_destroy_slot(struct pci_slot *slot);
d25b7c8d 681void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
1da177e4 682int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 683struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 684void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 685unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 686int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4 687void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 688struct resource *pci_find_parent_resource(const struct pci_dev *dev,
689 struct resource *res);
3df425f3 690u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 691int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 692u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1da177e4
LT		 693extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
694extern void pci_dev_put(struct pci_dev *dev);
695extern void pci_remove_bus(struct pci_bus *b);
6b22cf3f 696extern void __pci_remove_bus_device(struct pci_dev *dev);
210647af 697extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
24f8aa9b 698extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 699void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 700extern void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 701#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
702#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
703#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 704
705/* Generic PCI functions exported to card drivers */
706
388c8c16
JB		 707enum pci_lost_interrupt_reason {
708 PCI_LOST_IRQ_NO_INFORMATION = 0,
709 PCI_LOST_IRQ_DISABLE_MSI,
710 PCI_LOST_IRQ_DISABLE_MSIX,
711 PCI_LOST_IRQ_DISABLE_ACPI,
712};
713enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 714int pci_find_capability(struct pci_dev *dev, int cap);
715int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
716int pci_find_ext_capability(struct pci_dev *dev, int cap);
cf4c43dd
JB		 717int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
718 int cap);
05cca6e5
GKH		 719int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
720int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 721struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 722
d42552c3
AM		 723struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
724 struct pci_dev *from);
05cca6e5 725struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 726 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 727 struct pci_dev *from);
05cca6e5 728struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 729struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
730 unsigned int devfn);
731static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
732 unsigned int devfn)
733{
734 return pci_get_domain_bus_and_slot(0, bus, devfn);
735}
05cca6e5 736struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 737int pci_dev_present(const struct pci_device_id *ids);
738
05cca6e5
GKH		 739int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
740 int where, u8 *val);
741int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
742 int where, u16 *val);
743int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
744 int where, u32 *val);
745int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
746 int where, u8 val);
747int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
748 int where, u16 val);
749int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
750 int where, u32 val);
a72b46c3 751struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 752
bf362f75 753static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 754{
05cca6e5 755 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 756}
bf362f75 757static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 758{
05cca6e5 759 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 760}
bf362f75 761static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 762 u32 *val)
1da177e4 763{
05cca6e5 764 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 765}
bf362f75 766static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 767{
05cca6e5 768 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 769}
bf362f75 770static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 771{
05cca6e5 772 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 773}
bf362f75 774static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 775 u32 val)
1da177e4 776{
05cca6e5 777 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 778}
779
4a7fb636 780int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 781int __must_check pci_enable_device_io(struct pci_dev *dev);
782int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 783int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 784int __must_check pcim_enable_device(struct pci_dev *pdev);
785void pcim_pin_device(struct pci_dev *pdev);
786
296ccb08
YS		 787static inline int pci_is_enabled(struct pci_dev *pdev)
788{
789 return (atomic_read(&pdev->enable_cnt) > 0);
790}
791
9ac7849e
TH		 792static inline int pci_is_managed(struct pci_dev *pdev)
793{
794 return pdev->is_managed;
795}
796
1da177e4 797void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 798
799extern unsigned int pcibios_max_latency;
1da177e4 800void pci_set_master(struct pci_dev *dev);
6a479079 801void pci_clear_master(struct pci_dev *dev);
96c55900 802
f7bdd12d 803int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 804int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 805#define HAVE_PCI_SET_MWI
4a7fb636 806int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 807int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 808void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 809void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 810bool pci_intx_mask_supported(struct pci_dev *dev);
811bool pci_check_and_mask_intx(struct pci_dev *dev);
812bool pci_check_and_unmask_intx(struct pci_dev *dev);
f5f2b131 813void pci_msi_off(struct pci_dev *dev);
4d57cdfa 814int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
59fc67de 815int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
d556ad4b
PO		 816int pcix_get_max_mmrbc(struct pci_dev *dev);
817int pcix_get_mmrbc(struct pci_dev *dev);
818int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 819int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 820int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 821int pcie_get_mps(struct pci_dev *dev);
822int pcie_set_mps(struct pci_dev *dev, int mps);
8c1c699f 823int __pci_reset_function(struct pci_dev *dev);
a96d627a 824int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 825int pci_reset_function(struct pci_dev *dev);
14add80b 826void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 827int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 828int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 829int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 830
831/* ROM control related routines */
e416de5e
AC		 832int pci_enable_rom(struct pci_dev *pdev);
833void pci_disable_rom(struct pci_dev *pdev);
144a50ea 834void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 835void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 836size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1da177e4
LT		 837
838/* Power management related routines */
839int pci_save_state(struct pci_dev *dev);
1d3c16a8 840void pci_restore_state(struct pci_dev *dev);
ffbdd3f7
AW		 841struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
842int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
843int pci_load_and_free_saved_state(struct pci_dev *dev,
844 struct pci_saved_state **state);
0e5dd46b 845int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 846int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
847pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 848bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 849void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 850int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
851 bool runtime, bool enable);
0235c4fc 852int pci_wake_from_d3(struct pci_dev *dev, bool enable);
e5899e1b 853pci_power_t pci_target_state(struct pci_dev *dev);
404cc2d8
RW		 854int pci_prepare_to_sleep(struct pci_dev *dev);
855int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 856bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 857bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 858void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 859
6cbf8214
RW		 860static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
861 bool enable)
862{
863 return __pci_enable_wake(dev, state, false, enable);
864}
1da177e4 865
b48d4425
JB		 866#define PCI_EXP_IDO_REQUEST (1<<0)
867#define PCI_EXP_IDO_COMPLETION (1<<1)
868void pci_enable_ido(struct pci_dev *dev, unsigned long type);
869void pci_disable_ido(struct pci_dev *dev, unsigned long type);
870
48a92a81 871enum pci_obff_signal_type {
688398bb
MS		 872 PCI_EXP_OBFF_SIGNAL_L0 = 0,
873 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
48a92a81
JB		 874};
875int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
876void pci_disable_obff(struct pci_dev *dev);
877
51c2e0a7
JB		 878bool pci_ltr_supported(struct pci_dev *dev);
879int pci_enable_ltr(struct pci_dev *dev);
880void pci_disable_ltr(struct pci_dev *dev);
881int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
882
bb209c82
BH		 883/* For use by arch with custom probe code */
884void set_pcie_port_type(struct pci_dev *pdev);
885void set_pcie_hotplug_bridge(struct pci_dev *pdev);
886
ce5ccdef 887/* Functions for PCI Hotplug drivers to use */
05cca6e5 888int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
3ed4fd96 889#ifdef CONFIG_HOTPLUG
2f320521 890unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96
AC		 891unsigned int pci_rescan_bus(struct pci_bus *bus);
892#endif
ce5ccdef 893
287d19ce
SH		 894/* Vital product data routines */
895ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
896ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
db567943 897int pci_vpd_truncate(struct pci_dev *dev, size_t size);
287d19ce 898
1da177e4 899/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 900resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 901void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 902void pci_bus_size_bridges(struct pci_bus *bus);
903int pci_claim_resource(struct pci_dev *, int);
904void pci_assign_unassigned_resources(void);
6841ec68 905void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1da177e4 906void pdev_enable_device(struct pci_dev *);
842de40d 907int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 908void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 909 int (*)(const struct pci_dev *, u8, u8));
1da177e4 910#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 911int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 912int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 913void pci_release_regions(struct pci_dev *);
4a7fb636 914int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 915int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 916void pci_release_region(struct pci_dev *, int);
c87deff7 917int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 918int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 919void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 920
921/* drivers/pci/bus.c */
45ca9e97 922void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 923void pci_add_resource_offset(struct list_head *resources, struct resource *res,
924 resource_size_t offset);
45ca9e97 925void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 926void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
927struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
928void pci_bus_remove_resources(struct pci_bus *bus);
929
89a74ecc 930#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 931 for (i = 0; \
932 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
933 i++)
89a74ecc 934
4a7fb636
AM		 935int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
936 struct resource *res, resource_size_t size,
937 resource_size_t align, resource_size_t min,
938 unsigned int type_mask,
3b7a17fc
DB		 939 resource_size_t (*alignf)(void *,
940 const struct resource *,
b26b2d49
DB		 941 resource_size_t,
942 resource_size_t),
4a7fb636 943 void *alignf_data);
1da177e4
LT		 944void pci_enable_bridges(struct pci_bus *bus);
945
863b18f4 946/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 947int __must_check __pci_register_driver(struct pci_driver *, struct module *,
948 const char *mod_name);
bba81165
AM		 949
950/*
951 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
952 */
953#define pci_register_driver(driver) \
954 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 955
05cca6e5 956void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 957
958/**
959 * module_pci_driver() - Helper macro for registering a PCI driver
960 * @__pci_driver: pci_driver struct
961 *
962 * Helper macro for PCI drivers which do not do anything special in module
963 * init/exit. This eliminates a lot of boilerplate. Each module may only
964 * use this macro once, and calling it replaces module_init() and module_exit()
965 */
966#define module_pci_driver(__pci_driver) \
967 module_driver(__pci_driver, pci_register_driver, \
968 pci_unregister_driver)
969
6754b9e9 970void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
05cca6e5 971struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 972int pci_add_dynid(struct pci_driver *drv,
973 unsigned int vendor, unsigned int device,
974 unsigned int subvendor, unsigned int subdevice,
975 unsigned int class, unsigned int class_mask,
976 unsigned long driver_data);
05cca6e5
GKH		 977const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
978 struct pci_dev *dev);
979int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
980 int pass);
1da177e4 981
70298c6e 982void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 983 void *userdata);
70b9f7dc 984int pci_cfg_space_size_ext(struct pci_dev *dev);
ac7dc65a 985int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 986unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 987void pci_setup_bridge(struct pci_bus *bus);
cecf4864 988
3448a19d
DA		 989#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
990#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
991
deb2d2ec 992int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 993 unsigned int command_bits, u32 flags);
1da177e4
LT		 994/* kmem_cache style wrapper around pci_alloc_consistent() */
995
f41b1771 996#include <linux/pci-dma.h>
1da177e4
LT		 997#include <linux/dmapool.h>
998
999#define pci_pool dma_pool
1000#define pci_pool_create(name, pdev, size, align, allocation) \
1001 dma_pool_create(name, &pdev->dev, size, align, allocation)
1002#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1003#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1004#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1005
e24c2d96
DM		 1006enum pci_dma_burst_strategy {
1007 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1008 strategy_parameter is N/A */
1009 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1010 byte boundaries */
1011 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1012 strategy_parameter byte boundaries */
1013};
1014
1da177e4 1015struct msix_entry {
16dbef4a 1016 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1017 u16 entry; /* driver uses to specify entry, OS writes */
1018};
1019
0366f8f7 1020
1da177e4 1021#ifndef CONFIG_PCI_MSI
1c8d7b0a 1022static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
05cca6e5
GKH		 1023{
1024 return -1;
1025}
1026
d52877c7
YL		 1027static inline void pci_msi_shutdown(struct pci_dev *dev)
1028{ }
05cca6e5
GKH		 1029static inline void pci_disable_msi(struct pci_dev *dev)
1030{ }
1031
a52e2e35
RW		 1032static inline int pci_msix_table_size(struct pci_dev *dev)
1033{
1034 return 0;
1035}
05cca6e5
GKH		 1036static inline int pci_enable_msix(struct pci_dev *dev,
1037 struct msix_entry *entries, int nvec)
1038{
1039 return -1;
1040}
1041
d52877c7
YL		 1042static inline void pci_msix_shutdown(struct pci_dev *dev)
1043{ }
05cca6e5
GKH		 1044static inline void pci_disable_msix(struct pci_dev *dev)
1045{ }
1046
1047static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1048{ }
1049
1050static inline void pci_restore_msi_state(struct pci_dev *dev)
1051{ }
07ae95f9
AP		 1052static inline int pci_msi_enabled(void)
1053{
1054 return 0;
1055}
1da177e4 1056#else
1c8d7b0a 1057extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
d52877c7 1058extern void pci_msi_shutdown(struct pci_dev *dev);
1da177e4 1059extern void pci_disable_msi(struct pci_dev *dev);
a52e2e35 1060extern int pci_msix_table_size(struct pci_dev *dev);
05cca6e5 1061extern int pci_enable_msix(struct pci_dev *dev,
1da177e4 1062 struct msix_entry *entries, int nvec);
d52877c7 1063extern void pci_msix_shutdown(struct pci_dev *dev);
1da177e4
LT		 1064extern void pci_disable_msix(struct pci_dev *dev);
1065extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
94688cf2 1066extern void pci_restore_msi_state(struct pci_dev *dev);
07ae95f9 1067extern int pci_msi_enabled(void);
1da177e4
LT		 1068#endif
1069
ab0724ff 1070#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1071extern bool pcie_ports_disabled;
1072extern bool pcie_ports_auto;
ab0724ff
MT		 1073#else
1074#define pcie_ports_disabled true
1075#define pcie_ports_auto false
1076#endif
415e12b2 1077
3e1b1600 1078#ifndef CONFIG_PCIEASPM
8b8bae90
RW		 1079static inline int pcie_aspm_enabled(void) { return 0; }
1080static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1081#else
1082extern int pcie_aspm_enabled(void);
8b8bae90 1083extern bool pcie_aspm_support_enabled(void);
3e1b1600
AP		 1084#endif
1085
415e12b2
RW		 1086#ifdef CONFIG_PCIEAER
1087void pci_no_aer(void);
1088bool pci_aer_available(void);
1089#else
1090static inline void pci_no_aer(void) { }
1091static inline bool pci_aer_available(void) { return false; }
1092#endif
1093
43c16408
AP		 1094#ifndef CONFIG_PCIE_ECRC
1095static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1096{
1097 return;
1098}
1099static inline void pcie_ecrc_get_policy(char *str) {};
1100#else
1101extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1102extern void pcie_ecrc_get_policy(char *str);
1103#endif
1104
1c8d7b0a
MW		 1105#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1106
8b955b0d 1107#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1108/* The functions a driver should call */
1109int ht_create_irq(struct pci_dev *dev, int idx);
1110void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1111#endif /* CONFIG_HT_IRQ */
1112
fb51ccbf
JK		 1113extern void pci_cfg_access_lock(struct pci_dev *dev);
1114extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1115extern void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1116
4352dfd5
GKH		 1117/*
1118 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1119 * a PCI domain is defined to be a set of PCI busses which share
1120 * configuration space.
1121 */
32a2eea7
JG		 1122#ifdef CONFIG_PCI_DOMAINS
1123extern int pci_domains_supported;
1124#else
1125enum { pci_domains_supported = 0 };
05cca6e5
GKH		 1126static inline int pci_domain_nr(struct pci_bus *bus)
1127{
1128 return 0;
1129}
1130
4352dfd5
GKH		 1131static inline int pci_proc_domain(struct pci_bus *bus)
1132{
1133 return 0;
1134}
32a2eea7 1135#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1136
95a8b6ef
MT		 1137/* some architectures require additional setup to direct VGA traffic */
1138typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1139 unsigned int command_bits, u32 flags);
95a8b6ef
MT		 1140extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1141
4352dfd5 1142#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 1143
1144/*
1145 * If the system does not have PCI, clearly these return errors. Define
1146 * these as simple inline functions to avoid hair in drivers.
1147 */
1148
05cca6e5
GKH		 1149#define _PCI_NOP(o, s, t) \
1150 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1151 int where, t val) \
1da177e4 1152 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1153
1154#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1155 _PCI_NOP(o, word, u16 x) \
1156 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1157_PCI_NOP_ALL(read, *)
1158_PCI_NOP_ALL(write,)
1159
d42552c3 1160static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1161 unsigned int device,
1162 struct pci_dev *from)
1163{
1164 return NULL;
1165}
d42552c3 1166
05cca6e5
GKH		 1167static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1168 unsigned int device,
1169 unsigned int ss_vendor,
1170 unsigned int ss_device,
b08508c4 1171 struct pci_dev *from)
05cca6e5
GKH		 1172{
1173 return NULL;
1174}
1da177e4 1175
05cca6e5
GKH		 1176static inline struct pci_dev *pci_get_class(unsigned int class,
1177 struct pci_dev *from)
1178{
1179 return NULL;
1180}
1da177e4
LT		 1181
1182#define pci_dev_present(ids) (0)
ed4aaadb 1183#define no_pci_devices() (1)
1da177e4
LT		 1184#define pci_dev_put(dev) do { } while (0)
1185
05cca6e5
GKH		 1186static inline void pci_set_master(struct pci_dev *dev)
1187{ }
1188
1189static inline int pci_enable_device(struct pci_dev *dev)
1190{
1191 return -EIO;
1192}
1193
1194static inline void pci_disable_device(struct pci_dev *dev)
1195{ }
1196
1197static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1198{
1199 return -EIO;
1200}
1201
80be0385
RD		 1202static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1203{
1204 return -EIO;
1205}
1206
4d57cdfa
FT		 1207static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1208 unsigned int size)
1209{
1210 return -EIO;
1211}
1212
59fc67de
FT		 1213static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1214 unsigned long mask)
1215{
1216 return -EIO;
1217}
1218
05cca6e5
GKH		 1219static inline int pci_assign_resource(struct pci_dev *dev, int i)
1220{
1221 return -EBUSY;
1222}
1223
1224static inline int __pci_register_driver(struct pci_driver *drv,
1225 struct module *owner)
1226{
1227 return 0;
1228}
1229
1230static inline int pci_register_driver(struct pci_driver *drv)
1231{
1232 return 0;
1233}
1234
1235static inline void pci_unregister_driver(struct pci_driver *drv)
1236{ }
1237
1238static inline int pci_find_capability(struct pci_dev *dev, int cap)
1239{
1240 return 0;
1241}
1242
1243static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1244 int cap)
1245{
1246 return 0;
1247}
1248
1249static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1250{
1251 return 0;
1252}
1253
1da177e4 1254/* Power management related routines */
05cca6e5
GKH		 1255static inline int pci_save_state(struct pci_dev *dev)
1256{
1257 return 0;
1258}
1259
1d3c16a8
JM		 1260static inline void pci_restore_state(struct pci_dev *dev)
1261{ }
1da177e4 1262
05cca6e5
GKH		 1263static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1264{
1265 return 0;
1266}
1267
3449248c
RD		 1268static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1269{
1270 return 0;
1271}
1272
05cca6e5
GKH		 1273static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1274 pm_message_t state)
1275{
1276 return PCI_D0;
1277}
1278
1279static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1280 int enable)
1281{
1282 return 0;
1283}
1284
b48d4425
JB		 1285static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1286{
1287}
1288
1289static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1290{
1291}
1292
48a92a81
JB		 1293static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1294{
1295 return 0;
1296}
1297
1298static inline void pci_disable_obff(struct pci_dev *dev)
1299{
1300}
1301
05cca6e5
GKH		 1302static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1303{
1304 return -EIO;
1305}
1306
1307static inline void pci_release_regions(struct pci_dev *dev)
1308{ }
0da0ead9 1309
a46e8126
KG		 1310#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1311
fb51ccbf 1312static inline void pci_block_cfg_access(struct pci_dev *dev)
05cca6e5
GKH		 1313{ }
1314
fb51ccbf
JK		 1315static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1316{ return 0; }
1317
1318static inline void pci_unblock_cfg_access(struct pci_dev *dev)
05cca6e5 1319{ }
e04b0ea2 1320
d80d0217
RD		 1321static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1322{ return NULL; }
1323
1324static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1325 unsigned int devfn)
1326{ return NULL; }
1327
1328static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1329 unsigned int devfn)
1330{ return NULL; }
1331
92298e66
DA		 1332static inline int pci_domain_nr(struct pci_bus *bus)
1333{ return 0; }
1334
fb8a0d9d
WM		 1335#define dev_is_pci(d) (false)
1336#define dev_is_pf(d) (false)
1337#define dev_num_vf(d) (0)
4352dfd5 1338#endif /* CONFIG_PCI */
1da177e4 1339
4352dfd5
GKH		 1340/* Include architecture-dependent settings and functions */
1341
1342#include <asm/pci.h>
1da177e4 1343
1f82de10
YL		 1344#ifndef PCIBIOS_MAX_MEM_32
1345#define PCIBIOS_MAX_MEM_32 (-1)
1346#endif
1347
1da177e4
LT		 1348/* these helpers provide future and backwards compatibility
1349 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1350#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1351#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1352#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1353#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1354 ((pci_resource_start((dev), (bar)) == 0 && \
1355 pci_resource_end((dev), (bar)) == \
1356 pci_resource_start((dev), (bar))) ? 0 : \
1357 \
1358 (pci_resource_end((dev), (bar)) - \
1359 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1360
1361/* Similar to the helpers above, these manipulate per-pci_dev
1362 * driver-specific data. They are really just a wrapper around
1363 * the generic device structure functions of these calls.
1364 */
05cca6e5 1365static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1366{
1367 return dev_get_drvdata(&pdev->dev);
1368}
1369
05cca6e5 1370static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1371{
1372 dev_set_drvdata(&pdev->dev, data);
1373}
1374
1375/* If you want to know what to call your pci_dev, ask this function.
1376 * Again, it's a wrapper around the generic device.
1377 */
2fc90f61 1378static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1379{
c6c4f070 1380 return dev_name(&pdev->dev);
1da177e4
LT		 1381}
1382
2311b1f2
ME		 1383
1384/* Some archs don't want to expose struct resource to userland as-is
1385 * in sysfs and /proc
1386 */
1387#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1388static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1389 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1390 resource_size_t *end)
2311b1f2
ME		 1391{
1392 *start = rsrc->start;
1393 *end = rsrc->end;
1394}
1395#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1396
1397
1da177e4
LT		 1398/*
1399 * The world is not perfect and supplies us with broken PCI devices.
1400 * For at least a part of these bugs we need a work-around, so both
1401 * generic (drivers/pci/quirks.c) and per-architecture code can define
1402 * fixup hooks to be called for particular buggy devices.
1403 */
1404
1405struct pci_fixup {
f4ca5c6a
YL		 1406 u16 vendor; /* You can use PCI_ANY_ID here of course */
1407 u16 device; /* You can use PCI_ANY_ID here of course */
1408 u32 class; /* You can use PCI_ANY_ID here too */
1409 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1410 void (*hook)(struct pci_dev *dev);
1411};
1412
1413enum pci_fixup_pass {
1414 pci_fixup_early, /* Before probing BARs */
1415 pci_fixup_header, /* After reading configuration header */
1416 pci_fixup_final, /* Final phase of device fixups */
1417 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e
RW		 1418 pci_fixup_resume, /* pci_device_resume() */
1419 pci_fixup_suspend, /* pci_device_suspend */
1420 pci_fixup_resume_early, /* pci_device_resume_early() */
1da177e4
LT		 1421};
1422
1423/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1424#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1425 class_shift, hook) \
1426 static const struct pci_fixup const __pci_fixup_##name __used \
1427 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1428 = { vendor, device, class, class_shift, hook };
1429
1430#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1431 class_shift, hook) \
1432 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1433 vendor##device##hook, vendor, device, class, class_shift, hook)
1434#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1435 class_shift, hook) \
1436 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1437 vendor##device##hook, vendor, device, class, class_shift, hook)
1438#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1439 class_shift, hook) \
1440 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1441 vendor##device##hook, vendor, device, class, class_shift, hook)
1442#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1443 class_shift, hook) \
1444 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1445 vendor##device##hook, vendor, device, class, class_shift, hook)
1446#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1447 class_shift, hook) \
1448 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1449 resume##vendor##device##hook, vendor, device, class, \
1450 class_shift, hook)
1451#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1452 class_shift, hook) \
1453 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1454 resume_early##vendor##device##hook, vendor, device, \
1455 class, class_shift, hook)
1456#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1457 class_shift, hook) \
1458 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1459 suspend##vendor##device##hook, vendor, device, class, \
1460 class_shift, hook)
1461
1da177e4
LT		 1462#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1463 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
f4ca5c6a 1464 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1465#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1466 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
f4ca5c6a 1467 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1468#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1469 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
f4ca5c6a 1470 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1471#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1472 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
f4ca5c6a 1473 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1474#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1475 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
f4ca5c6a
YL		 1476 resume##vendor##device##hook, vendor, device, \
1477 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1478#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1479 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
f4ca5c6a
YL		 1480 resume_early##vendor##device##hook, vendor, device, \
1481 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1482#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1483 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
f4ca5c6a
YL		 1484 suspend##vendor##device##hook, vendor, device, \
1485 PCI_ANY_ID, 0, hook)
1da177e4 1486
93177a74 1487#ifdef CONFIG_PCI_QUIRKS
1da177e4 1488void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 1489#else
1490static inline void pci_fixup_device(enum pci_fixup_pass pass,
1491 struct pci_dev *dev) {}
1492#endif
1da177e4 1493
05cca6e5 1494void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1495void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1496void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1497int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1498int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1499 const char *name);
fb7ebfe4 1500void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1501
1da177e4 1502extern int pci_pci_problems;
236561e5 1503#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1504#define PCIPCI_TRITON 2
1505#define PCIPCI_NATOMA 4
1506#define PCIPCI_VIAETBF 8
1507#define PCIPCI_VSFX 16
236561e5
AC		 1508#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1509#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1510
4516a618
AN		 1511extern unsigned long pci_cardbus_io_size;
1512extern unsigned long pci_cardbus_mem_size;
491424c0 1513extern u8 __devinitdata pci_dfl_cache_line_size;
ac1aa47b 1514extern u8 pci_cache_line_size;
4516a618 1515
28760489
EB		 1516extern unsigned long pci_hotplug_io_size;
1517extern unsigned long pci_hotplug_mem_size;
1518
cfce9fb8 1519/* Architecture specific versions may override these (weak) */
19792a08
AB		 1520int pcibios_add_platform_entries(struct pci_dev *dev);
1521void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1522void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1523int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1524 enum pcie_reset_state state);
575e3348 1525
7752d5cf 1526#ifdef CONFIG_PCI_MMCONFIG
bb63b421 1527extern void __init pci_mmcfg_early_init(void);
7752d5cf
RH		 1528extern void __init pci_mmcfg_late_init(void);
1529#else
bb63b421 1530static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1531static inline void pci_mmcfg_late_init(void) { }
1532#endif
1533
0ef5f8f6
AP		 1534int pci_ext_cfg_avail(struct pci_dev *dev);
1535
1684f5dd 1536void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1537
dd7cc44d
YZ		 1538#ifdef CONFIG_PCI_IOV
1539extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1540extern void pci_disable_sriov(struct pci_dev *dev);
74bb1bcc 1541extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
fb8a0d9d 1542extern int pci_num_vf(struct pci_dev *dev);
dd7cc44d
YZ		 1543#else
1544static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1545{
1546 return -ENODEV;
1547}
1548static inline void pci_disable_sriov(struct pci_dev *dev)
1549{
1550}
74bb1bcc
YZ		 1551static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1552{
1553 return IRQ_NONE;
1554}
fb8a0d9d
WM		 1555static inline int pci_num_vf(struct pci_dev *dev)
1556{
1557 return 0;
1558}
dd7cc44d
YZ		 1559#endif
1560
c825bc94
KK		 1561#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1562extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1563extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1564#endif
1565
d7b7e605
KK		 1566/**
1567 * pci_pcie_cap - get the saved PCIe capability offset
1568 * @dev: PCI device
1569 *
1570 * PCIe capability offset is calculated at PCI device initialization
1571 * time and saved in the data structure. This function returns saved
1572 * PCIe capability offset. Using this instead of pci_find_capability()
1573 * reduces unnecessary search in the PCI configuration space. If you
1574 * need to calculate PCIe capability offset from raw device for some
1575 * reasons, please use pci_find_capability() instead.
1576 */
1577static inline int pci_pcie_cap(struct pci_dev *dev)
1578{
1579 return dev->pcie_cap;
1580}
1581
7eb776c4
KK		 1582/**
1583 * pci_is_pcie - check if the PCI device is PCI Express capable
1584 * @dev: PCI device
1585 *
1586 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1587 */
1588static inline bool pci_is_pcie(struct pci_dev *dev)
1589{
1590 return !!pci_pcie_cap(dev);
1591}
1592
5d990b62
CW		 1593void pci_request_acs(void);
1594
a2ce7662 1595
7ad506fa
MC		 1596#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1597#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1598
1599/* Large Resource Data Type Tag Item Names */
1600#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1601#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1602#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1603
1604#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1605#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1606#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1607
1608/* Small Resource Data Type Tag Item Names */
1609#define PCI_VPD_STIN_END 0x78 /* End */
1610
1611#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1612
1613#define PCI_VPD_SRDT_TIN_MASK 0x78
1614#define PCI_VPD_SRDT_LEN_MASK 0x07
1615
1616#define PCI_VPD_LRDT_TAG_SIZE 3
1617#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1618
e1d5bdab
MC		 1619#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1620
4067a854
MC		 1621#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1622#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1623#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1624#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1625
a2ce7662
MC		 1626/**
1627 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1628 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1629 *
1630 * Returns the extracted Large Resource Data Type length.
1631 */
1632static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1633{
1634 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1635}
1636
7ad506fa
MC		 1637/**
1638 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1639 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1640 *
1641 * Returns the extracted Small Resource Data Type length.
1642 */
1643static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1644{
1645 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1646}
1647
e1d5bdab
MC		 1648/**
1649 * pci_vpd_info_field_size - Extracts the information field length
1650 * @lrdt: Pointer to the beginning of an information field header
1651 *
1652 * Returns the extracted information field length.
1653 */
1654static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1655{
1656 return info_field[2];
1657}
1658
b55ac1b2
MC		 1659/**
1660 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1661 * @buf: Pointer to buffered vpd data
1662 * @off: The offset into the buffer at which to begin the search
1663 * @len: The length of the vpd buffer
1664 * @rdt: The Resource Data Type to search for
1665 *
1666 * Returns the index where the Resource Data Type was found or
1667 * -ENOENT otherwise.
1668 */
1669int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1670
4067a854
MC		 1671/**
1672 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1673 * @buf: Pointer to buffered vpd data
1674 * @off: The offset into the buffer at which to begin the search
1675 * @len: The length of the buffer area, relative to off, in which to search
1676 * @kw: The keyword to search for
1677 *
1678 * Returns the index where the information field keyword was found or
1679 * -ENOENT otherwise.
1680 */
1681int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1682 unsigned int len, const char *kw);
1683
98d9f30c
BH		 1684/* PCI <-> OF binding helpers */
1685#ifdef CONFIG_OF
1686struct device_node;
1687extern void pci_set_of_node(struct pci_dev *dev);
1688extern void pci_release_of_node(struct pci_dev *dev);
1689extern void pci_set_bus_of_node(struct pci_bus *bus);
1690extern void pci_release_bus_of_node(struct pci_bus *bus);
1691
1692/* Arch may override this (weak) */
1693extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1694
3df425f3
JC		 1695static inline struct device_node *
1696pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 1697{
1698 return pdev ? pdev->dev.of_node : NULL;
1699}
1700
ef3b4f8c
BH		 1701static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1702{
1703 return bus ? bus->dev.of_node : NULL;
1704}
1705
98d9f30c
BH		 1706#else /* CONFIG_OF */
1707static inline void pci_set_of_node(struct pci_dev *dev) { }
1708static inline void pci_release_of_node(struct pci_dev *dev) { }
1709static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1710static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1711#endif /* CONFIG_OF */
1712
eb740b5f
GS		 1713#ifdef CONFIG_EEH
1714static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1715{
1716 return pdev->dev.archdata.edev;
1717}
1718#endif
1719
166e9278
OBC		 1720/**
1721 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1722 * @pdev: the PCI device
1723 *
1724 * if the device is PCIE, return NULL
1725 * if the device isn't connected to a PCIe bridge (that is its parent is a
1726 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1727 * parent
1728 */
1729struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1730
1da177e4
LT		 1731#endif /* __KERNEL__ */
1732#endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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