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PCI: add generic device into pci_host_bridge struct
[deliverable/linux.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
f46753c5 20#include <linux/pci_regs.h> /* The pci register defines */
1da177e4 21
1da177e4
LT		 22/*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
05cca6e5 30#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
1da177e4
LT		 31#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32#define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34/* Ioctls for /proc/bus/pci/X/Y nodes. */
35#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41#ifdef __KERNEL__
42
778382e0
DW		 43#include <linux/mod_devicetable.h>
44
1da177e4 45#include <linux/types.h>
98db6f19 46#include <linux/init.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
f46753c5 51#include <linux/kobject.h>
60063497 52#include <linux/atomic.h>
1da177e4 53#include <linux/device.h>
1388cc96 54#include <linux/io.h>
74bb1bcc 55#include <linux/irqreturn.h>
1da177e4 56
7e7a43c3
AB		 57/* Include the ID list */
58#include <linux/pci_ids.h>
59
f46753c5
AC		 60/* pci_slot represents a physical slot */
61struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67};
68
0ad772ec
AC		 69static inline const char *pci_slot_name(const struct pci_slot *slot)
70{
71 return kobject_name(&slot->kobj);
72}
73
1da177e4
LT		 74/* File state for mmap()s on /proc/bus/pci/X/Y */
75enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78};
79
80/* This defines the direction arg to the DMA mapping routines. */
81#define PCI_DMA_BIDIRECTIONAL 0
82#define PCI_DMA_TODEVICE 1
83#define PCI_DMA_FROMDEVICE 2
84#define PCI_DMA_NONE 3
85
fde09c6d
YZ		 86/*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
d1b054da
YZ		 97 /* device specific resources */
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
fde09c6d
YZ		 103 /* resources assigned to buses behind the bridge */
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
cda57bf9 114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 115};
1da177e4
LT		 116
117typedef int __bitwise pci_power_t;
118
4352dfd5
GKH		 119#define PCI_D0 ((pci_power_t __force) 0)
120#define PCI_D1 ((pci_power_t __force) 1)
121#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 122#define PCI_D3hot ((pci_power_t __force) 3)
123#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 124#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 125#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 126
00240c38
AS		 127/* Remember to update this when the list above changes! */
128extern const char *pci_power_names[];
129
130static inline const char *pci_power_name(pci_power_t state)
131{
132 return pci_power_names[1 + (int) state];
133}
134
aa8c6c93
RW		 135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50
138
392a1ce7 139/** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143typedef unsigned int __bitwise pci_channel_state_t;
144
145enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154};
155
f7bdd12d
BK		 156typedef unsigned int __bitwise pcie_reset_state_t;
157
158enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167};
168
ba698ad4
DM		 169typedef unsigned short __bitwise pci_dev_flags_t;
170enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
979b1791
AC		 175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
6777829c
GR		 177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
ba698ad4
DM		 179};
180
e1d3a908
SA		 181enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184};
185
6e325a62
MT		 186typedef unsigned short __bitwise pci_bus_flags_t;
187enum pci_bus_flags {
d556ad4b
PO		 188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 190};
191
536c8cb4
MW		 192/* Based on the PCI Hotplug Spec, but some values are made up by us */
193enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
536c8cb4
MW		 210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 215 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 216 PCI_SPEED_UNKNOWN = 0xff,
217};
218
24a4742f 219struct pci_cap_saved_data {
41017f0c 220 char cap_nr;
24a4742f 221 unsigned int size;
41017f0c
SL		 222 u32 data[0];
223};
224
24a4742f
AW		 225struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228};
229
7d715a6c 230struct pcie_link_state;
ee69439c 231struct pci_vpd;
d1b054da 232struct pci_sriov;
302b4215 233struct pci_ats;
ee69439c 234
1da177e4
LT		 235/*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238struct pci_dev {
1da177e4
LT		 239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 245 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 253 u8 revision; /* PCI revision, low byte of class word */
1da177e4 254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
0efea000 255 u8 pcie_cap; /* PCI-E capability offset */
b03e7495
JM		 256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
1da177e4 258 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 259 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
4d57cdfa
FT		 268 struct device_dma_parameters dma_parms;
269
1da177e4
LT		 270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
337001b6
RW		 273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
c7f48656 277 unsigned int pme_interrupt:1;
379021d5 278 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
253d2e54
JP		 282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
e80bb09d 284 unsigned int wakeup_prepared:1;
1ae861e6 285 unsigned int d3_delay; /* D3->D0 transition time in ms */
1da177e4 286
7d715a6c
SL		 287#ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
289#endif
290
392a1ce7 291 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 292 struct device dev; /* Generic device interface */
293
1da177e4
LT		 294 int cfg_size; /* Size of configuration space */
295
296 /*
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
299 */
300 unsigned int irq;
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302
303 /* These fields are used by common fixups */
304 unsigned int transparent:1; /* Transparent PCI bridge */
305 unsigned int multifunction:1;/* Part of multi-function device */
306 /* keep track of device state */
8a1bc901 307 unsigned int is_added:1;
1da177e4 308 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 309 unsigned int no_msi:1; /* device may not use msi */
fb51ccbf 310 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 311 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 312 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
99dc804d
SL		 313 unsigned int msi_enabled:1;
314 unsigned int msix_enabled:1;
58c3a727 315 unsigned int ari_enabled:1; /* ARI forwarding */
9ac7849e 316 unsigned int is_managed:1;
6d3be84a
KK		 317 unsigned int is_pcie:1; /* Obsolete. Will be removed.
318 Use pci_is_pcie() instead */
260d703a 319 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 320 unsigned int state_saved:1;
d1b054da 321 unsigned int is_physfn:1;
dd7cc44d 322 unsigned int is_virtfn:1;
711d5779 323 unsigned int reset_fn:1;
28760489 324 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 325 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1;
ba698ad4 327 pci_dev_flags_t dev_flags;
bae94d02 328 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 329
1da177e4 330 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 331 struct hlist_head saved_cap_space;
1da177e4
LT		 332 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
333 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
334 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 335 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 336#ifdef CONFIG_PCI_MSI
4aa9bc95 337 struct list_head msi_list;
da8d1c8b 338 struct kset *msi_kset;
ded86d8d 339#endif
94e61088 340 struct pci_vpd *vpd;
466b3ddf 341#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 342 union {
343 struct pci_sriov *sriov; /* SR-IOV capability related */
344 struct pci_dev *physfn; /* the PF this VF is associated with */
345 };
302b4215 346 struct pci_ats *ats; /* Address Translation Service */
d1b054da 347#endif
1da177e4
LT		 348};
349
dda56549
Y		 350static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
351{
352#ifdef CONFIG_PCI_IOV
353 if (dev->is_virtfn)
354 dev = dev->physfn;
355#endif
356
357 return dev;
358}
359
65891215
ME		 360extern struct pci_dev *alloc_pci_dev(void);
361
1da177e4
LT		 362#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
363#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
364#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
365
a7369f1f
LV		 366static inline int pci_channel_offline(struct pci_dev *pdev)
367{
368 return (pdev->error_state != pci_channel_io_normal);
369}
370
0efd5aab
BH		 371struct pci_host_bridge_window {
372 struct list_head list;
373 struct resource *res; /* host bridge aperture (CPU address) */
374 resource_size_t offset; /* bus address + offset = CPU address */
375};
41017f0c 376
5a21d70d 377struct pci_host_bridge {
7b543663 378 struct device dev;
5a21d70d 379 struct pci_bus *bus; /* root bus */
0efd5aab 380 struct list_head windows; /* pci_host_bridge_windows */
5a21d70d 381};
41017f0c 382
7b543663
YL		 383#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
384
2fe2abf8
BH		 385/*
386 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
387 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
388 * buses below host bridges or subtractive decode bridges) go in the list.
389 * Use pci_bus_for_each_resource() to iterate through all the resources.
390 */
391
392/*
393 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
394 * and there's no way to program the bridge with the details of the window.
395 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
396 * decode bit set, because they are explicit and can be programmed with _SRS.
397 */
398#define PCI_SUBTRACTIVE_DECODE 0x1
399
400struct pci_bus_resource {
401 struct list_head list;
402 struct resource *res;
403 unsigned int flags;
404};
4352dfd5
GKH		 405
406#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 407
408struct pci_bus {
409 struct list_head node; /* node in list of buses */
410 struct pci_bus *parent; /* parent bus this bridge is on */
411 struct list_head children; /* list of child buses */
412 struct list_head devices; /* list of devices on this bus */
413 struct pci_dev *self; /* bridge device as seen by parent */
f46753c5 414 struct list_head slots; /* list of slots on this bus */
2fe2abf8
BH		 415 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
416 struct list_head resources; /* address space routed to this bus */
1da177e4
LT		 417
418 struct pci_ops *ops; /* configuration access functions */
419 void *sysdata; /* hook for sys-specific extension */
420 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
421
422 unsigned char number; /* bus number */
423 unsigned char primary; /* number of primary bridge */
424 unsigned char secondary; /* number of secondary bridge */
425 unsigned char subordinate; /* max number of subordinate buses */
3749c51a
MW		 426 unsigned char max_bus_speed; /* enum pci_bus_speed */
427 unsigned char cur_bus_speed; /* enum pci_bus_speed */
1da177e4
LT		 428
429 char name[48];
430
431 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 432 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4 433 struct device *bridge;
fd7d1ced 434 struct device dev;
1da177e4
LT		 435 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
436 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 437 unsigned int is_added:1;
1da177e4
LT		 438};
439
440#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
fd7d1ced 441#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 442
79af72d7
KK		 443/*
444 * Returns true if the pci bus is root (behind host-pci bridge),
445 * false otherwise
446 */
447static inline bool pci_is_root_bus(struct pci_bus *pbus)
448{
449 return !(pbus->parent);
450}
451
16cf0ebc
RW		 452#ifdef CONFIG_PCI_MSI
453static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
454{
455 return pci_dev->msi_enabled || pci_dev->msix_enabled;
456}
457#else
458static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
459#endif
460
1da177e4
LT		 461/*
462 * Error values that may be returned by PCI functions.
463 */
464#define PCIBIOS_SUCCESSFUL 0x00
465#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
466#define PCIBIOS_BAD_VENDOR_ID 0x83
467#define PCIBIOS_DEVICE_NOT_FOUND 0x86
468#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
469#define PCIBIOS_SET_FAILED 0x88
470#define PCIBIOS_BUFFER_TOO_SMALL 0x89
471
472/* Low-level architecture-dependent routines */
473
474struct pci_ops {
475 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
476 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
477};
478
b6ce068a
MW		 479/*
480 * ACPI needs to be able to access PCI config space before we've done a
481 * PCI bus scan and created pci_bus structures.
482 */
483extern int raw_pci_read(unsigned int domain, unsigned int bus,
484 unsigned int devfn, int reg, int len, u32 *val);
485extern int raw_pci_write(unsigned int domain, unsigned int bus,
486 unsigned int devfn, int reg, int len, u32 val);
1da177e4
LT		 487
488struct pci_bus_region {
c40a22e0
BH		 489 resource_size_t start;
490 resource_size_t end;
1da177e4
LT		 491};
492
493struct pci_dynids {
494 spinlock_t lock; /* protects list, index */
495 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 496};
497
392a1ce7 498/* ---------------------------------------------------------------- */
499/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
579082df 500 * a set of callbacks in struct pci_error_handlers, then that device driver
392a1ce7 501 * will be notified of PCI bus errors, and will be driven to recovery
502 * when an error occurs.
503 */
504
505typedef unsigned int __bitwise pci_ers_result_t;
506
507enum pci_ers_result {
508 /* no result/none/not supported in device driver */
509 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
510
511 /* Device driver can recover without slot reset */
512 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
513
514 /* Device driver wants slot to be reset. */
515 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
516
517 /* Device has completely failed, is unrecoverable */
518 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
519
520 /* Device driver is fully recovered and operational */
521 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
522};
523
524/* PCI bus error event callbacks */
05cca6e5 525struct pci_error_handlers {
392a1ce7 526 /* PCI bus error detected on this device */
527 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 528 enum pci_channel_state error);
392a1ce7 529
530 /* MMIO has been re-enabled, but not DMA */
531 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
532
533 /* PCI Express link has been reset */
534 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
535
536 /* PCI slot has been reset */
537 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
538
539 /* Device driver may resume normal operations */
540 void (*resume)(struct pci_dev *dev);
541};
542
543/* ---------------------------------------------------------------- */
544
1da177e4
LT		 545struct module;
546struct pci_driver {
547 struct list_head node;
42b21932 548 const char *name;
1da177e4
LT		 549 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
550 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
551 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
552 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 553 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
554 int (*resume_early) (struct pci_dev *dev);
1da177e4 555 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 556 void (*shutdown) (struct pci_dev *dev);
392a1ce7 557 struct pci_error_handlers *err_handler;
1da177e4
LT		 558 struct device_driver driver;
559 struct pci_dynids dynids;
560};
561
05cca6e5 562#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 563
90a1ba0c 564/**
9f9351bb 565 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 566 * @_table: device table name
567 *
568 * This macro is used to create a struct pci_device_id array (a device table)
569 * in a generic manner.
570 */
9f9351bb 571#define DEFINE_PCI_DEVICE_TABLE(_table) \
90a1ba0c
JB		 572 const struct pci_device_id _table[] __devinitconst
573
1da177e4
LT		 574/**
575 * PCI_DEVICE - macro used to describe a specific pci device
576 * @vend: the 16 bit PCI Vendor ID
577 * @dev: the 16 bit PCI Device ID
578 *
579 * This macro is used to create a struct pci_device_id that matches a
580 * specific device. The subvendor and subdevice fields will be set to
581 * PCI_ANY_ID.
582 */
583#define PCI_DEVICE(vend,dev) \
584 .vendor = (vend), .device = (dev), \
585 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
586
587/**
588 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
589 * @dev_class: the class, subclass, prog-if triple for this device
590 * @dev_class_mask: the class mask for this device
591 *
592 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 593 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 594 * fields will be set to PCI_ANY_ID.
595 */
596#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
597 .class = (dev_class), .class_mask = (dev_class_mask), \
598 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
599 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
600
1597cacb
AC		 601/**
602 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c322b28a
ZY		 603 * @vendor: the vendor name
604 * @device: the 16 bit PCI Device ID
1597cacb
AC		 605 *
606 * This macro is used to create a struct pci_device_id that matches a
607 * specific PCI device. The subvendor, and subdevice fields will be set
608 * to PCI_ANY_ID. The macro allows the next field to follow as the device
609 * private data.
610 */
611
612#define PCI_VDEVICE(vendor, device) \
613 PCI_VENDOR_ID_##vendor, (device), \
614 PCI_ANY_ID, PCI_ANY_ID, 0, 0
615
1da177e4
LT		 616/* these external functions are only available when PCI support is enabled */
617#ifdef CONFIG_PCI
618
b03e7495
JM		 619extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
620
621enum pcie_bus_config_types {
5f39e670 622 PCIE_BUS_TUNE_OFF,
b03e7495 623 PCIE_BUS_SAFE,
5f39e670 624 PCIE_BUS_PERFORMANCE,
b03e7495
JM		 625 PCIE_BUS_PEER2PEER,
626};
627
628extern enum pcie_bus_config_types pcie_bus_config;
629
1da177e4
LT		 630extern struct bus_type pci_bus_type;
631
632/* Do NOT directly access these two variables, unless you are arch specific pci
633 * code, or pci core code. */
634extern struct list_head pci_root_buses; /* list of all known PCI buses */
ed4aaadb
ZY		 635/* Some device drivers need know if pci is initiated */
636extern int no_pci_devices(void);
1da177e4
LT		 637
638void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 639int __must_check pcibios_enable_device(struct pci_dev *, int mask);
05cca6e5 640char *pcibios_setup(char *str);
1da177e4
LT		 641
642/* Used only when drivers/pci/setup.c is used */
3b7a17fc 643resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 644 resource_size_t,
e31dd6e4 645 resource_size_t);
1da177e4
LT		 646void pcibios_update_irq(struct pci_dev *, int irq);
647
2d1c8618
BH		 648/* Weak but can be overriden by arch */
649void pci_fixup_cardbus(struct pci_bus *);
650
1da177e4
LT		 651/* Generic PCI functions used internally */
652
36a66cd6
BH		 653void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
654 struct resource *res);
655void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
656 struct pci_bus_region *region);
d1fd4fb6 657void pcibios_scan_specific_bus(int busn);
1da177e4 658extern struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 659void pci_bus_add_devices(const struct pci_bus *bus);
05cca6e5
GKH		 660struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
661 struct pci_ops *ops, void *sysdata);
de4b2f76 662struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 663struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
664 struct pci_ops *ops, void *sysdata,
665 struct list_head *resources);
a2ebb827
BH		 666struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
667 struct pci_ops *ops, void *sysdata,
668 struct list_head *resources);
05cca6e5
GKH		 669struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
670 int busnr);
3749c51a 671void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 672struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 673 const char *name,
674 struct hotplug_slot *hotplug);
f46753c5 675void pci_destroy_slot(struct pci_slot *slot);
d25b7c8d 676void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
1da177e4 677int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 678struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 679void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 680unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 681int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4 682void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 683struct resource *pci_find_parent_resource(const struct pci_dev *dev,
684 struct resource *res);
57c2cf71 685u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
1da177e4 686int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 687u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1da177e4
LT		 688extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
689extern void pci_dev_put(struct pci_dev *dev);
690extern void pci_remove_bus(struct pci_bus *b);
6b22cf3f 691extern void __pci_remove_bus_device(struct pci_dev *dev);
210647af 692extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
24f8aa9b 693extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 694void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 695extern void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 696#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
697#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
698#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 699
700/* Generic PCI functions exported to card drivers */
701
388c8c16
JB		 702enum pci_lost_interrupt_reason {
703 PCI_LOST_IRQ_NO_INFORMATION = 0,
704 PCI_LOST_IRQ_DISABLE_MSI,
705 PCI_LOST_IRQ_DISABLE_MSIX,
706 PCI_LOST_IRQ_DISABLE_ACPI,
707};
708enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 709int pci_find_capability(struct pci_dev *dev, int cap);
710int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
711int pci_find_ext_capability(struct pci_dev *dev, int cap);
cf4c43dd
JB		 712int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
713 int cap);
05cca6e5
GKH		 714int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
715int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 716struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 717
d42552c3
AM		 718struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
719 struct pci_dev *from);
05cca6e5 720struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 721 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 722 struct pci_dev *from);
05cca6e5 723struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 724struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
725 unsigned int devfn);
726static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
727 unsigned int devfn)
728{
729 return pci_get_domain_bus_and_slot(0, bus, devfn);
730}
05cca6e5 731struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 732int pci_dev_present(const struct pci_device_id *ids);
733
05cca6e5
GKH		 734int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
735 int where, u8 *val);
736int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
737 int where, u16 *val);
738int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
739 int where, u32 *val);
740int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
741 int where, u8 val);
742int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
743 int where, u16 val);
744int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
745 int where, u32 val);
a72b46c3 746struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 747
bf362f75 748static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 749{
05cca6e5 750 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 751}
bf362f75 752static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 753{
05cca6e5 754 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 755}
bf362f75 756static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 757 u32 *val)
1da177e4 758{
05cca6e5 759 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 760}
bf362f75 761static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 762{
05cca6e5 763 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 764}
bf362f75 765static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 766{
05cca6e5 767 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 768}
bf362f75 769static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 770 u32 val)
1da177e4 771{
05cca6e5 772 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 773}
774
4a7fb636 775int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 776int __must_check pci_enable_device_io(struct pci_dev *dev);
777int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 778int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 779int __must_check pcim_enable_device(struct pci_dev *pdev);
780void pcim_pin_device(struct pci_dev *pdev);
781
296ccb08
YS		 782static inline int pci_is_enabled(struct pci_dev *pdev)
783{
784 return (atomic_read(&pdev->enable_cnt) > 0);
785}
786
9ac7849e
TH		 787static inline int pci_is_managed(struct pci_dev *pdev)
788{
789 return pdev->is_managed;
790}
791
1da177e4 792void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 793
794extern unsigned int pcibios_max_latency;
1da177e4 795void pci_set_master(struct pci_dev *dev);
6a479079 796void pci_clear_master(struct pci_dev *dev);
96c55900 797
f7bdd12d 798int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 799int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 800#define HAVE_PCI_SET_MWI
4a7fb636 801int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 802int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 803void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 804void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 805bool pci_intx_mask_supported(struct pci_dev *dev);
806bool pci_check_and_mask_intx(struct pci_dev *dev);
807bool pci_check_and_unmask_intx(struct pci_dev *dev);
f5f2b131 808void pci_msi_off(struct pci_dev *dev);
4d57cdfa 809int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
59fc67de 810int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
d556ad4b
PO		 811int pcix_get_max_mmrbc(struct pci_dev *dev);
812int pcix_get_mmrbc(struct pci_dev *dev);
813int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 814int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 815int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 816int pcie_get_mps(struct pci_dev *dev);
817int pcie_set_mps(struct pci_dev *dev, int mps);
8c1c699f 818int __pci_reset_function(struct pci_dev *dev);
a96d627a 819int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 820int pci_reset_function(struct pci_dev *dev);
14add80b 821void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 822int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 823int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 824int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 825
826/* ROM control related routines */
e416de5e
AC		 827int pci_enable_rom(struct pci_dev *pdev);
828void pci_disable_rom(struct pci_dev *pdev);
144a50ea 829void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 830void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 831size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1da177e4
LT		 832
833/* Power management related routines */
834int pci_save_state(struct pci_dev *dev);
1d3c16a8 835void pci_restore_state(struct pci_dev *dev);
ffbdd3f7
AW		 836struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
837int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
838int pci_load_and_free_saved_state(struct pci_dev *dev,
839 struct pci_saved_state **state);
0e5dd46b 840int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 841int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
842pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 843bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 844void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 845int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
846 bool runtime, bool enable);
0235c4fc 847int pci_wake_from_d3(struct pci_dev *dev, bool enable);
e5899e1b 848pci_power_t pci_target_state(struct pci_dev *dev);
404cc2d8
RW		 849int pci_prepare_to_sleep(struct pci_dev *dev);
850int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 851bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 852bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 853void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 854
6cbf8214
RW		 855static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
856 bool enable)
857{
858 return __pci_enable_wake(dev, state, false, enable);
859}
1da177e4 860
b48d4425
JB		 861#define PCI_EXP_IDO_REQUEST (1<<0)
862#define PCI_EXP_IDO_COMPLETION (1<<1)
863void pci_enable_ido(struct pci_dev *dev, unsigned long type);
864void pci_disable_ido(struct pci_dev *dev, unsigned long type);
865
48a92a81 866enum pci_obff_signal_type {
688398bb
MS		 867 PCI_EXP_OBFF_SIGNAL_L0 = 0,
868 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
48a92a81
JB		 869};
870int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
871void pci_disable_obff(struct pci_dev *dev);
872
51c2e0a7
JB		 873bool pci_ltr_supported(struct pci_dev *dev);
874int pci_enable_ltr(struct pci_dev *dev);
875void pci_disable_ltr(struct pci_dev *dev);
876int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
877
bb209c82
BH		 878/* For use by arch with custom probe code */
879void set_pcie_port_type(struct pci_dev *pdev);
880void set_pcie_hotplug_bridge(struct pci_dev *pdev);
881
ce5ccdef 882/* Functions for PCI Hotplug drivers to use */
05cca6e5 883int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
3ed4fd96 884#ifdef CONFIG_HOTPLUG
2f320521 885unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96
AC		 886unsigned int pci_rescan_bus(struct pci_bus *bus);
887#endif
ce5ccdef 888
287d19ce
SH		 889/* Vital product data routines */
890ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
891ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
db567943 892int pci_vpd_truncate(struct pci_dev *dev, size_t size);
287d19ce 893
1da177e4 894/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 895resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 896void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 897void pci_bus_size_bridges(struct pci_bus *bus);
898int pci_claim_resource(struct pci_dev *, int);
899void pci_assign_unassigned_resources(void);
6841ec68 900void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1da177e4 901void pdev_enable_device(struct pci_dev *);
842de40d 902int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 903void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 904 int (*)(const struct pci_dev *, u8, u8));
1da177e4 905#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 906int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 907int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 908void pci_release_regions(struct pci_dev *);
4a7fb636 909int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 910int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 911void pci_release_region(struct pci_dev *, int);
c87deff7 912int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 913int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 914void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 915
916/* drivers/pci/bus.c */
45ca9e97 917void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 918void pci_add_resource_offset(struct list_head *resources, struct resource *res,
919 resource_size_t offset);
45ca9e97 920void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 921void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
922struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
923void pci_bus_remove_resources(struct pci_bus *bus);
924
89a74ecc 925#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 926 for (i = 0; \
927 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
928 i++)
89a74ecc 929
4a7fb636
AM		 930int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
931 struct resource *res, resource_size_t size,
932 resource_size_t align, resource_size_t min,
933 unsigned int type_mask,
3b7a17fc
DB		 934 resource_size_t (*alignf)(void *,
935 const struct resource *,
b26b2d49
DB		 936 resource_size_t,
937 resource_size_t),
4a7fb636 938 void *alignf_data);
1da177e4
LT		 939void pci_enable_bridges(struct pci_bus *bus);
940
863b18f4 941/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 942int __must_check __pci_register_driver(struct pci_driver *, struct module *,
943 const char *mod_name);
bba81165
AM		 944
945/*
946 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
947 */
948#define pci_register_driver(driver) \
949 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 950
05cca6e5 951void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 952
953/**
954 * module_pci_driver() - Helper macro for registering a PCI driver
955 * @__pci_driver: pci_driver struct
956 *
957 * Helper macro for PCI drivers which do not do anything special in module
958 * init/exit. This eliminates a lot of boilerplate. Each module may only
959 * use this macro once, and calling it replaces module_init() and module_exit()
960 */
961#define module_pci_driver(__pci_driver) \
962 module_driver(__pci_driver, pci_register_driver, \
963 pci_unregister_driver)
964
6754b9e9 965void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
05cca6e5 966struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 967int pci_add_dynid(struct pci_driver *drv,
968 unsigned int vendor, unsigned int device,
969 unsigned int subvendor, unsigned int subdevice,
970 unsigned int class, unsigned int class_mask,
971 unsigned long driver_data);
05cca6e5
GKH		 972const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
973 struct pci_dev *dev);
974int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
975 int pass);
1da177e4 976
70298c6e 977void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 978 void *userdata);
70b9f7dc 979int pci_cfg_space_size_ext(struct pci_dev *dev);
ac7dc65a 980int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 981unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 982void pci_setup_bridge(struct pci_bus *bus);
cecf4864 983
3448a19d
DA		 984#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
985#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
986
deb2d2ec 987int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 988 unsigned int command_bits, u32 flags);
1da177e4
LT		 989/* kmem_cache style wrapper around pci_alloc_consistent() */
990
f41b1771 991#include <linux/pci-dma.h>
1da177e4
LT		 992#include <linux/dmapool.h>
993
994#define pci_pool dma_pool
995#define pci_pool_create(name, pdev, size, align, allocation) \
996 dma_pool_create(name, &pdev->dev, size, align, allocation)
997#define pci_pool_destroy(pool) dma_pool_destroy(pool)
998#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
999#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1000
e24c2d96
DM		 1001enum pci_dma_burst_strategy {
1002 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1003 strategy_parameter is N/A */
1004 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1005 byte boundaries */
1006 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1007 strategy_parameter byte boundaries */
1008};
1009
1da177e4 1010struct msix_entry {
16dbef4a 1011 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1012 u16 entry; /* driver uses to specify entry, OS writes */
1013};
1014
0366f8f7 1015
1da177e4 1016#ifndef CONFIG_PCI_MSI
1c8d7b0a 1017static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
05cca6e5
GKH		 1018{
1019 return -1;
1020}
1021
d52877c7
YL		 1022static inline void pci_msi_shutdown(struct pci_dev *dev)
1023{ }
05cca6e5
GKH		 1024static inline void pci_disable_msi(struct pci_dev *dev)
1025{ }
1026
a52e2e35
RW		 1027static inline int pci_msix_table_size(struct pci_dev *dev)
1028{
1029 return 0;
1030}
05cca6e5
GKH		 1031static inline int pci_enable_msix(struct pci_dev *dev,
1032 struct msix_entry *entries, int nvec)
1033{
1034 return -1;
1035}
1036
d52877c7
YL		 1037static inline void pci_msix_shutdown(struct pci_dev *dev)
1038{ }
05cca6e5
GKH		 1039static inline void pci_disable_msix(struct pci_dev *dev)
1040{ }
1041
1042static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1043{ }
1044
1045static inline void pci_restore_msi_state(struct pci_dev *dev)
1046{ }
07ae95f9
AP		 1047static inline int pci_msi_enabled(void)
1048{
1049 return 0;
1050}
1da177e4 1051#else
1c8d7b0a 1052extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
d52877c7 1053extern void pci_msi_shutdown(struct pci_dev *dev);
1da177e4 1054extern void pci_disable_msi(struct pci_dev *dev);
a52e2e35 1055extern int pci_msix_table_size(struct pci_dev *dev);
05cca6e5 1056extern int pci_enable_msix(struct pci_dev *dev,
1da177e4 1057 struct msix_entry *entries, int nvec);
d52877c7 1058extern void pci_msix_shutdown(struct pci_dev *dev);
1da177e4
LT		 1059extern void pci_disable_msix(struct pci_dev *dev);
1060extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
94688cf2 1061extern void pci_restore_msi_state(struct pci_dev *dev);
07ae95f9 1062extern int pci_msi_enabled(void);
1da177e4
LT		 1063#endif
1064
ab0724ff 1065#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1066extern bool pcie_ports_disabled;
1067extern bool pcie_ports_auto;
ab0724ff
MT		 1068#else
1069#define pcie_ports_disabled true
1070#define pcie_ports_auto false
1071#endif
415e12b2 1072
3e1b1600 1073#ifndef CONFIG_PCIEASPM
8b8bae90
RW		 1074static inline int pcie_aspm_enabled(void) { return 0; }
1075static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1076#else
1077extern int pcie_aspm_enabled(void);
8b8bae90 1078extern bool pcie_aspm_support_enabled(void);
3e1b1600
AP		 1079#endif
1080
415e12b2
RW		 1081#ifdef CONFIG_PCIEAER
1082void pci_no_aer(void);
1083bool pci_aer_available(void);
1084#else
1085static inline void pci_no_aer(void) { }
1086static inline bool pci_aer_available(void) { return false; }
1087#endif
1088
43c16408
AP		 1089#ifndef CONFIG_PCIE_ECRC
1090static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1091{
1092 return;
1093}
1094static inline void pcie_ecrc_get_policy(char *str) {};
1095#else
1096extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1097extern void pcie_ecrc_get_policy(char *str);
1098#endif
1099
1c8d7b0a
MW		 1100#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1101
8b955b0d 1102#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1103/* The functions a driver should call */
1104int ht_create_irq(struct pci_dev *dev, int idx);
1105void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1106#endif /* CONFIG_HT_IRQ */
1107
fb51ccbf
JK		 1108extern void pci_cfg_access_lock(struct pci_dev *dev);
1109extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1110extern void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1111
4352dfd5
GKH		 1112/*
1113 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1114 * a PCI domain is defined to be a set of PCI busses which share
1115 * configuration space.
1116 */
32a2eea7
JG		 1117#ifdef CONFIG_PCI_DOMAINS
1118extern int pci_domains_supported;
1119#else
1120enum { pci_domains_supported = 0 };
05cca6e5
GKH		 1121static inline int pci_domain_nr(struct pci_bus *bus)
1122{
1123 return 0;
1124}
1125
4352dfd5
GKH		 1126static inline int pci_proc_domain(struct pci_bus *bus)
1127{
1128 return 0;
1129}
32a2eea7 1130#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1131
95a8b6ef
MT		 1132/* some architectures require additional setup to direct VGA traffic */
1133typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1134 unsigned int command_bits, u32 flags);
95a8b6ef
MT		 1135extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1136
4352dfd5 1137#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 1138
1139/*
1140 * If the system does not have PCI, clearly these return errors. Define
1141 * these as simple inline functions to avoid hair in drivers.
1142 */
1143
05cca6e5
GKH		 1144#define _PCI_NOP(o, s, t) \
1145 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1146 int where, t val) \
1da177e4 1147 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1148
1149#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1150 _PCI_NOP(o, word, u16 x) \
1151 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1152_PCI_NOP_ALL(read, *)
1153_PCI_NOP_ALL(write,)
1154
d42552c3 1155static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1156 unsigned int device,
1157 struct pci_dev *from)
1158{
1159 return NULL;
1160}
d42552c3 1161
05cca6e5
GKH		 1162static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1163 unsigned int device,
1164 unsigned int ss_vendor,
1165 unsigned int ss_device,
b08508c4 1166 struct pci_dev *from)
05cca6e5
GKH		 1167{
1168 return NULL;
1169}
1da177e4 1170
05cca6e5
GKH		 1171static inline struct pci_dev *pci_get_class(unsigned int class,
1172 struct pci_dev *from)
1173{
1174 return NULL;
1175}
1da177e4
LT		 1176
1177#define pci_dev_present(ids) (0)
ed4aaadb 1178#define no_pci_devices() (1)
1da177e4
LT		 1179#define pci_dev_put(dev) do { } while (0)
1180
05cca6e5
GKH		 1181static inline void pci_set_master(struct pci_dev *dev)
1182{ }
1183
1184static inline int pci_enable_device(struct pci_dev *dev)
1185{
1186 return -EIO;
1187}
1188
1189static inline void pci_disable_device(struct pci_dev *dev)
1190{ }
1191
1192static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1193{
1194 return -EIO;
1195}
1196
80be0385
RD		 1197static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1198{
1199 return -EIO;
1200}
1201
4d57cdfa
FT		 1202static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1203 unsigned int size)
1204{
1205 return -EIO;
1206}
1207
59fc67de
FT		 1208static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1209 unsigned long mask)
1210{
1211 return -EIO;
1212}
1213
05cca6e5
GKH		 1214static inline int pci_assign_resource(struct pci_dev *dev, int i)
1215{
1216 return -EBUSY;
1217}
1218
1219static inline int __pci_register_driver(struct pci_driver *drv,
1220 struct module *owner)
1221{
1222 return 0;
1223}
1224
1225static inline int pci_register_driver(struct pci_driver *drv)
1226{
1227 return 0;
1228}
1229
1230static inline void pci_unregister_driver(struct pci_driver *drv)
1231{ }
1232
1233static inline int pci_find_capability(struct pci_dev *dev, int cap)
1234{
1235 return 0;
1236}
1237
1238static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1239 int cap)
1240{
1241 return 0;
1242}
1243
1244static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1245{
1246 return 0;
1247}
1248
1da177e4 1249/* Power management related routines */
05cca6e5
GKH		 1250static inline int pci_save_state(struct pci_dev *dev)
1251{
1252 return 0;
1253}
1254
1d3c16a8
JM		 1255static inline void pci_restore_state(struct pci_dev *dev)
1256{ }
1da177e4 1257
05cca6e5
GKH		 1258static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1259{
1260 return 0;
1261}
1262
3449248c
RD		 1263static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1264{
1265 return 0;
1266}
1267
05cca6e5
GKH		 1268static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1269 pm_message_t state)
1270{
1271 return PCI_D0;
1272}
1273
1274static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1275 int enable)
1276{
1277 return 0;
1278}
1279
b48d4425
JB		 1280static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1281{
1282}
1283
1284static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1285{
1286}
1287
48a92a81
JB		 1288static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1289{
1290 return 0;
1291}
1292
1293static inline void pci_disable_obff(struct pci_dev *dev)
1294{
1295}
1296
05cca6e5
GKH		 1297static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1298{
1299 return -EIO;
1300}
1301
1302static inline void pci_release_regions(struct pci_dev *dev)
1303{ }
0da0ead9 1304
a46e8126
KG		 1305#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1306
fb51ccbf 1307static inline void pci_block_cfg_access(struct pci_dev *dev)
05cca6e5
GKH		 1308{ }
1309
fb51ccbf
JK		 1310static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1311{ return 0; }
1312
1313static inline void pci_unblock_cfg_access(struct pci_dev *dev)
05cca6e5 1314{ }
e04b0ea2 1315
d80d0217
RD		 1316static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1317{ return NULL; }
1318
1319static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1320 unsigned int devfn)
1321{ return NULL; }
1322
1323static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1324 unsigned int devfn)
1325{ return NULL; }
1326
92298e66
DA		 1327static inline int pci_domain_nr(struct pci_bus *bus)
1328{ return 0; }
1329
fb8a0d9d
WM		 1330#define dev_is_pci(d) (false)
1331#define dev_is_pf(d) (false)
1332#define dev_num_vf(d) (0)
4352dfd5 1333#endif /* CONFIG_PCI */
1da177e4 1334
4352dfd5
GKH		 1335/* Include architecture-dependent settings and functions */
1336
1337#include <asm/pci.h>
1da177e4 1338
1f82de10
YL		 1339#ifndef PCIBIOS_MAX_MEM_32
1340#define PCIBIOS_MAX_MEM_32 (-1)
1341#endif
1342
1da177e4
LT		 1343/* these helpers provide future and backwards compatibility
1344 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1345#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1346#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1347#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1348#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1349 ((pci_resource_start((dev), (bar)) == 0 && \
1350 pci_resource_end((dev), (bar)) == \
1351 pci_resource_start((dev), (bar))) ? 0 : \
1352 \
1353 (pci_resource_end((dev), (bar)) - \
1354 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1355
1356/* Similar to the helpers above, these manipulate per-pci_dev
1357 * driver-specific data. They are really just a wrapper around
1358 * the generic device structure functions of these calls.
1359 */
05cca6e5 1360static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1361{
1362 return dev_get_drvdata(&pdev->dev);
1363}
1364
05cca6e5 1365static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1366{
1367 dev_set_drvdata(&pdev->dev, data);
1368}
1369
1370/* If you want to know what to call your pci_dev, ask this function.
1371 * Again, it's a wrapper around the generic device.
1372 */
2fc90f61 1373static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1374{
c6c4f070 1375 return dev_name(&pdev->dev);
1da177e4
LT		 1376}
1377
2311b1f2
ME		 1378
1379/* Some archs don't want to expose struct resource to userland as-is
1380 * in sysfs and /proc
1381 */
1382#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1383static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1384 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1385 resource_size_t *end)
2311b1f2
ME		 1386{
1387 *start = rsrc->start;
1388 *end = rsrc->end;
1389}
1390#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1391
1392
1da177e4
LT		 1393/*
1394 * The world is not perfect and supplies us with broken PCI devices.
1395 * For at least a part of these bugs we need a work-around, so both
1396 * generic (drivers/pci/quirks.c) and per-architecture code can define
1397 * fixup hooks to be called for particular buggy devices.
1398 */
1399
1400struct pci_fixup {
f4ca5c6a
YL		 1401 u16 vendor; /* You can use PCI_ANY_ID here of course */
1402 u16 device; /* You can use PCI_ANY_ID here of course */
1403 u32 class; /* You can use PCI_ANY_ID here too */
1404 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1405 void (*hook)(struct pci_dev *dev);
1406};
1407
1408enum pci_fixup_pass {
1409 pci_fixup_early, /* Before probing BARs */
1410 pci_fixup_header, /* After reading configuration header */
1411 pci_fixup_final, /* Final phase of device fixups */
1412 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e
RW		 1413 pci_fixup_resume, /* pci_device_resume() */
1414 pci_fixup_suspend, /* pci_device_suspend */
1415 pci_fixup_resume_early, /* pci_device_resume_early() */
1da177e4
LT		 1416};
1417
1418/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1419#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1420 class_shift, hook) \
1421 static const struct pci_fixup const __pci_fixup_##name __used \
1422 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1423 = { vendor, device, class, class_shift, hook };
1424
1425#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1426 class_shift, hook) \
1427 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1428 vendor##device##hook, vendor, device, class, class_shift, hook)
1429#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1430 class_shift, hook) \
1431 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1432 vendor##device##hook, vendor, device, class, class_shift, hook)
1433#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1434 class_shift, hook) \
1435 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1436 vendor##device##hook, vendor, device, class, class_shift, hook)
1437#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1438 class_shift, hook) \
1439 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1440 vendor##device##hook, vendor, device, class, class_shift, hook)
1441#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1442 class_shift, hook) \
1443 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1444 resume##vendor##device##hook, vendor, device, class, \
1445 class_shift, hook)
1446#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1447 class_shift, hook) \
1448 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1449 resume_early##vendor##device##hook, vendor, device, \
1450 class, class_shift, hook)
1451#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1452 class_shift, hook) \
1453 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1454 suspend##vendor##device##hook, vendor, device, class, \
1455 class_shift, hook)
1456
1da177e4
LT		 1457#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1458 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
f4ca5c6a 1459 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1460#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1461 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
f4ca5c6a 1462 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1463#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1464 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
f4ca5c6a 1465 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1466#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1467 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
f4ca5c6a 1468 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1469#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1470 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
f4ca5c6a
YL		 1471 resume##vendor##device##hook, vendor, device, \
1472 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1473#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1474 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
f4ca5c6a
YL		 1475 resume_early##vendor##device##hook, vendor, device, \
1476 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1477#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1478 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
f4ca5c6a
YL		 1479 suspend##vendor##device##hook, vendor, device, \
1480 PCI_ANY_ID, 0, hook)
1da177e4 1481
93177a74 1482#ifdef CONFIG_PCI_QUIRKS
1da177e4 1483void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 1484#else
1485static inline void pci_fixup_device(enum pci_fixup_pass pass,
1486 struct pci_dev *dev) {}
1487#endif
1da177e4 1488
05cca6e5 1489void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1490void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1491void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1492int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1493int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1494 const char *name);
fb7ebfe4 1495void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1496
1da177e4 1497extern int pci_pci_problems;
236561e5 1498#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1499#define PCIPCI_TRITON 2
1500#define PCIPCI_NATOMA 4
1501#define PCIPCI_VIAETBF 8
1502#define PCIPCI_VSFX 16
236561e5
AC		 1503#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1504#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1505
4516a618
AN		 1506extern unsigned long pci_cardbus_io_size;
1507extern unsigned long pci_cardbus_mem_size;
491424c0 1508extern u8 __devinitdata pci_dfl_cache_line_size;
ac1aa47b 1509extern u8 pci_cache_line_size;
4516a618 1510
28760489
EB		 1511extern unsigned long pci_hotplug_io_size;
1512extern unsigned long pci_hotplug_mem_size;
1513
cfce9fb8 1514/* Architecture specific versions may override these (weak) */
19792a08
AB		 1515int pcibios_add_platform_entries(struct pci_dev *dev);
1516void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1517void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1518int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1519 enum pcie_reset_state state);
575e3348 1520
7752d5cf 1521#ifdef CONFIG_PCI_MMCONFIG
bb63b421 1522extern void __init pci_mmcfg_early_init(void);
7752d5cf
RH		 1523extern void __init pci_mmcfg_late_init(void);
1524#else
bb63b421 1525static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1526static inline void pci_mmcfg_late_init(void) { }
1527#endif
1528
0ef5f8f6
AP		 1529int pci_ext_cfg_avail(struct pci_dev *dev);
1530
1684f5dd 1531void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1532
dd7cc44d
YZ		 1533#ifdef CONFIG_PCI_IOV
1534extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1535extern void pci_disable_sriov(struct pci_dev *dev);
74bb1bcc 1536extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
fb8a0d9d 1537extern int pci_num_vf(struct pci_dev *dev);
dd7cc44d
YZ		 1538#else
1539static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1540{
1541 return -ENODEV;
1542}
1543static inline void pci_disable_sriov(struct pci_dev *dev)
1544{
1545}
74bb1bcc
YZ		 1546static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1547{
1548 return IRQ_NONE;
1549}
fb8a0d9d
WM		 1550static inline int pci_num_vf(struct pci_dev *dev)
1551{
1552 return 0;
1553}
dd7cc44d
YZ		 1554#endif
1555
c825bc94
KK		 1556#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1557extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1558extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1559#endif
1560
d7b7e605
KK		 1561/**
1562 * pci_pcie_cap - get the saved PCIe capability offset
1563 * @dev: PCI device
1564 *
1565 * PCIe capability offset is calculated at PCI device initialization
1566 * time and saved in the data structure. This function returns saved
1567 * PCIe capability offset. Using this instead of pci_find_capability()
1568 * reduces unnecessary search in the PCI configuration space. If you
1569 * need to calculate PCIe capability offset from raw device for some
1570 * reasons, please use pci_find_capability() instead.
1571 */
1572static inline int pci_pcie_cap(struct pci_dev *dev)
1573{
1574 return dev->pcie_cap;
1575}
1576
7eb776c4
KK		 1577/**
1578 * pci_is_pcie - check if the PCI device is PCI Express capable
1579 * @dev: PCI device
1580 *
1581 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1582 */
1583static inline bool pci_is_pcie(struct pci_dev *dev)
1584{
1585 return !!pci_pcie_cap(dev);
1586}
1587
5d990b62
CW		 1588void pci_request_acs(void);
1589
a2ce7662 1590
7ad506fa
MC		 1591#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1592#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1593
1594/* Large Resource Data Type Tag Item Names */
1595#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1596#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1597#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1598
1599#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1600#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1601#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1602
1603/* Small Resource Data Type Tag Item Names */
1604#define PCI_VPD_STIN_END 0x78 /* End */
1605
1606#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1607
1608#define PCI_VPD_SRDT_TIN_MASK 0x78
1609#define PCI_VPD_SRDT_LEN_MASK 0x07
1610
1611#define PCI_VPD_LRDT_TAG_SIZE 3
1612#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1613
e1d5bdab
MC		 1614#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1615
4067a854
MC		 1616#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1617#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1618#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1619#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1620
a2ce7662
MC		 1621/**
1622 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1623 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1624 *
1625 * Returns the extracted Large Resource Data Type length.
1626 */
1627static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1628{
1629 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1630}
1631
7ad506fa
MC		 1632/**
1633 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1634 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1635 *
1636 * Returns the extracted Small Resource Data Type length.
1637 */
1638static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1639{
1640 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1641}
1642
e1d5bdab
MC		 1643/**
1644 * pci_vpd_info_field_size - Extracts the information field length
1645 * @lrdt: Pointer to the beginning of an information field header
1646 *
1647 * Returns the extracted information field length.
1648 */
1649static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1650{
1651 return info_field[2];
1652}
1653
b55ac1b2
MC		 1654/**
1655 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1656 * @buf: Pointer to buffered vpd data
1657 * @off: The offset into the buffer at which to begin the search
1658 * @len: The length of the vpd buffer
1659 * @rdt: The Resource Data Type to search for
1660 *
1661 * Returns the index where the Resource Data Type was found or
1662 * -ENOENT otherwise.
1663 */
1664int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1665
4067a854
MC		 1666/**
1667 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1668 * @buf: Pointer to buffered vpd data
1669 * @off: The offset into the buffer at which to begin the search
1670 * @len: The length of the buffer area, relative to off, in which to search
1671 * @kw: The keyword to search for
1672 *
1673 * Returns the index where the information field keyword was found or
1674 * -ENOENT otherwise.
1675 */
1676int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1677 unsigned int len, const char *kw);
1678
98d9f30c
BH		 1679/* PCI <-> OF binding helpers */
1680#ifdef CONFIG_OF
1681struct device_node;
1682extern void pci_set_of_node(struct pci_dev *dev);
1683extern void pci_release_of_node(struct pci_dev *dev);
1684extern void pci_set_bus_of_node(struct pci_bus *bus);
1685extern void pci_release_bus_of_node(struct pci_bus *bus);
1686
1687/* Arch may override this (weak) */
1688extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1689
64099d98
BH		 1690static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1691{
1692 return pdev ? pdev->dev.of_node : NULL;
1693}
1694
ef3b4f8c
BH		 1695static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1696{
1697 return bus ? bus->dev.of_node : NULL;
1698}
1699
98d9f30c
BH		 1700#else /* CONFIG_OF */
1701static inline void pci_set_of_node(struct pci_dev *dev) { }
1702static inline void pci_release_of_node(struct pci_dev *dev) { }
1703static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1704static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1705#endif /* CONFIG_OF */
1706
eb740b5f
GS		 1707#ifdef CONFIG_EEH
1708static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1709{
1710 return pdev->dev.archdata.edev;
1711}
1712#endif
1713
166e9278
OBC		 1714/**
1715 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1716 * @pdev: the PCI device
1717 *
1718 * if the device is PCIE, return NULL
1719 * if the device isn't connected to a PCIe bridge (that is its parent is a
1720 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1721 * parent
1722 */
1723struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1724
1da177e4
LT		 1725#endif /* __KERNEL__ */
1726#endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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