projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add support for Andes NDS32:
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
35c08157
KLC		 12013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
2 Wei-Cheng Wang <cole945@gmail.com>
3
4 * nds32.h: New file for Andes NDS32.
5
594d8fa8
MF		 62013-12-07 Mike Frysinger <vapier@gentoo.org>
7
8 * bfin.h: Remove +x file mode.
9
87b8eed7
YZ		 102013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
11
12 * aarch64.h (aarch64_pstatefields): Change element type to
13 aarch64_sys_reg.
14
c9fb6e58
YZ		 152013-11-18 Renlin Li <Renlin.Li@arm.com>
16
17 * arm.h (ARM_AEXT_V7VE): New define.
18 (ARM_ARCH_V7VE): New define.
19 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
20
a203d9b7
YZ		 212013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
22
23 Revert
24
25 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
26
27 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
28 (aarch64_sys_reg_writeonly_p): Ditto.
29
75468c93
YZ		 302013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
31
32 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
33 (aarch64_sys_reg_writeonly_p): Ditto.
34
49eec193
YZ		 352013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
36
37 * aarch64.h (aarch64_sys_reg): New typedef.
38 (aarch64_sys_regs): Change to define with the new type.
39 (aarch64_sys_reg_deprecated_p): Declare.
40
68a64283
YZ		 412013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
42
43 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
44 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
45
387a82f1
CF		 462013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
47
48 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
49 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
50 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
51 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
52 For MIPS, update extension character sequences after +.
53 (ASE_MSA): New define.
54 (ASE_MSA64): New define.
55 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
56 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
57 For microMIPS, update extension character sequences after +.
58
9aff4b7a
NC		 592013-08-23 Yuri Chornoivan <yurchor@ukr.net>
60
61 PR binutils/15834
62 * i960.h: Fix typos.
63
e423441d
RS		 642013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
65
66 * mips.h: Remove references to "+I" and imm2_expr.
67
5e0dc5ba
RS		 682013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
69
70 * mips.h (M_DEXT, M_DINS): Delete.
71
0f35dbc4
RS		 722013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
73
74 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
75 (mips_optional_operand_p): New function.
76
14daeee3
RS		 772013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
78 Richard Sandiford <rdsandiford@googlemail.com>
79
80 * mips.h: Document new VU0 operand characters.
81 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
82 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
83 (OP_REG_R5900_ACC): New mips_reg_operand_types.
84 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
85 (mips_vu0_channel_mask): Declare.
86
3ccad066
RS		 872013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
88
89 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
90 (mips_int_operand_min, mips_int_operand_max): New functions.
91 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
92
fc76e730
RS		 932013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
94
95 * mips.h (mips_decode_reg_operand): New function.
96 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
97 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
98 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
99 New macros.
100 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
101 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
102 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
103 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
104 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
105 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
106 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
107 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
108 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
109 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
110 macros to cover the gaps.
111 (INSN2_MOD_SP): Replace with...
112 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
113 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
114 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
115 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
116 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
117 Delete.
118
26545944
RS		 1192013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
120
121 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
122 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
123 (MIPS16_INSN_COND_BRANCH): Delete.
124
7e8b059b
L		 1252013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
126 Kirill Yukhin <kirill.yukhin@intel.com>
127 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
128
129 * i386.h (BND_PREFIX_OPCODE): New.
130
c3c07478
RS		 1312013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
132
133 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
134 OP_SAVE_RESTORE_LIST.
135 (decode_mips16_operand): Declare.
136
ab902481
RS		 1372013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
138
139 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
140 (mips_operand, mips_int_operand, mips_mapped_int_operand)
141 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
142 (mips_pcrel_operand): New structures.
143 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
144 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
145 (decode_mips_operand, decode_micromips_operand): Declare.
146
cc537e56
RS		 1472013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
148
149 * mips.h: Document MIPS16 "I" opcode.
150
f2ae14a1
RS		 1512013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
152
153 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
154 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
155 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
156 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
157 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
158 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
159 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
160 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
161 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
162 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
163 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
164 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
165 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
166 Rename to...
167 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
168 (M_USD_AB): ...these.
169
5c324c16
RS		 1702013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
171
172 * mips.h: Remove documentation of "[" and "]". Update documentation
173 of "k" and the MDMX formats.
174
23e69e47
RS		 1752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
176
177 * mips.h: Update documentation of "+s" and "+S".
178
27c5c572
RS		 1792013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
180
181 * mips.h: Document "+i".
182
e76ff5ab
RS		 1832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
184
185 * mips.h: Remove "mi" documentation. Update "mh" documentation.
186 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
187 Delete.
188 (INSN2_WRITE_GPR_MHI): Rename to...
189 (INSN2_WRITE_GPR_MH): ...this.
190
fa7616a4
RS		 1912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
192
193 * mips.h: Remove documentation of "+D" and "+T".
194
18870af7
RS		 1952013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
196
197 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
198 Use "source" rather than "destination" for microMIPS "G".
199
833794fc
MR		 2002013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
201
202 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
203 values.
204
c3678916
RS		 2052013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
206
207 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
208
7f3c4072
CM		 2092013-06-17 Catherine Moore <clm@codesourcery.com>
210 Maciej W. Rozycki <macro@codesourcery.com>
211 Chao-Ying Fu <fu@mips.com>
212
213 * mips.h (OP_SH_EVAOFFSET): Define.
214 (OP_MASK_EVAOFFSET): Define.
215 (INSN_ASE_MASK): Delete.
216 (ASE_EVA): Define.
217 (M_CACHEE_AB, M_CACHEE_OB): New.
218 (M_LBE_OB, M_LBE_AB): New.
219 (M_LBUE_OB, M_LBUE_AB): New.
220 (M_LHE_OB, M_LHE_AB): New.
221 (M_LHUE_OB, M_LHUE_AB): New.
222 (M_LLE_AB, M_LLE_OB): New.
223 (M_LWE_OB, M_LWE_AB): New.
224 (M_LWLE_AB, M_LWLE_OB): New.
225 (M_LWRE_AB, M_LWRE_OB): New.
226 (M_PREFE_AB, M_PREFE_OB): New.
227 (M_SCE_AB, M_SCE_OB): New.
228 (M_SBE_OB, M_SBE_AB): New.
229 (M_SHE_OB, M_SHE_AB): New.
230 (M_SWE_OB, M_SWE_AB): New.
231 (M_SWLE_AB, M_SWLE_OB): New.
232 (M_SWRE_AB, M_SWRE_OB): New.
233 (MICROMIPSOP_SH_EVAOFFSET): Define.
234 (MICROMIPSOP_MASK_EVAOFFSET): Define.
235
0c8fe7cf
SL		 2362013-06-12 Sandra Loosemore <sandra@codesourcery.com>
237
238 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
239
c77c0862
RS		 2402013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
241
242 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
243
b015e599
AP		 2442013-05-09 Andrew Pinski <apinski@cavium.com>
245
246 * mips.h (OP_MASK_CODE10): Correct definition.
247 (OP_SH_CODE10): Likewise.
248 Add a comment that "+J" is used now for OP_*CODE10.
249 (INSN_ASE_MASK): Update.
250 (INSN_VIRT): New macro.
251 (INSN_VIRT64): New macro
252
13761a11
NC		 2532013-05-02 Nick Clifton <nickc@redhat.com>
254
255 * msp430.h: Add patterns for MSP430X instructions.
256
0afd1215
DM		 2572013-04-06 David S. Miller <davem@davemloft.net>
258
259 * sparc.h (F_PREFERRED): Define.
260 (F_PREF_ALIAS): Define.
261
41702d50
NC		 2622013-04-03 Nick Clifton <nickc@redhat.com>
263
264 * v850.h (V850_INVERSE_PCREL): Define.
265
e21e1a51
NC		 2662013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
267
268 PR binutils/15068
269 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
270
51dcdd4d
NC		 2712013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
272
273 PR binutils/15068
274 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
275 Add 16-bit opcodes.
276 * tic6xc-opcode-table.h: Add 16-bit insns.
277 * tic6x.h: Add support for 16-bit insns.
278
81f5558e
NC		 2792013-03-21 Michael Schewe <michael.schewe@gmx.net>
280
281 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
282 and mov.b/w/l Rs,@(d:32,ERd).
283
165546ad
NC		 2842013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
285
286 PR gas/15082
287 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
288 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
289 tic6x_operand_xregpair operand coding type.
290 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
291 opcode field, usu ORXREGD1324 for the src2 operand and remove the
292 TIC6X_FLAG_NO_CROSS.
293
795b8e6b
NC		 2942013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
295
296 PR gas/15095
297 * tic6x.h (enum tic6x_coding_method): Add
298 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
299 separately the msb and lsb of a register pair. This is needed to
300 encode the opcodes in the same way as TI assembler does.
301 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
302 and rsqrdp opcodes to use the new field coding types.
303
dd5181d5
KT		 3042013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
305
306 * arm.h (CRC_EXT_ARMV8): New constant.
307 (ARCH_CRC_ARMV8): New macro.
308
e60bb1dd
YZ		 3092013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
310
311 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
312
36591ba1
SL		 3132013-02-06 Sandra Loosemore <sandra@codesourcery.com>
314 Andrew Jenner <andrew@codesourcery.com>
315
316 Based on patches from Altera Corporation.
317
318 * nios2.h: New file.
319
e30181a5
YZ		 3202013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
321
322 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
323
0c9573f4
NC		 3242013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
325
326 PR gas/15069
327 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
328
981dc7f1
NC		 3292013-01-24 Nick Clifton <nickc@redhat.com>
330
331 * v850.h: Add e3v5 support.
332
f5555712
YZ		 3332013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
334
335 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
336
5817ffd1
PB		 3372013-01-10 Peter Bergner <bergner@vnet.ibm.com>
338
339 * ppc.h (PPC_OPCODE_POWER8): New define.
340 (PPC_OPCODE_HTM): Likewise.
341
a3c62988
NC		 3422013-01-10 Will Newton <will.newton@imgtec.com>
343
344 * metag.h: New file.
345
73335eae
NC		 3462013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
347
348 * cr16.h (make_instruction): Rename to cr16_make_instruction.
349 (match_opcode): Rename to cr16_match_opcode.
350
e407c74b
NC		 3512013-01-04 Juergen Urban <JuergenUrban@gmx.de>
352
353 * mips.h: Add support for r5900 instructions including lq and sq.
354
bab4becb
NC		 3552013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
356
357 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
358 (make_instruction,match_opcode): Added function prototypes.
359 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
360
776fc418
AM		 3612012-11-23 Alan Modra <amodra@gmail.com>
362
363 * ppc.h (ppc_parse_cpu): Update prototype.
364
f05682d4
DA		 3652012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
366
367 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
368 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
369
cfc72779
AK		 3702012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
371
372 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
373
b3e14eda
L		 3742012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
375
376 * ia64.h (ia64_opnd): Add new operand types.
377
2c63854f
DM		 3782012-08-21 David S. Miller <davem@davemloft.net>
379
380 * sparc.h (F3F4): New macro.
381
a06ea964 3822012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 383 Laurent Desnogues <laurent.desnogues@arm.com>
384 Jim MacArthur <jim.macarthur@arm.com>
385 Marcus Shawcroft <marcus.shawcroft@arm.com>
386 Nigel Stephens <nigel.stephens@arm.com>
387 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
388 Richard Earnshaw <rearnsha@arm.com>
389 Sofiane Naci <sofiane.naci@arm.com>
390 Tejas Belagod <tejas.belagod@arm.com>
391 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 392
393 * aarch64.h: New file.
394
35d0a169 3952012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 396 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 397
398 * mips.h (mips_opcode): Add the exclusions field.
399 (OPCODE_IS_MEMBER): Remove macro.
400 (cpu_is_member): New inline function.
401 (opcode_is_member): Likewise.
402
03f66e8a 4032012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 404 Catherine Moore <clm@codesourcery.com>
405 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 406
407 * mips.h: Document microMIPS DSP ASE usage.
408 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
409 microMIPS DSP ASE support.
410 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
411 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
412 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
413 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
414 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
415 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
416 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
417
9d7b4c23
MR		 4182012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
419
420 * mips.h: Fix a typo in description.
421
76e879f8
NC		 4222012-06-07 Georg-Johann Lay <avr@gjlay.de>
423
424 * avr.h: (AVR_ISA_XCH): New define.
425 (AVR_ISA_XMEGA): Use it.
426 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
427
6927f982
NC		 4282012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
429
430 * m68hc11.h: Add XGate definitions.
431 (struct m68hc11_opcode): Add xg_mask field.
432
b9c361e0
JL		 4332012-05-14 Catherine Moore <clm@codesourcery.com>
434 Maciej W. Rozycki <macro@codesourcery.com>
435 Rhonda Wittels <rhonda@codesourcery.com>
436
6927f982 437 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 438 (PPC_OP_SA): New macro.
439 (PPC_OP_SE_VLE): New macro.
440 (PPC_OP): Use a variable shift amount.
441 (powerpc_operand): Update comments.
442 (PPC_OPSHIFT_INV): New macro.
443 (PPC_OPERAND_CR): Replace with...
444 (PPC_OPERAND_CR_BIT): ...this and
445 (PPC_OPERAND_CR_REG): ...this.
446
447
f6c1a2d5
NC		 4482012-05-03 Sean Keys <skeys@ipdatasys.com>
449
450 * xgate.h: Header file for XGATE assembler.
451
ec668d69
DM		 4522012-04-27 David S. Miller <davem@davemloft.net>
453
6cda1326
DM		 454 * sparc.h: Document new arg code' )' for crypto RS3
455 immediates.
456
ec668d69
DM		 457 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
458 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
459 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
460 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
461 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
462 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
463 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
464 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
465 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
466 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
467 HWCAP_CBCOND, HWCAP_CRC32): New defines.
468
aea77599
AM		 4692012-03-10 Edmar Wienskoski <edmar@freescale.com>
470
471 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
472
1f42f8b3
AM		 4732012-02-27 Alan Modra <amodra@gmail.com>
474
475 * crx.h (cst4_map): Update declaration.
476
6f7be959
WL		 4772012-02-25 Walter Lee <walt@tilera.com>
478
479 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
480 TILEGX_OPC_LD_TLS.
481 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
482 TILEPRO_OPC_LW_TLS_SN.
483
42164a71
L		 4842012-02-08 H.J. Lu <hongjiu.lu@intel.com>
485
486 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
487 (XRELEASE_PREFIX_OPCODE): Likewise.
488
432233b3 4892011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 490 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 491
492 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
493 (INSN_OCTEON2): New macro.
494 (CPU_OCTEON2): New macro.
495 (OPCODE_IS_MEMBER): Add Octeon2.
496
dd6a37e7
AP		 4972011-11-29 Andrew Pinski <apinski@cavium.com>
498
499 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
500 (INSN_OCTEONP): New macro.
501 (CPU_OCTEONP): New macro.
502 (OPCODE_IS_MEMBER): Add Octeon+.
503 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
504
99c513f6
DD		 5052011-11-01 DJ Delorie <dj@redhat.com>
506
507 * rl78.h: New file.
508
26f85d7a
MR		 5092011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
510
511 * mips.h: Fix a typo in description.
512
9e8c70f9
DM		 5132011-09-21 David S. Miller <davem@davemloft.net>
514
515 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
516 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
517 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
518 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
519
dec0624d 5202011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 521 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 522
523 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
524 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
525 (INSN_ASE_MASK): Add the MCU bit.
526 (INSN_MCU): New macro.
527 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
528 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
529
2b0c8b40
MR		 5302011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
531
532 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
533 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
534 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
535 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
536 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
537 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
538 (INSN2_READ_GPR_MMN): Likewise.
539 (INSN2_READ_FPR_D): Change the bit used.
540 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
541 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
542 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
543 (INSN2_COND_BRANCH): Likewise.
544 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
545 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
546 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
547 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
548 (INSN2_MOD_GPR_MN): Likewise.
549
ea783ef3
DM		 5502011-08-05 David S. Miller <davem@davemloft.net>
551
552 * sparc.h: Document new format codes '4', '5', and '('.
553 (OPF_LOW4, RS3): New macros.
554
7c176fa8
MR		 5552011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
556
557 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
558 order of flags documented.
559
2309ddf2
MR		 5602011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
561
562 * mips.h: Clarify the description of microMIPS instruction
563 manipulation macros.
564 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
565
df58fc94 5662011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 567 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 568
569 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
570 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
571 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
572 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
573 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
574 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
575 (OP_MASK_RS3, OP_SH_RS3): Likewise.
576 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
577 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
578 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
579 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
580 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
581 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
582 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
583 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
584 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
585 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
586 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
587 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
588 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
589 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
590 (INSN_WRITE_GPR_S): New macro.
591 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
592 (INSN2_READ_FPR_D): Likewise.
593 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
594 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
595 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
596 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
597 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
598 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
599 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
600 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
601 (CPU_MICROMIPS): New macro.
602 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
603 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
604 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
605 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
606 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
607 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
608 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
609 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
610 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
611 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
612 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
613 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
614 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
615 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
616 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
617 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
618 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
619 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
620 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
621 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
622 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
623 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
624 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
625 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
626 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
627 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
628 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
629 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
630 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
631 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
632 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
633 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
634 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
635 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
636 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
637 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
638 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
639 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
640 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
641 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
642 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
643 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
644 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
645 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
646 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
647 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
648 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
649 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
650 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
651 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
652 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
653 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
654 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
655 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
656 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
657 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
658 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
659 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
660 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
661 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
662 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
663 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
664 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
665 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
666 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
667 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
668 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
669 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
670 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
671 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
672 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
673 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
674 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
675 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
676 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
677 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
678 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
679 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
680 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
681 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
682 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
683 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
684 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
685 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
686 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
687 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
688 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
689 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
690 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
691 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
692 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
693 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
694 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
695 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
696 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
697 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
698 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
699 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
700 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
701 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
702 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
703 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
704 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
705 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
706 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
707 (micromips_opcodes): New declaration.
708 (bfd_micromips_num_opcodes): Likewise.
709
bcd530a7
RS		 7102011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
711
712 * mips.h (INSN_TRAP): Rename to...
713 (INSN_NO_DELAY_SLOT): ... this.
714 (INSN_SYNC): Remove macro.
715
2dad5a91
EW		 7162011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
717
718 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
719 a duplicate of AVR_ISA_SPM.
720
5d73b1f1
NC		 7212011-07-01 Nick Clifton <nickc@redhat.com>
722
723 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
724
ef26d60e
MF		 7252011-06-18 Robin Getz <robin.getz@analog.com>
726
727 * bfin.h (is_macmod_signed): New func
728
8fb8dca7
MF		 7292011-06-18 Mike Frysinger <vapier@gentoo.org>
730
731 * bfin.h (is_macmod_pmove): Add missing space before func args.
732 (is_macmod_hmove): Likewise.
733
aa137e4d
NC		 7342011-06-13 Walter Lee <walt@tilera.com>
735
736 * tilegx.h: New file.
737 * tilepro.h: New file.
738
3b2f0793
PB		 7392011-05-31 Paul Brook <paul@codesourcery.com>
740
aa137e4d
NC		 741 * arm.h (ARM_ARCH_V7R_IDIV): Define.
742
7432011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
744
745 * s390.h: Replace S390_OPERAND_REG_EVEN with
746 S390_OPERAND_REG_PAIR.
747
7482011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
749
750 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 751
ac7f631b
NC		 7522011-04-18 Julian Brown <julian@codesourcery.com>
753
754 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
755
84701018
NC		 7562011-04-11 Dan McDonald <dan@wellkeeper.com>
757
758 PR gas/12296
759 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
760
8cc66334
EW		 7612011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
762
763 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
764 New instruction set flags.
765 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
766
3eebd5eb
MR		 7672011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
768
769 * mips.h (M_PREF_AB): New enum value.
770
26bb3ddd
MF		 7712011-02-12 Mike Frysinger <vapier@gentoo.org>
772
89c0d58c
MR		 773 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
774 M_IU): Define.
775 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 776
dd76fcb8
MF		 7772011-02-11 Mike Frysinger <vapier@gentoo.org>
778
779 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
780
98d23bef
BS		 7812011-02-04 Bernd Schmidt <bernds@codesourcery.com>
782
783 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
784 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
785
3c853d93
DA		 7862010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
787
788 PR gas/11395
789 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
790 "bb" entries.
791
79676006
DA		 7922010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
793
794 PR gas/11395
795 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
796
1bec78e9
RS		 7972010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
798
799 * mips.h: Update commentary after last commit.
800
98675402
RS		 8012010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
802
803 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
804 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
805 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
806
aa137e4d
NC		 8072010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
808
809 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
810
435b94a4
RS		 8112010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
812
813 * mips.h: Fix previous commit.
814
d051516a
NC		 8152010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
816
817 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
818 (INSN_LOONGSON_3A): Clear bit 31.
819
251665fc
MGD		 8202010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
821
822 PR gas/12198
823 * arm.h (ARM_AEXT_V6M_ONLY): New define.
824 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
825 (ARM_ARCH_V6M_ONLY): New define.
826
fd503541
NC		 8272010-11-11 Mingming Sun <mingm.sun@gmail.com>
828
829 * mips.h (INSN_LOONGSON_3A): Defined.
830 (CPU_LOONGSON_3A): Defined.
831 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
832
4469d2be
AM		 8332010-10-09 Matt Rice <ratmice@gmail.com>
834
835 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
836 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
837
90ec0d68
MGD		 8382010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
839
840 * arm.h (ARM_EXT_VIRT): New define.
841 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
842 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
843 Extensions.
844
eea54501 8452010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 846
eea54501
MGD		 847 * arm.h (ARM_AEXT_ADIV): New define.
848 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
849
b2a5fbdc
MGD		 8502010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
851
852 * arm.h (ARM_EXT_OS): New define.
853 (ARM_AEXT_V6SM): Likewise.
854 (ARM_ARCH_V6SM): Likewise.
855
60e5ef9f
MGD		 8562010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
857
858 * arm.h (ARM_EXT_MP): Add.
859 (ARM_ARCH_V7A_MP): Likewise.
860
73a63ccf
MF		 8612010-09-22 Mike Frysinger <vapier@gentoo.org>
862
863 * bfin.h: Declare pseudoChr structs/defines.
864
ee99860a
MF		 8652010-09-21 Mike Frysinger <vapier@gentoo.org>
866
867 * bfin.h: Strip trailing whitespace.
868
f9c7014e
DD		 8692010-07-29 DJ Delorie <dj@redhat.com>
870
871 * rx.h (RX_Operand_Type): Add TwoReg.
872 (RX_Opcode_ID): Remove ediv and ediv2.
873
93378652
DD		 8742010-07-27 DJ Delorie <dj@redhat.com>
875
876 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
877
1cd986c5
NC		 8782010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
879 Ina Pandit <ina.pandit@kpitcummins.com>
880
881 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
882 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
883 PROCESSOR_V850E2_ALL.
884 Remove PROCESSOR_V850EA support.
885 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
886 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
887 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
888 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
889 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
890 V850_OPERAND_PERCENT.
891 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
892 V850_NOT_R0.
893 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
894 and V850E_PUSH_POP
895
9a2c7088
MR		 8962010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
897
898 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
899 (MIPS16_INSN_BRANCH): Rename to...
900 (MIPS16_INSN_COND_BRANCH): ... this.
901
bdc70b4a
AM		 9022010-07-03 Alan Modra <amodra@gmail.com>
903
904 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
905 Renumber other PPC_OPCODE defines.
906
f2bae120
AM		 9072010-07-03 Alan Modra <amodra@gmail.com>
908
909 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
910
360cfc9c
AM		 9112010-06-29 Alan Modra <amodra@gmail.com>
912
913 * maxq.h: Delete file.
914
e01d869a
AM		 9152010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
916
917 * ppc.h (PPC_OPCODE_E500): Define.
918
f79e2745
CM		 9192010-05-26 Catherine Moore <clm@codesourcery.com>
920
921 * opcode/mips.h (INSN_MIPS16): Remove.
922
2462afa1
JM		 9232010-04-21 Joseph Myers <joseph@codesourcery.com>
924
925 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
926
e4e42b45
NC		 9272010-04-15 Nick Clifton <nickc@redhat.com>
928
929 * alpha.h: Update copyright notice to use GPLv3.
930 * arc.h: Likewise.
931 * arm.h: Likewise.
932 * avr.h: Likewise.
933 * bfin.h: Likewise.
934 * cgen.h: Likewise.
935 * convex.h: Likewise.
936 * cr16.h: Likewise.
937 * cris.h: Likewise.
938 * crx.h: Likewise.
939 * d10v.h: Likewise.
940 * d30v.h: Likewise.
941 * dlx.h: Likewise.
942 * h8300.h: Likewise.
943 * hppa.h: Likewise.
944 * i370.h: Likewise.
945 * i386.h: Likewise.
946 * i860.h: Likewise.
947 * i960.h: Likewise.
948 * ia64.h: Likewise.
949 * m68hc11.h: Likewise.
950 * m68k.h: Likewise.
951 * m88k.h: Likewise.
952 * maxq.h: Likewise.
953 * mips.h: Likewise.
954 * mmix.h: Likewise.
955 * mn10200.h: Likewise.
956 * mn10300.h: Likewise.
957 * msp430.h: Likewise.
958 * np1.h: Likewise.
959 * ns32k.h: Likewise.
960 * or32.h: Likewise.
961 * pdp11.h: Likewise.
962 * pj.h: Likewise.
963 * pn.h: Likewise.
964 * ppc.h: Likewise.
965 * pyr.h: Likewise.
966 * rx.h: Likewise.
967 * s390.h: Likewise.
968 * score-datadep.h: Likewise.
969 * score-inst.h: Likewise.
970 * sparc.h: Likewise.
971 * spu-insns.h: Likewise.
972 * spu.h: Likewise.
973 * tic30.h: Likewise.
974 * tic4x.h: Likewise.
975 * tic54x.h: Likewise.
976 * tic80.h: Likewise.
977 * v850.h: Likewise.
978 * vax.h: Likewise.
979
40b36596
JM		 9802010-03-25 Joseph Myers <joseph@codesourcery.com>
981
982 * tic6x-control-registers.h, tic6x-insn-formats.h,
983 tic6x-opcode-table.h, tic6x.h: New.
984
c67a084a
NC		 9852010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
986
987 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
988
466ef64f
AM		 9892010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
990
991 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
992
1319d143
L		 9932010-01-14 H.J. Lu <hongjiu.lu@intel.com>
994
995 * ia64.h (ia64_find_opcode): Remove argument name.
996 (ia64_find_next_opcode): Likewise.
997 (ia64_dis_opcode): Likewise.
998 (ia64_free_opcode): Likewise.
999 (ia64_find_dependency): Likewise.
1000
1fbb9298
DE		 10012009-11-22 Doug Evans <dje@sebabeach.org>
1002
1003 * cgen.h: Include bfd_stdint.h.
1004 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1005
ada65aa3
PB		 10062009-11-18 Paul Brook <paul@codesourcery.com>
1007
1008 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1009
9e3c6df6
PB		 10102009-11-17 Paul Brook <paul@codesourcery.com>
1011 Daniel Jacobowitz <dan@codesourcery.com>
1012
1013 * arm.h (ARM_EXT_V6_DSP): Define.
1014 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1015 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1016
0d734b5d
DD		 10172009-11-04 DJ Delorie <dj@redhat.com>
1018
1019 * rx.h (rx_decode_opcode) (mvtipl): Add.
1020 (mvtcp, mvfcp, opecp): Remove.
1021
62f3b8c8
PB		 10222009-11-02 Paul Brook <paul@codesourcery.com>
1023
1024 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1025 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1026 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1027 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1028 FPU_ARCH_NEON_VFP_V4): Define.
1029
ac1e9eca
DE		 10302009-10-23 Doug Evans <dje@sebabeach.org>
1031
1032 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1033 * cgen.h: Update. Improve multi-inclusion macro name.
1034
9fe54b1c
PB		 10352009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1036
1037 * ppc.h (PPC_OPCODE_476): Define.
1038
634b50f2
PB		 10392009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1040
1041 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1042
c7927a3c
NC		 10432009-09-29 DJ Delorie <dj@redhat.com>
1044
1045 * rx.h: New file.
1046
b961e85b
AM		 10472009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1048
1049 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1050
e0d602ec
BE		 10512009-09-21 Ben Elliston <bje@au.ibm.com>
1052
1053 * ppc.h (PPC_OPCODE_PPCA2): New.
1054
96d56e9f
NC		 10552009-09-05 Martin Thuresson <martin@mtme.org>
1056
1057 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1058
d3ce72d0
NC		 10592009-08-29 Martin Thuresson <martin@mtme.org>
1060
1061 * tic30.h (template): Rename type template to
1062 insn_template. Updated code to use new name.
1063 * tic54x.h (template): Rename type template to
1064 insn_template.
1065
824b28db
NH		 10662009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1067
1068 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1069
f865a31d
AG		 10702009-06-11 Anthony Green <green@moxielogic.com>
1071
1072 * moxie.h (MOXIE_F3_PCREL): Define.
1073 (moxie_form3_opc_info): Grow.
1074
0e7c7f11
AG		 10752009-06-06 Anthony Green <green@moxielogic.com>
1076
1077 * moxie.h (MOXIE_F1_M): Define.
1078
20135e4c
NC		 10792009-04-15 Anthony Green <green@moxielogic.com>
1080
1081 * moxie.h: Created.
1082
bcb012d3
DD		 10832009-04-06 DJ Delorie <dj@redhat.com>
1084
1085 * h8300.h: Add relaxation attributes to MOVA opcodes.
1086
69fe9ce5
AM		 10872009-03-10 Alan Modra <amodra@bigpond.net.au>
1088
1089 * ppc.h (ppc_parse_cpu): Declare.
1090
c3b7224a
NC		 10912009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1092
1093 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1094 and _IMM11 for mbitclr and mbitset.
1095 * score-datadep.h: Update dependency information.
1096
066be9f7
PB		 10972009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1098
1099 * ppc.h (PPC_OPCODE_POWER7): New.
1100
fedc618e
DE		 11012009-02-06 Doug Evans <dje@google.com>
1102
1103 * i386.h: Add comment regarding sse* insns and prefixes.
1104
52b6b6b9
JM		 11052009-02-03 Sandip Matte <sandip@rmicorp.com>
1106
1107 * mips.h (INSN_XLR): Define.
1108 (INSN_CHIP_MASK): Update.
1109 (CPU_XLR): Define.
1110 (OPCODE_IS_MEMBER): Update.
1111 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1112
35669430
DE		 11132009-01-28 Doug Evans <dje@google.com>
1114
1115 * opcode/i386.h: Add multiple inclusion protection.
1116 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1117 (EDI_REG_NUM): New macros.
1118 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1119 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1120 (REX_PREFIX_P): New macro.
35669430 1121
1cb0a767
PB		 11222009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1123
1124 * ppc.h (struct powerpc_opcode): New field "deprecated".
1125 (PPC_OPCODE_NOPOWER4): Delete.
1126
3aa3176b
TS		 11272008-11-28 Joshua Kinard <kumba@gentoo.org>
1128
1129 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1130 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1131
8e79c3df
CM		 11322008-11-18 Catherine Moore <clm@codesourcery.com>
1133
1134 * arm.h (FPU_NEON_FP16): New.
1135 (FPU_ARCH_NEON_FP16): New.
1136
de9a3e51
CF		 11372008-11-06 Chao-ying Fu <fu@mips.com>
1138
1139 * mips.h: Doucument '1' for 5-bit sync type.
1140
1ca35711
L		 11412008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1142
1143 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1144 IA64_RS_CR.
1145
9b4e5766
PB		 11462008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1147
1148 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1149
081ba1b3
AM		 11502008-07-30 Michael J. Eager <eager@eagercon.com>
1151
1152 * ppc.h (PPC_OPCODE_405): Define.
1153 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1154
fa452fa6
PB		 11552008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1156
1157 * ppc.h (ppc_cpu_t): New typedef.
1158 (struct powerpc_opcode <flags>): Use it.
1159 (struct powerpc_operand <insert, extract>): Likewise.
1160 (struct powerpc_macro <flags>): Likewise.
1161
bb35fb24
NC		 11622008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1163
1164 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1165 Update comment before MIPS16 field descriptors to mention MIPS16.
1166 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1167 BBIT.
1168 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1169 New bit masks and shift counts for cins and exts.
1170
dd3cbb7e
NC		 1171 * mips.h: Document new field descriptors +Q.
1172 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1173
d0799671
AN		 11742008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1175
9aff4b7a 1176 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1177 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1178
19a6653c
AM		 11792008-04-14 Edmar Wienskoski <edmar@freescale.com>
1180
1181 * ppc.h: (PPC_OPCODE_E500MC): New.
1182
c0f3af97
L		 11832008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1184
1185 * i386.h (MAX_OPERANDS): Set to 5.
1186 (MAX_MNEM_SIZE): Changed to 20.
1187
e210c36b
NC		 11882008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1189
1190 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1191
b1cc4aeb
PB		 11922008-03-09 Paul Brook <paul@codesourcery.com>
1193
1194 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1195
7e806470
PB		 11962008-03-04 Paul Brook <paul@codesourcery.com>
1197
1198 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1199 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1200 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1201
7b2185f9 12022008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1203 Nick Clifton <nickc@redhat.com>
1204
1205 PR 3134
1206 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1207 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1208 set.
af7329f0 1209
796d5313
NC		 12102008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1211
1212 * cr16.h (cr16_num_optab): Declared.
1213
d669d37f
NC		 12142008-02-14 Hakan Ardo <hakan@debian.org>
1215
1216 PR gas/2626
1217 * avr.h (AVR_ISA_2xxe): Define.
1218
e6429699
AN		 12192008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1220
1221 * mips.h: Update copyright.
1222 (INSN_CHIP_MASK): New macro.
1223 (INSN_OCTEON): New macro.
1224 (CPU_OCTEON): New macro.
1225 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1226
e210c36b
NC		 12272008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1228
1229 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1230
12312008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1232
1233 * avr.h (AVR_ISA_USB162): Add new opcode set.
1234 (AVR_ISA_AVR3): Likewise.
1235
350cc38d
MS		 12362007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1237
1238 * mips.h (INSN_LOONGSON_2E): New.
1239 (INSN_LOONGSON_2F): New.
1240 (CPU_LOONGSON_2E): New.
1241 (CPU_LOONGSON_2F): New.
1242 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1243
56950294
MS		 12442007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1245
1246 * mips.h (INSN_ISA*): Redefine certain values as an
1247 enumeration. Update comments.
1248 (mips_isa_table): New.
1249 (ISA_MIPS*): Redefine to match enumeration.
1250 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1251 values.
1252
c3d65c1c
BE		 12532007-08-08 Ben Elliston <bje@au.ibm.com>
1254
1255 * ppc.h (PPC_OPCODE_PPCPS): New.
1256
0fdaa005
L		 12572007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1258
1259 * m68k.h: Document j K & E.
1260
12612007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1262
1263 * cr16.h: New file for CR16 target.
1264
3896c469
AM		 12652007-05-02 Alan Modra <amodra@bigpond.net.au>
1266
1267 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1268
9a2e615a
NS		 12692007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1270
1271 * m68k.h (mcfisa_c): New.
1272 (mcfusp, mcf_mask): Adjust.
1273
b84bf58a
AM		 12742007-04-20 Alan Modra <amodra@bigpond.net.au>
1275
1276 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1277 (num_powerpc_operands): Declare.
1278 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1279 (PPC_OPERAND_PLUS1): Define.
1280
831480e9 12812007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1282
1283 * i386.h (REX_MODE64): Renamed to ...
1284 (REX_W): This.
1285 (REX_EXTX): Renamed to ...
1286 (REX_R): This.
1287 (REX_EXTY): Renamed to ...
1288 (REX_X): This.
1289 (REX_EXTZ): Renamed to ...
1290 (REX_B): This.
1291
0b1cf022
L		 12922007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1293
1294 * i386.h: Add entries from config/tc-i386.h and move tables
1295 to opcodes/i386-opc.h.
1296
d796c0ad
L		 12972007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1298
1299 * i386.h (FloatDR): Removed.
1300 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1301
30ac7323
AM		 13022007-03-01 Alan Modra <amodra@bigpond.net.au>
1303
1304 * spu-insns.h: Add soma double-float insns.
1305
8b082fb1 13062007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1307 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1308
1309 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1310 (INSN_DSPR2): Add flag for DSP R2 instructions.
1311 (M_BALIGN): New macro.
1312
4eed87de
AM		 13132007-02-14 Alan Modra <amodra@bigpond.net.au>
1314
1315 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1316 and Seg3ShortFrom with Shortform.
1317
fda592e8
L		 13182007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1319
1320 PR gas/4027
1321 * i386.h (i386_optab): Put the real "test" before the pseudo
1322 one.
1323
3bdcfdf4
KH		 13242007-01-08 Kazu Hirata <kazu@codesourcery.com>
1325
1326 * m68k.h (m68010up): OR fido_a.
1327
9840d27e
KH		 13282006-12-25 Kazu Hirata <kazu@codesourcery.com>
1329
1330 * m68k.h (fido_a): New.
1331
c629cdac
KH		 13322006-12-24 Kazu Hirata <kazu@codesourcery.com>
1333
1334 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1335 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1336 values.
1337
b7d9ef37
L		 13382006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1339
1340 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1341
b138abaa
NC		 13422006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1343
1344 * score-inst.h (enum score_insn_type): Add Insn_internal.
1345
e9f53129
AM		 13462006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1347 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1348 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1349 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1350 Alan Modra <amodra@bigpond.net.au>
1351
1352 * spu-insns.h: New file.
1353 * spu.h: New file.
1354
ede602d7
AM		 13552006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1356
1357 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1358
7918206c
MM		 13592006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1360
e4e42b45 1361 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1362 in amdfam10 architecture.
1363
ef05d495
L		 13642006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1365
1366 * i386.h: Replace CpuMNI with CpuSSSE3.
1367
2d447fca 13682006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1369 Joseph Myers <joseph@codesourcery.com>
1370 Ian Lance Taylor <ian@wasabisystems.com>
1371 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1372
1373 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1374
1c0d3aa6
NC		 13752006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1376
1377 * score-datadep.h: New file.
1378 * score-inst.h: New file.
1379
c2f0420e
L		 13802006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1381
1382 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1383 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1384 movdq2q and movq2dq.
1385
050dfa73
MM		 13862006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1387 Michael Meissner <michael.meissner@amd.com>
1388
1389 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1390
15965411
L		 13912006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1392
1393 * i386.h (i386_optab): Add "nop" with memory reference.
1394
46e883c5
L		 13952006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1396
1397 * i386.h (i386_optab): Update comment for 64bit NOP.
1398
9622b051
AM		 13992006-06-06 Ben Elliston <bje@au.ibm.com>
1400 Anton Blanchard <anton@samba.org>
1401
1402 * ppc.h (PPC_OPCODE_POWER6): Define.
1403 Adjust whitespace.
1404
a9e24354
TS		 14052006-06-05 Thiemo Seufer <ths@mips.com>
1406
e4e42b45 1407 * mips.h: Improve description of MT flags.
a9e24354 1408
a596001e
RS		 14092006-05-25 Richard Sandiford <richard@codesourcery.com>
1410
1411 * m68k.h (mcf_mask): Define.
1412
d43b4baf 14132006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1414 David Ung <davidu@mips.com>
d43b4baf
TS		 1415
1416 * mips.h (enum): Add macro M_CACHE_AB.
1417
39a7806d 14182006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1419 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1420 David Ung <davidu@mips.com>
1421
1422 * mips.h: Add INSN_SMARTMIPS define.
1423
9bcd4f99 14242006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1425 David Ung <davidu@mips.com>
9bcd4f99
TS		 1426
1427 * mips.h: Defines udi bits and masks. Add description of
1428 characters which may appear in the args field of udi
1429 instructions.
1430
ef0ee844
TS		 14312006-04-26 Thiemo Seufer <ths@networkno.de>
1432
1433 * mips.h: Improve comments describing the bitfield instruction
1434 fields.
1435
f7675147
L		 14362006-04-26 Julian Brown <julian@codesourcery.com>
1437
1438 * arm.h (FPU_VFP_EXT_V3): Define constant.
1439 (FPU_NEON_EXT_V1): Likewise.
1440 (FPU_VFP_HARD): Update.
1441 (FPU_VFP_V3): Define macro.
1442 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1443
ef0ee844 14442006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1445
1446 * avr.h (AVR_ISA_PWMx): New.
1447
2da12c60
NS		 14482006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1449
1450 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1451 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1452 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1453 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1454 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1455
0715c387
PB		 14562006-03-10 Paul Brook <paul@codesourcery.com>
1457
1458 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1459
34bdd094
DA		 14602006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1461
1462 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1463 first. Correct mask of bb "B" opcode.
1464
331d2d0d
L		 14652006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1466
1467 * i386.h (i386_optab): Support Intel Merom New Instructions.
1468
62b3e311
PB		 14692006-02-24 Paul Brook <paul@codesourcery.com>
1470
1471 * arm.h: Add V7 feature bits.
1472
59cf82fe
L		 14732006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1474
1475 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1476
e74cfd16
PB		 14772006-01-31 Paul Brook <paul@codesourcery.com>
1478 Richard Earnshaw <rearnsha@arm.com>
1479
1480 * arm.h: Use ARM_CPU_FEATURE.
1481 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1482 (arm_feature_set): Change to a structure.
1483 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1484 ARM_FEATURE): New macros.
1485
5b3f8a92
HPN		 14862005-12-07 Hans-Peter Nilsson <hp@axis.com>
1487
1488 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1489 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1490 (ADD_PC_INCR_OPCODE): Don't define.
1491
cb712a9e
L		 14922005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1493
1494 PR gas/1874
1495 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1496
0499d65b
TS		 14972005-11-14 David Ung <davidu@mips.com>
1498
1499 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1500 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1501 save/restore encoding of the args field.
1502
ea5ca089
DB		 15032005-10-28 Dave Brolley <brolley@redhat.com>
1504
1505 Contribute the following changes:
1506 2005-02-16 Dave Brolley <brolley@redhat.com>
1507
1508 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1509 cgen_isa_mask_* to cgen_bitset_*.
1510 * cgen.h: Likewise.
1511
16175d96
DB		 1512 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1513
1514 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1515 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1516 (CGEN_CPU_TABLE): Make isas a ponter.
1517
1518 2003-09-29 Dave Brolley <brolley@redhat.com>
1519
1520 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1521 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1522 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1523
1524 2002-12-13 Dave Brolley <brolley@redhat.com>
1525
1526 * cgen.h (symcat.h): #include it.
1527 (cgen-bitset.h): #include it.
1528 (CGEN_ATTR_VALUE_TYPE): Now a union.
1529 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1530 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1531 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1532 * cgen-bitset.h: New file.
1533
3c9b82ba
NC		 15342005-09-30 Catherine Moore <clm@cm00re.com>
1535
1536 * bfin.h: New file.
1537
6a2375c6
JB		 15382005-10-24 Jan Beulich <jbeulich@novell.com>
1539
1540 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1541 indirect operands.
1542
c06a12f8
DA		 15432005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1544
1545 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1546 Add FLAG_STRICT to pa10 ftest opcode.
1547
4d443107
DA		 15482005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1549
1550 * hppa.h (pa_opcodes): Remove lha entries.
1551
f0a3b40f
DA		 15522005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1553
1554 * hppa.h (FLAG_STRICT): Revise comment.
1555 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1556 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1557 entries for "fdc".
1558
e210c36b
NC		 15592005-09-30 Catherine Moore <clm@cm00re.com>
1560
1561 * bfin.h: New file.
1562
1b7e1362
DA		 15632005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1564
1565 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1566
089b39de
CF		 15672005-09-06 Chao-ying Fu <fu@mips.com>
1568
1569 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1570 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1571 define.
1572 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1573 (INSN_ASE_MASK): Update to include INSN_MT.
1574 (INSN_MT): New define for MT ASE.
1575
93c34b9b
CF		 15762005-08-25 Chao-ying Fu <fu@mips.com>
1577
1578 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1579 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1580 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1581 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1582 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1583 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1584 instructions.
1585 (INSN_DSP): New define for DSP ASE.
1586
848cf006
AM		 15872005-08-18 Alan Modra <amodra@bigpond.net.au>
1588
1589 * a29k.h: Delete.
1590
36ae0db3
DJ		 15912005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1592
1593 * ppc.h (PPC_OPCODE_E300): Define.
1594
8c929562
MS		 15952005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1596
1597 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1598
f7b8cccc
DA		 15992005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1600
1601 PR gas/336
1602 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1603 and pitlb.
1604
8b5328ac
JB		 16052005-07-27 Jan Beulich <jbeulich@novell.com>
1606
1607 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1608 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1609 Add movq-s as 64-bit variants of movd-s.
1610
f417d200
DA		 16112005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1612
18b3bdfc
DA		 1613 * hppa.h: Fix punctuation in comment.
1614
f417d200
DA		 1615 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1616 implicit space-register addressing. Set space-register bits on opcodes
1617 using implicit space-register addressing. Add various missing pa20
1618 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1619 space-register addressing. Use "fE" instead of "fe" in various
1620 fstw opcodes.
1621
9a145ce6
JB		 16222005-07-18 Jan Beulich <jbeulich@novell.com>
1623
1624 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1625
90700ea2
L		 16262007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1627
1628 * i386.h (i386_optab): Support Intel VMX Instructions.
1629
48f130a8
DA		 16302005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1631
1632 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1633
30123838
JB		 16342005-07-05 Jan Beulich <jbeulich@novell.com>
1635
1636 * i386.h (i386_optab): Add new insns.
1637
47b0e7ad
NC		 16382005-07-01 Nick Clifton <nickc@redhat.com>
1639
1640 * sparc.h: Add typedefs to structure declarations.
1641
b300c311
L		 16422005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1643
1644 PR 1013
1645 * i386.h (i386_optab): Update comments for 64bit addressing on
1646 mov. Allow 64bit addressing for mov and movq.
1647
2db495be
DA		 16482005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1649
1650 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1651 respectively, in various floating-point load and store patterns.
1652
caa05036
DA		 16532005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1654
1655 * hppa.h (FLAG_STRICT): Correct comment.
1656 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1657 PA 2.0 mneumonics when equivalent. Entries with cache control
1658 completers now require PA 1.1. Adjust whitespace.
1659
f4411256
AM		 16602005-05-19 Anton Blanchard <anton@samba.org>
1661
1662 * ppc.h (PPC_OPCODE_POWER5): Define.
1663
e172dbf8
NC		 16642005-05-10 Nick Clifton <nickc@redhat.com>
1665
1666 * Update the address and phone number of the FSF organization in
1667 the GPL notices in the following files:
1668 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1669 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1670 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1671 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1672 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1673 tic54x.h, tic80.h, v850.h, vax.h
1674
e44823cf
JB		 16752005-05-09 Jan Beulich <jbeulich@novell.com>
1676
1677 * i386.h (i386_optab): Add ht and hnt.
1678
791fe849
MK		 16792005-04-18 Mark Kettenis <kettenis@gnu.org>
1680
1681 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1682 Add xcrypt-ctr. Provide aliases without hyphens.
1683
faa7ef87
L		 16842005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1685
a63027e5
L		 1686 Moved from ../ChangeLog
1687
faa7ef87
L		 1688 2005-04-12 Paul Brook <paul@codesourcery.com>
1689 * m88k.h: Rename psr macros to avoid conflicts.
1690
1691 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1692 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1693 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1694 and ARM_ARCH_V6ZKT2.
1695
1696 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1697 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1698 Remove redundant instruction types.
1699 (struct argument): X_op - new field.
1700 (struct cst4_entry): Remove.
1701 (no_op_insn): Declare.
1702
1703 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1704 * crx.h (enum argtype): Rename types, remove unused types.
1705
1706 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1707 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1708 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1709 (enum operand_type): Rearrange operands, edit comments.
1710 replace us<N> with ui<N> for unsigned immediate.
1711 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1712 displacements (respectively).
1713 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1714 (instruction type): Add NO_TYPE_INS.
1715 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1716 (operand_entry): New field - 'flags'.
1717 (operand flags): New.
1718
1719 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1720 * crx.h (operand_type): Remove redundant types i3, i4,
1721 i5, i8, i12.
1722 Add new unsigned immediate types us3, us4, us5, us16.
1723
bc4bd9ab
MK		 17242005-04-12 Mark Kettenis <kettenis@gnu.org>
1725
1726 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1727 adjust them accordingly.
1728
373ff435
JB		 17292005-04-01 Jan Beulich <jbeulich@novell.com>
1730
1731 * i386.h (i386_optab): Add rdtscp.
1732
4cc91dba
L		 17332005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1734
1735 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1736 between memory and segment register. Allow movq for moving between
1737 general-purpose register and segment register.
4cc91dba 1738
9ae09ff9
JB		 17392005-02-09 Jan Beulich <jbeulich@novell.com>
1740
1741 PR gas/707
1742 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1743 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1744 fnstsw.
1745
638e7a64
NS		 17462006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1747
1748 * m68k.h (m68008, m68ec030, m68882): Remove.
1749 (m68k_mask): New.
1750 (cpu_m68k, cpu_cf): New.
1751 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1752 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1753
90219bd0
AO		 17542005-01-25 Alexandre Oliva <aoliva@redhat.com>
1755
1756 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1757 * cgen.h (enum cgen_parse_operand_type): Add
1758 CGEN_PARSE_OPERAND_SYMBOLIC.
1759
239cb185
FF		 17602005-01-21 Fred Fish <fnf@specifixinc.com>
1761
1762 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1763 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1764 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1765
dc9a9f39
FF		 17662005-01-19 Fred Fish <fnf@specifixinc.com>
1767
1768 * mips.h (struct mips_opcode): Add new pinfo2 member.
1769 (INSN_ALIAS): New define for opcode table entries that are
1770 specific instances of another entry, such as 'move' for an 'or'
1771 with a zero operand.
1772 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1773 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1774
98e7aba8
ILT		 17752004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1776
1777 * mips.h (CPU_RM9000): Define.
1778 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1779
37edbb65
JB		 17802004-11-25 Jan Beulich <jbeulich@novell.com>
1781
1782 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1783 to/from test registers are illegal in 64-bit mode. Add missing
1784 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1785 (previously one had to explicitly encode a rex64 prefix). Re-enable
1786 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1787 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1788
17892004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1790
1791 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1792 available only with SSE2. Change the MMX additions introduced by SSE
1793 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1794 instructions by their now designated identifier (since combining i686
1795 and 3DNow! does not really imply 3DNow!A).
1796
f5c7edf4
AM		 17972004-11-19 Alan Modra <amodra@bigpond.net.au>
1798
1799 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1800 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1801
7499d566
NC		 18022004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1803 Vineet Sharma <vineets@noida.hcltech.com>
1804
1805 * maxq.h: New file: Disassembly information for the maxq port.
1806
bcb9eebe
L		 18072004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1808
1809 * i386.h (i386_optab): Put back "movzb".
1810
94bb3d38
HPN		 18112004-11-04 Hans-Peter Nilsson <hp@axis.com>
1812
1813 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1814 comments. Remove member cris_ver_sim. Add members
1815 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1816 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1817 (struct cris_support_reg, struct cris_cond15): New types.
1818 (cris_conds15): Declare.
1819 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1820 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1821 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1822 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1823 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1824 SIZE_FIELD_UNSIGNED.
1825
37edbb65 18262004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1827
1828 * i386.h (sldx_Suf): Remove.
1829 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1830 (q_FP): Define, implying no REX64.
1831 (x_FP, sl_FP): Imply FloatMF.
1832 (i386_optab): Split reg and mem forms of moving from segment registers
1833 so that the memory forms can ignore the 16-/32-bit operand size
1834 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1835 all non-floating-point instructions. Unite 32- and 64-bit forms of
1836 movsx, movzx, and movd. Adjust floating point operations for the above
1837 changes to the *FP macros. Add DefaultSize to floating point control
1838 insns operating on larger memory ranges. Remove left over comments
1839 hinting at certain insns being Intel-syntax ones where the ones
1840 actually meant are already gone.
1841
48c9f030
NC		 18422004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1843
1844 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1845 instruction type.
1846
0dd132b6
NC		 18472004-09-30 Paul Brook <paul@codesourcery.com>
1848
1849 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1850 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1851
23794b24
MM		 18522004-09-11 Theodore A. Roth <troth@openavr.org>
1853
1854 * avr.h: Add support for
1855 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1856
2a309db0
AM		 18572004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1858
1859 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1860
b18c562e
NC		 18612004-08-24 Dmitry Diky <diwil@spec.ru>
1862
1863 * msp430.h (msp430_opc): Add new instructions.
1864 (msp430_rcodes): Declare new instructions.
1865 (msp430_hcodes): Likewise..
1866
45d313cd
NC		 18672004-08-13 Nick Clifton <nickc@redhat.com>
1868
1869 PR/301
1870 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1871 processors.
1872
30d1c836
ML		 18732004-08-30 Michal Ludvig <mludvig@suse.cz>
1874
1875 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1876
9a45f1c2
L		 18772004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1878
1879 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1880
543613e9
NC		 18812004-07-21 Jan Beulich <jbeulich@novell.com>
1882
1883 * i386.h: Adjust instruction descriptions to better match the
1884 specification.
1885
b781e558
RE		 18862004-07-16 Richard Earnshaw <rearnsha@arm.com>
1887
1888 * arm.h: Remove all old content. Replace with architecture defines
1889 from gas/config/tc-arm.c.
1890
8577e690
AS		 18912004-07-09 Andreas Schwab <schwab@suse.de>
1892
1893 * m68k.h: Fix comment.
1894
1fe1f39c
NC		 18952004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1896
1897 * crx.h: New file.
1898
1d9f512f
AM		 18992004-06-24 Alan Modra <amodra@bigpond.net.au>
1900
1901 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1902
be8c092b
NC		 19032004-05-24 Peter Barada <peter@the-baradas.com>
1904
1905 * m68k.h: Add 'size' to m68k_opcode.
1906
6b6e92f4
NC		 19072004-05-05 Peter Barada <peter@the-baradas.com>
1908
1909 * m68k.h: Switch from ColdFire chip name to core variant.
1910
19112004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1912
1913 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1914 descriptions for new EMAC cases.
1915 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1916 handle Motorola MAC syntax.
1917 Allow disassembly of ColdFire V4e object files.
1918
fdd12ef3
AM		 19192004-03-16 Alan Modra <amodra@bigpond.net.au>
1920
1921 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1922
3922a64c
L		 19232004-03-12 Jakub Jelinek <jakub@redhat.com>
1924
1925 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1926
1f45d988
ML		 19272004-03-12 Michal Ludvig <mludvig@suse.cz>
1928
1929 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1930
0f10071e
ML		 19312004-03-12 Michal Ludvig <mludvig@suse.cz>
1932
1933 * i386.h (i386_optab): Added xstore/xcrypt insns.
1934
3255318a
NC		 19352004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1936
1937 * h8300.h (32bit ldc/stc): Add relaxing support.
1938
ca9a79a1 19392004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1940
ca9a79a1
NC		 1941 * h8300.h (BITOP): Pass MEMRELAX flag.
1942
875a0b14
NC		 19432004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1944
1945 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1946 except for the H8S.
252b5132 1947
c9e214e5 1948For older changes see ChangeLog-9103
252b5132 1949\f
752937aa
NC		 1950Copyright (C) 2004-2012 Free Software Foundation, Inc.
1951
1952Copying and distribution of this file, with or without modification,
1953are permitted in any medium without royalty provided the copyright
1954notice and this notice are preserved.
1955
252b5132 1956Local Variables:
c9e214e5
AM		 1957mode: change-log
1958left-margin: 8
1959fill-column: 74
252b5132
RH		 1960version-control: never
1961End:
GDB Binutils - Deliverables
This page took 0.912267 seconds and 4 git commands to generate.