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New ARC implementation.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
886a2506
NC		 12015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
2 Cupertino Miranda <cmiranda@synopsys.com>
3
4 * arc-func.h: New file.
5 * arc.h: Likewise.
6
e141d84e
YQ		 72015-10-02 Yao Qi <yao.qi@linaro.org>
8
9 * aarch64.h (aarch64_zero_register_p): Move the declaration
10 to column one.
11
36f4aab1
YQ		 122015-10-02 Yao Qi <yao.qi@linaro.org>
13
14 * aarch64.h (aarch64_decode_insn): Declare it.
15
7ecc513a
DV		 162015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
17
18 * s390.h (S390_INSTR_FLAG_HTM): New flag.
19 (S390_INSTR_FLAG_VX): New flag.
20 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
21
b6518b38
NC		 222015-09-23 Nick Clifton <nickc@redhat.com>
23
24 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
25 shifting.
26
f04265ec
NC		 272015-09-22 Nick Clifton <nickc@redhat.com>
28
29 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
30
7bdf96ef
NC		 312015-09-09 Daniel Santos <daniel.santos@pobox.com>
32
33 * visium.h (gen_reg_table): Make static.
34 (fp_reg_table): Likewise.
35 (cc_table): Likewise.
36
f33026a9
MW		 372015-07-20 Matthew Wahab <matthew.wahab@arm.com>
38
39 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
40 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
41 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
42 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
43
ef5a96d5
AM		 442015-07-03 Alan Modra <amodra@gmail.com>
45
46 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
47
c8c8175b
SL		 482015-07-01 Sandra Loosemore <sandra@codesourcery.com>
49 Cesar Philippidis <cesar@codesourcery.com>
50
51 * nios2.h (enum iw_format_type): Add R2 formats.
52 (enum overflow_type): Add signed_immed12_overflow and
53 enumeration_overflow for R2.
54 (struct nios2_opcode): Document new argument letters for R2.
55 (REG_3BIT, REG_LDWM, REG_POP): Define.
56 (includes): Include nios2r2.h.
57 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
58 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
59 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
60 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
61 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
62 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
63 Declare.
64 * nios2r2.h: New file.
65
11a0cf2e
PB		 662015-06-19 Peter Bergner <bergner@vnet.ibm.com>
67
68 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
69 (ppc_optional_operand_value): New inline function.
70
88f0ea34
MW		 712015-06-04 Matthew Wahab <matthew.wahab@arm.com>
72
73 * aarch64.h (AARCH64_V8_1): New.
74
a5932920
MW		 752015-06-03 Matthew Wahab <matthew.wahab@arm.com>
76
77 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
78 (ARM_ARCH_V8_1A): New.
79 (ARM_ARCH_V8_1A_FP): New.
80 (ARM_ARCH_V8_1A_SIMD): New.
81 (ARM_ARCH_V8_1A_CRYPTOV1): New.
82 (ARM_FEATURE_CORE): New.
83
ddfded2f
MW		 842015-06-02 Matthew Wahab <matthew.wahab@arm.com>
85
86 * arm.h (ARM_EXT2_PAN): New.
87 (ARM_FEATURE_CORE_HIGH): New.
88
1af1dd51
MW		 892015-06-02 Matthew Wahab <matthew.wahab@arm.com>
90
91 * arm.h (ARM_FEATURE_ALL): New.
92
9e1f0fa7
MW		 932015-06-02 Matthew Wahab <matthew.wahab@arm.com>
94
95 * aarch64.h (AARCH64_FEATURE_RDMA): New.
96
290806fd
MW		 972015-06-02 Matthew Wahab <matthew.wahab@arm.com>
98
99 * aarch64.h (AARCH64_FEATURE_LOR): New.
100
f21cce2c
MW		 1012015-06-01 Matthew Wahab <matthew.wahab@arm.com>
102
103 * aarch64.h (AARCH64_FEATURE_PAN): New.
104 (aarch64_sys_reg_supported_p): Declare.
105 (aarch64_pstatefield_supported_p): Declare.
106
0952813b
DD		 1072015-04-30 DJ Delorie <dj@redhat.com>
108
109 * rl78.h (RL78_Dis_Isa): New.
110 (rl78_decode_opcode): Add ISA parameter.
111
823d2571
TG		 1122015-03-24 Terry Guo <terry.guo@arm.com>
113
114 * arm.h (arm_feature_set): Extended to provide more available bits.
115 (ARM_ANY): Updated to follow above new definition.
116 (ARM_CPU_HAS_FEATURE): Likewise.
117 (ARM_CPU_IS_ANY): Likewise.
118 (ARM_MERGE_FEATURE_SETS): Likewise.
119 (ARM_CLEAR_FEATURE): Likewise.
120 (ARM_FEATURE): Likewise.
121 (ARM_FEATURE_COPY): New macro.
122 (ARM_FEATURE_EQUAL): Likewise.
123 (ARM_FEATURE_ZERO): Likewise.
124 (ARM_FEATURE_CORE_EQUAL): Likewise.
125 (ARM_FEATURE_LOW): Likewise.
126 (ARM_FEATURE_CORE_LOW): Likewise.
127 (ARM_FEATURE_CORE_COPROC): Likewise.
128
f63c1776
PA		 1292015-02-19 Pedro Alves <palves@redhat.com>
130
131 * cgen.h [__cplusplus]: Wrap in extern "C".
132 * msp430-decode.h [__cplusplus]: Likewise.
133 * nios2.h [__cplusplus]: Likewise.
134 * rl78.h [__cplusplus]: Likewise.
135 * rx.h [__cplusplus]: Likewise.
136 * tilegx.h [__cplusplus]: Likewise.
137
3f8107ab
AM		 1382015-01-28 James Bowman <james.bowman@ftdichip.com>
139
140 * ft32.h: New file.
141
1e2e8c52
AK		 1422015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
143
144 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
145
b90efa5b
AM		 1462015-01-01 Alan Modra <amodra@gmail.com>
147
148 Update year range in copyright notice of all files.
149
bffb6004
AG		 1502014-12-27 Anthony Green <green@moxielogic.com>
151
152 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
153 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
154
1945cfa5
EB		 1552014-12-06 Eric Botcazou <ebotcazou@adacore.com>
156
157 * visium.h: New file.
158
d306ce58
SL		 1592014-11-28 Sandra Loosemore <sandra@codesourcery.com>
160
161 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
162 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
163 (NIOS2_INSN_OPTARG): Renumber.
164
b4714c7c
SL		 1652014-11-06 Sandra Loosemore <sandra@codesourcery.com>
166
167 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
168 declaration. Fix obsolete comment.
169
96ba4233
SL		 1702014-10-23 Sandra Loosemore <sandra@codesourcery.com>
171
172 * nios2.h (enum iw_format_type): New.
173 (struct nios2_opcode): Update comments. Add size and format fields.
174 (NIOS2_INSN_OPTARG): New.
175 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
176 (struct nios2_reg): Add regtype field.
177 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
178 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
179 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
180 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
181 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
182 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
183 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
184 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
185 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
186 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
187 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
188 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
189 (OP_MASK_OP, OP_SH_OP): Delete.
190 (OP_MASK_IOP, OP_SH_IOP): Delete.
191 (OP_MASK_IRD, OP_SH_IRD): Delete.
192 (OP_MASK_IRT, OP_SH_IRT): Delete.
193 (OP_MASK_IRS, OP_SH_IRS): Delete.
194 (OP_MASK_ROP, OP_SH_ROP): Delete.
195 (OP_MASK_RRD, OP_SH_RRD): Delete.
196 (OP_MASK_RRT, OP_SH_RRT): Delete.
197 (OP_MASK_RRS, OP_SH_RRS): Delete.
198 (OP_MASK_JOP, OP_SH_JOP): Delete.
199 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
200 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
201 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
202 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
203 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
204 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
205 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
206 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
207 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
208 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
209 (OP_MASK_<insn>, OP_MASK): Delete.
210 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
211 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
212 Include nios2r1.h to define new instruction opcode constants
213 and accessors.
214 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
215 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
216 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
217 (NUMOPCODES, NUMREGISTERS): Delete.
218 * nios2r1.h: New file.
219
0b6be415
JM		 2202014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
221
222 * sparc.h (HWCAP2_VIS3B): Documentation improved.
223
3d68f91c
JM		 2242014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
225
226 * sparc.h (sparc_opcode): new field `hwcaps2'.
227 (HWCAP2_FJATHPLUS): New define.
228 (HWCAP2_VIS3B): Likewise.
229 (HWCAP2_ADP): Likewise.
230 (HWCAP2_SPARC5): Likewise.
231 (HWCAP2_MWAIT): Likewise.
232 (HWCAP2_XMPMUL): Likewise.
233 (HWCAP2_XMONT): Likewise.
234 (HWCAP2_NSEC): Likewise.
235 (HWCAP2_FJATHHPC): Likewise.
236 (HWCAP2_FJDES): Likewise.
237 (HWCAP2_FJAES): Likewise.
238 Document the new operand kind `{', corresponding to the mcdper
239 ancillary state register.
240 Document the new operand kind }, which represents frsd floating
241 point registers (double precision) which must be the same than
242 frs1 in its containing instruction.
243
40c7a7cb
KLC		 2442014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
245
72f4393d 246 * nds32.h: Add new opcode declaration.
40c7a7cb 247
7361da2c
AB		 2482014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
249 Matthew Fortune <matthew.fortune@imgtec.com>
250
251 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
252 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
253 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
254 +I, +O, +R, +:, +\, +", +;
255 (mips_check_prev_operand): New struct.
256 (INSN2_FORBIDDEN_SLOT): New define.
257 (INSN_ISA32R6): New define.
258 (INSN_ISA64R6): New define.
259 (INSN_UPTO32R6): New define.
260 (INSN_UPTO64R6): New define.
261 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
262 (ISA_MIPS32R6): New define.
263 (ISA_MIPS64R6): New define.
264 (CPU_MIPS32R6): New define.
265 (CPU_MIPS64R6): New define.
266 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
267
ee804238
JW		 2682014-09-03 Jiong Wang <jiong.wang@arm.com>
269
270 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
271 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
272 (aarch64_insn_class): Add lse_atomic.
273 (F_LSE_SZ): New field added.
274 (opcode_has_special_coder): Recognize F_LSE_SZ.
275
5575639b
MR		 2762014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
277
278 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
279 over to `+J'.
280
43885403
MF		 2812014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
282
283 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
284 (INSN_LOAD_COPROC): New define.
285 (INSN_COPROC_MOVE_DELAY): Rename to...
286 (INSN_COPROC_MOVE): New define.
287
f36e8886 2882014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 289 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
290 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
291 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 292
293 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
294 (AVR_ISA_2xxxa): Define ISA without LPM.
295 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
296 Add doc for contraint used in 16 bit lds/sts.
297 Adjust ISA group for icall, ijmp, pop and push.
298 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
299
00b32ff2
NC		 3002014-05-19 Nick Clifton <nickc@redhat.com>
301
302 * msp430.h (struct msp430_operand_s): Add vshift field.
303
ae52f483
AB		 3042014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
305
306 * mips.h (INSN_ISA_MASK): Updated.
307 (INSN_ISA32R3): New define.
308 (INSN_ISA32R5): New define.
309 (INSN_ISA64R3): New define.
310 (INSN_ISA64R5): New define.
311 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
312 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
313 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
314 mips64r5.
315 (INSN_UPTO32R3): New define.
316 (INSN_UPTO32R5): New define.
317 (INSN_UPTO64R3): New define.
318 (INSN_UPTO64R5): New define.
319 (ISA_MIPS32R3): New define.
320 (ISA_MIPS32R5): New define.
321 (ISA_MIPS64R3): New define.
322 (ISA_MIPS64R5): New define.
323 (CPU_MIPS32R3): New define.
324 (CPU_MIPS32R5): New define.
325 (CPU_MIPS64R3): New define.
326 (CPU_MIPS64R5): New define.
327
3efe9ec5
RS		 3282014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
329
330 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
331
73589c9d
CS		 3322014-04-22 Christian Svensson <blue@cmd.nu>
333
334 * or32.h: Delete.
335
4b95cf5c
AM		 3362014-03-05 Alan Modra <amodra@gmail.com>
337
338 Update copyright years.
339
e269fea7
AB		 3402013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
341
342 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
343 microMIPS.
344
35c08157
KLC		 3452013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
346 Wei-Cheng Wang <cole945@gmail.com>
347
348 * nds32.h: New file for Andes NDS32.
349
594d8fa8
MF		 3502013-12-07 Mike Frysinger <vapier@gentoo.org>
351
352 * bfin.h: Remove +x file mode.
353
87b8eed7
YZ		 3542013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
355
356 * aarch64.h (aarch64_pstatefields): Change element type to
357 aarch64_sys_reg.
358
c9fb6e58
YZ		 3592013-11-18 Renlin Li <Renlin.Li@arm.com>
360
361 * arm.h (ARM_AEXT_V7VE): New define.
362 (ARM_ARCH_V7VE): New define.
363 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
364
a203d9b7
YZ		 3652013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
366
367 Revert
368
369 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
370
371 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
372 (aarch64_sys_reg_writeonly_p): Ditto.
373
75468c93
YZ		 3742013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
375
376 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
377 (aarch64_sys_reg_writeonly_p): Ditto.
378
49eec193
YZ		 3792013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
380
381 * aarch64.h (aarch64_sys_reg): New typedef.
382 (aarch64_sys_regs): Change to define with the new type.
383 (aarch64_sys_reg_deprecated_p): Declare.
384
68a64283
YZ		 3852013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
386
387 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
388 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
389
387a82f1
CF		 3902013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
391
392 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
393 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
394 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
395 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
396 For MIPS, update extension character sequences after +.
397 (ASE_MSA): New define.
398 (ASE_MSA64): New define.
399 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
400 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
401 For microMIPS, update extension character sequences after +.
402
9aff4b7a
NC		 4032013-08-23 Yuri Chornoivan <yurchor@ukr.net>
404
405 PR binutils/15834
406 * i960.h: Fix typos.
407
e423441d
RS		 4082013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
409
410 * mips.h: Remove references to "+I" and imm2_expr.
411
5e0dc5ba
RS		 4122013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
413
414 * mips.h (M_DEXT, M_DINS): Delete.
415
0f35dbc4
RS		 4162013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
417
418 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
419 (mips_optional_operand_p): New function.
420
14daeee3
RS		 4212013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
422 Richard Sandiford <rdsandiford@googlemail.com>
423
424 * mips.h: Document new VU0 operand characters.
425 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
426 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
427 (OP_REG_R5900_ACC): New mips_reg_operand_types.
428 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
429 (mips_vu0_channel_mask): Declare.
430
3ccad066
RS		 4312013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
432
433 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
434 (mips_int_operand_min, mips_int_operand_max): New functions.
435 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
436
fc76e730
RS		 4372013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
438
439 * mips.h (mips_decode_reg_operand): New function.
440 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
441 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
442 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
443 New macros.
444 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
445 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
446 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
447 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
448 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
449 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
450 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
451 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
452 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
453 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
454 macros to cover the gaps.
455 (INSN2_MOD_SP): Replace with...
456 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
457 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
458 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
459 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
460 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
461 Delete.
462
26545944
RS		 4632013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
464
465 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
466 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
467 (MIPS16_INSN_COND_BRANCH): Delete.
468
7e8b059b
L		 4692013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
470 Kirill Yukhin <kirill.yukhin@intel.com>
471 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
472
473 * i386.h (BND_PREFIX_OPCODE): New.
474
c3c07478
RS		 4752013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
476
477 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
478 OP_SAVE_RESTORE_LIST.
479 (decode_mips16_operand): Declare.
480
ab902481
RS		 4812013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
482
483 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
484 (mips_operand, mips_int_operand, mips_mapped_int_operand)
485 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
486 (mips_pcrel_operand): New structures.
487 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
488 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
489 (decode_mips_operand, decode_micromips_operand): Declare.
490
cc537e56
RS		 4912013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
492
493 * mips.h: Document MIPS16 "I" opcode.
494
f2ae14a1
RS		 4952013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
496
497 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
498 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
499 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
500 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
501 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
502 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
503 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
504 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
505 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
506 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
507 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
508 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
509 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
510 Rename to...
511 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
512 (M_USD_AB): ...these.
513
5c324c16
RS		 5142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
515
516 * mips.h: Remove documentation of "[" and "]". Update documentation
517 of "k" and the MDMX formats.
518
23e69e47
RS		 5192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
520
521 * mips.h: Update documentation of "+s" and "+S".
522
27c5c572
RS		 5232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
524
525 * mips.h: Document "+i".
526
e76ff5ab
RS		 5272013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
528
529 * mips.h: Remove "mi" documentation. Update "mh" documentation.
530 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
531 Delete.
532 (INSN2_WRITE_GPR_MHI): Rename to...
533 (INSN2_WRITE_GPR_MH): ...this.
534
fa7616a4
RS		 5352013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
536
537 * mips.h: Remove documentation of "+D" and "+T".
538
18870af7
RS		 5392013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
540
541 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
542 Use "source" rather than "destination" for microMIPS "G".
543
833794fc
MR		 5442013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
545
546 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
547 values.
548
c3678916
RS		 5492013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
550
551 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
552
7f3c4072
CM		 5532013-06-17 Catherine Moore <clm@codesourcery.com>
554 Maciej W. Rozycki <macro@codesourcery.com>
555 Chao-Ying Fu <fu@mips.com>
556
557 * mips.h (OP_SH_EVAOFFSET): Define.
558 (OP_MASK_EVAOFFSET): Define.
559 (INSN_ASE_MASK): Delete.
560 (ASE_EVA): Define.
561 (M_CACHEE_AB, M_CACHEE_OB): New.
562 (M_LBE_OB, M_LBE_AB): New.
563 (M_LBUE_OB, M_LBUE_AB): New.
564 (M_LHE_OB, M_LHE_AB): New.
565 (M_LHUE_OB, M_LHUE_AB): New.
566 (M_LLE_AB, M_LLE_OB): New.
567 (M_LWE_OB, M_LWE_AB): New.
568 (M_LWLE_AB, M_LWLE_OB): New.
569 (M_LWRE_AB, M_LWRE_OB): New.
570 (M_PREFE_AB, M_PREFE_OB): New.
571 (M_SCE_AB, M_SCE_OB): New.
572 (M_SBE_OB, M_SBE_AB): New.
573 (M_SHE_OB, M_SHE_AB): New.
574 (M_SWE_OB, M_SWE_AB): New.
575 (M_SWLE_AB, M_SWLE_OB): New.
576 (M_SWRE_AB, M_SWRE_OB): New.
577 (MICROMIPSOP_SH_EVAOFFSET): Define.
578 (MICROMIPSOP_MASK_EVAOFFSET): Define.
579
0c8fe7cf
SL		 5802013-06-12 Sandra Loosemore <sandra@codesourcery.com>
581
582 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
583
c77c0862
RS		 5842013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
585
586 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
587
b015e599
AP		 5882013-05-09 Andrew Pinski <apinski@cavium.com>
589
590 * mips.h (OP_MASK_CODE10): Correct definition.
591 (OP_SH_CODE10): Likewise.
592 Add a comment that "+J" is used now for OP_*CODE10.
593 (INSN_ASE_MASK): Update.
594 (INSN_VIRT): New macro.
595 (INSN_VIRT64): New macro
596
13761a11
NC		 5972013-05-02 Nick Clifton <nickc@redhat.com>
598
599 * msp430.h: Add patterns for MSP430X instructions.
600
0afd1215
DM		 6012013-04-06 David S. Miller <davem@davemloft.net>
602
603 * sparc.h (F_PREFERRED): Define.
604 (F_PREF_ALIAS): Define.
605
41702d50
NC		 6062013-04-03 Nick Clifton <nickc@redhat.com>
607
608 * v850.h (V850_INVERSE_PCREL): Define.
609
e21e1a51
NC		 6102013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
611
612 PR binutils/15068
613 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
614
51dcdd4d
NC		 6152013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
616
617 PR binutils/15068
618 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
619 Add 16-bit opcodes.
620 * tic6xc-opcode-table.h: Add 16-bit insns.
621 * tic6x.h: Add support for 16-bit insns.
622
81f5558e
NC		 6232013-03-21 Michael Schewe <michael.schewe@gmx.net>
624
625 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
626 and mov.b/w/l Rs,@(d:32,ERd).
627
165546ad
NC		 6282013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
629
630 PR gas/15082
631 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
632 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
633 tic6x_operand_xregpair operand coding type.
634 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
635 opcode field, usu ORXREGD1324 for the src2 operand and remove the
636 TIC6X_FLAG_NO_CROSS.
637
795b8e6b
NC		 6382013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
639
640 PR gas/15095
641 * tic6x.h (enum tic6x_coding_method): Add
642 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
643 separately the msb and lsb of a register pair. This is needed to
644 encode the opcodes in the same way as TI assembler does.
645 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
646 and rsqrdp opcodes to use the new field coding types.
647
dd5181d5
KT		 6482013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
649
650 * arm.h (CRC_EXT_ARMV8): New constant.
651 (ARCH_CRC_ARMV8): New macro.
652
e60bb1dd
YZ		 6532013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
654
655 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
656
36591ba1 6572013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 658 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 659
660 Based on patches from Altera Corporation.
661
662 * nios2.h: New file.
663
e30181a5
YZ		 6642013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
665
666 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
667
0c9573f4
NC		 6682013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
669
670 PR gas/15069
671 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
672
981dc7f1
NC		 6732013-01-24 Nick Clifton <nickc@redhat.com>
674
675 * v850.h: Add e3v5 support.
676
f5555712
YZ		 6772013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
678
679 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
680
5817ffd1
PB		 6812013-01-10 Peter Bergner <bergner@vnet.ibm.com>
682
683 * ppc.h (PPC_OPCODE_POWER8): New define.
684 (PPC_OPCODE_HTM): Likewise.
685
a3c62988
NC		 6862013-01-10 Will Newton <will.newton@imgtec.com>
687
688 * metag.h: New file.
689
73335eae
NC		 6902013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
691
692 * cr16.h (make_instruction): Rename to cr16_make_instruction.
693 (match_opcode): Rename to cr16_match_opcode.
694
e407c74b
NC		 6952013-01-04 Juergen Urban <JuergenUrban@gmx.de>
696
697 * mips.h: Add support for r5900 instructions including lq and sq.
698
bab4becb
NC		 6992013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
700
701 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
702 (make_instruction,match_opcode): Added function prototypes.
703 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
704
776fc418
AM		 7052012-11-23 Alan Modra <amodra@gmail.com>
706
707 * ppc.h (ppc_parse_cpu): Update prototype.
708
f05682d4
DA		 7092012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
710
711 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
712 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
713
cfc72779
AK		 7142012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
715
716 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
717
b3e14eda
L		 7182012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
719
720 * ia64.h (ia64_opnd): Add new operand types.
721
2c63854f
DM		 7222012-08-21 David S. Miller <davem@davemloft.net>
723
724 * sparc.h (F3F4): New macro.
725
a06ea964 7262012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 727 Laurent Desnogues <laurent.desnogues@arm.com>
728 Jim MacArthur <jim.macarthur@arm.com>
729 Marcus Shawcroft <marcus.shawcroft@arm.com>
730 Nigel Stephens <nigel.stephens@arm.com>
731 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
732 Richard Earnshaw <rearnsha@arm.com>
733 Sofiane Naci <sofiane.naci@arm.com>
734 Tejas Belagod <tejas.belagod@arm.com>
735 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 736
737 * aarch64.h: New file.
738
35d0a169 7392012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 740 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 741
742 * mips.h (mips_opcode): Add the exclusions field.
743 (OPCODE_IS_MEMBER): Remove macro.
744 (cpu_is_member): New inline function.
745 (opcode_is_member): Likewise.
746
03f66e8a 7472012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 748 Catherine Moore <clm@codesourcery.com>
749 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 750
751 * mips.h: Document microMIPS DSP ASE usage.
752 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
753 microMIPS DSP ASE support.
754 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
755 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
756 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
757 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
758 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
759 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
760 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
761
9d7b4c23
MR		 7622012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
763
764 * mips.h: Fix a typo in description.
765
76e879f8
NC		 7662012-06-07 Georg-Johann Lay <avr@gjlay.de>
767
768 * avr.h: (AVR_ISA_XCH): New define.
769 (AVR_ISA_XMEGA): Use it.
770 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
771
6927f982
NC		 7722012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
773
774 * m68hc11.h: Add XGate definitions.
775 (struct m68hc11_opcode): Add xg_mask field.
776
b9c361e0
JL		 7772012-05-14 Catherine Moore <clm@codesourcery.com>
778 Maciej W. Rozycki <macro@codesourcery.com>
779 Rhonda Wittels <rhonda@codesourcery.com>
780
6927f982 781 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 782 (PPC_OP_SA): New macro.
783 (PPC_OP_SE_VLE): New macro.
784 (PPC_OP): Use a variable shift amount.
785 (powerpc_operand): Update comments.
786 (PPC_OPSHIFT_INV): New macro.
787 (PPC_OPERAND_CR): Replace with...
788 (PPC_OPERAND_CR_BIT): ...this and
789 (PPC_OPERAND_CR_REG): ...this.
790
791
f6c1a2d5
NC		 7922012-05-03 Sean Keys <skeys@ipdatasys.com>
793
794 * xgate.h: Header file for XGATE assembler.
795
ec668d69
DM		 7962012-04-27 David S. Miller <davem@davemloft.net>
797
6cda1326
DM		 798 * sparc.h: Document new arg code' )' for crypto RS3
799 immediates.
800
ec668d69
DM		 801 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
802 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
803 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
804 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
805 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
806 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
807 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
808 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
809 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
810 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
811 HWCAP_CBCOND, HWCAP_CRC32): New defines.
812
aea77599
AM		 8132012-03-10 Edmar Wienskoski <edmar@freescale.com>
814
815 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
816
1f42f8b3
AM		 8172012-02-27 Alan Modra <amodra@gmail.com>
818
819 * crx.h (cst4_map): Update declaration.
820
6f7be959
WL		 8212012-02-25 Walter Lee <walt@tilera.com>
822
823 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
824 TILEGX_OPC_LD_TLS.
825 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
826 TILEPRO_OPC_LW_TLS_SN.
827
42164a71
L		 8282012-02-08 H.J. Lu <hongjiu.lu@intel.com>
829
830 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
831 (XRELEASE_PREFIX_OPCODE): Likewise.
832
432233b3 8332011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 834 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 835
836 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
837 (INSN_OCTEON2): New macro.
838 (CPU_OCTEON2): New macro.
839 (OPCODE_IS_MEMBER): Add Octeon2.
840
dd6a37e7
AP		 8412011-11-29 Andrew Pinski <apinski@cavium.com>
842
843 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
844 (INSN_OCTEONP): New macro.
845 (CPU_OCTEONP): New macro.
846 (OPCODE_IS_MEMBER): Add Octeon+.
847 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
848
99c513f6
DD		 8492011-11-01 DJ Delorie <dj@redhat.com>
850
851 * rl78.h: New file.
852
26f85d7a
MR		 8532011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
854
855 * mips.h: Fix a typo in description.
856
9e8c70f9
DM		 8572011-09-21 David S. Miller <davem@davemloft.net>
858
859 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
860 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
861 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
862 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
863
dec0624d 8642011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 865 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 866
867 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
868 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
869 (INSN_ASE_MASK): Add the MCU bit.
870 (INSN_MCU): New macro.
871 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
872 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
873
2b0c8b40
MR		 8742011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
875
876 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
877 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
878 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
879 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
880 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
881 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
882 (INSN2_READ_GPR_MMN): Likewise.
883 (INSN2_READ_FPR_D): Change the bit used.
884 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
885 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
886 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
887 (INSN2_COND_BRANCH): Likewise.
888 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
889 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
890 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
891 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
892 (INSN2_MOD_GPR_MN): Likewise.
893
ea783ef3
DM		 8942011-08-05 David S. Miller <davem@davemloft.net>
895
896 * sparc.h: Document new format codes '4', '5', and '('.
897 (OPF_LOW4, RS3): New macros.
898
7c176fa8
MR		 8992011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
900
901 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
902 order of flags documented.
903
2309ddf2
MR		 9042011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
905
906 * mips.h: Clarify the description of microMIPS instruction
907 manipulation macros.
908 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
909
df58fc94 9102011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 911 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 912
913 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
914 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
915 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
916 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
917 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
918 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
919 (OP_MASK_RS3, OP_SH_RS3): Likewise.
920 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
921 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
922 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
923 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
924 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
925 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
926 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
927 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
928 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
929 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
930 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
931 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
932 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
933 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
934 (INSN_WRITE_GPR_S): New macro.
935 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
936 (INSN2_READ_FPR_D): Likewise.
937 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
938 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
939 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
940 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
941 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
942 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
943 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
944 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
945 (CPU_MICROMIPS): New macro.
946 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
947 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
948 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
949 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
950 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
951 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
952 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
953 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
954 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
955 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
956 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
957 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
958 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
959 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
960 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
961 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
962 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
963 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
964 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
965 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
966 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
967 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
968 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
969 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
970 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
971 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
972 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
973 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
974 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
975 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
976 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
977 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
978 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
979 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
980 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
981 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
982 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
983 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
984 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
985 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
986 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
987 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
988 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
989 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
990 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
991 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
992 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
993 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
994 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
995 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
996 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
997 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
998 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
999 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1000 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1001 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1002 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1003 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1004 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1005 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1006 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1007 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1008 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1009 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1010 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1011 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1012 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1013 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1014 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1015 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1016 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1017 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1018 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1019 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1020 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1021 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1022 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1023 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1024 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1025 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1026 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1027 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1028 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1029 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1030 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1031 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1032 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1033 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1034 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1035 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1036 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1037 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1038 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1039 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1040 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1041 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1042 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1043 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1044 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1045 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1046 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1047 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1048 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1049 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1050 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1051 (micromips_opcodes): New declaration.
1052 (bfd_micromips_num_opcodes): Likewise.
1053
bcd530a7
RS		 10542011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1055
1056 * mips.h (INSN_TRAP): Rename to...
1057 (INSN_NO_DELAY_SLOT): ... this.
1058 (INSN_SYNC): Remove macro.
1059
2dad5a91
EW		 10602011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1061
1062 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1063 a duplicate of AVR_ISA_SPM.
1064
5d73b1f1
NC		 10652011-07-01 Nick Clifton <nickc@redhat.com>
1066
1067 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1068
ef26d60e
MF		 10692011-06-18 Robin Getz <robin.getz@analog.com>
1070
1071 * bfin.h (is_macmod_signed): New func
1072
8fb8dca7
MF		 10732011-06-18 Mike Frysinger <vapier@gentoo.org>
1074
1075 * bfin.h (is_macmod_pmove): Add missing space before func args.
1076 (is_macmod_hmove): Likewise.
1077
aa137e4d
NC		 10782011-06-13 Walter Lee <walt@tilera.com>
1079
1080 * tilegx.h: New file.
1081 * tilepro.h: New file.
1082
3b2f0793
PB		 10832011-05-31 Paul Brook <paul@codesourcery.com>
1084
aa137e4d
NC		 1085 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1086
10872011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1088
1089 * s390.h: Replace S390_OPERAND_REG_EVEN with
1090 S390_OPERAND_REG_PAIR.
1091
10922011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1093
1094 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1095
ac7f631b
NC		 10962011-04-18 Julian Brown <julian@codesourcery.com>
1097
1098 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1099
84701018
NC		 11002011-04-11 Dan McDonald <dan@wellkeeper.com>
1101
1102 PR gas/12296
1103 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1104
8cc66334
EW		 11052011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1106
1107 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1108 New instruction set flags.
1109 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1110
3eebd5eb
MR		 11112011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1112
1113 * mips.h (M_PREF_AB): New enum value.
1114
26bb3ddd
MF		 11152011-02-12 Mike Frysinger <vapier@gentoo.org>
1116
89c0d58c
MR		 1117 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1118 M_IU): Define.
1119 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1120
dd76fcb8
MF		 11212011-02-11 Mike Frysinger <vapier@gentoo.org>
1122
1123 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1124
98d23bef
BS		 11252011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1126
1127 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1128 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1129
3c853d93
DA		 11302010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1131
1132 PR gas/11395
1133 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1134 "bb" entries.
1135
79676006
DA		 11362010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1137
1138 PR gas/11395
1139 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1140
1bec78e9
RS		 11412010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1142
1143 * mips.h: Update commentary after last commit.
1144
98675402
RS		 11452010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1146
1147 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1148 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1149 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1150
aa137e4d
NC		 11512010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1152
1153 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1154
435b94a4
RS		 11552010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1156
1157 * mips.h: Fix previous commit.
1158
d051516a
NC		 11592010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1160
1161 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1162 (INSN_LOONGSON_3A): Clear bit 31.
1163
251665fc
MGD		 11642010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1165
1166 PR gas/12198
1167 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1168 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1169 (ARM_ARCH_V6M_ONLY): New define.
1170
fd503541
NC		 11712010-11-11 Mingming Sun <mingm.sun@gmail.com>
1172
1173 * mips.h (INSN_LOONGSON_3A): Defined.
1174 (CPU_LOONGSON_3A): Defined.
1175 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1176
4469d2be
AM		 11772010-10-09 Matt Rice <ratmice@gmail.com>
1178
1179 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1180 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1181
90ec0d68
MGD		 11822010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1183
1184 * arm.h (ARM_EXT_VIRT): New define.
1185 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1186 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1187 Extensions.
1188
eea54501 11892010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1190
eea54501
MGD		 1191 * arm.h (ARM_AEXT_ADIV): New define.
1192 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1193
b2a5fbdc
MGD		 11942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1195
1196 * arm.h (ARM_EXT_OS): New define.
1197 (ARM_AEXT_V6SM): Likewise.
1198 (ARM_ARCH_V6SM): Likewise.
1199
60e5ef9f
MGD		 12002010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1201
1202 * arm.h (ARM_EXT_MP): Add.
1203 (ARM_ARCH_V7A_MP): Likewise.
1204
73a63ccf
MF		 12052010-09-22 Mike Frysinger <vapier@gentoo.org>
1206
1207 * bfin.h: Declare pseudoChr structs/defines.
1208
ee99860a
MF		 12092010-09-21 Mike Frysinger <vapier@gentoo.org>
1210
1211 * bfin.h: Strip trailing whitespace.
1212
f9c7014e
DD		 12132010-07-29 DJ Delorie <dj@redhat.com>
1214
1215 * rx.h (RX_Operand_Type): Add TwoReg.
1216 (RX_Opcode_ID): Remove ediv and ediv2.
1217
93378652
DD		 12182010-07-27 DJ Delorie <dj@redhat.com>
1219
1220 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1221
1cd986c5
NC		 12222010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1223 Ina Pandit <ina.pandit@kpitcummins.com>
1224
1225 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1226 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1227 PROCESSOR_V850E2_ALL.
1228 Remove PROCESSOR_V850EA support.
1229 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1230 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1231 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1232 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1233 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1234 V850_OPERAND_PERCENT.
1235 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1236 V850_NOT_R0.
1237 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1238 and V850E_PUSH_POP
1239
9a2c7088
MR		 12402010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1241
1242 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1243 (MIPS16_INSN_BRANCH): Rename to...
1244 (MIPS16_INSN_COND_BRANCH): ... this.
1245
bdc70b4a
AM		 12462010-07-03 Alan Modra <amodra@gmail.com>
1247
1248 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1249 Renumber other PPC_OPCODE defines.
1250
f2bae120
AM		 12512010-07-03 Alan Modra <amodra@gmail.com>
1252
1253 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1254
360cfc9c
AM		 12552010-06-29 Alan Modra <amodra@gmail.com>
1256
1257 * maxq.h: Delete file.
1258
e01d869a
AM		 12592010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1260
1261 * ppc.h (PPC_OPCODE_E500): Define.
1262
f79e2745
CM		 12632010-05-26 Catherine Moore <clm@codesourcery.com>
1264
1265 * opcode/mips.h (INSN_MIPS16): Remove.
1266
2462afa1
JM		 12672010-04-21 Joseph Myers <joseph@codesourcery.com>
1268
1269 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1270
e4e42b45
NC		 12712010-04-15 Nick Clifton <nickc@redhat.com>
1272
1273 * alpha.h: Update copyright notice to use GPLv3.
1274 * arc.h: Likewise.
1275 * arm.h: Likewise.
1276 * avr.h: Likewise.
1277 * bfin.h: Likewise.
1278 * cgen.h: Likewise.
1279 * convex.h: Likewise.
1280 * cr16.h: Likewise.
1281 * cris.h: Likewise.
1282 * crx.h: Likewise.
1283 * d10v.h: Likewise.
1284 * d30v.h: Likewise.
1285 * dlx.h: Likewise.
1286 * h8300.h: Likewise.
1287 * hppa.h: Likewise.
1288 * i370.h: Likewise.
1289 * i386.h: Likewise.
1290 * i860.h: Likewise.
1291 * i960.h: Likewise.
1292 * ia64.h: Likewise.
1293 * m68hc11.h: Likewise.
1294 * m68k.h: Likewise.
1295 * m88k.h: Likewise.
1296 * maxq.h: Likewise.
1297 * mips.h: Likewise.
1298 * mmix.h: Likewise.
1299 * mn10200.h: Likewise.
1300 * mn10300.h: Likewise.
1301 * msp430.h: Likewise.
1302 * np1.h: Likewise.
1303 * ns32k.h: Likewise.
1304 * or32.h: Likewise.
1305 * pdp11.h: Likewise.
1306 * pj.h: Likewise.
1307 * pn.h: Likewise.
1308 * ppc.h: Likewise.
1309 * pyr.h: Likewise.
1310 * rx.h: Likewise.
1311 * s390.h: Likewise.
1312 * score-datadep.h: Likewise.
1313 * score-inst.h: Likewise.
1314 * sparc.h: Likewise.
1315 * spu-insns.h: Likewise.
1316 * spu.h: Likewise.
1317 * tic30.h: Likewise.
1318 * tic4x.h: Likewise.
1319 * tic54x.h: Likewise.
1320 * tic80.h: Likewise.
1321 * v850.h: Likewise.
1322 * vax.h: Likewise.
1323
40b36596
JM		 13242010-03-25 Joseph Myers <joseph@codesourcery.com>
1325
1326 * tic6x-control-registers.h, tic6x-insn-formats.h,
1327 tic6x-opcode-table.h, tic6x.h: New.
1328
c67a084a
NC		 13292010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1330
1331 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1332
466ef64f
AM		 13332010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1334
1335 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1336
1319d143
L		 13372010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1338
1339 * ia64.h (ia64_find_opcode): Remove argument name.
1340 (ia64_find_next_opcode): Likewise.
1341 (ia64_dis_opcode): Likewise.
1342 (ia64_free_opcode): Likewise.
1343 (ia64_find_dependency): Likewise.
1344
1fbb9298
DE		 13452009-11-22 Doug Evans <dje@sebabeach.org>
1346
1347 * cgen.h: Include bfd_stdint.h.
1348 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1349
ada65aa3
PB		 13502009-11-18 Paul Brook <paul@codesourcery.com>
1351
1352 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1353
9e3c6df6
PB		 13542009-11-17 Paul Brook <paul@codesourcery.com>
1355 Daniel Jacobowitz <dan@codesourcery.com>
1356
1357 * arm.h (ARM_EXT_V6_DSP): Define.
1358 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1359 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1360
0d734b5d
DD		 13612009-11-04 DJ Delorie <dj@redhat.com>
1362
1363 * rx.h (rx_decode_opcode) (mvtipl): Add.
1364 (mvtcp, mvfcp, opecp): Remove.
1365
62f3b8c8
PB		 13662009-11-02 Paul Brook <paul@codesourcery.com>
1367
1368 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1369 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1370 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1371 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1372 FPU_ARCH_NEON_VFP_V4): Define.
1373
ac1e9eca
DE		 13742009-10-23 Doug Evans <dje@sebabeach.org>
1375
1376 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1377 * cgen.h: Update. Improve multi-inclusion macro name.
1378
9fe54b1c
PB		 13792009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1380
1381 * ppc.h (PPC_OPCODE_476): Define.
1382
634b50f2
PB		 13832009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1384
1385 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1386
c7927a3c
NC		 13872009-09-29 DJ Delorie <dj@redhat.com>
1388
1389 * rx.h: New file.
1390
b961e85b
AM		 13912009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1392
1393 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1394
e0d602ec
BE		 13952009-09-21 Ben Elliston <bje@au.ibm.com>
1396
1397 * ppc.h (PPC_OPCODE_PPCA2): New.
1398
96d56e9f
NC		 13992009-09-05 Martin Thuresson <martin@mtme.org>
1400
1401 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1402
d3ce72d0
NC		 14032009-08-29 Martin Thuresson <martin@mtme.org>
1404
1405 * tic30.h (template): Rename type template to
1406 insn_template. Updated code to use new name.
1407 * tic54x.h (template): Rename type template to
1408 insn_template.
1409
824b28db
NH		 14102009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1411
1412 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1413
f865a31d
AG		 14142009-06-11 Anthony Green <green@moxielogic.com>
1415
1416 * moxie.h (MOXIE_F3_PCREL): Define.
1417 (moxie_form3_opc_info): Grow.
1418
0e7c7f11
AG		 14192009-06-06 Anthony Green <green@moxielogic.com>
1420
1421 * moxie.h (MOXIE_F1_M): Define.
1422
20135e4c
NC		 14232009-04-15 Anthony Green <green@moxielogic.com>
1424
1425 * moxie.h: Created.
1426
bcb012d3
DD		 14272009-04-06 DJ Delorie <dj@redhat.com>
1428
1429 * h8300.h: Add relaxation attributes to MOVA opcodes.
1430
69fe9ce5
AM		 14312009-03-10 Alan Modra <amodra@bigpond.net.au>
1432
1433 * ppc.h (ppc_parse_cpu): Declare.
1434
c3b7224a
NC		 14352009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1436
1437 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1438 and _IMM11 for mbitclr and mbitset.
1439 * score-datadep.h: Update dependency information.
1440
066be9f7
PB		 14412009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1442
1443 * ppc.h (PPC_OPCODE_POWER7): New.
1444
fedc618e
DE		 14452009-02-06 Doug Evans <dje@google.com>
1446
1447 * i386.h: Add comment regarding sse* insns and prefixes.
1448
52b6b6b9
JM		 14492009-02-03 Sandip Matte <sandip@rmicorp.com>
1450
1451 * mips.h (INSN_XLR): Define.
1452 (INSN_CHIP_MASK): Update.
1453 (CPU_XLR): Define.
1454 (OPCODE_IS_MEMBER): Update.
1455 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1456
35669430
DE		 14572009-01-28 Doug Evans <dje@google.com>
1458
1459 * opcode/i386.h: Add multiple inclusion protection.
1460 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1461 (EDI_REG_NUM): New macros.
1462 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1463 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1464 (REX_PREFIX_P): New macro.
35669430 1465
1cb0a767
PB		 14662009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1467
1468 * ppc.h (struct powerpc_opcode): New field "deprecated".
1469 (PPC_OPCODE_NOPOWER4): Delete.
1470
3aa3176b
TS		 14712008-11-28 Joshua Kinard <kumba@gentoo.org>
1472
1473 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1474 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1475
8e79c3df
CM		 14762008-11-18 Catherine Moore <clm@codesourcery.com>
1477
1478 * arm.h (FPU_NEON_FP16): New.
1479 (FPU_ARCH_NEON_FP16): New.
1480
de9a3e51
CF		 14812008-11-06 Chao-ying Fu <fu@mips.com>
1482
1483 * mips.h: Doucument '1' for 5-bit sync type.
1484
1ca35711
L		 14852008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1486
1487 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1488 IA64_RS_CR.
1489
9b4e5766
PB		 14902008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1491
1492 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1493
081ba1b3
AM		 14942008-07-30 Michael J. Eager <eager@eagercon.com>
1495
1496 * ppc.h (PPC_OPCODE_405): Define.
1497 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1498
fa452fa6
PB		 14992008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1500
1501 * ppc.h (ppc_cpu_t): New typedef.
1502 (struct powerpc_opcode <flags>): Use it.
1503 (struct powerpc_operand <insert, extract>): Likewise.
1504 (struct powerpc_macro <flags>): Likewise.
1505
bb35fb24
NC		 15062008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1507
1508 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1509 Update comment before MIPS16 field descriptors to mention MIPS16.
1510 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1511 BBIT.
1512 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1513 New bit masks and shift counts for cins and exts.
1514
dd3cbb7e
NC		 1515 * mips.h: Document new field descriptors +Q.
1516 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1517
d0799671
AN		 15182008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1519
9aff4b7a 1520 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1521 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1522
19a6653c
AM		 15232008-04-14 Edmar Wienskoski <edmar@freescale.com>
1524
1525 * ppc.h: (PPC_OPCODE_E500MC): New.
1526
c0f3af97
L		 15272008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1528
1529 * i386.h (MAX_OPERANDS): Set to 5.
1530 (MAX_MNEM_SIZE): Changed to 20.
1531
e210c36b
NC		 15322008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1533
1534 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1535
b1cc4aeb
PB		 15362008-03-09 Paul Brook <paul@codesourcery.com>
1537
1538 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1539
7e806470
PB		 15402008-03-04 Paul Brook <paul@codesourcery.com>
1541
1542 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1543 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1544 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1545
7b2185f9 15462008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1547 Nick Clifton <nickc@redhat.com>
1548
1549 PR 3134
1550 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1551 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1552 set.
af7329f0 1553
796d5313
NC		 15542008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1555
1556 * cr16.h (cr16_num_optab): Declared.
1557
d669d37f
NC		 15582008-02-14 Hakan Ardo <hakan@debian.org>
1559
1560 PR gas/2626
1561 * avr.h (AVR_ISA_2xxe): Define.
1562
e6429699
AN		 15632008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1564
1565 * mips.h: Update copyright.
1566 (INSN_CHIP_MASK): New macro.
1567 (INSN_OCTEON): New macro.
1568 (CPU_OCTEON): New macro.
1569 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1570
e210c36b
NC		 15712008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1572
1573 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1574
15752008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1576
1577 * avr.h (AVR_ISA_USB162): Add new opcode set.
1578 (AVR_ISA_AVR3): Likewise.
1579
350cc38d
MS		 15802007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1581
1582 * mips.h (INSN_LOONGSON_2E): New.
1583 (INSN_LOONGSON_2F): New.
1584 (CPU_LOONGSON_2E): New.
1585 (CPU_LOONGSON_2F): New.
1586 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1587
56950294
MS		 15882007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1589
1590 * mips.h (INSN_ISA*): Redefine certain values as an
1591 enumeration. Update comments.
1592 (mips_isa_table): New.
1593 (ISA_MIPS*): Redefine to match enumeration.
1594 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1595 values.
1596
c3d65c1c
BE		 15972007-08-08 Ben Elliston <bje@au.ibm.com>
1598
1599 * ppc.h (PPC_OPCODE_PPCPS): New.
1600
0fdaa005
L		 16012007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1602
1603 * m68k.h: Document j K & E.
1604
16052007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1606
1607 * cr16.h: New file for CR16 target.
1608
3896c469
AM		 16092007-05-02 Alan Modra <amodra@bigpond.net.au>
1610
1611 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1612
9a2e615a
NS		 16132007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1614
1615 * m68k.h (mcfisa_c): New.
1616 (mcfusp, mcf_mask): Adjust.
1617
b84bf58a
AM		 16182007-04-20 Alan Modra <amodra@bigpond.net.au>
1619
1620 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1621 (num_powerpc_operands): Declare.
1622 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1623 (PPC_OPERAND_PLUS1): Define.
1624
831480e9 16252007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1626
1627 * i386.h (REX_MODE64): Renamed to ...
1628 (REX_W): This.
1629 (REX_EXTX): Renamed to ...
1630 (REX_R): This.
1631 (REX_EXTY): Renamed to ...
1632 (REX_X): This.
1633 (REX_EXTZ): Renamed to ...
1634 (REX_B): This.
1635
0b1cf022
L		 16362007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1637
1638 * i386.h: Add entries from config/tc-i386.h and move tables
1639 to opcodes/i386-opc.h.
1640
d796c0ad
L		 16412007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1642
1643 * i386.h (FloatDR): Removed.
1644 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1645
30ac7323
AM		 16462007-03-01 Alan Modra <amodra@bigpond.net.au>
1647
1648 * spu-insns.h: Add soma double-float insns.
1649
8b082fb1 16502007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1651 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1652
1653 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1654 (INSN_DSPR2): Add flag for DSP R2 instructions.
1655 (M_BALIGN): New macro.
1656
4eed87de
AM		 16572007-02-14 Alan Modra <amodra@bigpond.net.au>
1658
1659 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1660 and Seg3ShortFrom with Shortform.
1661
fda592e8
L		 16622007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1663
1664 PR gas/4027
1665 * i386.h (i386_optab): Put the real "test" before the pseudo
1666 one.
1667
3bdcfdf4
KH		 16682007-01-08 Kazu Hirata <kazu@codesourcery.com>
1669
1670 * m68k.h (m68010up): OR fido_a.
1671
9840d27e
KH		 16722006-12-25 Kazu Hirata <kazu@codesourcery.com>
1673
1674 * m68k.h (fido_a): New.
1675
c629cdac
KH		 16762006-12-24 Kazu Hirata <kazu@codesourcery.com>
1677
1678 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1679 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1680 values.
1681
b7d9ef37
L		 16822006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1683
1684 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1685
b138abaa
NC		 16862006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1687
1688 * score-inst.h (enum score_insn_type): Add Insn_internal.
1689
e9f53129
AM		 16902006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1691 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1692 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1693 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1694 Alan Modra <amodra@bigpond.net.au>
1695
1696 * spu-insns.h: New file.
1697 * spu.h: New file.
1698
ede602d7
AM		 16992006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1700
1701 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1702
7918206c
MM		 17032006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1704
e4e42b45 1705 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1706 in amdfam10 architecture.
1707
ef05d495
L		 17082006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1709
1710 * i386.h: Replace CpuMNI with CpuSSSE3.
1711
2d447fca 17122006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1713 Joseph Myers <joseph@codesourcery.com>
1714 Ian Lance Taylor <ian@wasabisystems.com>
1715 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1716
1717 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1718
1c0d3aa6
NC		 17192006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1720
1721 * score-datadep.h: New file.
1722 * score-inst.h: New file.
1723
c2f0420e
L		 17242006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1725
1726 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1727 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1728 movdq2q and movq2dq.
1729
050dfa73
MM		 17302006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1731 Michael Meissner <michael.meissner@amd.com>
1732
1733 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1734
15965411
L		 17352006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1736
1737 * i386.h (i386_optab): Add "nop" with memory reference.
1738
46e883c5
L		 17392006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1740
1741 * i386.h (i386_optab): Update comment for 64bit NOP.
1742
9622b051
AM		 17432006-06-06 Ben Elliston <bje@au.ibm.com>
1744 Anton Blanchard <anton@samba.org>
1745
1746 * ppc.h (PPC_OPCODE_POWER6): Define.
1747 Adjust whitespace.
1748
a9e24354
TS		 17492006-06-05 Thiemo Seufer <ths@mips.com>
1750
e4e42b45 1751 * mips.h: Improve description of MT flags.
a9e24354 1752
a596001e
RS		 17532006-05-25 Richard Sandiford <richard@codesourcery.com>
1754
1755 * m68k.h (mcf_mask): Define.
1756
d43b4baf 17572006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1758 David Ung <davidu@mips.com>
d43b4baf
TS		 1759
1760 * mips.h (enum): Add macro M_CACHE_AB.
1761
39a7806d 17622006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1763 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1764 David Ung <davidu@mips.com>
1765
1766 * mips.h: Add INSN_SMARTMIPS define.
1767
9bcd4f99 17682006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1769 David Ung <davidu@mips.com>
9bcd4f99
TS		 1770
1771 * mips.h: Defines udi bits and masks. Add description of
1772 characters which may appear in the args field of udi
1773 instructions.
1774
ef0ee844
TS		 17752006-04-26 Thiemo Seufer <ths@networkno.de>
1776
1777 * mips.h: Improve comments describing the bitfield instruction
1778 fields.
1779
f7675147
L		 17802006-04-26 Julian Brown <julian@codesourcery.com>
1781
1782 * arm.h (FPU_VFP_EXT_V3): Define constant.
1783 (FPU_NEON_EXT_V1): Likewise.
1784 (FPU_VFP_HARD): Update.
1785 (FPU_VFP_V3): Define macro.
1786 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1787
ef0ee844 17882006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1789
1790 * avr.h (AVR_ISA_PWMx): New.
1791
2da12c60
NS		 17922006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1793
1794 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1795 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1796 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1797 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1798 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1799
0715c387
PB		 18002006-03-10 Paul Brook <paul@codesourcery.com>
1801
1802 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1803
34bdd094
DA		 18042006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1805
1806 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1807 first. Correct mask of bb "B" opcode.
1808
331d2d0d
L		 18092006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1810
1811 * i386.h (i386_optab): Support Intel Merom New Instructions.
1812
62b3e311
PB		 18132006-02-24 Paul Brook <paul@codesourcery.com>
1814
1815 * arm.h: Add V7 feature bits.
1816
59cf82fe
L		 18172006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1818
1819 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1820
e74cfd16
PB		 18212006-01-31 Paul Brook <paul@codesourcery.com>
1822 Richard Earnshaw <rearnsha@arm.com>
1823
1824 * arm.h: Use ARM_CPU_FEATURE.
1825 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1826 (arm_feature_set): Change to a structure.
1827 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1828 ARM_FEATURE): New macros.
1829
5b3f8a92
HPN		 18302005-12-07 Hans-Peter Nilsson <hp@axis.com>
1831
1832 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1833 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1834 (ADD_PC_INCR_OPCODE): Don't define.
1835
cb712a9e
L		 18362005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1837
1838 PR gas/1874
1839 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1840
0499d65b
TS		 18412005-11-14 David Ung <davidu@mips.com>
1842
1843 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1844 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1845 save/restore encoding of the args field.
1846
ea5ca089
DB		 18472005-10-28 Dave Brolley <brolley@redhat.com>
1848
1849 Contribute the following changes:
1850 2005-02-16 Dave Brolley <brolley@redhat.com>
1851
1852 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1853 cgen_isa_mask_* to cgen_bitset_*.
1854 * cgen.h: Likewise.
1855
16175d96
DB		 1856 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1857
1858 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1859 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1860 (CGEN_CPU_TABLE): Make isas a ponter.
1861
1862 2003-09-29 Dave Brolley <brolley@redhat.com>
1863
1864 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1865 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1866 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1867
1868 2002-12-13 Dave Brolley <brolley@redhat.com>
1869
1870 * cgen.h (symcat.h): #include it.
1871 (cgen-bitset.h): #include it.
1872 (CGEN_ATTR_VALUE_TYPE): Now a union.
1873 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1874 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1875 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1876 * cgen-bitset.h: New file.
1877
3c9b82ba
NC		 18782005-09-30 Catherine Moore <clm@cm00re.com>
1879
1880 * bfin.h: New file.
1881
6a2375c6
JB		 18822005-10-24 Jan Beulich <jbeulich@novell.com>
1883
1884 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1885 indirect operands.
1886
c06a12f8
DA		 18872005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1888
1889 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1890 Add FLAG_STRICT to pa10 ftest opcode.
1891
4d443107
DA		 18922005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1893
1894 * hppa.h (pa_opcodes): Remove lha entries.
1895
f0a3b40f
DA		 18962005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1897
1898 * hppa.h (FLAG_STRICT): Revise comment.
1899 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1900 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1901 entries for "fdc".
1902
e210c36b
NC		 19032005-09-30 Catherine Moore <clm@cm00re.com>
1904
1905 * bfin.h: New file.
1906
1b7e1362
DA		 19072005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1908
1909 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1910
089b39de
CF		 19112005-09-06 Chao-ying Fu <fu@mips.com>
1912
1913 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1914 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1915 define.
1916 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1917 (INSN_ASE_MASK): Update to include INSN_MT.
1918 (INSN_MT): New define for MT ASE.
1919
93c34b9b
CF		 19202005-08-25 Chao-ying Fu <fu@mips.com>
1921
1922 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1923 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1924 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1925 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1926 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1927 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1928 instructions.
1929 (INSN_DSP): New define for DSP ASE.
1930
848cf006
AM		 19312005-08-18 Alan Modra <amodra@bigpond.net.au>
1932
1933 * a29k.h: Delete.
1934
36ae0db3
DJ		 19352005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1936
1937 * ppc.h (PPC_OPCODE_E300): Define.
1938
8c929562
MS		 19392005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1940
1941 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1942
f7b8cccc
DA		 19432005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1944
1945 PR gas/336
1946 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1947 and pitlb.
1948
8b5328ac
JB		 19492005-07-27 Jan Beulich <jbeulich@novell.com>
1950
1951 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1952 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1953 Add movq-s as 64-bit variants of movd-s.
1954
f417d200
DA		 19552005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1956
18b3bdfc
DA		 1957 * hppa.h: Fix punctuation in comment.
1958
f417d200
DA		 1959 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1960 implicit space-register addressing. Set space-register bits on opcodes
1961 using implicit space-register addressing. Add various missing pa20
1962 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1963 space-register addressing. Use "fE" instead of "fe" in various
1964 fstw opcodes.
1965
9a145ce6
JB		 19662005-07-18 Jan Beulich <jbeulich@novell.com>
1967
1968 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1969
90700ea2
L		 19702007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1971
1972 * i386.h (i386_optab): Support Intel VMX Instructions.
1973
48f130a8
DA		 19742005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1975
1976 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1977
30123838
JB		 19782005-07-05 Jan Beulich <jbeulich@novell.com>
1979
1980 * i386.h (i386_optab): Add new insns.
1981
47b0e7ad
NC		 19822005-07-01 Nick Clifton <nickc@redhat.com>
1983
1984 * sparc.h: Add typedefs to structure declarations.
1985
b300c311
L		 19862005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1987
1988 PR 1013
1989 * i386.h (i386_optab): Update comments for 64bit addressing on
1990 mov. Allow 64bit addressing for mov and movq.
1991
2db495be
DA		 19922005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1993
1994 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1995 respectively, in various floating-point load and store patterns.
1996
caa05036
DA		 19972005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1998
1999 * hppa.h (FLAG_STRICT): Correct comment.
2000 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2001 PA 2.0 mneumonics when equivalent. Entries with cache control
2002 completers now require PA 1.1. Adjust whitespace.
2003
f4411256
AM		 20042005-05-19 Anton Blanchard <anton@samba.org>
2005
2006 * ppc.h (PPC_OPCODE_POWER5): Define.
2007
e172dbf8
NC		 20082005-05-10 Nick Clifton <nickc@redhat.com>
2009
2010 * Update the address and phone number of the FSF organization in
2011 the GPL notices in the following files:
2012 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2013 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2014 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2015 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2016 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2017 tic54x.h, tic80.h, v850.h, vax.h
2018
e44823cf
JB		 20192005-05-09 Jan Beulich <jbeulich@novell.com>
2020
2021 * i386.h (i386_optab): Add ht and hnt.
2022
791fe849
MK		 20232005-04-18 Mark Kettenis <kettenis@gnu.org>
2024
2025 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2026 Add xcrypt-ctr. Provide aliases without hyphens.
2027
faa7ef87
L		 20282005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2029
a63027e5
L		 2030 Moved from ../ChangeLog
2031
faa7ef87
L		 2032 2005-04-12 Paul Brook <paul@codesourcery.com>
2033 * m88k.h: Rename psr macros to avoid conflicts.
2034
2035 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2036 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2037 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2038 and ARM_ARCH_V6ZKT2.
2039
2040 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2041 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2042 Remove redundant instruction types.
2043 (struct argument): X_op - new field.
2044 (struct cst4_entry): Remove.
2045 (no_op_insn): Declare.
2046
2047 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2048 * crx.h (enum argtype): Rename types, remove unused types.
2049
2050 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2051 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2052 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2053 (enum operand_type): Rearrange operands, edit comments.
2054 replace us<N> with ui<N> for unsigned immediate.
2055 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2056 displacements (respectively).
2057 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2058 (instruction type): Add NO_TYPE_INS.
2059 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2060 (operand_entry): New field - 'flags'.
2061 (operand flags): New.
2062
2063 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2064 * crx.h (operand_type): Remove redundant types i3, i4,
2065 i5, i8, i12.
2066 Add new unsigned immediate types us3, us4, us5, us16.
2067
bc4bd9ab
MK		 20682005-04-12 Mark Kettenis <kettenis@gnu.org>
2069
2070 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2071 adjust them accordingly.
2072
373ff435
JB		 20732005-04-01 Jan Beulich <jbeulich@novell.com>
2074
2075 * i386.h (i386_optab): Add rdtscp.
2076
4cc91dba
L		 20772005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2078
2079 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2080 between memory and segment register. Allow movq for moving between
2081 general-purpose register and segment register.
4cc91dba 2082
9ae09ff9
JB		 20832005-02-09 Jan Beulich <jbeulich@novell.com>
2084
2085 PR gas/707
2086 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2087 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2088 fnstsw.
2089
638e7a64
NS		 20902006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2091
2092 * m68k.h (m68008, m68ec030, m68882): Remove.
2093 (m68k_mask): New.
2094 (cpu_m68k, cpu_cf): New.
2095 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2096 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2097
90219bd0
AO		 20982005-01-25 Alexandre Oliva <aoliva@redhat.com>
2099
2100 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2101 * cgen.h (enum cgen_parse_operand_type): Add
2102 CGEN_PARSE_OPERAND_SYMBOLIC.
2103
239cb185
FF		 21042005-01-21 Fred Fish <fnf@specifixinc.com>
2105
2106 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2107 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2108 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2109
dc9a9f39
FF		 21102005-01-19 Fred Fish <fnf@specifixinc.com>
2111
2112 * mips.h (struct mips_opcode): Add new pinfo2 member.
2113 (INSN_ALIAS): New define for opcode table entries that are
2114 specific instances of another entry, such as 'move' for an 'or'
2115 with a zero operand.
2116 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2117 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2118
98e7aba8
ILT		 21192004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2120
2121 * mips.h (CPU_RM9000): Define.
2122 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2123
37edbb65
JB		 21242004-11-25 Jan Beulich <jbeulich@novell.com>
2125
2126 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2127 to/from test registers are illegal in 64-bit mode. Add missing
2128 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2129 (previously one had to explicitly encode a rex64 prefix). Re-enable
2130 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2131 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2132
21332004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2134
2135 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2136 available only with SSE2. Change the MMX additions introduced by SSE
2137 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2138 instructions by their now designated identifier (since combining i686
2139 and 3DNow! does not really imply 3DNow!A).
2140
f5c7edf4
AM		 21412004-11-19 Alan Modra <amodra@bigpond.net.au>
2142
2143 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2144 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2145
7499d566
NC		 21462004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2147 Vineet Sharma <vineets@noida.hcltech.com>
2148
2149 * maxq.h: New file: Disassembly information for the maxq port.
2150
bcb9eebe
L		 21512004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2152
2153 * i386.h (i386_optab): Put back "movzb".
2154
94bb3d38
HPN		 21552004-11-04 Hans-Peter Nilsson <hp@axis.com>
2156
2157 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2158 comments. Remove member cris_ver_sim. Add members
2159 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2160 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2161 (struct cris_support_reg, struct cris_cond15): New types.
2162 (cris_conds15): Declare.
2163 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2164 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2165 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2166 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2167 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2168 SIZE_FIELD_UNSIGNED.
2169
37edbb65 21702004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2171
2172 * i386.h (sldx_Suf): Remove.
2173 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2174 (q_FP): Define, implying no REX64.
2175 (x_FP, sl_FP): Imply FloatMF.
2176 (i386_optab): Split reg and mem forms of moving from segment registers
2177 so that the memory forms can ignore the 16-/32-bit operand size
2178 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2179 all non-floating-point instructions. Unite 32- and 64-bit forms of
2180 movsx, movzx, and movd. Adjust floating point operations for the above
2181 changes to the *FP macros. Add DefaultSize to floating point control
2182 insns operating on larger memory ranges. Remove left over comments
2183 hinting at certain insns being Intel-syntax ones where the ones
2184 actually meant are already gone.
2185
48c9f030
NC		 21862004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2187
2188 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2189 instruction type.
2190
0dd132b6
NC		 21912004-09-30 Paul Brook <paul@codesourcery.com>
2192
2193 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2194 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2195
23794b24
MM		 21962004-09-11 Theodore A. Roth <troth@openavr.org>
2197
2198 * avr.h: Add support for
2199 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2200
2a309db0
AM		 22012004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2202
2203 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2204
b18c562e
NC		 22052004-08-24 Dmitry Diky <diwil@spec.ru>
2206
2207 * msp430.h (msp430_opc): Add new instructions.
2208 (msp430_rcodes): Declare new instructions.
2209 (msp430_hcodes): Likewise..
2210
45d313cd
NC		 22112004-08-13 Nick Clifton <nickc@redhat.com>
2212
2213 PR/301
2214 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2215 processors.
2216
30d1c836
ML		 22172004-08-30 Michal Ludvig <mludvig@suse.cz>
2218
2219 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2220
9a45f1c2
L		 22212004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2222
2223 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2224
543613e9
NC		 22252004-07-21 Jan Beulich <jbeulich@novell.com>
2226
2227 * i386.h: Adjust instruction descriptions to better match the
2228 specification.
2229
b781e558
RE		 22302004-07-16 Richard Earnshaw <rearnsha@arm.com>
2231
2232 * arm.h: Remove all old content. Replace with architecture defines
2233 from gas/config/tc-arm.c.
2234
8577e690
AS		 22352004-07-09 Andreas Schwab <schwab@suse.de>
2236
2237 * m68k.h: Fix comment.
2238
1fe1f39c
NC		 22392004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2240
2241 * crx.h: New file.
2242
1d9f512f
AM		 22432004-06-24 Alan Modra <amodra@bigpond.net.au>
2244
2245 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2246
be8c092b
NC		 22472004-05-24 Peter Barada <peter@the-baradas.com>
2248
2249 * m68k.h: Add 'size' to m68k_opcode.
2250
6b6e92f4
NC		 22512004-05-05 Peter Barada <peter@the-baradas.com>
2252
2253 * m68k.h: Switch from ColdFire chip name to core variant.
2254
22552004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2256
2257 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2258 descriptions for new EMAC cases.
2259 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2260 handle Motorola MAC syntax.
2261 Allow disassembly of ColdFire V4e object files.
2262
fdd12ef3
AM		 22632004-03-16 Alan Modra <amodra@bigpond.net.au>
2264
2265 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2266
3922a64c
L		 22672004-03-12 Jakub Jelinek <jakub@redhat.com>
2268
2269 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2270
1f45d988
ML		 22712004-03-12 Michal Ludvig <mludvig@suse.cz>
2272
2273 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2274
0f10071e
ML		 22752004-03-12 Michal Ludvig <mludvig@suse.cz>
2276
2277 * i386.h (i386_optab): Added xstore/xcrypt insns.
2278
3255318a
NC		 22792004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2280
2281 * h8300.h (32bit ldc/stc): Add relaxing support.
2282
ca9a79a1 22832004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2284
ca9a79a1
NC		 2285 * h8300.h (BITOP): Pass MEMRELAX flag.
2286
875a0b14
NC		 22872004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2288
2289 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2290 except for the H8S.
252b5132 2291
c9e214e5 2292For older changes see ChangeLog-9103
252b5132 2293\f
b90efa5b 2294Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2295
2296Copying and distribution of this file, with or without modification,
2297are permitted in any medium without royalty provided the copyright
2298notice and this notice are preserved.
2299
252b5132 2300Local Variables:
c9e214e5
AM		 2301mode: change-log
2302left-margin: 8
2303fill-column: 74
252b5132
RH		 2304version-control: never
2305End:
GDB Binutils - Deliverables
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