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Add support for RX V2 Instruction Set
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
3067d3b9
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (enum aarch64_opnd_qualifier): Add
4 AARCH64_OPND_QLF_V_2H.
5
a117b0a5
YS		 62015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
7
8 * rx.h: Add new instructions.
9
1e6f4800
MW		 102015-12-11 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
13 * aarch64-asm-2.c: Regenerate.
14 * aarch64-dis-2.c: Regenerate.
15 * aarch64-opc-2.c: Regenerate.
16 * aarch64-opc.c (aarch64_hint_options): Add "csync".
17 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
18 * aarch64-tbl.h (aarch64_feature_stat_profile): New.
19 (STAT_PROFILE): New.
20 (aarch64_opcode_table): Add "psb".
21 (AARCH64_OPERANDS): Add "BARRIER_PSB".
22
9ed608f9
MW		 232015-12-11 Matthew Wahab <matthew.wahab@arm.com>
24
25 * aarch64.h (aarch64_hint_options): Declare.
26 (aarch64_opnd_info): Add field hint_option.
27
73af8ed6
MW		 282015-12-11 Matthew Wahab <matthew.wahab@arm.com>
29
30 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
31
d6bf7ce6
MW		 322015-12-10 Matthew Wahab <matthew.wahab@arm.com>
33
34 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
35
ea2deeec
MW		 362015-12-10 Matthew Wahab <matthew.wahab@arm.com>
37
38 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
39 (aarch64_sys_ins_reg_has_xt): Declare.
40
c8a6db6f
MW		 412015-12-10 Matthew Wahab <matthew.wahab@arm.com>
42
43 * aarch64.h (AARCH64_FEATURE_RAS): New.
44 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
45
af117b3c
MW		 462015-12-10 Matthew Wahab <matthew.wahab@arm.com>
47
48 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
49 AARCH64_FEATURE_V8_1.
50 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
51 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
52 AARCH64_FEATURE_V8_1.
53
24b368f8
CZ		 542015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
55
56 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
57
d685192a
MW		 582015-11-27 Matthew Wahab <matthew.wahab@arm.com>
59
60 * aarch64.h (aarch64_op): Add OP_BFC.
61
87018195
MW		 622015-11-27 Matthew Wahab <matthew.wahab@arm.com>
63
64 * aarch64.h (AARCH64_FEATURE_F16): New.
65 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
66 features.
67
250aafa4
MW		 682015-11-20 Matthew Wahab <matthew.wahab@arm.com>
69
70 * aarch64.h (AARCH64_FEATURE_V8_1): New.
71 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
72
56a1b672
MW		 732015-11-19 Matthew Wahab <matthew.wahab@arm.com>
74
75 * arm.h (ARM_EXT2_V8_2A): New.
76 (ARM_ARCH_V8_2A): New.
77
acb787b0
MW		 782015-11-19 Matthew Wahab <matthew.wahab@arm.com>
79
80 * aarch64.h (AARCH64_FEATURE_V8_2): New.
81 (AARCH64_ARCH_V8_2): New.
82
a680de9a
PB		 832015-11-11 Alan Modra <amodra@gmail.com>
84 Peter Bergner <bergner@vnet.ibm.com>
85
86 * ppc.h (PPC_OPCODE_POWER9): New define.
87 (PPC_OPCODE_VSX3): Likewise.
88
854eb72b
NC		 892015-11-02 Nick Clifton <nickc@redhat.com>
90
91 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
92
e292aa7a
NC		 932015-11-02 Nick Clifton <nickc@redhat.com>
94
95 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
96
43cdf5ae
YQ		 972015-10-28 Yao Qi <yao.qi@linaro.org>
98
99 * aarch64.h (aarch64_decode_insn): Update declaration.
100
875880c6
YQ		 1012015-10-07 Yao Qi <yao.qi@linaro.org>
102
103 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
104 <name>: New field.
105
d3e12b29
YQ		 1062015-10-07 Yao Qi <yao.qi@linaro.org>
107
108 * aarch64.h [__cplusplus]: Wrap in extern "C".
109
886a2506
NC		 1102015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
111 Cupertino Miranda <cmiranda@synopsys.com>
112
113 * arc-func.h: New file.
114 * arc.h: Likewise.
115
e141d84e
YQ		 1162015-10-02 Yao Qi <yao.qi@linaro.org>
117
118 * aarch64.h (aarch64_zero_register_p): Move the declaration
119 to column one.
120
36f4aab1
YQ		 1212015-10-02 Yao Qi <yao.qi@linaro.org>
122
123 * aarch64.h (aarch64_decode_insn): Declare it.
124
7ecc513a
DV		 1252015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
126
127 * s390.h (S390_INSTR_FLAG_HTM): New flag.
128 (S390_INSTR_FLAG_VX): New flag.
129 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
130
b6518b38
NC		 1312015-09-23 Nick Clifton <nickc@redhat.com>
132
133 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
134 shifting.
135
f04265ec
NC		 1362015-09-22 Nick Clifton <nickc@redhat.com>
137
138 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
139
7bdf96ef
NC		 1402015-09-09 Daniel Santos <daniel.santos@pobox.com>
141
142 * visium.h (gen_reg_table): Make static.
143 (fp_reg_table): Likewise.
144 (cc_table): Likewise.
145
f33026a9
MW		 1462015-07-20 Matthew Wahab <matthew.wahab@arm.com>
147
148 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
149 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
150 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
151 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
152
ef5a96d5
AM		 1532015-07-03 Alan Modra <amodra@gmail.com>
154
155 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
156
c8c8175b
SL		 1572015-07-01 Sandra Loosemore <sandra@codesourcery.com>
158 Cesar Philippidis <cesar@codesourcery.com>
159
160 * nios2.h (enum iw_format_type): Add R2 formats.
161 (enum overflow_type): Add signed_immed12_overflow and
162 enumeration_overflow for R2.
163 (struct nios2_opcode): Document new argument letters for R2.
164 (REG_3BIT, REG_LDWM, REG_POP): Define.
165 (includes): Include nios2r2.h.
166 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
167 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
168 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
169 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
170 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
171 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
172 Declare.
173 * nios2r2.h: New file.
174
11a0cf2e
PB		 1752015-06-19 Peter Bergner <bergner@vnet.ibm.com>
176
177 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
178 (ppc_optional_operand_value): New inline function.
179
88f0ea34
MW		 1802015-06-04 Matthew Wahab <matthew.wahab@arm.com>
181
182 * aarch64.h (AARCH64_V8_1): New.
183
a5932920
MW		 1842015-06-03 Matthew Wahab <matthew.wahab@arm.com>
185
186 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
187 (ARM_ARCH_V8_1A): New.
188 (ARM_ARCH_V8_1A_FP): New.
189 (ARM_ARCH_V8_1A_SIMD): New.
190 (ARM_ARCH_V8_1A_CRYPTOV1): New.
191 (ARM_FEATURE_CORE): New.
192
ddfded2f
MW		 1932015-06-02 Matthew Wahab <matthew.wahab@arm.com>
194
195 * arm.h (ARM_EXT2_PAN): New.
196 (ARM_FEATURE_CORE_HIGH): New.
197
1af1dd51
MW		 1982015-06-02 Matthew Wahab <matthew.wahab@arm.com>
199
200 * arm.h (ARM_FEATURE_ALL): New.
201
9e1f0fa7
MW		 2022015-06-02 Matthew Wahab <matthew.wahab@arm.com>
203
204 * aarch64.h (AARCH64_FEATURE_RDMA): New.
205
290806fd
MW		 2062015-06-02 Matthew Wahab <matthew.wahab@arm.com>
207
208 * aarch64.h (AARCH64_FEATURE_LOR): New.
209
f21cce2c
MW		 2102015-06-01 Matthew Wahab <matthew.wahab@arm.com>
211
212 * aarch64.h (AARCH64_FEATURE_PAN): New.
213 (aarch64_sys_reg_supported_p): Declare.
214 (aarch64_pstatefield_supported_p): Declare.
215
0952813b
DD		 2162015-04-30 DJ Delorie <dj@redhat.com>
217
218 * rl78.h (RL78_Dis_Isa): New.
219 (rl78_decode_opcode): Add ISA parameter.
220
823d2571
TG		 2212015-03-24 Terry Guo <terry.guo@arm.com>
222
223 * arm.h (arm_feature_set): Extended to provide more available bits.
224 (ARM_ANY): Updated to follow above new definition.
225 (ARM_CPU_HAS_FEATURE): Likewise.
226 (ARM_CPU_IS_ANY): Likewise.
227 (ARM_MERGE_FEATURE_SETS): Likewise.
228 (ARM_CLEAR_FEATURE): Likewise.
229 (ARM_FEATURE): Likewise.
230 (ARM_FEATURE_COPY): New macro.
231 (ARM_FEATURE_EQUAL): Likewise.
232 (ARM_FEATURE_ZERO): Likewise.
233 (ARM_FEATURE_CORE_EQUAL): Likewise.
234 (ARM_FEATURE_LOW): Likewise.
235 (ARM_FEATURE_CORE_LOW): Likewise.
236 (ARM_FEATURE_CORE_COPROC): Likewise.
237
f63c1776
PA		 2382015-02-19 Pedro Alves <palves@redhat.com>
239
240 * cgen.h [__cplusplus]: Wrap in extern "C".
241 * msp430-decode.h [__cplusplus]: Likewise.
242 * nios2.h [__cplusplus]: Likewise.
243 * rl78.h [__cplusplus]: Likewise.
244 * rx.h [__cplusplus]: Likewise.
245 * tilegx.h [__cplusplus]: Likewise.
246
3f8107ab
AM		 2472015-01-28 James Bowman <james.bowman@ftdichip.com>
248
249 * ft32.h: New file.
250
1e2e8c52
AK		 2512015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
252
253 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
254
b90efa5b
AM		 2552015-01-01 Alan Modra <amodra@gmail.com>
256
257 Update year range in copyright notice of all files.
258
bffb6004
AG		 2592014-12-27 Anthony Green <green@moxielogic.com>
260
261 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
262 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
263
1945cfa5
EB		 2642014-12-06 Eric Botcazou <ebotcazou@adacore.com>
265
266 * visium.h: New file.
267
d306ce58
SL		 2682014-11-28 Sandra Loosemore <sandra@codesourcery.com>
269
270 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
271 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
272 (NIOS2_INSN_OPTARG): Renumber.
273
b4714c7c
SL		 2742014-11-06 Sandra Loosemore <sandra@codesourcery.com>
275
276 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
277 declaration. Fix obsolete comment.
278
96ba4233
SL		 2792014-10-23 Sandra Loosemore <sandra@codesourcery.com>
280
281 * nios2.h (enum iw_format_type): New.
282 (struct nios2_opcode): Update comments. Add size and format fields.
283 (NIOS2_INSN_OPTARG): New.
284 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
285 (struct nios2_reg): Add regtype field.
286 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
287 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
288 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
289 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
290 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
291 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
292 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
293 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
294 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
295 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
296 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
297 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
298 (OP_MASK_OP, OP_SH_OP): Delete.
299 (OP_MASK_IOP, OP_SH_IOP): Delete.
300 (OP_MASK_IRD, OP_SH_IRD): Delete.
301 (OP_MASK_IRT, OP_SH_IRT): Delete.
302 (OP_MASK_IRS, OP_SH_IRS): Delete.
303 (OP_MASK_ROP, OP_SH_ROP): Delete.
304 (OP_MASK_RRD, OP_SH_RRD): Delete.
305 (OP_MASK_RRT, OP_SH_RRT): Delete.
306 (OP_MASK_RRS, OP_SH_RRS): Delete.
307 (OP_MASK_JOP, OP_SH_JOP): Delete.
308 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
309 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
310 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
311 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
312 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
313 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
314 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
315 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
316 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
317 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
318 (OP_MASK_<insn>, OP_MASK): Delete.
319 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
320 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
321 Include nios2r1.h to define new instruction opcode constants
322 and accessors.
323 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
324 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
325 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
326 (NUMOPCODES, NUMREGISTERS): Delete.
327 * nios2r1.h: New file.
328
0b6be415
JM		 3292014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
330
331 * sparc.h (HWCAP2_VIS3B): Documentation improved.
332
3d68f91c
JM		 3332014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
334
335 * sparc.h (sparc_opcode): new field `hwcaps2'.
336 (HWCAP2_FJATHPLUS): New define.
337 (HWCAP2_VIS3B): Likewise.
338 (HWCAP2_ADP): Likewise.
339 (HWCAP2_SPARC5): Likewise.
340 (HWCAP2_MWAIT): Likewise.
341 (HWCAP2_XMPMUL): Likewise.
342 (HWCAP2_XMONT): Likewise.
343 (HWCAP2_NSEC): Likewise.
344 (HWCAP2_FJATHHPC): Likewise.
345 (HWCAP2_FJDES): Likewise.
346 (HWCAP2_FJAES): Likewise.
347 Document the new operand kind `{', corresponding to the mcdper
348 ancillary state register.
349 Document the new operand kind }, which represents frsd floating
350 point registers (double precision) which must be the same than
351 frs1 in its containing instruction.
352
40c7a7cb
KLC		 3532014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
354
72f4393d 355 * nds32.h: Add new opcode declaration.
40c7a7cb 356
7361da2c
AB		 3572014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
358 Matthew Fortune <matthew.fortune@imgtec.com>
359
360 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
361 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
362 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
363 +I, +O, +R, +:, +\, +", +;
364 (mips_check_prev_operand): New struct.
365 (INSN2_FORBIDDEN_SLOT): New define.
366 (INSN_ISA32R6): New define.
367 (INSN_ISA64R6): New define.
368 (INSN_UPTO32R6): New define.
369 (INSN_UPTO64R6): New define.
370 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
371 (ISA_MIPS32R6): New define.
372 (ISA_MIPS64R6): New define.
373 (CPU_MIPS32R6): New define.
374 (CPU_MIPS64R6): New define.
375 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
376
ee804238
JW		 3772014-09-03 Jiong Wang <jiong.wang@arm.com>
378
379 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
380 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
381 (aarch64_insn_class): Add lse_atomic.
382 (F_LSE_SZ): New field added.
383 (opcode_has_special_coder): Recognize F_LSE_SZ.
384
5575639b
MR		 3852014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
386
387 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
388 over to `+J'.
389
43885403
MF		 3902014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
391
392 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
393 (INSN_LOAD_COPROC): New define.
394 (INSN_COPROC_MOVE_DELAY): Rename to...
395 (INSN_COPROC_MOVE): New define.
396
f36e8886 3972014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 398 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
399 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
400 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 401
402 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
403 (AVR_ISA_2xxxa): Define ISA without LPM.
404 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
405 Add doc for contraint used in 16 bit lds/sts.
406 Adjust ISA group for icall, ijmp, pop and push.
407 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
408
00b32ff2
NC		 4092014-05-19 Nick Clifton <nickc@redhat.com>
410
411 * msp430.h (struct msp430_operand_s): Add vshift field.
412
ae52f483
AB		 4132014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
414
415 * mips.h (INSN_ISA_MASK): Updated.
416 (INSN_ISA32R3): New define.
417 (INSN_ISA32R5): New define.
418 (INSN_ISA64R3): New define.
419 (INSN_ISA64R5): New define.
420 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
421 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
422 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
423 mips64r5.
424 (INSN_UPTO32R3): New define.
425 (INSN_UPTO32R5): New define.
426 (INSN_UPTO64R3): New define.
427 (INSN_UPTO64R5): New define.
428 (ISA_MIPS32R3): New define.
429 (ISA_MIPS32R5): New define.
430 (ISA_MIPS64R3): New define.
431 (ISA_MIPS64R5): New define.
432 (CPU_MIPS32R3): New define.
433 (CPU_MIPS32R5): New define.
434 (CPU_MIPS64R3): New define.
435 (CPU_MIPS64R5): New define.
436
3efe9ec5
RS		 4372014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
438
439 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
440
73589c9d
CS		 4412014-04-22 Christian Svensson <blue@cmd.nu>
442
443 * or32.h: Delete.
444
4b95cf5c
AM		 4452014-03-05 Alan Modra <amodra@gmail.com>
446
447 Update copyright years.
448
e269fea7
AB		 4492013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
450
451 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
452 microMIPS.
453
35c08157
KLC		 4542013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
455 Wei-Cheng Wang <cole945@gmail.com>
456
457 * nds32.h: New file for Andes NDS32.
458
594d8fa8
MF		 4592013-12-07 Mike Frysinger <vapier@gentoo.org>
460
461 * bfin.h: Remove +x file mode.
462
87b8eed7
YZ		 4632013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
464
465 * aarch64.h (aarch64_pstatefields): Change element type to
466 aarch64_sys_reg.
467
c9fb6e58
YZ		 4682013-11-18 Renlin Li <Renlin.Li@arm.com>
469
470 * arm.h (ARM_AEXT_V7VE): New define.
471 (ARM_ARCH_V7VE): New define.
472 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
473
a203d9b7
YZ		 4742013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
475
476 Revert
477
478 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
479
480 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
481 (aarch64_sys_reg_writeonly_p): Ditto.
482
75468c93
YZ		 4832013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
484
485 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
486 (aarch64_sys_reg_writeonly_p): Ditto.
487
49eec193
YZ		 4882013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
489
490 * aarch64.h (aarch64_sys_reg): New typedef.
491 (aarch64_sys_regs): Change to define with the new type.
492 (aarch64_sys_reg_deprecated_p): Declare.
493
68a64283
YZ		 4942013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
495
496 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
497 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
498
387a82f1
CF		 4992013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
500
501 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
502 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
503 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
504 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
505 For MIPS, update extension character sequences after +.
506 (ASE_MSA): New define.
507 (ASE_MSA64): New define.
508 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
509 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
510 For microMIPS, update extension character sequences after +.
511
9aff4b7a
NC		 5122013-08-23 Yuri Chornoivan <yurchor@ukr.net>
513
514 PR binutils/15834
515 * i960.h: Fix typos.
516
e423441d
RS		 5172013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
518
519 * mips.h: Remove references to "+I" and imm2_expr.
520
5e0dc5ba
RS		 5212013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
522
523 * mips.h (M_DEXT, M_DINS): Delete.
524
0f35dbc4
RS		 5252013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
526
527 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
528 (mips_optional_operand_p): New function.
529
14daeee3
RS		 5302013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
531 Richard Sandiford <rdsandiford@googlemail.com>
532
533 * mips.h: Document new VU0 operand characters.
534 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
535 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
536 (OP_REG_R5900_ACC): New mips_reg_operand_types.
537 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
538 (mips_vu0_channel_mask): Declare.
539
3ccad066
RS		 5402013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
541
542 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
543 (mips_int_operand_min, mips_int_operand_max): New functions.
544 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
545
fc76e730
RS		 5462013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
547
548 * mips.h (mips_decode_reg_operand): New function.
549 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
550 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
551 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
552 New macros.
553 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
554 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
555 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
556 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
557 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
558 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
559 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
560 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
561 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
562 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
563 macros to cover the gaps.
564 (INSN2_MOD_SP): Replace with...
565 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
566 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
567 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
568 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
569 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
570 Delete.
571
26545944
RS		 5722013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
573
574 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
575 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
576 (MIPS16_INSN_COND_BRANCH): Delete.
577
7e8b059b
L		 5782013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
579 Kirill Yukhin <kirill.yukhin@intel.com>
580 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
581
582 * i386.h (BND_PREFIX_OPCODE): New.
583
c3c07478
RS		 5842013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
585
586 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
587 OP_SAVE_RESTORE_LIST.
588 (decode_mips16_operand): Declare.
589
ab902481
RS		 5902013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
591
592 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
593 (mips_operand, mips_int_operand, mips_mapped_int_operand)
594 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
595 (mips_pcrel_operand): New structures.
596 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
597 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
598 (decode_mips_operand, decode_micromips_operand): Declare.
599
cc537e56
RS		 6002013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
601
602 * mips.h: Document MIPS16 "I" opcode.
603
f2ae14a1
RS		 6042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
605
606 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
607 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
608 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
609 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
610 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
611 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
612 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
613 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
614 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
615 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
616 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
617 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
618 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
619 Rename to...
620 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
621 (M_USD_AB): ...these.
622
5c324c16
RS		 6232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
624
625 * mips.h: Remove documentation of "[" and "]". Update documentation
626 of "k" and the MDMX formats.
627
23e69e47
RS		 6282013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
629
630 * mips.h: Update documentation of "+s" and "+S".
631
27c5c572
RS		 6322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
633
634 * mips.h: Document "+i".
635
e76ff5ab
RS		 6362013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
637
638 * mips.h: Remove "mi" documentation. Update "mh" documentation.
639 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
640 Delete.
641 (INSN2_WRITE_GPR_MHI): Rename to...
642 (INSN2_WRITE_GPR_MH): ...this.
643
fa7616a4
RS		 6442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
645
646 * mips.h: Remove documentation of "+D" and "+T".
647
18870af7
RS		 6482013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
649
650 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
651 Use "source" rather than "destination" for microMIPS "G".
652
833794fc
MR		 6532013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
654
655 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
656 values.
657
c3678916
RS		 6582013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
659
660 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
661
7f3c4072
CM		 6622013-06-17 Catherine Moore <clm@codesourcery.com>
663 Maciej W. Rozycki <macro@codesourcery.com>
664 Chao-Ying Fu <fu@mips.com>
665
666 * mips.h (OP_SH_EVAOFFSET): Define.
667 (OP_MASK_EVAOFFSET): Define.
668 (INSN_ASE_MASK): Delete.
669 (ASE_EVA): Define.
670 (M_CACHEE_AB, M_CACHEE_OB): New.
671 (M_LBE_OB, M_LBE_AB): New.
672 (M_LBUE_OB, M_LBUE_AB): New.
673 (M_LHE_OB, M_LHE_AB): New.
674 (M_LHUE_OB, M_LHUE_AB): New.
675 (M_LLE_AB, M_LLE_OB): New.
676 (M_LWE_OB, M_LWE_AB): New.
677 (M_LWLE_AB, M_LWLE_OB): New.
678 (M_LWRE_AB, M_LWRE_OB): New.
679 (M_PREFE_AB, M_PREFE_OB): New.
680 (M_SCE_AB, M_SCE_OB): New.
681 (M_SBE_OB, M_SBE_AB): New.
682 (M_SHE_OB, M_SHE_AB): New.
683 (M_SWE_OB, M_SWE_AB): New.
684 (M_SWLE_AB, M_SWLE_OB): New.
685 (M_SWRE_AB, M_SWRE_OB): New.
686 (MICROMIPSOP_SH_EVAOFFSET): Define.
687 (MICROMIPSOP_MASK_EVAOFFSET): Define.
688
0c8fe7cf
SL		 6892013-06-12 Sandra Loosemore <sandra@codesourcery.com>
690
691 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
692
c77c0862
RS		 6932013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
694
695 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
696
b015e599
AP		 6972013-05-09 Andrew Pinski <apinski@cavium.com>
698
699 * mips.h (OP_MASK_CODE10): Correct definition.
700 (OP_SH_CODE10): Likewise.
701 Add a comment that "+J" is used now for OP_*CODE10.
702 (INSN_ASE_MASK): Update.
703 (INSN_VIRT): New macro.
704 (INSN_VIRT64): New macro
705
13761a11
NC		 7062013-05-02 Nick Clifton <nickc@redhat.com>
707
708 * msp430.h: Add patterns for MSP430X instructions.
709
0afd1215
DM		 7102013-04-06 David S. Miller <davem@davemloft.net>
711
712 * sparc.h (F_PREFERRED): Define.
713 (F_PREF_ALIAS): Define.
714
41702d50
NC		 7152013-04-03 Nick Clifton <nickc@redhat.com>
716
717 * v850.h (V850_INVERSE_PCREL): Define.
718
e21e1a51
NC		 7192013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
720
721 PR binutils/15068
722 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
723
51dcdd4d
NC		 7242013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
725
726 PR binutils/15068
727 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
728 Add 16-bit opcodes.
729 * tic6xc-opcode-table.h: Add 16-bit insns.
730 * tic6x.h: Add support for 16-bit insns.
731
81f5558e
NC		 7322013-03-21 Michael Schewe <michael.schewe@gmx.net>
733
734 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
735 and mov.b/w/l Rs,@(d:32,ERd).
736
165546ad
NC		 7372013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
738
739 PR gas/15082
740 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
741 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
742 tic6x_operand_xregpair operand coding type.
743 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
744 opcode field, usu ORXREGD1324 for the src2 operand and remove the
745 TIC6X_FLAG_NO_CROSS.
746
795b8e6b
NC		 7472013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
748
749 PR gas/15095
750 * tic6x.h (enum tic6x_coding_method): Add
751 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
752 separately the msb and lsb of a register pair. This is needed to
753 encode the opcodes in the same way as TI assembler does.
754 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
755 and rsqrdp opcodes to use the new field coding types.
756
dd5181d5
KT		 7572013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
758
759 * arm.h (CRC_EXT_ARMV8): New constant.
760 (ARCH_CRC_ARMV8): New macro.
761
e60bb1dd
YZ		 7622013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
763
764 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
765
36591ba1 7662013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 767 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 768
769 Based on patches from Altera Corporation.
770
771 * nios2.h: New file.
772
e30181a5
YZ		 7732013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
774
775 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
776
0c9573f4
NC		 7772013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
778
779 PR gas/15069
780 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
781
981dc7f1
NC		 7822013-01-24 Nick Clifton <nickc@redhat.com>
783
784 * v850.h: Add e3v5 support.
785
f5555712
YZ		 7862013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
787
788 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
789
5817ffd1
PB		 7902013-01-10 Peter Bergner <bergner@vnet.ibm.com>
791
792 * ppc.h (PPC_OPCODE_POWER8): New define.
793 (PPC_OPCODE_HTM): Likewise.
794
a3c62988
NC		 7952013-01-10 Will Newton <will.newton@imgtec.com>
796
797 * metag.h: New file.
798
73335eae
NC		 7992013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
800
801 * cr16.h (make_instruction): Rename to cr16_make_instruction.
802 (match_opcode): Rename to cr16_match_opcode.
803
e407c74b
NC		 8042013-01-04 Juergen Urban <JuergenUrban@gmx.de>
805
806 * mips.h: Add support for r5900 instructions including lq and sq.
807
bab4becb
NC		 8082013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
809
810 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
811 (make_instruction,match_opcode): Added function prototypes.
812 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
813
776fc418
AM		 8142012-11-23 Alan Modra <amodra@gmail.com>
815
816 * ppc.h (ppc_parse_cpu): Update prototype.
817
f05682d4
DA		 8182012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
819
820 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
821 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
822
cfc72779
AK		 8232012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
824
825 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
826
b3e14eda
L		 8272012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
828
829 * ia64.h (ia64_opnd): Add new operand types.
830
2c63854f
DM		 8312012-08-21 David S. Miller <davem@davemloft.net>
832
833 * sparc.h (F3F4): New macro.
834
a06ea964 8352012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 836 Laurent Desnogues <laurent.desnogues@arm.com>
837 Jim MacArthur <jim.macarthur@arm.com>
838 Marcus Shawcroft <marcus.shawcroft@arm.com>
839 Nigel Stephens <nigel.stephens@arm.com>
840 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
841 Richard Earnshaw <rearnsha@arm.com>
842 Sofiane Naci <sofiane.naci@arm.com>
843 Tejas Belagod <tejas.belagod@arm.com>
844 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 845
846 * aarch64.h: New file.
847
35d0a169 8482012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 849 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 850
851 * mips.h (mips_opcode): Add the exclusions field.
852 (OPCODE_IS_MEMBER): Remove macro.
853 (cpu_is_member): New inline function.
854 (opcode_is_member): Likewise.
855
03f66e8a 8562012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 857 Catherine Moore <clm@codesourcery.com>
858 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 859
860 * mips.h: Document microMIPS DSP ASE usage.
861 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
862 microMIPS DSP ASE support.
863 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
864 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
865 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
866 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
867 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
868 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
869 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
870
9d7b4c23
MR		 8712012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
872
873 * mips.h: Fix a typo in description.
874
76e879f8
NC		 8752012-06-07 Georg-Johann Lay <avr@gjlay.de>
876
877 * avr.h: (AVR_ISA_XCH): New define.
878 (AVR_ISA_XMEGA): Use it.
879 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
880
6927f982
NC		 8812012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
882
883 * m68hc11.h: Add XGate definitions.
884 (struct m68hc11_opcode): Add xg_mask field.
885
b9c361e0
JL		 8862012-05-14 Catherine Moore <clm@codesourcery.com>
887 Maciej W. Rozycki <macro@codesourcery.com>
888 Rhonda Wittels <rhonda@codesourcery.com>
889
6927f982 890 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 891 (PPC_OP_SA): New macro.
892 (PPC_OP_SE_VLE): New macro.
893 (PPC_OP): Use a variable shift amount.
894 (powerpc_operand): Update comments.
895 (PPC_OPSHIFT_INV): New macro.
896 (PPC_OPERAND_CR): Replace with...
897 (PPC_OPERAND_CR_BIT): ...this and
898 (PPC_OPERAND_CR_REG): ...this.
899
900
f6c1a2d5
NC		 9012012-05-03 Sean Keys <skeys@ipdatasys.com>
902
903 * xgate.h: Header file for XGATE assembler.
904
ec668d69
DM		 9052012-04-27 David S. Miller <davem@davemloft.net>
906
6cda1326
DM		 907 * sparc.h: Document new arg code' )' for crypto RS3
908 immediates.
909
ec668d69
DM		 910 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
911 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
912 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
913 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
914 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
915 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
916 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
917 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
918 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
919 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
920 HWCAP_CBCOND, HWCAP_CRC32): New defines.
921
aea77599
AM		 9222012-03-10 Edmar Wienskoski <edmar@freescale.com>
923
924 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
925
1f42f8b3
AM		 9262012-02-27 Alan Modra <amodra@gmail.com>
927
928 * crx.h (cst4_map): Update declaration.
929
6f7be959
WL		 9302012-02-25 Walter Lee <walt@tilera.com>
931
932 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
933 TILEGX_OPC_LD_TLS.
934 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
935 TILEPRO_OPC_LW_TLS_SN.
936
42164a71
L		 9372012-02-08 H.J. Lu <hongjiu.lu@intel.com>
938
939 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
940 (XRELEASE_PREFIX_OPCODE): Likewise.
941
432233b3 9422011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 943 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 944
945 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
946 (INSN_OCTEON2): New macro.
947 (CPU_OCTEON2): New macro.
948 (OPCODE_IS_MEMBER): Add Octeon2.
949
dd6a37e7
AP		 9502011-11-29 Andrew Pinski <apinski@cavium.com>
951
952 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
953 (INSN_OCTEONP): New macro.
954 (CPU_OCTEONP): New macro.
955 (OPCODE_IS_MEMBER): Add Octeon+.
956 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
957
99c513f6
DD		 9582011-11-01 DJ Delorie <dj@redhat.com>
959
960 * rl78.h: New file.
961
26f85d7a
MR		 9622011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
963
964 * mips.h: Fix a typo in description.
965
9e8c70f9
DM		 9662011-09-21 David S. Miller <davem@davemloft.net>
967
968 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
969 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
970 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
971 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
972
dec0624d 9732011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 974 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 975
976 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
977 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
978 (INSN_ASE_MASK): Add the MCU bit.
979 (INSN_MCU): New macro.
980 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
981 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
982
2b0c8b40
MR		 9832011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
984
985 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
986 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
987 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
988 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
989 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
990 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
991 (INSN2_READ_GPR_MMN): Likewise.
992 (INSN2_READ_FPR_D): Change the bit used.
993 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
994 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
995 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
996 (INSN2_COND_BRANCH): Likewise.
997 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
998 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
999 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
1000 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
1001 (INSN2_MOD_GPR_MN): Likewise.
1002
ea783ef3
DM		 10032011-08-05 David S. Miller <davem@davemloft.net>
1004
1005 * sparc.h: Document new format codes '4', '5', and '('.
1006 (OPF_LOW4, RS3): New macros.
1007
7c176fa8
MR		 10082011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
1009
1010 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
1011 order of flags documented.
1012
2309ddf2
MR		 10132011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
1014
1015 * mips.h: Clarify the description of microMIPS instruction
1016 manipulation macros.
1017 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1018
df58fc94 10192011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 1020 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 1021
1022 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1023 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1024 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1025 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1026 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1027 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1028 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1029 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1030 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1031 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1032 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1033 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1034 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1035 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1036 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1037 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1038 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1039 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1040 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1041 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1042 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1043 (INSN_WRITE_GPR_S): New macro.
1044 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1045 (INSN2_READ_FPR_D): Likewise.
1046 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1047 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1048 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1049 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1050 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1051 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1052 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1053 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1054 (CPU_MICROMIPS): New macro.
1055 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1056 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1057 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1058 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1059 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1060 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1061 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1062 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1063 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1064 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1065 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1066 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1067 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1068 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1069 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1070 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1071 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1072 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1073 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1074 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1075 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1076 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1077 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1078 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1079 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1080 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1081 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1082 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1083 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1084 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1085 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1086 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1087 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1088 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1089 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1090 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1091 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1092 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1093 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1094 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1095 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1096 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1097 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1098 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1099 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1100 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1101 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1102 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1103 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1104 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1105 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1106 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1107 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1108 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1109 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1110 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1111 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1112 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1113 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1114 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1115 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1116 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1117 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1118 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1119 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1120 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1121 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1122 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1123 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1124 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1125 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1126 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1127 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1128 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1129 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1130 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1131 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1132 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1133 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1134 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1135 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1136 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1137 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1138 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1139 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1140 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1141 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1142 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1143 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1144 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1145 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1146 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1147 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1148 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1149 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1150 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1151 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1152 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1153 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1154 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1155 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1156 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1157 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1158 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1159 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1160 (micromips_opcodes): New declaration.
1161 (bfd_micromips_num_opcodes): Likewise.
1162
bcd530a7
RS		 11632011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1164
1165 * mips.h (INSN_TRAP): Rename to...
1166 (INSN_NO_DELAY_SLOT): ... this.
1167 (INSN_SYNC): Remove macro.
1168
2dad5a91
EW		 11692011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1170
1171 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1172 a duplicate of AVR_ISA_SPM.
1173
5d73b1f1
NC		 11742011-07-01 Nick Clifton <nickc@redhat.com>
1175
1176 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1177
ef26d60e
MF		 11782011-06-18 Robin Getz <robin.getz@analog.com>
1179
1180 * bfin.h (is_macmod_signed): New func
1181
8fb8dca7
MF		 11822011-06-18 Mike Frysinger <vapier@gentoo.org>
1183
1184 * bfin.h (is_macmod_pmove): Add missing space before func args.
1185 (is_macmod_hmove): Likewise.
1186
aa137e4d
NC		 11872011-06-13 Walter Lee <walt@tilera.com>
1188
1189 * tilegx.h: New file.
1190 * tilepro.h: New file.
1191
3b2f0793
PB		 11922011-05-31 Paul Brook <paul@codesourcery.com>
1193
aa137e4d
NC		 1194 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1195
11962011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1197
1198 * s390.h: Replace S390_OPERAND_REG_EVEN with
1199 S390_OPERAND_REG_PAIR.
1200
12012011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1202
1203 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1204
ac7f631b
NC		 12052011-04-18 Julian Brown <julian@codesourcery.com>
1206
1207 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1208
84701018
NC		 12092011-04-11 Dan McDonald <dan@wellkeeper.com>
1210
1211 PR gas/12296
1212 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1213
8cc66334
EW		 12142011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1215
1216 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1217 New instruction set flags.
1218 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1219
3eebd5eb
MR		 12202011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1221
1222 * mips.h (M_PREF_AB): New enum value.
1223
26bb3ddd
MF		 12242011-02-12 Mike Frysinger <vapier@gentoo.org>
1225
89c0d58c
MR		 1226 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1227 M_IU): Define.
1228 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1229
dd76fcb8
MF		 12302011-02-11 Mike Frysinger <vapier@gentoo.org>
1231
1232 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1233
98d23bef
BS		 12342011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1235
1236 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1237 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1238
3c853d93
DA		 12392010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1240
1241 PR gas/11395
1242 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1243 "bb" entries.
1244
79676006
DA		 12452010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1246
1247 PR gas/11395
1248 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1249
1bec78e9
RS		 12502010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1251
1252 * mips.h: Update commentary after last commit.
1253
98675402
RS		 12542010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1255
1256 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1257 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1258 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1259
aa137e4d
NC		 12602010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1261
1262 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1263
435b94a4
RS		 12642010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1265
1266 * mips.h: Fix previous commit.
1267
d051516a
NC		 12682010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1269
1270 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1271 (INSN_LOONGSON_3A): Clear bit 31.
1272
251665fc
MGD		 12732010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1274
1275 PR gas/12198
1276 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1277 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1278 (ARM_ARCH_V6M_ONLY): New define.
1279
fd503541
NC		 12802010-11-11 Mingming Sun <mingm.sun@gmail.com>
1281
1282 * mips.h (INSN_LOONGSON_3A): Defined.
1283 (CPU_LOONGSON_3A): Defined.
1284 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1285
4469d2be
AM		 12862010-10-09 Matt Rice <ratmice@gmail.com>
1287
1288 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1289 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1290
90ec0d68
MGD		 12912010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1292
1293 * arm.h (ARM_EXT_VIRT): New define.
1294 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1295 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1296 Extensions.
1297
eea54501 12982010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1299
eea54501
MGD		 1300 * arm.h (ARM_AEXT_ADIV): New define.
1301 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1302
b2a5fbdc
MGD		 13032010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1304
1305 * arm.h (ARM_EXT_OS): New define.
1306 (ARM_AEXT_V6SM): Likewise.
1307 (ARM_ARCH_V6SM): Likewise.
1308
60e5ef9f
MGD		 13092010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1310
1311 * arm.h (ARM_EXT_MP): Add.
1312 (ARM_ARCH_V7A_MP): Likewise.
1313
73a63ccf
MF		 13142010-09-22 Mike Frysinger <vapier@gentoo.org>
1315
1316 * bfin.h: Declare pseudoChr structs/defines.
1317
ee99860a
MF		 13182010-09-21 Mike Frysinger <vapier@gentoo.org>
1319
1320 * bfin.h: Strip trailing whitespace.
1321
f9c7014e
DD		 13222010-07-29 DJ Delorie <dj@redhat.com>
1323
1324 * rx.h (RX_Operand_Type): Add TwoReg.
1325 (RX_Opcode_ID): Remove ediv and ediv2.
1326
93378652
DD		 13272010-07-27 DJ Delorie <dj@redhat.com>
1328
1329 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1330
1cd986c5
NC		 13312010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1332 Ina Pandit <ina.pandit@kpitcummins.com>
1333
1334 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1335 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1336 PROCESSOR_V850E2_ALL.
1337 Remove PROCESSOR_V850EA support.
1338 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1339 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1340 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1341 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1342 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1343 V850_OPERAND_PERCENT.
1344 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1345 V850_NOT_R0.
1346 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1347 and V850E_PUSH_POP
1348
9a2c7088
MR		 13492010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1350
1351 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1352 (MIPS16_INSN_BRANCH): Rename to...
1353 (MIPS16_INSN_COND_BRANCH): ... this.
1354
bdc70b4a
AM		 13552010-07-03 Alan Modra <amodra@gmail.com>
1356
1357 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1358 Renumber other PPC_OPCODE defines.
1359
f2bae120
AM		 13602010-07-03 Alan Modra <amodra@gmail.com>
1361
1362 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1363
360cfc9c
AM		 13642010-06-29 Alan Modra <amodra@gmail.com>
1365
1366 * maxq.h: Delete file.
1367
e01d869a
AM		 13682010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1369
1370 * ppc.h (PPC_OPCODE_E500): Define.
1371
f79e2745
CM		 13722010-05-26 Catherine Moore <clm@codesourcery.com>
1373
1374 * opcode/mips.h (INSN_MIPS16): Remove.
1375
2462afa1
JM		 13762010-04-21 Joseph Myers <joseph@codesourcery.com>
1377
1378 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1379
e4e42b45
NC		 13802010-04-15 Nick Clifton <nickc@redhat.com>
1381
1382 * alpha.h: Update copyright notice to use GPLv3.
1383 * arc.h: Likewise.
1384 * arm.h: Likewise.
1385 * avr.h: Likewise.
1386 * bfin.h: Likewise.
1387 * cgen.h: Likewise.
1388 * convex.h: Likewise.
1389 * cr16.h: Likewise.
1390 * cris.h: Likewise.
1391 * crx.h: Likewise.
1392 * d10v.h: Likewise.
1393 * d30v.h: Likewise.
1394 * dlx.h: Likewise.
1395 * h8300.h: Likewise.
1396 * hppa.h: Likewise.
1397 * i370.h: Likewise.
1398 * i386.h: Likewise.
1399 * i860.h: Likewise.
1400 * i960.h: Likewise.
1401 * ia64.h: Likewise.
1402 * m68hc11.h: Likewise.
1403 * m68k.h: Likewise.
1404 * m88k.h: Likewise.
1405 * maxq.h: Likewise.
1406 * mips.h: Likewise.
1407 * mmix.h: Likewise.
1408 * mn10200.h: Likewise.
1409 * mn10300.h: Likewise.
1410 * msp430.h: Likewise.
1411 * np1.h: Likewise.
1412 * ns32k.h: Likewise.
1413 * or32.h: Likewise.
1414 * pdp11.h: Likewise.
1415 * pj.h: Likewise.
1416 * pn.h: Likewise.
1417 * ppc.h: Likewise.
1418 * pyr.h: Likewise.
1419 * rx.h: Likewise.
1420 * s390.h: Likewise.
1421 * score-datadep.h: Likewise.
1422 * score-inst.h: Likewise.
1423 * sparc.h: Likewise.
1424 * spu-insns.h: Likewise.
1425 * spu.h: Likewise.
1426 * tic30.h: Likewise.
1427 * tic4x.h: Likewise.
1428 * tic54x.h: Likewise.
1429 * tic80.h: Likewise.
1430 * v850.h: Likewise.
1431 * vax.h: Likewise.
1432
40b36596
JM		 14332010-03-25 Joseph Myers <joseph@codesourcery.com>
1434
1435 * tic6x-control-registers.h, tic6x-insn-formats.h,
1436 tic6x-opcode-table.h, tic6x.h: New.
1437
c67a084a
NC		 14382010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1439
1440 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1441
466ef64f
AM		 14422010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1443
1444 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1445
1319d143
L		 14462010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1447
1448 * ia64.h (ia64_find_opcode): Remove argument name.
1449 (ia64_find_next_opcode): Likewise.
1450 (ia64_dis_opcode): Likewise.
1451 (ia64_free_opcode): Likewise.
1452 (ia64_find_dependency): Likewise.
1453
1fbb9298
DE		 14542009-11-22 Doug Evans <dje@sebabeach.org>
1455
1456 * cgen.h: Include bfd_stdint.h.
1457 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1458
ada65aa3
PB		 14592009-11-18 Paul Brook <paul@codesourcery.com>
1460
1461 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1462
9e3c6df6
PB		 14632009-11-17 Paul Brook <paul@codesourcery.com>
1464 Daniel Jacobowitz <dan@codesourcery.com>
1465
1466 * arm.h (ARM_EXT_V6_DSP): Define.
1467 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1468 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1469
0d734b5d
DD		 14702009-11-04 DJ Delorie <dj@redhat.com>
1471
1472 * rx.h (rx_decode_opcode) (mvtipl): Add.
1473 (mvtcp, mvfcp, opecp): Remove.
1474
62f3b8c8
PB		 14752009-11-02 Paul Brook <paul@codesourcery.com>
1476
1477 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1478 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1479 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1480 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1481 FPU_ARCH_NEON_VFP_V4): Define.
1482
ac1e9eca
DE		 14832009-10-23 Doug Evans <dje@sebabeach.org>
1484
1485 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1486 * cgen.h: Update. Improve multi-inclusion macro name.
1487
9fe54b1c
PB		 14882009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1489
1490 * ppc.h (PPC_OPCODE_476): Define.
1491
634b50f2
PB		 14922009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1493
1494 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1495
c7927a3c
NC		 14962009-09-29 DJ Delorie <dj@redhat.com>
1497
1498 * rx.h: New file.
1499
b961e85b
AM		 15002009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1501
1502 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1503
e0d602ec
BE		 15042009-09-21 Ben Elliston <bje@au.ibm.com>
1505
1506 * ppc.h (PPC_OPCODE_PPCA2): New.
1507
96d56e9f
NC		 15082009-09-05 Martin Thuresson <martin@mtme.org>
1509
1510 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1511
d3ce72d0
NC		 15122009-08-29 Martin Thuresson <martin@mtme.org>
1513
1514 * tic30.h (template): Rename type template to
1515 insn_template. Updated code to use new name.
1516 * tic54x.h (template): Rename type template to
1517 insn_template.
1518
824b28db
NH		 15192009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1520
1521 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1522
f865a31d
AG		 15232009-06-11 Anthony Green <green@moxielogic.com>
1524
1525 * moxie.h (MOXIE_F3_PCREL): Define.
1526 (moxie_form3_opc_info): Grow.
1527
0e7c7f11
AG		 15282009-06-06 Anthony Green <green@moxielogic.com>
1529
1530 * moxie.h (MOXIE_F1_M): Define.
1531
20135e4c
NC		 15322009-04-15 Anthony Green <green@moxielogic.com>
1533
1534 * moxie.h: Created.
1535
bcb012d3
DD		 15362009-04-06 DJ Delorie <dj@redhat.com>
1537
1538 * h8300.h: Add relaxation attributes to MOVA opcodes.
1539
69fe9ce5
AM		 15402009-03-10 Alan Modra <amodra@bigpond.net.au>
1541
1542 * ppc.h (ppc_parse_cpu): Declare.
1543
c3b7224a
NC		 15442009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1545
1546 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1547 and _IMM11 for mbitclr and mbitset.
1548 * score-datadep.h: Update dependency information.
1549
066be9f7
PB		 15502009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1551
1552 * ppc.h (PPC_OPCODE_POWER7): New.
1553
fedc618e
DE		 15542009-02-06 Doug Evans <dje@google.com>
1555
1556 * i386.h: Add comment regarding sse* insns and prefixes.
1557
52b6b6b9
JM		 15582009-02-03 Sandip Matte <sandip@rmicorp.com>
1559
1560 * mips.h (INSN_XLR): Define.
1561 (INSN_CHIP_MASK): Update.
1562 (CPU_XLR): Define.
1563 (OPCODE_IS_MEMBER): Update.
1564 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1565
35669430
DE		 15662009-01-28 Doug Evans <dje@google.com>
1567
1568 * opcode/i386.h: Add multiple inclusion protection.
1569 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1570 (EDI_REG_NUM): New macros.
1571 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1572 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1573 (REX_PREFIX_P): New macro.
35669430 1574
1cb0a767
PB		 15752009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1576
1577 * ppc.h (struct powerpc_opcode): New field "deprecated".
1578 (PPC_OPCODE_NOPOWER4): Delete.
1579
3aa3176b
TS		 15802008-11-28 Joshua Kinard <kumba@gentoo.org>
1581
1582 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1583 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1584
8e79c3df
CM		 15852008-11-18 Catherine Moore <clm@codesourcery.com>
1586
1587 * arm.h (FPU_NEON_FP16): New.
1588 (FPU_ARCH_NEON_FP16): New.
1589
de9a3e51
CF		 15902008-11-06 Chao-ying Fu <fu@mips.com>
1591
1592 * mips.h: Doucument '1' for 5-bit sync type.
1593
1ca35711
L		 15942008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1595
1596 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1597 IA64_RS_CR.
1598
9b4e5766
PB		 15992008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1600
1601 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1602
081ba1b3
AM		 16032008-07-30 Michael J. Eager <eager@eagercon.com>
1604
1605 * ppc.h (PPC_OPCODE_405): Define.
1606 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1607
fa452fa6
PB		 16082008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1609
1610 * ppc.h (ppc_cpu_t): New typedef.
1611 (struct powerpc_opcode <flags>): Use it.
1612 (struct powerpc_operand <insert, extract>): Likewise.
1613 (struct powerpc_macro <flags>): Likewise.
1614
bb35fb24
NC		 16152008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1616
1617 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1618 Update comment before MIPS16 field descriptors to mention MIPS16.
1619 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1620 BBIT.
1621 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1622 New bit masks and shift counts for cins and exts.
1623
dd3cbb7e
NC		 1624 * mips.h: Document new field descriptors +Q.
1625 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1626
d0799671
AN		 16272008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1628
9aff4b7a 1629 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1630 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1631
19a6653c
AM		 16322008-04-14 Edmar Wienskoski <edmar@freescale.com>
1633
1634 * ppc.h: (PPC_OPCODE_E500MC): New.
1635
c0f3af97
L		 16362008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1637
1638 * i386.h (MAX_OPERANDS): Set to 5.
1639 (MAX_MNEM_SIZE): Changed to 20.
1640
e210c36b
NC		 16412008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1642
1643 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1644
b1cc4aeb
PB		 16452008-03-09 Paul Brook <paul@codesourcery.com>
1646
1647 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1648
7e806470
PB		 16492008-03-04 Paul Brook <paul@codesourcery.com>
1650
1651 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1652 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1653 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1654
7b2185f9 16552008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1656 Nick Clifton <nickc@redhat.com>
1657
1658 PR 3134
1659 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1660 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1661 set.
af7329f0 1662
796d5313
NC		 16632008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1664
1665 * cr16.h (cr16_num_optab): Declared.
1666
d669d37f
NC		 16672008-02-14 Hakan Ardo <hakan@debian.org>
1668
1669 PR gas/2626
1670 * avr.h (AVR_ISA_2xxe): Define.
1671
e6429699
AN		 16722008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1673
1674 * mips.h: Update copyright.
1675 (INSN_CHIP_MASK): New macro.
1676 (INSN_OCTEON): New macro.
1677 (CPU_OCTEON): New macro.
1678 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1679
e210c36b
NC		 16802008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1681
1682 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1683
16842008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1685
1686 * avr.h (AVR_ISA_USB162): Add new opcode set.
1687 (AVR_ISA_AVR3): Likewise.
1688
350cc38d
MS		 16892007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1690
1691 * mips.h (INSN_LOONGSON_2E): New.
1692 (INSN_LOONGSON_2F): New.
1693 (CPU_LOONGSON_2E): New.
1694 (CPU_LOONGSON_2F): New.
1695 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1696
56950294
MS		 16972007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1698
1699 * mips.h (INSN_ISA*): Redefine certain values as an
1700 enumeration. Update comments.
1701 (mips_isa_table): New.
1702 (ISA_MIPS*): Redefine to match enumeration.
1703 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1704 values.
1705
c3d65c1c
BE		 17062007-08-08 Ben Elliston <bje@au.ibm.com>
1707
1708 * ppc.h (PPC_OPCODE_PPCPS): New.
1709
0fdaa005
L		 17102007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1711
1712 * m68k.h: Document j K & E.
1713
17142007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1715
1716 * cr16.h: New file for CR16 target.
1717
3896c469
AM		 17182007-05-02 Alan Modra <amodra@bigpond.net.au>
1719
1720 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1721
9a2e615a
NS		 17222007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1723
1724 * m68k.h (mcfisa_c): New.
1725 (mcfusp, mcf_mask): Adjust.
1726
b84bf58a
AM		 17272007-04-20 Alan Modra <amodra@bigpond.net.au>
1728
1729 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1730 (num_powerpc_operands): Declare.
1731 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1732 (PPC_OPERAND_PLUS1): Define.
1733
831480e9 17342007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1735
1736 * i386.h (REX_MODE64): Renamed to ...
1737 (REX_W): This.
1738 (REX_EXTX): Renamed to ...
1739 (REX_R): This.
1740 (REX_EXTY): Renamed to ...
1741 (REX_X): This.
1742 (REX_EXTZ): Renamed to ...
1743 (REX_B): This.
1744
0b1cf022
L		 17452007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1746
1747 * i386.h: Add entries from config/tc-i386.h and move tables
1748 to opcodes/i386-opc.h.
1749
d796c0ad
L		 17502007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1751
1752 * i386.h (FloatDR): Removed.
1753 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1754
30ac7323
AM		 17552007-03-01 Alan Modra <amodra@bigpond.net.au>
1756
1757 * spu-insns.h: Add soma double-float insns.
1758
8b082fb1 17592007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1760 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1761
1762 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1763 (INSN_DSPR2): Add flag for DSP R2 instructions.
1764 (M_BALIGN): New macro.
1765
4eed87de
AM		 17662007-02-14 Alan Modra <amodra@bigpond.net.au>
1767
1768 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1769 and Seg3ShortFrom with Shortform.
1770
fda592e8
L		 17712007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1772
1773 PR gas/4027
1774 * i386.h (i386_optab): Put the real "test" before the pseudo
1775 one.
1776
3bdcfdf4
KH		 17772007-01-08 Kazu Hirata <kazu@codesourcery.com>
1778
1779 * m68k.h (m68010up): OR fido_a.
1780
9840d27e
KH		 17812006-12-25 Kazu Hirata <kazu@codesourcery.com>
1782
1783 * m68k.h (fido_a): New.
1784
c629cdac
KH		 17852006-12-24 Kazu Hirata <kazu@codesourcery.com>
1786
1787 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1788 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1789 values.
1790
b7d9ef37
L		 17912006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1792
1793 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1794
b138abaa
NC		 17952006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1796
1797 * score-inst.h (enum score_insn_type): Add Insn_internal.
1798
e9f53129
AM		 17992006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1800 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1801 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1802 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1803 Alan Modra <amodra@bigpond.net.au>
1804
1805 * spu-insns.h: New file.
1806 * spu.h: New file.
1807
ede602d7
AM		 18082006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1809
1810 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1811
7918206c
MM		 18122006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1813
e4e42b45 1814 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1815 in amdfam10 architecture.
1816
ef05d495
L		 18172006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1818
1819 * i386.h: Replace CpuMNI with CpuSSSE3.
1820
2d447fca 18212006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1822 Joseph Myers <joseph@codesourcery.com>
1823 Ian Lance Taylor <ian@wasabisystems.com>
1824 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1825
1826 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1827
1c0d3aa6
NC		 18282006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1829
1830 * score-datadep.h: New file.
1831 * score-inst.h: New file.
1832
c2f0420e
L		 18332006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1834
1835 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1836 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1837 movdq2q and movq2dq.
1838
050dfa73
MM		 18392006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1840 Michael Meissner <michael.meissner@amd.com>
1841
1842 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1843
15965411
L		 18442006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1845
1846 * i386.h (i386_optab): Add "nop" with memory reference.
1847
46e883c5
L		 18482006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1849
1850 * i386.h (i386_optab): Update comment for 64bit NOP.
1851
9622b051
AM		 18522006-06-06 Ben Elliston <bje@au.ibm.com>
1853 Anton Blanchard <anton@samba.org>
1854
1855 * ppc.h (PPC_OPCODE_POWER6): Define.
1856 Adjust whitespace.
1857
a9e24354
TS		 18582006-06-05 Thiemo Seufer <ths@mips.com>
1859
e4e42b45 1860 * mips.h: Improve description of MT flags.
a9e24354 1861
a596001e
RS		 18622006-05-25 Richard Sandiford <richard@codesourcery.com>
1863
1864 * m68k.h (mcf_mask): Define.
1865
d43b4baf 18662006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1867 David Ung <davidu@mips.com>
d43b4baf
TS		 1868
1869 * mips.h (enum): Add macro M_CACHE_AB.
1870
39a7806d 18712006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1872 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1873 David Ung <davidu@mips.com>
1874
1875 * mips.h: Add INSN_SMARTMIPS define.
1876
9bcd4f99 18772006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1878 David Ung <davidu@mips.com>
9bcd4f99
TS		 1879
1880 * mips.h: Defines udi bits and masks. Add description of
1881 characters which may appear in the args field of udi
1882 instructions.
1883
ef0ee844
TS		 18842006-04-26 Thiemo Seufer <ths@networkno.de>
1885
1886 * mips.h: Improve comments describing the bitfield instruction
1887 fields.
1888
f7675147
L		 18892006-04-26 Julian Brown <julian@codesourcery.com>
1890
1891 * arm.h (FPU_VFP_EXT_V3): Define constant.
1892 (FPU_NEON_EXT_V1): Likewise.
1893 (FPU_VFP_HARD): Update.
1894 (FPU_VFP_V3): Define macro.
1895 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1896
ef0ee844 18972006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1898
1899 * avr.h (AVR_ISA_PWMx): New.
1900
2da12c60
NS		 19012006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1902
1903 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1904 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1905 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1906 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1907 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1908
0715c387
PB		 19092006-03-10 Paul Brook <paul@codesourcery.com>
1910
1911 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1912
34bdd094
DA		 19132006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1914
1915 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1916 first. Correct mask of bb "B" opcode.
1917
331d2d0d
L		 19182006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1919
1920 * i386.h (i386_optab): Support Intel Merom New Instructions.
1921
62b3e311
PB		 19222006-02-24 Paul Brook <paul@codesourcery.com>
1923
1924 * arm.h: Add V7 feature bits.
1925
59cf82fe
L		 19262006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1927
1928 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1929
e74cfd16
PB		 19302006-01-31 Paul Brook <paul@codesourcery.com>
1931 Richard Earnshaw <rearnsha@arm.com>
1932
1933 * arm.h: Use ARM_CPU_FEATURE.
1934 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1935 (arm_feature_set): Change to a structure.
1936 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1937 ARM_FEATURE): New macros.
1938
5b3f8a92
HPN		 19392005-12-07 Hans-Peter Nilsson <hp@axis.com>
1940
1941 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1942 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1943 (ADD_PC_INCR_OPCODE): Don't define.
1944
cb712a9e
L		 19452005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1946
1947 PR gas/1874
1948 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1949
0499d65b
TS		 19502005-11-14 David Ung <davidu@mips.com>
1951
1952 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1953 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1954 save/restore encoding of the args field.
1955
ea5ca089
DB		 19562005-10-28 Dave Brolley <brolley@redhat.com>
1957
1958 Contribute the following changes:
1959 2005-02-16 Dave Brolley <brolley@redhat.com>
1960
1961 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1962 cgen_isa_mask_* to cgen_bitset_*.
1963 * cgen.h: Likewise.
1964
16175d96
DB		 1965 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1966
1967 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1968 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1969 (CGEN_CPU_TABLE): Make isas a ponter.
1970
1971 2003-09-29 Dave Brolley <brolley@redhat.com>
1972
1973 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1974 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1975 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1976
1977 2002-12-13 Dave Brolley <brolley@redhat.com>
1978
1979 * cgen.h (symcat.h): #include it.
1980 (cgen-bitset.h): #include it.
1981 (CGEN_ATTR_VALUE_TYPE): Now a union.
1982 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1983 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1984 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1985 * cgen-bitset.h: New file.
1986
3c9b82ba
NC		 19872005-09-30 Catherine Moore <clm@cm00re.com>
1988
1989 * bfin.h: New file.
1990
6a2375c6
JB		 19912005-10-24 Jan Beulich <jbeulich@novell.com>
1992
1993 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1994 indirect operands.
1995
c06a12f8
DA		 19962005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1997
1998 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1999 Add FLAG_STRICT to pa10 ftest opcode.
2000
4d443107
DA		 20012005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2002
2003 * hppa.h (pa_opcodes): Remove lha entries.
2004
f0a3b40f
DA		 20052005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2006
2007 * hppa.h (FLAG_STRICT): Revise comment.
2008 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
2009 before corresponding pa11 opcodes. Add strict pa10 register-immediate
2010 entries for "fdc".
2011
e210c36b
NC		 20122005-09-30 Catherine Moore <clm@cm00re.com>
2013
2014 * bfin.h: New file.
2015
1b7e1362
DA		 20162005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2017
2018 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2019
089b39de
CF		 20202005-09-06 Chao-ying Fu <fu@mips.com>
2021
2022 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2023 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2024 define.
2025 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2026 (INSN_ASE_MASK): Update to include INSN_MT.
2027 (INSN_MT): New define for MT ASE.
2028
93c34b9b
CF		 20292005-08-25 Chao-ying Fu <fu@mips.com>
2030
2031 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2032 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2033 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2034 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2035 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2036 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2037 instructions.
2038 (INSN_DSP): New define for DSP ASE.
2039
848cf006
AM		 20402005-08-18 Alan Modra <amodra@bigpond.net.au>
2041
2042 * a29k.h: Delete.
2043
36ae0db3
DJ		 20442005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2045
2046 * ppc.h (PPC_OPCODE_E300): Define.
2047
8c929562
MS		 20482005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2049
2050 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2051
f7b8cccc
DA		 20522005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2053
2054 PR gas/336
2055 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2056 and pitlb.
2057
8b5328ac
JB		 20582005-07-27 Jan Beulich <jbeulich@novell.com>
2059
2060 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2061 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2062 Add movq-s as 64-bit variants of movd-s.
2063
f417d200
DA		 20642005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2065
18b3bdfc
DA		 2066 * hppa.h: Fix punctuation in comment.
2067
f417d200
DA		 2068 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2069 implicit space-register addressing. Set space-register bits on opcodes
2070 using implicit space-register addressing. Add various missing pa20
2071 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2072 space-register addressing. Use "fE" instead of "fe" in various
2073 fstw opcodes.
2074
9a145ce6
JB		 20752005-07-18 Jan Beulich <jbeulich@novell.com>
2076
2077 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2078
90700ea2
L		 20792007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2080
2081 * i386.h (i386_optab): Support Intel VMX Instructions.
2082
48f130a8
DA		 20832005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2084
2085 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2086
30123838
JB		 20872005-07-05 Jan Beulich <jbeulich@novell.com>
2088
2089 * i386.h (i386_optab): Add new insns.
2090
47b0e7ad
NC		 20912005-07-01 Nick Clifton <nickc@redhat.com>
2092
2093 * sparc.h: Add typedefs to structure declarations.
2094
b300c311
L		 20952005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2096
2097 PR 1013
2098 * i386.h (i386_optab): Update comments for 64bit addressing on
2099 mov. Allow 64bit addressing for mov and movq.
2100
2db495be
DA		 21012005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2102
2103 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2104 respectively, in various floating-point load and store patterns.
2105
caa05036
DA		 21062005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2107
2108 * hppa.h (FLAG_STRICT): Correct comment.
2109 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2110 PA 2.0 mneumonics when equivalent. Entries with cache control
2111 completers now require PA 1.1. Adjust whitespace.
2112
f4411256
AM		 21132005-05-19 Anton Blanchard <anton@samba.org>
2114
2115 * ppc.h (PPC_OPCODE_POWER5): Define.
2116
e172dbf8
NC		 21172005-05-10 Nick Clifton <nickc@redhat.com>
2118
2119 * Update the address and phone number of the FSF organization in
2120 the GPL notices in the following files:
2121 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2122 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2123 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2124 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2125 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2126 tic54x.h, tic80.h, v850.h, vax.h
2127
e44823cf
JB		 21282005-05-09 Jan Beulich <jbeulich@novell.com>
2129
2130 * i386.h (i386_optab): Add ht and hnt.
2131
791fe849
MK		 21322005-04-18 Mark Kettenis <kettenis@gnu.org>
2133
2134 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2135 Add xcrypt-ctr. Provide aliases without hyphens.
2136
faa7ef87
L		 21372005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2138
a63027e5
L		 2139 Moved from ../ChangeLog
2140
faa7ef87
L		 2141 2005-04-12 Paul Brook <paul@codesourcery.com>
2142 * m88k.h: Rename psr macros to avoid conflicts.
2143
2144 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2145 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2146 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2147 and ARM_ARCH_V6ZKT2.
2148
2149 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2150 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2151 Remove redundant instruction types.
2152 (struct argument): X_op - new field.
2153 (struct cst4_entry): Remove.
2154 (no_op_insn): Declare.
2155
2156 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2157 * crx.h (enum argtype): Rename types, remove unused types.
2158
2159 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2160 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2161 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2162 (enum operand_type): Rearrange operands, edit comments.
2163 replace us<N> with ui<N> for unsigned immediate.
2164 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2165 displacements (respectively).
2166 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2167 (instruction type): Add NO_TYPE_INS.
2168 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2169 (operand_entry): New field - 'flags'.
2170 (operand flags): New.
2171
2172 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2173 * crx.h (operand_type): Remove redundant types i3, i4,
2174 i5, i8, i12.
2175 Add new unsigned immediate types us3, us4, us5, us16.
2176
bc4bd9ab
MK		 21772005-04-12 Mark Kettenis <kettenis@gnu.org>
2178
2179 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2180 adjust them accordingly.
2181
373ff435
JB		 21822005-04-01 Jan Beulich <jbeulich@novell.com>
2183
2184 * i386.h (i386_optab): Add rdtscp.
2185
4cc91dba
L		 21862005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2187
2188 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2189 between memory and segment register. Allow movq for moving between
2190 general-purpose register and segment register.
4cc91dba 2191
9ae09ff9
JB		 21922005-02-09 Jan Beulich <jbeulich@novell.com>
2193
2194 PR gas/707
2195 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2196 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2197 fnstsw.
2198
638e7a64
NS		 21992006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2200
2201 * m68k.h (m68008, m68ec030, m68882): Remove.
2202 (m68k_mask): New.
2203 (cpu_m68k, cpu_cf): New.
2204 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2205 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2206
90219bd0
AO		 22072005-01-25 Alexandre Oliva <aoliva@redhat.com>
2208
2209 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2210 * cgen.h (enum cgen_parse_operand_type): Add
2211 CGEN_PARSE_OPERAND_SYMBOLIC.
2212
239cb185
FF		 22132005-01-21 Fred Fish <fnf@specifixinc.com>
2214
2215 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2216 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2217 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2218
dc9a9f39
FF		 22192005-01-19 Fred Fish <fnf@specifixinc.com>
2220
2221 * mips.h (struct mips_opcode): Add new pinfo2 member.
2222 (INSN_ALIAS): New define for opcode table entries that are
2223 specific instances of another entry, such as 'move' for an 'or'
2224 with a zero operand.
2225 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2226 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2227
98e7aba8
ILT		 22282004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2229
2230 * mips.h (CPU_RM9000): Define.
2231 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2232
37edbb65
JB		 22332004-11-25 Jan Beulich <jbeulich@novell.com>
2234
2235 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2236 to/from test registers are illegal in 64-bit mode. Add missing
2237 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2238 (previously one had to explicitly encode a rex64 prefix). Re-enable
2239 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2240 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2241
22422004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2243
2244 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2245 available only with SSE2. Change the MMX additions introduced by SSE
2246 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2247 instructions by their now designated identifier (since combining i686
2248 and 3DNow! does not really imply 3DNow!A).
2249
f5c7edf4
AM		 22502004-11-19 Alan Modra <amodra@bigpond.net.au>
2251
2252 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2253 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2254
7499d566
NC		 22552004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2256 Vineet Sharma <vineets@noida.hcltech.com>
2257
2258 * maxq.h: New file: Disassembly information for the maxq port.
2259
bcb9eebe
L		 22602004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2261
2262 * i386.h (i386_optab): Put back "movzb".
2263
94bb3d38
HPN		 22642004-11-04 Hans-Peter Nilsson <hp@axis.com>
2265
2266 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2267 comments. Remove member cris_ver_sim. Add members
2268 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2269 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2270 (struct cris_support_reg, struct cris_cond15): New types.
2271 (cris_conds15): Declare.
2272 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2273 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2274 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2275 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2276 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2277 SIZE_FIELD_UNSIGNED.
2278
37edbb65 22792004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2280
2281 * i386.h (sldx_Suf): Remove.
2282 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2283 (q_FP): Define, implying no REX64.
2284 (x_FP, sl_FP): Imply FloatMF.
2285 (i386_optab): Split reg and mem forms of moving from segment registers
2286 so that the memory forms can ignore the 16-/32-bit operand size
2287 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2288 all non-floating-point instructions. Unite 32- and 64-bit forms of
2289 movsx, movzx, and movd. Adjust floating point operations for the above
2290 changes to the *FP macros. Add DefaultSize to floating point control
2291 insns operating on larger memory ranges. Remove left over comments
2292 hinting at certain insns being Intel-syntax ones where the ones
2293 actually meant are already gone.
2294
48c9f030
NC		 22952004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2296
2297 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2298 instruction type.
2299
0dd132b6
NC		 23002004-09-30 Paul Brook <paul@codesourcery.com>
2301
2302 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2303 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2304
23794b24
MM		 23052004-09-11 Theodore A. Roth <troth@openavr.org>
2306
2307 * avr.h: Add support for
2308 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2309
2a309db0
AM		 23102004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2311
2312 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2313
b18c562e
NC		 23142004-08-24 Dmitry Diky <diwil@spec.ru>
2315
2316 * msp430.h (msp430_opc): Add new instructions.
2317 (msp430_rcodes): Declare new instructions.
2318 (msp430_hcodes): Likewise..
2319
45d313cd
NC		 23202004-08-13 Nick Clifton <nickc@redhat.com>
2321
2322 PR/301
2323 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2324 processors.
2325
30d1c836
ML		 23262004-08-30 Michal Ludvig <mludvig@suse.cz>
2327
2328 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2329
9a45f1c2
L		 23302004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2331
2332 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2333
543613e9
NC		 23342004-07-21 Jan Beulich <jbeulich@novell.com>
2335
2336 * i386.h: Adjust instruction descriptions to better match the
2337 specification.
2338
b781e558
RE		 23392004-07-16 Richard Earnshaw <rearnsha@arm.com>
2340
2341 * arm.h: Remove all old content. Replace with architecture defines
2342 from gas/config/tc-arm.c.
2343
8577e690
AS		 23442004-07-09 Andreas Schwab <schwab@suse.de>
2345
2346 * m68k.h: Fix comment.
2347
1fe1f39c
NC		 23482004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2349
2350 * crx.h: New file.
2351
1d9f512f
AM		 23522004-06-24 Alan Modra <amodra@bigpond.net.au>
2353
2354 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2355
be8c092b
NC		 23562004-05-24 Peter Barada <peter@the-baradas.com>
2357
2358 * m68k.h: Add 'size' to m68k_opcode.
2359
6b6e92f4
NC		 23602004-05-05 Peter Barada <peter@the-baradas.com>
2361
2362 * m68k.h: Switch from ColdFire chip name to core variant.
2363
23642004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2365
2366 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2367 descriptions for new EMAC cases.
2368 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2369 handle Motorola MAC syntax.
2370 Allow disassembly of ColdFire V4e object files.
2371
fdd12ef3
AM		 23722004-03-16 Alan Modra <amodra@bigpond.net.au>
2373
2374 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2375
3922a64c
L		 23762004-03-12 Jakub Jelinek <jakub@redhat.com>
2377
2378 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2379
1f45d988
ML		 23802004-03-12 Michal Ludvig <mludvig@suse.cz>
2381
2382 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2383
0f10071e
ML		 23842004-03-12 Michal Ludvig <mludvig@suse.cz>
2385
2386 * i386.h (i386_optab): Added xstore/xcrypt insns.
2387
3255318a
NC		 23882004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2389
2390 * h8300.h (32bit ldc/stc): Add relaxing support.
2391
ca9a79a1 23922004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2393
ca9a79a1
NC		 2394 * h8300.h (BITOP): Pass MEMRELAX flag.
2395
875a0b14
NC		 23962004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2397
2398 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2399 except for the H8S.
252b5132 2400
c9e214e5 2401For older changes see ChangeLog-9103
252b5132 2402\f
b90efa5b 2403Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2404
2405Copying and distribution of this file, with or without modification,
2406are permitted in any medium without royalty provided the copyright
2407notice and this notice are preserved.
2408
252b5132 2409Local Variables:
c9e214e5
AM		 2410mode: change-log
2411left-margin: 8
2412fill-column: 74
252b5132
RH		 2413version-control: never
2414End:
GDB Binutils - Deliverables
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