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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
dd6a37e7
AP		 12011-11-29 Andrew Pinski <apinski@cavium.com>
2
3 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
4 (INSN_OCTEONP): New macro.
5 (CPU_OCTEONP): New macro.
6 (OPCODE_IS_MEMBER): Add Octeon+.
7 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
8
99c513f6
DD		 92011-11-01 DJ Delorie <dj@redhat.com>
10
11 * rl78.h: New file.
12
26f85d7a
MR		 132011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
14
15 * mips.h: Fix a typo in description.
16
9e8c70f9
DM		 172011-09-21 David S. Miller <davem@davemloft.net>
18
19 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
20 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
21 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
22 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
23
dec0624d
MR		 242011-08-09 Chao-ying Fu <fu@mips.com>
25 Maciej W. Rozycki <macro@codesourcery.com>
26
27 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
28 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
29 (INSN_ASE_MASK): Add the MCU bit.
30 (INSN_MCU): New macro.
31 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
32 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
33
2b0c8b40
MR		 342011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
35
36 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
37 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
38 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
39 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
40 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
41 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
42 (INSN2_READ_GPR_MMN): Likewise.
43 (INSN2_READ_FPR_D): Change the bit used.
44 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
45 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
46 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
47 (INSN2_COND_BRANCH): Likewise.
48 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
49 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
50 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
51 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
52 (INSN2_MOD_GPR_MN): Likewise.
53
ea783ef3
DM		 542011-08-05 David S. Miller <davem@davemloft.net>
55
56 * sparc.h: Document new format codes '4', '5', and '('.
57 (OPF_LOW4, RS3): New macros.
58
7c176fa8
MR		 592011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
60
61 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
62 order of flags documented.
63
2309ddf2
MR		 642011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
65
66 * mips.h: Clarify the description of microMIPS instruction
67 manipulation macros.
68 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
69
df58fc94
RS		 702011-07-24 Chao-ying Fu <fu@mips.com>
71 Maciej W. Rozycki <macro@codesourcery.com>
72
73 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
74 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
75 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
76 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
77 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
78 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
79 (OP_MASK_RS3, OP_SH_RS3): Likewise.
80 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
81 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
82 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
83 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
84 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
85 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
86 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
87 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
88 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
89 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
90 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
91 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
92 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
93 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
94 (INSN_WRITE_GPR_S): New macro.
95 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
96 (INSN2_READ_FPR_D): Likewise.
97 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
98 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
99 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
100 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
101 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
102 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
103 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
104 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
105 (CPU_MICROMIPS): New macro.
106 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
107 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
108 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
109 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
110 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
111 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
112 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
113 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
114 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
115 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
116 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
117 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
118 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
119 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
120 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
121 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
122 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
123 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
124 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
125 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
126 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
127 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
128 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
129 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
130 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
131 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
132 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
133 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
134 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
135 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
136 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
137 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
138 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
139 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
140 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
141 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
142 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
143 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
144 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
145 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
146 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
147 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
148 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
149 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
150 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
151 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
152 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
153 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
154 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
155 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
156 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
157 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
158 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
159 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
160 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
161 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
162 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
163 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
164 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
165 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
166 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
167 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
168 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
169 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
170 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
171 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
172 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
173 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
174 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
175 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
176 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
177 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
178 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
179 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
180 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
181 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
182 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
183 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
184 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
185 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
186 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
187 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
188 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
189 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
190 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
191 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
192 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
193 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
194 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
195 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
196 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
197 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
198 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
199 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
200 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
201 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
202 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
203 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
204 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
205 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
206 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
207 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
208 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
209 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
210 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
211 (micromips_opcodes): New declaration.
212 (bfd_micromips_num_opcodes): Likewise.
213
bcd530a7
RS		 2142011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
215
216 * mips.h (INSN_TRAP): Rename to...
217 (INSN_NO_DELAY_SLOT): ... this.
218 (INSN_SYNC): Remove macro.
219
2dad5a91
EW		 2202011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
221
222 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
223 a duplicate of AVR_ISA_SPM.
224
5d73b1f1
NC		 2252011-07-01 Nick Clifton <nickc@redhat.com>
226
227 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
228
ef26d60e
MF		 2292011-06-18 Robin Getz <robin.getz@analog.com>
230
231 * bfin.h (is_macmod_signed): New func
232
8fb8dca7
MF		 2332011-06-18 Mike Frysinger <vapier@gentoo.org>
234
235 * bfin.h (is_macmod_pmove): Add missing space before func args.
236 (is_macmod_hmove): Likewise.
237
aa137e4d
NC		 2382011-06-13 Walter Lee <walt@tilera.com>
239
240 * tilegx.h: New file.
241 * tilepro.h: New file.
242
3b2f0793
PB		 2432011-05-31 Paul Brook <paul@codesourcery.com>
244
aa137e4d
NC		 245 * arm.h (ARM_ARCH_V7R_IDIV): Define.
246
2472011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
248
249 * s390.h: Replace S390_OPERAND_REG_EVEN with
250 S390_OPERAND_REG_PAIR.
251
2522011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
253
254 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 255
ac7f631b
NC		 2562011-04-18 Julian Brown <julian@codesourcery.com>
257
258 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
259
84701018
NC		 2602011-04-11 Dan McDonald <dan@wellkeeper.com>
261
262 PR gas/12296
263 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
264
8cc66334
EW		 2652011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
266
267 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
268 New instruction set flags.
269 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
270
3eebd5eb
MR		 2712011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
272
273 * mips.h (M_PREF_AB): New enum value.
274
26bb3ddd
MF		 2752011-02-12 Mike Frysinger <vapier@gentoo.org>
276
89c0d58c
MR		 277 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
278 M_IU): Define.
279 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 280
dd76fcb8
MF		 2812011-02-11 Mike Frysinger <vapier@gentoo.org>
282
283 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
284
98d23bef
BS		 2852011-02-04 Bernd Schmidt <bernds@codesourcery.com>
286
287 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
288 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
289
3c853d93
DA		 2902010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
291
292 PR gas/11395
293 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
294 "bb" entries.
295
79676006
DA		 2962010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
297
298 PR gas/11395
299 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
300
1bec78e9
RS		 3012010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
302
303 * mips.h: Update commentary after last commit.
304
98675402
RS		 3052010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
306
307 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
308 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
309 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
310
aa137e4d
NC		 3112010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
312
313 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
314
435b94a4
RS		 3152010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
316
317 * mips.h: Fix previous commit.
318
d051516a
NC		 3192010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
320
321 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
322 (INSN_LOONGSON_3A): Clear bit 31.
323
251665fc
MGD		 3242010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
325
326 PR gas/12198
327 * arm.h (ARM_AEXT_V6M_ONLY): New define.
328 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
329 (ARM_ARCH_V6M_ONLY): New define.
330
fd503541
NC		 3312010-11-11 Mingming Sun <mingm.sun@gmail.com>
332
333 * mips.h (INSN_LOONGSON_3A): Defined.
334 (CPU_LOONGSON_3A): Defined.
335 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
336
4469d2be
AM		 3372010-10-09 Matt Rice <ratmice@gmail.com>
338
339 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
340 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
341
90ec0d68
MGD		 3422010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
343
344 * arm.h (ARM_EXT_VIRT): New define.
345 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
346 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
347 Extensions.
348
eea54501 3492010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 350
eea54501
MGD		 351 * arm.h (ARM_AEXT_ADIV): New define.
352 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
353
b2a5fbdc
MGD		 3542010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
355
356 * arm.h (ARM_EXT_OS): New define.
357 (ARM_AEXT_V6SM): Likewise.
358 (ARM_ARCH_V6SM): Likewise.
359
60e5ef9f
MGD		 3602010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
361
362 * arm.h (ARM_EXT_MP): Add.
363 (ARM_ARCH_V7A_MP): Likewise.
364
73a63ccf
MF		 3652010-09-22 Mike Frysinger <vapier@gentoo.org>
366
367 * bfin.h: Declare pseudoChr structs/defines.
368
ee99860a
MF		 3692010-09-21 Mike Frysinger <vapier@gentoo.org>
370
371 * bfin.h: Strip trailing whitespace.
372
f9c7014e
DD		 3732010-07-29 DJ Delorie <dj@redhat.com>
374
375 * rx.h (RX_Operand_Type): Add TwoReg.
376 (RX_Opcode_ID): Remove ediv and ediv2.
377
93378652
DD		 3782010-07-27 DJ Delorie <dj@redhat.com>
379
380 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
381
1cd986c5
NC		 3822010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
383 Ina Pandit <ina.pandit@kpitcummins.com>
384
385 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
386 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
387 PROCESSOR_V850E2_ALL.
388 Remove PROCESSOR_V850EA support.
389 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
390 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
391 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
392 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
393 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
394 V850_OPERAND_PERCENT.
395 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
396 V850_NOT_R0.
397 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
398 and V850E_PUSH_POP
399
9a2c7088
MR		 4002010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
401
402 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
403 (MIPS16_INSN_BRANCH): Rename to...
404 (MIPS16_INSN_COND_BRANCH): ... this.
405
bdc70b4a
AM		 4062010-07-03 Alan Modra <amodra@gmail.com>
407
408 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
409 Renumber other PPC_OPCODE defines.
410
f2bae120
AM		 4112010-07-03 Alan Modra <amodra@gmail.com>
412
413 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
414
360cfc9c
AM		 4152010-06-29 Alan Modra <amodra@gmail.com>
416
417 * maxq.h: Delete file.
418
e01d869a
AM		 4192010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
420
421 * ppc.h (PPC_OPCODE_E500): Define.
422
f79e2745
CM		 4232010-05-26 Catherine Moore <clm@codesourcery.com>
424
425 * opcode/mips.h (INSN_MIPS16): Remove.
426
2462afa1
JM		 4272010-04-21 Joseph Myers <joseph@codesourcery.com>
428
429 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
430
e4e42b45
NC		 4312010-04-15 Nick Clifton <nickc@redhat.com>
432
433 * alpha.h: Update copyright notice to use GPLv3.
434 * arc.h: Likewise.
435 * arm.h: Likewise.
436 * avr.h: Likewise.
437 * bfin.h: Likewise.
438 * cgen.h: Likewise.
439 * convex.h: Likewise.
440 * cr16.h: Likewise.
441 * cris.h: Likewise.
442 * crx.h: Likewise.
443 * d10v.h: Likewise.
444 * d30v.h: Likewise.
445 * dlx.h: Likewise.
446 * h8300.h: Likewise.
447 * hppa.h: Likewise.
448 * i370.h: Likewise.
449 * i386.h: Likewise.
450 * i860.h: Likewise.
451 * i960.h: Likewise.
452 * ia64.h: Likewise.
453 * m68hc11.h: Likewise.
454 * m68k.h: Likewise.
455 * m88k.h: Likewise.
456 * maxq.h: Likewise.
457 * mips.h: Likewise.
458 * mmix.h: Likewise.
459 * mn10200.h: Likewise.
460 * mn10300.h: Likewise.
461 * msp430.h: Likewise.
462 * np1.h: Likewise.
463 * ns32k.h: Likewise.
464 * or32.h: Likewise.
465 * pdp11.h: Likewise.
466 * pj.h: Likewise.
467 * pn.h: Likewise.
468 * ppc.h: Likewise.
469 * pyr.h: Likewise.
470 * rx.h: Likewise.
471 * s390.h: Likewise.
472 * score-datadep.h: Likewise.
473 * score-inst.h: Likewise.
474 * sparc.h: Likewise.
475 * spu-insns.h: Likewise.
476 * spu.h: Likewise.
477 * tic30.h: Likewise.
478 * tic4x.h: Likewise.
479 * tic54x.h: Likewise.
480 * tic80.h: Likewise.
481 * v850.h: Likewise.
482 * vax.h: Likewise.
483
40b36596
JM		 4842010-03-25 Joseph Myers <joseph@codesourcery.com>
485
486 * tic6x-control-registers.h, tic6x-insn-formats.h,
487 tic6x-opcode-table.h, tic6x.h: New.
488
c67a084a
NC		 4892010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
490
491 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
492
466ef64f
AM		 4932010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
494
495 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
496
1319d143
L		 4972010-01-14 H.J. Lu <hongjiu.lu@intel.com>
498
499 * ia64.h (ia64_find_opcode): Remove argument name.
500 (ia64_find_next_opcode): Likewise.
501 (ia64_dis_opcode): Likewise.
502 (ia64_free_opcode): Likewise.
503 (ia64_find_dependency): Likewise.
504
1fbb9298
DE		 5052009-11-22 Doug Evans <dje@sebabeach.org>
506
507 * cgen.h: Include bfd_stdint.h.
508 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
509
ada65aa3
PB		 5102009-11-18 Paul Brook <paul@codesourcery.com>
511
512 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
513
9e3c6df6
PB		 5142009-11-17 Paul Brook <paul@codesourcery.com>
515 Daniel Jacobowitz <dan@codesourcery.com>
516
517 * arm.h (ARM_EXT_V6_DSP): Define.
518 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
519 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
520
0d734b5d
DD		 5212009-11-04 DJ Delorie <dj@redhat.com>
522
523 * rx.h (rx_decode_opcode) (mvtipl): Add.
524 (mvtcp, mvfcp, opecp): Remove.
525
62f3b8c8
PB		 5262009-11-02 Paul Brook <paul@codesourcery.com>
527
528 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
529 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
530 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
531 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
532 FPU_ARCH_NEON_VFP_V4): Define.
533
ac1e9eca
DE		 5342009-10-23 Doug Evans <dje@sebabeach.org>
535
536 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
537 * cgen.h: Update. Improve multi-inclusion macro name.
538
9fe54b1c
PB		 5392009-10-02 Peter Bergner <bergner@vnet.ibm.com>
540
541 * ppc.h (PPC_OPCODE_476): Define.
542
634b50f2
PB		 5432009-10-01 Peter Bergner <bergner@vnet.ibm.com>
544
545 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
546
c7927a3c
NC		 5472009-09-29 DJ Delorie <dj@redhat.com>
548
549 * rx.h: New file.
550
b961e85b
AM		 5512009-09-22 Peter Bergner <bergner@vnet.ibm.com>
552
553 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
554
e0d602ec
BE		 5552009-09-21 Ben Elliston <bje@au.ibm.com>
556
557 * ppc.h (PPC_OPCODE_PPCA2): New.
558
96d56e9f
NC		 5592009-09-05 Martin Thuresson <martin@mtme.org>
560
561 * ia64.h (struct ia64_operand): Renamed member class to op_class.
562
d3ce72d0
NC		 5632009-08-29 Martin Thuresson <martin@mtme.org>
564
565 * tic30.h (template): Rename type template to
566 insn_template. Updated code to use new name.
567 * tic54x.h (template): Rename type template to
568 insn_template.
569
824b28db
NH		 5702009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
571
572 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
573
f865a31d
AG		 5742009-06-11 Anthony Green <green@moxielogic.com>
575
576 * moxie.h (MOXIE_F3_PCREL): Define.
577 (moxie_form3_opc_info): Grow.
578
0e7c7f11
AG		 5792009-06-06 Anthony Green <green@moxielogic.com>
580
581 * moxie.h (MOXIE_F1_M): Define.
582
20135e4c
NC		 5832009-04-15 Anthony Green <green@moxielogic.com>
584
585 * moxie.h: Created.
586
bcb012d3
DD		 5872009-04-06 DJ Delorie <dj@redhat.com>
588
589 * h8300.h: Add relaxation attributes to MOVA opcodes.
590
69fe9ce5
AM		 5912009-03-10 Alan Modra <amodra@bigpond.net.au>
592
593 * ppc.h (ppc_parse_cpu): Declare.
594
c3b7224a
NC		 5952009-03-02 Qinwei <qinwei@sunnorth.com.cn>
596
597 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
598 and _IMM11 for mbitclr and mbitset.
599 * score-datadep.h: Update dependency information.
600
066be9f7
PB		 6012009-02-26 Peter Bergner <bergner@vnet.ibm.com>
602
603 * ppc.h (PPC_OPCODE_POWER7): New.
604
fedc618e
DE		 6052009-02-06 Doug Evans <dje@google.com>
606
607 * i386.h: Add comment regarding sse* insns and prefixes.
608
52b6b6b9
JM		 6092009-02-03 Sandip Matte <sandip@rmicorp.com>
610
611 * mips.h (INSN_XLR): Define.
612 (INSN_CHIP_MASK): Update.
613 (CPU_XLR): Define.
614 (OPCODE_IS_MEMBER): Update.
615 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
616
35669430
DE		 6172009-01-28 Doug Evans <dje@google.com>
618
619 * opcode/i386.h: Add multiple inclusion protection.
620 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
621 (EDI_REG_NUM): New macros.
622 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
623 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 624 (REX_PREFIX_P): New macro.
35669430 625
1cb0a767
PB		 6262009-01-09 Peter Bergner <bergner@vnet.ibm.com>
627
628 * ppc.h (struct powerpc_opcode): New field "deprecated".
629 (PPC_OPCODE_NOPOWER4): Delete.
630
3aa3176b
TS		 6312008-11-28 Joshua Kinard <kumba@gentoo.org>
632
633 * mips.h: Define CPU_R14000, CPU_R16000.
634 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
635
8e79c3df
CM		 6362008-11-18 Catherine Moore <clm@codesourcery.com>
637
638 * arm.h (FPU_NEON_FP16): New.
639 (FPU_ARCH_NEON_FP16): New.
640
de9a3e51
CF		 6412008-11-06 Chao-ying Fu <fu@mips.com>
642
643 * mips.h: Doucument '1' for 5-bit sync type.
644
1ca35711
L		 6452008-08-28 H.J. Lu <hongjiu.lu@intel.com>
646
647 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
648 IA64_RS_CR.
649
9b4e5766
PB		 6502008-08-01 Peter Bergner <bergner@vnet.ibm.com>
651
652 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
653
081ba1b3
AM		 6542008-07-30 Michael J. Eager <eager@eagercon.com>
655
656 * ppc.h (PPC_OPCODE_405): Define.
657 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
658
fa452fa6
PB		 6592008-06-13 Peter Bergner <bergner@vnet.ibm.com>
660
661 * ppc.h (ppc_cpu_t): New typedef.
662 (struct powerpc_opcode <flags>): Use it.
663 (struct powerpc_operand <insert, extract>): Likewise.
664 (struct powerpc_macro <flags>): Likewise.
665
bb35fb24
NC		 6662008-06-12 Adam Nemet <anemet@caviumnetworks.com>
667
668 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
669 Update comment before MIPS16 field descriptors to mention MIPS16.
670 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
671 BBIT.
672 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
673 New bit masks and shift counts for cins and exts.
674
dd3cbb7e
NC		 675 * mips.h: Document new field descriptors +Q.
676 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
677
d0799671
AN		 6782008-04-28 Adam Nemet <anemet@caviumnetworks.com>
679
680 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
681 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
682
19a6653c
AM		 6832008-04-14 Edmar Wienskoski <edmar@freescale.com>
684
685 * ppc.h: (PPC_OPCODE_E500MC): New.
686
c0f3af97
L		 6872008-04-03 H.J. Lu <hongjiu.lu@intel.com>
688
689 * i386.h (MAX_OPERANDS): Set to 5.
690 (MAX_MNEM_SIZE): Changed to 20.
691
e210c36b
NC		 6922008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
693
694 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
695
b1cc4aeb
PB		 6962008-03-09 Paul Brook <paul@codesourcery.com>
697
698 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
699
7e806470
PB		 7002008-03-04 Paul Brook <paul@codesourcery.com>
701
702 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
703 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
704 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
705
7b2185f9 7062008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 707 Nick Clifton <nickc@redhat.com>
708
709 PR 3134
710 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
711 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 712 set.
af7329f0 713
796d5313
NC		 7142008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
715
716 * cr16.h (cr16_num_optab): Declared.
717
d669d37f
NC		 7182008-02-14 Hakan Ardo <hakan@debian.org>
719
720 PR gas/2626
721 * avr.h (AVR_ISA_2xxe): Define.
722
e6429699
AN		 7232008-02-04 Adam Nemet <anemet@caviumnetworks.com>
724
725 * mips.h: Update copyright.
726 (INSN_CHIP_MASK): New macro.
727 (INSN_OCTEON): New macro.
728 (CPU_OCTEON): New macro.
729 (OPCODE_IS_MEMBER): Handle Octeon instructions.
730
e210c36b
NC		 7312008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
732
733 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
734
7352008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
736
737 * avr.h (AVR_ISA_USB162): Add new opcode set.
738 (AVR_ISA_AVR3): Likewise.
739
350cc38d
MS		 7402007-11-29 Mark Shinwell <shinwell@codesourcery.com>
741
742 * mips.h (INSN_LOONGSON_2E): New.
743 (INSN_LOONGSON_2F): New.
744 (CPU_LOONGSON_2E): New.
745 (CPU_LOONGSON_2F): New.
746 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
747
56950294
MS		 7482007-11-29 Mark Shinwell <shinwell@codesourcery.com>
749
750 * mips.h (INSN_ISA*): Redefine certain values as an
751 enumeration. Update comments.
752 (mips_isa_table): New.
753 (ISA_MIPS*): Redefine to match enumeration.
754 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
755 values.
756
c3d65c1c
BE		 7572007-08-08 Ben Elliston <bje@au.ibm.com>
758
759 * ppc.h (PPC_OPCODE_PPCPS): New.
760
0fdaa005
L		 7612007-07-03 Nathan Sidwell <nathan@codesourcery.com>
762
763 * m68k.h: Document j K & E.
764
7652007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 766
767 * cr16.h: New file for CR16 target.
768
3896c469
AM		 7692007-05-02 Alan Modra <amodra@bigpond.net.au>
770
771 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
772
9a2e615a
NS		 7732007-04-23 Nathan Sidwell <nathan@codesourcery.com>
774
775 * m68k.h (mcfisa_c): New.
776 (mcfusp, mcf_mask): Adjust.
777
b84bf58a
AM		 7782007-04-20 Alan Modra <amodra@bigpond.net.au>
779
780 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
781 (num_powerpc_operands): Declare.
782 (PPC_OPERAND_SIGNED et al): Redefine as hex.
783 (PPC_OPERAND_PLUS1): Define.
784
831480e9 7852007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 786
787 * i386.h (REX_MODE64): Renamed to ...
788 (REX_W): This.
789 (REX_EXTX): Renamed to ...
790 (REX_R): This.
791 (REX_EXTY): Renamed to ...
792 (REX_X): This.
793 (REX_EXTZ): Renamed to ...
794 (REX_B): This.
795
0b1cf022
L		 7962007-03-15 H.J. Lu <hongjiu.lu@intel.com>
797
798 * i386.h: Add entries from config/tc-i386.h and move tables
799 to opcodes/i386-opc.h.
800
d796c0ad
L		 8012007-03-13 H.J. Lu <hongjiu.lu@intel.com>
802
803 * i386.h (FloatDR): Removed.
804 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
805
30ac7323
AM		 8062007-03-01 Alan Modra <amodra@bigpond.net.au>
807
808 * spu-insns.h: Add soma double-float insns.
809
8b082fb1 8102007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 811 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 812
813 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
814 (INSN_DSPR2): Add flag for DSP R2 instructions.
815 (M_BALIGN): New macro.
816
4eed87de
AM		 8172007-02-14 Alan Modra <amodra@bigpond.net.au>
818
819 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
820 and Seg3ShortFrom with Shortform.
821
fda592e8
L		 8222007-02-11 H.J. Lu <hongjiu.lu@intel.com>
823
824 PR gas/4027
825 * i386.h (i386_optab): Put the real "test" before the pseudo
826 one.
827
3bdcfdf4
KH		 8282007-01-08 Kazu Hirata <kazu@codesourcery.com>
829
830 * m68k.h (m68010up): OR fido_a.
831
9840d27e
KH		 8322006-12-25 Kazu Hirata <kazu@codesourcery.com>
833
834 * m68k.h (fido_a): New.
835
c629cdac
KH		 8362006-12-24 Kazu Hirata <kazu@codesourcery.com>
837
838 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
839 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
840 values.
841
b7d9ef37
L		 8422006-11-08 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
845
b138abaa
NC		 8462006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
847
848 * score-inst.h (enum score_insn_type): Add Insn_internal.
849
e9f53129
AM		 8502006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
851 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
852 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
853 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
854 Alan Modra <amodra@bigpond.net.au>
855
856 * spu-insns.h: New file.
857 * spu.h: New file.
858
ede602d7
AM		 8592006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
860
861 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 862
7918206c
MM		 8632006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
864
e4e42b45 865 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 866 in amdfam10 architecture.
867
ef05d495
L		 8682006-09-28 H.J. Lu <hongjiu.lu@intel.com>
869
870 * i386.h: Replace CpuMNI with CpuSSSE3.
871
2d447fca
JM		 8722006-09-26 Mark Shinwell <shinwell@codesourcery.com>
873 Joseph Myers <joseph@codesourcery.com>
874 Ian Lance Taylor <ian@wasabisystems.com>
875 Ben Elliston <bje@wasabisystems.com>
876
877 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
878
1c0d3aa6
NC		 8792006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
880
881 * score-datadep.h: New file.
882 * score-inst.h: New file.
883
c2f0420e
L		 8842006-07-14 H.J. Lu <hongjiu.lu@intel.com>
885
886 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
887 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
888 movdq2q and movq2dq.
889
050dfa73
MM		 8902006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
891 Michael Meissner <michael.meissner@amd.com>
892
893 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
894
15965411
L		 8952006-06-12 H.J. Lu <hongjiu.lu@intel.com>
896
897 * i386.h (i386_optab): Add "nop" with memory reference.
898
46e883c5
L		 8992006-06-12 H.J. Lu <hongjiu.lu@intel.com>
900
901 * i386.h (i386_optab): Update comment for 64bit NOP.
902
9622b051
AM		 9032006-06-06 Ben Elliston <bje@au.ibm.com>
904 Anton Blanchard <anton@samba.org>
905
906 * ppc.h (PPC_OPCODE_POWER6): Define.
907 Adjust whitespace.
908
a9e24354
TS		 9092006-06-05 Thiemo Seufer <ths@mips.com>
910
e4e42b45 911 * mips.h: Improve description of MT flags.
a9e24354 912
a596001e
RS		 9132006-05-25 Richard Sandiford <richard@codesourcery.com>
914
915 * m68k.h (mcf_mask): Define.
916
d43b4baf
TS		 9172006-05-05 Thiemo Seufer <ths@mips.com>
918 David Ung <davidu@mips.com>
919
920 * mips.h (enum): Add macro M_CACHE_AB.
921
39a7806d
TS		 9222006-05-04 Thiemo Seufer <ths@mips.com>
923 Nigel Stephens <nigel@mips.com>
924 David Ung <davidu@mips.com>
925
926 * mips.h: Add INSN_SMARTMIPS define.
927
9bcd4f99
TS		 9282006-04-30 Thiemo Seufer <ths@mips.com>
929 David Ung <davidu@mips.com>
930
931 * mips.h: Defines udi bits and masks. Add description of
932 characters which may appear in the args field of udi
933 instructions.
934
ef0ee844
TS		 9352006-04-26 Thiemo Seufer <ths@networkno.de>
936
937 * mips.h: Improve comments describing the bitfield instruction
938 fields.
939
f7675147
L		 9402006-04-26 Julian Brown <julian@codesourcery.com>
941
942 * arm.h (FPU_VFP_EXT_V3): Define constant.
943 (FPU_NEON_EXT_V1): Likewise.
944 (FPU_VFP_HARD): Update.
945 (FPU_VFP_V3): Define macro.
946 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
947
ef0ee844 9482006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 949
950 * avr.h (AVR_ISA_PWMx): New.
951
2da12c60
NS		 9522006-03-28 Nathan Sidwell <nathan@codesourcery.com>
953
954 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
955 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
956 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
957 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
958 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
959
0715c387
PB		 9602006-03-10 Paul Brook <paul@codesourcery.com>
961
962 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
963
34bdd094
DA		 9642006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
965
966 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
967 first. Correct mask of bb "B" opcode.
968
331d2d0d
L		 9692006-02-27 H.J. Lu <hongjiu.lu@intel.com>
970
971 * i386.h (i386_optab): Support Intel Merom New Instructions.
972
62b3e311
PB		 9732006-02-24 Paul Brook <paul@codesourcery.com>
974
975 * arm.h: Add V7 feature bits.
976
59cf82fe
L		 9772006-02-23 H.J. Lu <hongjiu.lu@intel.com>
978
979 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
980
e74cfd16
PB		 9812006-01-31 Paul Brook <paul@codesourcery.com>
982 Richard Earnshaw <rearnsha@arm.com>
983
984 * arm.h: Use ARM_CPU_FEATURE.
985 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
986 (arm_feature_set): Change to a structure.
987 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
988 ARM_FEATURE): New macros.
989
5b3f8a92
HPN		 9902005-12-07 Hans-Peter Nilsson <hp@axis.com>
991
992 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
993 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
994 (ADD_PC_INCR_OPCODE): Don't define.
995
cb712a9e
L		 9962005-12-06 H.J. Lu <hongjiu.lu@intel.com>
997
998 PR gas/1874
999 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1000
0499d65b
TS		 10012005-11-14 David Ung <davidu@mips.com>
1002
1003 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1004 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1005 save/restore encoding of the args field.
1006
ea5ca089
DB		 10072005-10-28 Dave Brolley <brolley@redhat.com>
1008
1009 Contribute the following changes:
1010 2005-02-16 Dave Brolley <brolley@redhat.com>
1011
1012 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1013 cgen_isa_mask_* to cgen_bitset_*.
1014 * cgen.h: Likewise.
1015
16175d96
DB		 1016 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1017
1018 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1019 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1020 (CGEN_CPU_TABLE): Make isas a ponter.
1021
1022 2003-09-29 Dave Brolley <brolley@redhat.com>
1023
1024 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1025 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1026 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1027
1028 2002-12-13 Dave Brolley <brolley@redhat.com>
1029
1030 * cgen.h (symcat.h): #include it.
1031 (cgen-bitset.h): #include it.
1032 (CGEN_ATTR_VALUE_TYPE): Now a union.
1033 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1034 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1035 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1036 * cgen-bitset.h: New file.
1037
3c9b82ba
NC		 10382005-09-30 Catherine Moore <clm@cm00re.com>
1039
1040 * bfin.h: New file.
1041
6a2375c6
JB		 10422005-10-24 Jan Beulich <jbeulich@novell.com>
1043
1044 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1045 indirect operands.
1046
c06a12f8
DA		 10472005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1048
1049 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1050 Add FLAG_STRICT to pa10 ftest opcode.
1051
4d443107
DA		 10522005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1053
1054 * hppa.h (pa_opcodes): Remove lha entries.
1055
f0a3b40f
DA		 10562005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1057
1058 * hppa.h (FLAG_STRICT): Revise comment.
1059 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1060 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1061 entries for "fdc".
1062
e210c36b
NC		 10632005-09-30 Catherine Moore <clm@cm00re.com>
1064
1065 * bfin.h: New file.
1066
1b7e1362
DA		 10672005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1068
1069 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1070
089b39de
CF		 10712005-09-06 Chao-ying Fu <fu@mips.com>
1072
1073 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1074 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1075 define.
1076 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1077 (INSN_ASE_MASK): Update to include INSN_MT.
1078 (INSN_MT): New define for MT ASE.
1079
93c34b9b
CF		 10802005-08-25 Chao-ying Fu <fu@mips.com>
1081
1082 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1083 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1084 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1085 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1086 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1087 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1088 instructions.
1089 (INSN_DSP): New define for DSP ASE.
1090
848cf006
AM		 10912005-08-18 Alan Modra <amodra@bigpond.net.au>
1092
1093 * a29k.h: Delete.
1094
36ae0db3
DJ		 10952005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1096
1097 * ppc.h (PPC_OPCODE_E300): Define.
1098
8c929562
MS		 10992005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1100
1101 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1102
f7b8cccc
DA		 11032005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1104
1105 PR gas/336
1106 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1107 and pitlb.
1108
8b5328ac
JB		 11092005-07-27 Jan Beulich <jbeulich@novell.com>
1110
1111 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1112 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1113 Add movq-s as 64-bit variants of movd-s.
1114
f417d200
DA		 11152005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1116
18b3bdfc
DA		 1117 * hppa.h: Fix punctuation in comment.
1118
f417d200
DA		 1119 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1120 implicit space-register addressing. Set space-register bits on opcodes
1121 using implicit space-register addressing. Add various missing pa20
1122 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1123 space-register addressing. Use "fE" instead of "fe" in various
1124 fstw opcodes.
1125
9a145ce6
JB		 11262005-07-18 Jan Beulich <jbeulich@novell.com>
1127
1128 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1129
90700ea2
L		 11302007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1131
1132 * i386.h (i386_optab): Support Intel VMX Instructions.
1133
48f130a8
DA		 11342005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1135
1136 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1137
30123838
JB		 11382005-07-05 Jan Beulich <jbeulich@novell.com>
1139
1140 * i386.h (i386_optab): Add new insns.
1141
47b0e7ad
NC		 11422005-07-01 Nick Clifton <nickc@redhat.com>
1143
1144 * sparc.h: Add typedefs to structure declarations.
1145
b300c311
L		 11462005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1147
1148 PR 1013
1149 * i386.h (i386_optab): Update comments for 64bit addressing on
1150 mov. Allow 64bit addressing for mov and movq.
1151
2db495be
DA		 11522005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1153
1154 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1155 respectively, in various floating-point load and store patterns.
1156
caa05036
DA		 11572005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1158
1159 * hppa.h (FLAG_STRICT): Correct comment.
1160 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1161 PA 2.0 mneumonics when equivalent. Entries with cache control
1162 completers now require PA 1.1. Adjust whitespace.
1163
f4411256
AM		 11642005-05-19 Anton Blanchard <anton@samba.org>
1165
1166 * ppc.h (PPC_OPCODE_POWER5): Define.
1167
e172dbf8
NC		 11682005-05-10 Nick Clifton <nickc@redhat.com>
1169
1170 * Update the address and phone number of the FSF organization in
1171 the GPL notices in the following files:
1172 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1173 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1174 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1175 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1176 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1177 tic54x.h, tic80.h, v850.h, vax.h
1178
e44823cf
JB		 11792005-05-09 Jan Beulich <jbeulich@novell.com>
1180
1181 * i386.h (i386_optab): Add ht and hnt.
1182
791fe849
MK		 11832005-04-18 Mark Kettenis <kettenis@gnu.org>
1184
1185 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1186 Add xcrypt-ctr. Provide aliases without hyphens.
1187
faa7ef87
L		 11882005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1189
a63027e5
L		 1190 Moved from ../ChangeLog
1191
faa7ef87
L		 1192 2005-04-12 Paul Brook <paul@codesourcery.com>
1193 * m88k.h: Rename psr macros to avoid conflicts.
1194
1195 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1196 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1197 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1198 and ARM_ARCH_V6ZKT2.
1199
1200 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1201 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1202 Remove redundant instruction types.
1203 (struct argument): X_op - new field.
1204 (struct cst4_entry): Remove.
1205 (no_op_insn): Declare.
1206
1207 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1208 * crx.h (enum argtype): Rename types, remove unused types.
1209
1210 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1211 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1212 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1213 (enum operand_type): Rearrange operands, edit comments.
1214 replace us<N> with ui<N> for unsigned immediate.
1215 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1216 displacements (respectively).
1217 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1218 (instruction type): Add NO_TYPE_INS.
1219 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1220 (operand_entry): New field - 'flags'.
1221 (operand flags): New.
1222
1223 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1224 * crx.h (operand_type): Remove redundant types i3, i4,
1225 i5, i8, i12.
1226 Add new unsigned immediate types us3, us4, us5, us16.
1227
bc4bd9ab
MK		 12282005-04-12 Mark Kettenis <kettenis@gnu.org>
1229
1230 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1231 adjust them accordingly.
1232
373ff435
JB		 12332005-04-01 Jan Beulich <jbeulich@novell.com>
1234
1235 * i386.h (i386_optab): Add rdtscp.
1236
4cc91dba
L		 12372005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1238
1239 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1240 between memory and segment register. Allow movq for moving between
1241 general-purpose register and segment register.
4cc91dba 1242
9ae09ff9
JB		 12432005-02-09 Jan Beulich <jbeulich@novell.com>
1244
1245 PR gas/707
1246 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1247 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1248 fnstsw.
1249
638e7a64
NS		 12502006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1251
1252 * m68k.h (m68008, m68ec030, m68882): Remove.
1253 (m68k_mask): New.
1254 (cpu_m68k, cpu_cf): New.
1255 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1256 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1257
90219bd0
AO		 12582005-01-25 Alexandre Oliva <aoliva@redhat.com>
1259
1260 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1261 * cgen.h (enum cgen_parse_operand_type): Add
1262 CGEN_PARSE_OPERAND_SYMBOLIC.
1263
239cb185
FF		 12642005-01-21 Fred Fish <fnf@specifixinc.com>
1265
1266 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1267 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1268 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1269
dc9a9f39
FF		 12702005-01-19 Fred Fish <fnf@specifixinc.com>
1271
1272 * mips.h (struct mips_opcode): Add new pinfo2 member.
1273 (INSN_ALIAS): New define for opcode table entries that are
1274 specific instances of another entry, such as 'move' for an 'or'
1275 with a zero operand.
1276 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1277 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1278
98e7aba8
ILT		 12792004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1280
1281 * mips.h (CPU_RM9000): Define.
1282 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1283
37edbb65
JB		 12842004-11-25 Jan Beulich <jbeulich@novell.com>
1285
1286 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1287 to/from test registers are illegal in 64-bit mode. Add missing
1288 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1289 (previously one had to explicitly encode a rex64 prefix). Re-enable
1290 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1291 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1292
12932004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1294
1295 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1296 available only with SSE2. Change the MMX additions introduced by SSE
1297 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1298 instructions by their now designated identifier (since combining i686
1299 and 3DNow! does not really imply 3DNow!A).
1300
f5c7edf4
AM		 13012004-11-19 Alan Modra <amodra@bigpond.net.au>
1302
1303 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1304 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1305
7499d566
NC		 13062004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1307 Vineet Sharma <vineets@noida.hcltech.com>
1308
1309 * maxq.h: New file: Disassembly information for the maxq port.
1310
bcb9eebe
L		 13112004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1312
1313 * i386.h (i386_optab): Put back "movzb".
1314
94bb3d38
HPN		 13152004-11-04 Hans-Peter Nilsson <hp@axis.com>
1316
1317 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1318 comments. Remove member cris_ver_sim. Add members
1319 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1320 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1321 (struct cris_support_reg, struct cris_cond15): New types.
1322 (cris_conds15): Declare.
1323 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1324 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1325 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1326 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1327 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1328 SIZE_FIELD_UNSIGNED.
1329
37edbb65 13302004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1331
1332 * i386.h (sldx_Suf): Remove.
1333 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1334 (q_FP): Define, implying no REX64.
1335 (x_FP, sl_FP): Imply FloatMF.
1336 (i386_optab): Split reg and mem forms of moving from segment registers
1337 so that the memory forms can ignore the 16-/32-bit operand size
1338 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1339 all non-floating-point instructions. Unite 32- and 64-bit forms of
1340 movsx, movzx, and movd. Adjust floating point operations for the above
1341 changes to the *FP macros. Add DefaultSize to floating point control
1342 insns operating on larger memory ranges. Remove left over comments
1343 hinting at certain insns being Intel-syntax ones where the ones
1344 actually meant are already gone.
1345
48c9f030
NC		 13462004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1347
1348 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1349 instruction type.
1350
0dd132b6
NC		 13512004-09-30 Paul Brook <paul@codesourcery.com>
1352
1353 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1354 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1355
23794b24
MM		 13562004-09-11 Theodore A. Roth <troth@openavr.org>
1357
1358 * avr.h: Add support for
1359 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1360
2a309db0
AM		 13612004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1362
1363 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1364
b18c562e
NC		 13652004-08-24 Dmitry Diky <diwil@spec.ru>
1366
1367 * msp430.h (msp430_opc): Add new instructions.
1368 (msp430_rcodes): Declare new instructions.
1369 (msp430_hcodes): Likewise..
1370
45d313cd
NC		 13712004-08-13 Nick Clifton <nickc@redhat.com>
1372
1373 PR/301
1374 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1375 processors.
1376
30d1c836
ML		 13772004-08-30 Michal Ludvig <mludvig@suse.cz>
1378
1379 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1380
9a45f1c2
L		 13812004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1382
1383 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1384
543613e9
NC		 13852004-07-21 Jan Beulich <jbeulich@novell.com>
1386
1387 * i386.h: Adjust instruction descriptions to better match the
1388 specification.
1389
b781e558
RE		 13902004-07-16 Richard Earnshaw <rearnsha@arm.com>
1391
1392 * arm.h: Remove all old content. Replace with architecture defines
1393 from gas/config/tc-arm.c.
1394
8577e690
AS		 13952004-07-09 Andreas Schwab <schwab@suse.de>
1396
1397 * m68k.h: Fix comment.
1398
1fe1f39c
NC		 13992004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1400
1401 * crx.h: New file.
1402
1d9f512f
AM		 14032004-06-24 Alan Modra <amodra@bigpond.net.au>
1404
1405 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1406
be8c092b
NC		 14072004-05-24 Peter Barada <peter@the-baradas.com>
1408
1409 * m68k.h: Add 'size' to m68k_opcode.
1410
6b6e92f4
NC		 14112004-05-05 Peter Barada <peter@the-baradas.com>
1412
1413 * m68k.h: Switch from ColdFire chip name to core variant.
1414
14152004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1416
1417 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1418 descriptions for new EMAC cases.
1419 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1420 handle Motorola MAC syntax.
1421 Allow disassembly of ColdFire V4e object files.
1422
fdd12ef3
AM		 14232004-03-16 Alan Modra <amodra@bigpond.net.au>
1424
1425 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1426
3922a64c
L		 14272004-03-12 Jakub Jelinek <jakub@redhat.com>
1428
1429 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1430
1f45d988
ML		 14312004-03-12 Michal Ludvig <mludvig@suse.cz>
1432
1433 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1434
0f10071e
ML		 14352004-03-12 Michal Ludvig <mludvig@suse.cz>
1436
1437 * i386.h (i386_optab): Added xstore/xcrypt insns.
1438
3255318a
NC		 14392004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1440
1441 * h8300.h (32bit ldc/stc): Add relaxing support.
1442
ca9a79a1 14432004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1444
ca9a79a1
NC		 1445 * h8300.h (BITOP): Pass MEMRELAX flag.
1446
875a0b14
NC		 14472004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1448
1449 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1450 except for the H8S.
252b5132 1451
c9e214e5 1452For older changes see ChangeLog-9103
252b5132
RH		 1453\f
1454Local Variables:
c9e214e5
AM		 1455mode: change-log
1456left-margin: 8
1457fill-column: 74
252b5132
RH		 1458version-control: never
1459End:
GDB Binutils - Deliverables
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