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[AArch64] Add ARMv8.3 command line option and feature flag
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
6f2750fe 3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
40#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 41#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 42#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 43#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
44#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
45#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 46#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 47#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 48#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 49#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 50#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 51#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 52#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 53#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 54#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 55#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
a06ea964
NC		 56
57/* Architectures are the sum of the base and extensions. */
58#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
59 AARCH64_FEATURE_FP \
60 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 61#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
62 AARCH64_FEATURE_CRC \
250aafa4 63 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
1924ff75 68#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 69 AARCH64_FEATURE_V8_2 \
87018195 70 | AARCH64_FEATURE_F16 \
1924ff75
SN		 71 | AARCH64_FEATURE_RAS)
72#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
73 AARCH64_FEATURE_V8_3)
88f0ea34 74
a06ea964
NC		 75#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
76#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
77
78/* CPU-specific features. */
79typedef unsigned long aarch64_feature_set;
80
93d8990c
SN		 81#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
82 ((~(CPU) & (FEAT)) == 0)
83
84#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 85 (((CPU) & (FEAT)) != 0)
86
93d8990c
SN		 87#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
88 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
89
a06ea964
NC		 90#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
91 do \
92 { \
93 (TARG) = (F1) | (F2); \
94 } \
95 while (0)
96
97#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
98 do \
99 { \
100 (TARG) = (F1) &~ (F2); \
101 } \
102 while (0)
103
104#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
105
a06ea964
NC		 106enum aarch64_operand_class
107{
108 AARCH64_OPND_CLASS_NIL,
109 AARCH64_OPND_CLASS_INT_REG,
110 AARCH64_OPND_CLASS_MODIFIED_REG,
111 AARCH64_OPND_CLASS_FP_REG,
112 AARCH64_OPND_CLASS_SIMD_REG,
113 AARCH64_OPND_CLASS_SIMD_ELEMENT,
114 AARCH64_OPND_CLASS_SISD_REG,
115 AARCH64_OPND_CLASS_SIMD_REGLIST,
116 AARCH64_OPND_CLASS_CP_REG,
f11ad6bc
RS		 117 AARCH64_OPND_CLASS_SVE_REG,
118 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 119 AARCH64_OPND_CLASS_ADDRESS,
120 AARCH64_OPND_CLASS_IMMEDIATE,
121 AARCH64_OPND_CLASS_SYSTEM,
68a64283 122 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 123};
124
125/* Operand code that helps both parsing and coding.
126 Keep AARCH64_OPERANDS synced. */
127
128enum aarch64_opnd
129{
130 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
131
132 AARCH64_OPND_Rd, /* Integer register as destination. */
133 AARCH64_OPND_Rn, /* Integer register as source. */
134 AARCH64_OPND_Rm, /* Integer register as source. */
135 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
136 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
137 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
138 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
139 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
140
141 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
142 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
ee804238 143 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 144 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
145 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
146
147 AARCH64_OPND_Fd, /* Floating-point Fd. */
148 AARCH64_OPND_Fn, /* Floating-point Fn. */
149 AARCH64_OPND_Fm, /* Floating-point Fm. */
150 AARCH64_OPND_Fa, /* Floating-point Fa. */
151 AARCH64_OPND_Ft, /* Floating-point Ft. */
152 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
153
154 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
155 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
156 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
157
158 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
159 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
160 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
161 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
162 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
163 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
164 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
165 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
166 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
167 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
168 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
169 structure to all lanes. */
170 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
171
172 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
173 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
174
175 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
176 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
177 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
178 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
179 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
180 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
181 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
182 (no encoding). */
183 AARCH64_OPND_IMM0, /* Immediate for #0. */
184 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
185 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
186 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
187 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
188 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
189 AARCH64_OPND_IMM, /* Immediate. */
190 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
191 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
192 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
194 AARCH64_OPND_BIT_NUM, /* Immediate. */
195 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
196 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 197 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 198 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
199 each condition flag. */
200
201 AARCH64_OPND_LIMM, /* Logical Immediate. */
202 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
203 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
204 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
205 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
206
207 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 208 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 209
210 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
211 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
212 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
213 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
214 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
215
216 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
217 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
218 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
219 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
220 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
221 negative or unaligned and there is
222 no writeback allowed. This operand code
223 is only used to support the programmer-
224 friendly feature of using LDR/STR as the
225 the mnemonic name for LDUR/STUR instructions
226 wherever there is no ambiguity. */
227 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
228 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
229 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
230
231 AARCH64_OPND_SYSREG, /* System register operand. */
232 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
233 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
234 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
235 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
236 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
237 AARCH64_OPND_BARRIER, /* Barrier operand. */
238 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
239 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 240 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 241
98907a70
RS		 242 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
243 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
244 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
245 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
246 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
247 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 248 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
249 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
250 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
251 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
252 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
253 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
254 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
255 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
256 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
257 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
258 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
259 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
260 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
261 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
262 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
263 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
264 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
265 Bit 14 controls S/U choice. */
266 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
267 Bit 22 controls S/U choice. */
268 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
269 Bit 14 controls S/U choice. */
270 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
271 Bit 22 controls S/U choice. */
272 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
273 Bit 14 controls S/U choice. */
274 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
275 Bit 22 controls S/U choice. */
276 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
277 Bit 14 controls S/U choice. */
278 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
279 Bit 22 controls S/U choice. */
280 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
281 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
282 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
283 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
284 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
285 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
286 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 287 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
288 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 289 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
290 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
291 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
292 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
e950b345
RS		 293 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
294 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
295 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 296 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 297 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 298 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 299 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
300 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
301 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
302 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
303 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
304 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
305 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
306 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 307 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
308 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 309 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
310 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
311 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
312 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
313 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
314 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
315 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
316 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
317 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
318 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
319 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
320 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 321 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
322 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
323 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
324 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 325 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
326 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
327 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
328 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
329 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
330 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
331 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
332 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
333 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
334 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
a06ea964
NC		 335};
336
337/* Qualifier constrains an operand. It either specifies a variant of an
338 operand type or limits values available to an operand type.
339
340 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
341
342enum aarch64_opnd_qualifier
343{
344 /* Indicating no further qualification on an operand. */
345 AARCH64_OPND_QLF_NIL,
346
347 /* Qualifying an operand which is a general purpose (integer) register;
348 indicating the operand data size or a specific register. */
349 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
350 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
351 AARCH64_OPND_QLF_WSP, /* WSP. */
352 AARCH64_OPND_QLF_SP, /* SP. */
353
354 /* Qualifying an operand which is a floating-point register, a SIMD
355 vector element or a SIMD vector element list; indicating operand data
356 size or the size of each SIMD vector element in the case of a SIMD
357 vector element list.
358 These qualifiers are also used to qualify an address operand to
359 indicate the size of data element a load/store instruction is
360 accessing.
361 They are also used for the immediate shift operand in e.g. SSHR. Such
362 a use is only for the ease of operand encoding/decoding and qualifier
363 sequence matching; such a use should not be applied widely; use the value
364 constraint qualifiers for immediate operands wherever possible. */
365 AARCH64_OPND_QLF_S_B,
366 AARCH64_OPND_QLF_S_H,
367 AARCH64_OPND_QLF_S_S,
368 AARCH64_OPND_QLF_S_D,
369 AARCH64_OPND_QLF_S_Q,
370
371 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
372 register list; indicating register shape.
373 They are also used for the immediate shift operand in e.g. SSHR. Such
374 a use is only for the ease of operand encoding/decoding and qualifier
375 sequence matching; such a use should not be applied widely; use the value
376 constraint qualifiers for immediate operands wherever possible. */
377 AARCH64_OPND_QLF_V_8B,
378 AARCH64_OPND_QLF_V_16B,
3067d3b9 379 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 380 AARCH64_OPND_QLF_V_4H,
381 AARCH64_OPND_QLF_V_8H,
382 AARCH64_OPND_QLF_V_2S,
383 AARCH64_OPND_QLF_V_4S,
384 AARCH64_OPND_QLF_V_1D,
385 AARCH64_OPND_QLF_V_2D,
386 AARCH64_OPND_QLF_V_1Q,
387
d50c751e
RS		 388 AARCH64_OPND_QLF_P_Z,
389 AARCH64_OPND_QLF_P_M,
390
a06ea964
NC		 391 /* Constraint on value. */
392 AARCH64_OPND_QLF_imm_0_7,
393 AARCH64_OPND_QLF_imm_0_15,
394 AARCH64_OPND_QLF_imm_0_31,
395 AARCH64_OPND_QLF_imm_0_63,
396 AARCH64_OPND_QLF_imm_1_32,
397 AARCH64_OPND_QLF_imm_1_64,
398
399 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
400 or shift-ones. */
401 AARCH64_OPND_QLF_LSL,
402 AARCH64_OPND_QLF_MSL,
403
404 /* Special qualifier helping retrieve qualifier information during the
405 decoding time (currently not in use). */
406 AARCH64_OPND_QLF_RETRIEVE,
407};
408\f
409/* Instruction class. */
410
411enum aarch64_insn_class
412{
413 addsub_carry,
414 addsub_ext,
415 addsub_imm,
416 addsub_shift,
417 asimdall,
418 asimddiff,
419 asimdelem,
420 asimdext,
421 asimdimm,
422 asimdins,
423 asimdmisc,
424 asimdperm,
425 asimdsame,
426 asimdshf,
427 asimdtbl,
428 asisddiff,
429 asisdelem,
430 asisdlse,
431 asisdlsep,
432 asisdlso,
433 asisdlsop,
434 asisdmisc,
435 asisdone,
436 asisdpair,
437 asisdsame,
438 asisdshf,
439 bitfield,
440 branch_imm,
441 branch_reg,
442 compbranch,
443 condbranch,
444 condcmp_imm,
445 condcmp_reg,
446 condsel,
447 cryptoaes,
448 cryptosha2,
449 cryptosha3,
450 dp_1src,
451 dp_2src,
452 dp_3src,
453 exception,
454 extract,
455 float2fix,
456 float2int,
457 floatccmp,
458 floatcmp,
459 floatdp1,
460 floatdp2,
461 floatdp3,
462 floatimm,
463 floatsel,
464 ldst_immpost,
465 ldst_immpre,
466 ldst_imm9, /* immpost or immpre */
467 ldst_pos,
468 ldst_regoff,
469 ldst_unpriv,
470 ldst_unscaled,
471 ldstexcl,
472 ldstnapair_offs,
473 ldstpair_off,
474 ldstpair_indexed,
475 loadlit,
476 log_imm,
477 log_shift,
ee804238 478 lse_atomic,
a06ea964
NC		 479 movewide,
480 pcreladdr,
481 ic_system,
116b6019
RS		 482 sve_cpy,
483 sve_index,
484 sve_limm,
485 sve_misc,
486 sve_movprfx,
487 sve_pred_zm,
488 sve_shift_pred,
489 sve_shift_unpred,
490 sve_size_bhs,
491 sve_size_bhsd,
492 sve_size_hsd,
493 sve_size_sd,
a06ea964
NC		 494 testbranch,
495};
496
497/* Opcode enumerators. */
498
499enum aarch64_op
500{
501 OP_NIL,
502 OP_STRB_POS,
503 OP_LDRB_POS,
504 OP_LDRSB_POS,
505 OP_STRH_POS,
506 OP_LDRH_POS,
507 OP_LDRSH_POS,
508 OP_STR_POS,
509 OP_LDR_POS,
510 OP_STRF_POS,
511 OP_LDRF_POS,
512 OP_LDRSW_POS,
513 OP_PRFM_POS,
514
515 OP_STURB,
516 OP_LDURB,
517 OP_LDURSB,
518 OP_STURH,
519 OP_LDURH,
520 OP_LDURSH,
521 OP_STUR,
522 OP_LDUR,
523 OP_STURV,
524 OP_LDURV,
525 OP_LDURSW,
526 OP_PRFUM,
527
528 OP_LDR_LIT,
529 OP_LDRV_LIT,
530 OP_LDRSW_LIT,
531 OP_PRFM_LIT,
532
533 OP_ADD,
534 OP_B,
535 OP_BL,
536
537 OP_MOVN,
538 OP_MOVZ,
539 OP_MOVK,
540
541 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
542 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
543 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
544
545 OP_MOV_V, /* MOV alias for moving vector register. */
546
547 OP_ASR_IMM,
548 OP_LSR_IMM,
549 OP_LSL_IMM,
550
551 OP_BIC,
552
553 OP_UBFX,
554 OP_BFXIL,
555 OP_SBFX,
556 OP_SBFIZ,
557 OP_BFI,
d685192a 558 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 559 OP_UBFIZ,
560 OP_UXTB,
561 OP_UXTH,
562 OP_UXTW,
563
a06ea964
NC		 564 OP_CINC,
565 OP_CINV,
566 OP_CNEG,
567 OP_CSET,
568 OP_CSETM,
569
570 OP_FCVT,
571 OP_FCVTN,
572 OP_FCVTN2,
573 OP_FCVTL,
574 OP_FCVTL2,
575 OP_FCVTXN_S, /* Scalar version. */
576
577 OP_ROR_IMM,
578
e30181a5
YZ		 579 OP_SXTL,
580 OP_SXTL2,
581 OP_UXTL,
582 OP_UXTL2,
583
c0890d26
RS		 584 OP_MOV_P_P,
585 OP_MOV_Z_P_Z,
586 OP_MOV_Z_V,
587 OP_MOV_Z_Z,
588 OP_MOV_Z_Zi,
589 OP_MOVM_P_P_P,
590 OP_MOVS_P_P,
591 OP_MOVZS_P_P_P,
592 OP_MOVZ_P_P_P,
593 OP_NOTS_P_P_P_Z,
594 OP_NOT_P_P_P_Z,
595
a06ea964
NC		 596 OP_TOTAL_NUM, /* Pseudo. */
597};
598
599/* Maximum number of operands an instruction can have. */
600#define AARCH64_MAX_OPND_NUM 6
601/* Maximum number of qualifier sequences an instruction can have. */
602#define AARCH64_MAX_QLF_SEQ_NUM 10
603/* Operand qualifier typedef; optimized for the size. */
604typedef unsigned char aarch64_opnd_qualifier_t;
605/* Operand qualifier sequence typedef. */
606typedef aarch64_opnd_qualifier_t \
607 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
608
609/* FIXME: improve the efficiency. */
610static inline bfd_boolean
611empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
612{
613 int i;
614 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
615 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
616 return FALSE;
617 return TRUE;
618}
619
620/* This structure holds information for a particular opcode. */
621
622struct aarch64_opcode
623{
624 /* The name of the mnemonic. */
625 const char *name;
626
627 /* The opcode itself. Those bits which will be filled in with
628 operands are zeroes. */
629 aarch64_insn opcode;
630
631 /* The opcode mask. This is used by the disassembler. This is a
632 mask containing ones indicating those bits which must match the
633 opcode field, and zeroes indicating those bits which need not
634 match (and are presumably filled in by operands). */
635 aarch64_insn mask;
636
637 /* Instruction class. */
638 enum aarch64_insn_class iclass;
639
640 /* Enumerator identifier. */
641 enum aarch64_op op;
642
643 /* Which architecture variant provides this instruction. */
644 const aarch64_feature_set *avariant;
645
646 /* An array of operand codes. Each code is an index into the
647 operand table. They appear in the order which the operands must
648 appear in assembly code, and are terminated by a zero. */
649 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
650
651 /* A list of operand qualifier code sequence. Each operand qualifier
652 code qualifies the corresponding operand code. Each operand
653 qualifier sequence specifies a valid opcode variant and related
654 constraint on operands. */
655 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
656
657 /* Flags providing information about this instruction */
658 uint32_t flags;
4bd13cde 659
0c608d6b
RS		 660 /* If nonzero, this operand and operand 0 are both registers and
661 are required to have the same register number. */
662 unsigned char tied_operand;
663
4bd13cde
NC		 664 /* If non-NULL, a function to verify that a given instruction is valid. */
665 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 666};
667
668typedef struct aarch64_opcode aarch64_opcode;
669
670/* Table describing all the AArch64 opcodes. */
671extern aarch64_opcode aarch64_opcode_table[];
672
673/* Opcode flags. */
674#define F_ALIAS (1 << 0)
675#define F_HAS_ALIAS (1 << 1)
676/* Disassembly preference priority 1-3 (the larger the higher). If nothing
677 is specified, it is the priority 0 by default, i.e. the lowest priority. */
678#define F_P1 (1 << 2)
679#define F_P2 (2 << 2)
680#define F_P3 (3 << 2)
681/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
682#define F_COND (1 << 4)
683/* Instruction has the field of 'sf'. */
684#define F_SF (1 << 5)
685/* Instruction has the field of 'size:Q'. */
686#define F_SIZEQ (1 << 6)
687/* Floating-point instruction has the field of 'type'. */
688#define F_FPTYPE (1 << 7)
689/* AdvSIMD scalar instruction has the field of 'size'. */
690#define F_SSIZE (1 << 8)
691/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
692#define F_T (1 << 9)
693/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
694#define F_GPRSIZE_IN_Q (1 << 10)
695/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
696#define F_LDS_SIZE (1 << 11)
697/* Optional operand; assume maximum of 1 operand can be optional. */
698#define F_OPD0_OPT (1 << 12)
699#define F_OPD1_OPT (2 << 12)
700#define F_OPD2_OPT (3 << 12)
701#define F_OPD3_OPT (4 << 12)
702#define F_OPD4_OPT (5 << 12)
703/* Default value for the optional operand when omitted from the assembly. */
704#define F_DEFAULT(X) (((X) & 0x1f) << 15)
705/* Instruction that is an alias of another instruction needs to be
706 encoded/decoded by converting it to/from the real form, followed by
707 the encoding/decoding according to the rules of the real opcode.
708 This compares to the direct coding using the alias's information.
709 N.B. this flag requires F_ALIAS to be used together. */
710#define F_CONV (1 << 20)
711/* Use together with F_ALIAS to indicate an alias opcode is a programmer
712 friendly pseudo instruction available only in the assembly code (thus will
713 not show up in the disassembly). */
714#define F_PSEUDO (1 << 21)
715/* Instruction has miscellaneous encoding/decoding rules. */
716#define F_MISC (1 << 22)
717/* Instruction has the field of 'N'; used in conjunction with F_SF. */
718#define F_N (1 << 23)
719/* Opcode dependent field. */
720#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 721/* Instruction has the field of 'sz'. */
722#define F_LSE_SZ (1 << 27)
4989adac
RS		 723/* Require an exact qualifier match, even for NIL qualifiers. */
724#define F_STRICT (1ULL << 28)
725/* Next bit is 29. */
a06ea964
NC		 726
727static inline bfd_boolean
728alias_opcode_p (const aarch64_opcode *opcode)
729{
730 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
731}
732
733static inline bfd_boolean
734opcode_has_alias (const aarch64_opcode *opcode)
735{
736 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
737}
738
739/* Priority for disassembling preference. */
740static inline int
741opcode_priority (const aarch64_opcode *opcode)
742{
743 return (opcode->flags >> 2) & 0x3;
744}
745
746static inline bfd_boolean
747pseudo_opcode_p (const aarch64_opcode *opcode)
748{
749 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
750}
751
752static inline bfd_boolean
753optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
754{
755 return (((opcode->flags >> 12) & 0x7) == idx + 1)
756 ? TRUE : FALSE;
757}
758
759static inline aarch64_insn
760get_optional_operand_default_value (const aarch64_opcode *opcode)
761{
762 return (opcode->flags >> 15) & 0x1f;
763}
764
765static inline unsigned int
766get_opcode_dependent_value (const aarch64_opcode *opcode)
767{
768 return (opcode->flags >> 24) & 0x7;
769}
770
771static inline bfd_boolean
772opcode_has_special_coder (const aarch64_opcode *opcode)
773{
ee804238 774 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 775 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
776 : FALSE;
777}
778\f
779struct aarch64_name_value_pair
780{
781 const char * name;
782 aarch64_insn value;
783};
784
785extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 786extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
787extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 788extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 789
49eec193
YZ		 790typedef struct
791{
792 const char * name;
793 aarch64_insn value;
794 uint32_t flags;
795} aarch64_sys_reg;
796
797extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 798extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 799extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 800extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
801 const aarch64_sys_reg *);
802extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
803 const aarch64_sys_reg *);
49eec193 804
a06ea964
NC		 805typedef struct
806{
875880c6 807 const char *name;
a06ea964 808 uint32_t value;
ea2deeec 809 uint32_t flags ;
a06ea964
NC		 810} aarch64_sys_ins_reg;
811
ea2deeec 812extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 813extern bfd_boolean
814aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
815 const aarch64_sys_ins_reg *);
ea2deeec 816
a06ea964
NC		 817extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
818extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
819extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
820extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
821
822/* Shift/extending operator kinds.
823 N.B. order is important; keep aarch64_operand_modifiers synced. */
824enum aarch64_modifier_kind
825{
826 AARCH64_MOD_NONE,
827 AARCH64_MOD_MSL,
828 AARCH64_MOD_ROR,
829 AARCH64_MOD_ASR,
830 AARCH64_MOD_LSR,
831 AARCH64_MOD_LSL,
832 AARCH64_MOD_UXTB,
833 AARCH64_MOD_UXTH,
834 AARCH64_MOD_UXTW,
835 AARCH64_MOD_UXTX,
836 AARCH64_MOD_SXTB,
837 AARCH64_MOD_SXTH,
838 AARCH64_MOD_SXTW,
839 AARCH64_MOD_SXTX,
2442d846 840 AARCH64_MOD_MUL,
98907a70 841 AARCH64_MOD_MUL_VL,
a06ea964
NC		 842};
843
844bfd_boolean
845aarch64_extend_operator_p (enum aarch64_modifier_kind);
846
847enum aarch64_modifier_kind
848aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
849/* Condition. */
850
851typedef struct
852{
853 /* A list of names with the first one as the disassembly preference;
854 terminated by NULL if fewer than 3. */
bb7eff52 855 const char *names[4];
a06ea964
NC		 856 aarch64_insn value;
857} aarch64_cond;
858
859extern const aarch64_cond aarch64_conds[16];
860
861const aarch64_cond* get_cond_from_value (aarch64_insn value);
862const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
863\f
864/* Structure representing an operand. */
865
866struct aarch64_opnd_info
867{
868 enum aarch64_opnd type;
869 aarch64_opnd_qualifier_t qualifier;
870 int idx;
871
872 union
873 {
874 struct
875 {
876 unsigned regno;
877 } reg;
878 struct
879 {
dab26bf4
RS		 880 unsigned int regno;
881 int64_t index;
a06ea964
NC		 882 } reglane;
883 /* e.g. LVn. */
884 struct
885 {
886 unsigned first_regno : 5;
887 unsigned num_regs : 3;
888 /* 1 if it is a list of reg element. */
889 unsigned has_index : 1;
890 /* Lane index; valid only when has_index is 1. */
dab26bf4 891 int64_t index;
a06ea964
NC		 892 } reglist;
893 /* e.g. immediate or pc relative address offset. */
894 struct
895 {
896 int64_t value;
897 unsigned is_fp : 1;
898 } imm;
899 /* e.g. address in STR (register offset). */
900 struct
901 {
902 unsigned base_regno;
903 struct
904 {
905 union
906 {
907 int imm;
908 unsigned regno;
909 };
910 unsigned is_reg;
911 } offset;
912 unsigned pcrel : 1; /* PC-relative. */
913 unsigned writeback : 1;
914 unsigned preind : 1; /* Pre-indexed. */
915 unsigned postind : 1; /* Post-indexed. */
916 } addr;
917 const aarch64_cond *cond;
918 /* The encoding of the system register. */
919 aarch64_insn sysreg;
920 /* The encoding of the PSTATE field. */
921 aarch64_insn pstatefield;
922 const aarch64_sys_ins_reg *sysins_op;
923 const struct aarch64_name_value_pair *barrier;
9ed608f9 924 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 925 const struct aarch64_name_value_pair *prfop;
926 };
927
928 /* Operand shifter; in use when the operand is a register offset address,
929 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
930 struct
931 {
932 enum aarch64_modifier_kind kind;
a06ea964
NC		 933 unsigned operator_present: 1; /* Only valid during encoding. */
934 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
935 unsigned amount_present: 1;
2442d846 936 int64_t amount;
a06ea964
NC		 937 } shifter;
938
939 unsigned skip:1; /* Operand is not completed if there is a fixup needed
940 to be done on it. In some (but not all) of these
941 cases, we need to tell libopcodes to skip the
942 constraint checking and the encoding for this
943 operand, so that the libopcodes can pick up the
944 right opcode before the operand is fixed-up. This
945 flag should only be used during the
946 assembling/encoding. */
947 unsigned present:1; /* Whether this operand is present in the assembly
948 line; not used during the disassembly. */
949};
950
951typedef struct aarch64_opnd_info aarch64_opnd_info;
952
953/* Structure representing an instruction.
954
955 It is used during both the assembling and disassembling. The assembler
956 fills an aarch64_inst after a successful parsing and then passes it to the
957 encoding routine to do the encoding. During the disassembling, the
958 disassembler calls the decoding routine to decode a binary instruction; on a
959 successful return, such a structure will be filled with information of the
960 instruction; then the disassembler uses the information to print out the
961 instruction. */
962
963struct aarch64_inst
964{
965 /* The value of the binary instruction. */
966 aarch64_insn value;
967
968 /* Corresponding opcode entry. */
969 const aarch64_opcode *opcode;
970
971 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
972 const aarch64_cond *cond;
973
974 /* Operands information. */
975 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
976};
977
978typedef struct aarch64_inst aarch64_inst;
979\f
980/* Diagnosis related declaration and interface. */
981
982/* Operand error kind enumerators.
983
984 AARCH64_OPDE_RECOVERABLE
985 Less severe error found during the parsing, very possibly because that
986 GAS has picked up a wrong instruction template for the parsing.
987
988 AARCH64_OPDE_SYNTAX_ERROR
989 General syntax error; it can be either a user error, or simply because
990 that GAS is trying a wrong instruction template.
991
992 AARCH64_OPDE_FATAL_SYNTAX_ERROR
993 Definitely a user syntax error.
994
995 AARCH64_OPDE_INVALID_VARIANT
996 No syntax error, but the operands are not a valid combination, e.g.
997 FMOV D0,S0
998
0c608d6b
RS		 999 AARCH64_OPDE_UNTIED_OPERAND
1000 The asm failed to use the same register for a destination operand
1001 and a tied source operand.
1002
a06ea964
NC		 1003 AARCH64_OPDE_OUT_OF_RANGE
1004 Error about some immediate value out of a valid range.
1005
1006 AARCH64_OPDE_UNALIGNED
1007 Error about some immediate value not properly aligned (i.e. not being a
1008 multiple times of a certain value).
1009
1010 AARCH64_OPDE_REG_LIST
1011 Error about the register list operand having unexpected number of
1012 registers.
1013
1014 AARCH64_OPDE_OTHER_ERROR
1015 Error of the highest severity and used for any severe issue that does not
1016 fall into any of the above categories.
1017
1018 The enumerators are only interesting to GAS. They are declared here (in
1019 libopcodes) because that some errors are detected (and then notified to GAS)
1020 by libopcodes (rather than by GAS solely).
1021
1022 The first three errors are only deteced by GAS while the
1023 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1024 only libopcodes has the information about the valid variants of each
1025 instruction.
1026
1027 The enumerators have an increasing severity. This is helpful when there are
1028 multiple instruction templates available for a given mnemonic name (e.g.
1029 FMOV); this mechanism will help choose the most suitable template from which
1030 the generated diagnostics can most closely describe the issues, if any. */
1031
1032enum aarch64_operand_error_kind
1033{
1034 AARCH64_OPDE_NIL,
1035 AARCH64_OPDE_RECOVERABLE,
1036 AARCH64_OPDE_SYNTAX_ERROR,
1037 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1038 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1039 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1040 AARCH64_OPDE_OUT_OF_RANGE,
1041 AARCH64_OPDE_UNALIGNED,
1042 AARCH64_OPDE_REG_LIST,
1043 AARCH64_OPDE_OTHER_ERROR
1044};
1045
1046/* N.B. GAS assumes that this structure work well with shallow copy. */
1047struct aarch64_operand_error
1048{
1049 enum aarch64_operand_error_kind kind;
1050 int index;
1051 const char *error;
1052 int data[3]; /* Some data for extra information. */
1053};
1054
1055typedef struct aarch64_operand_error aarch64_operand_error;
1056
1057/* Encoding entrypoint. */
1058
1059extern int
1060aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1061 aarch64_insn *, aarch64_opnd_qualifier_t *,
1062 aarch64_operand_error *);
1063
1064extern const aarch64_opcode *
1065aarch64_replace_opcode (struct aarch64_inst *,
1066 const aarch64_opcode *);
1067
1068/* Given the opcode enumerator OP, return the pointer to the corresponding
1069 opcode entry. */
1070
1071extern const aarch64_opcode *
1072aarch64_get_opcode (enum aarch64_op);
1073
1074/* Generate the string representation of an operand. */
1075extern void
1076aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1077 const aarch64_opnd_info *, int, int *, bfd_vma *);
1078
1079/* Miscellaneous interface. */
1080
1081extern int
1082aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1083
1084extern aarch64_opnd_qualifier_t
1085aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1086 const aarch64_opnd_qualifier_t, int);
1087
1088extern int
1089aarch64_num_of_operands (const aarch64_opcode *);
1090
1091extern int
1092aarch64_stack_pointer_p (const aarch64_opnd_info *);
1093
e141d84e
YQ		 1094extern int
1095aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1096
36f4aab1 1097extern int
43cdf5ae 1098aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1099
a06ea964
NC		 1100/* Given an operand qualifier, return the expected data element size
1101 of a qualified operand. */
1102extern unsigned char
1103aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1104
1105extern enum aarch64_operand_class
1106aarch64_get_operand_class (enum aarch64_opnd);
1107
1108extern const char *
1109aarch64_get_operand_name (enum aarch64_opnd);
1110
1111extern const char *
1112aarch64_get_operand_desc (enum aarch64_opnd);
1113
e950b345
RS		 1114extern bfd_boolean
1115aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1116
a06ea964
NC		 1117#ifdef DEBUG_AARCH64
1118extern int debug_dump;
1119
1120extern void
1121aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1122
1123#define DEBUG_TRACE(M, ...) \
1124 { \
1125 if (debug_dump) \
1126 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1127 }
1128
1129#define DEBUG_TRACE_IF(C, M, ...) \
1130 { \
1131 if (debug_dump && (C)) \
1132 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1133 }
1134#else /* !DEBUG_AARCH64 */
1135#define DEBUG_TRACE(M, ...) ;
1136#define DEBUG_TRACE_IF(C, M, ...) ;
1137#endif /* DEBUG_AARCH64 */
1138
245d2e3f
RS		 1139extern const char *const aarch64_sve_pattern_array[32];
1140extern const char *const aarch64_sve_prfop_array[16];
1141
d3e12b29
YQ		 1142#ifdef __cplusplus
1143}
1144#endif
1145
a06ea964 1146#endif /* OPCODE_AARCH64_H */
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