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[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
13c60ad7 75
a06ea964
NC		 76/* Architectures are the sum of the base and extensions. */
77#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
78 AARCH64_FEATURE_FP \
79 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 80#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
81 AARCH64_FEATURE_CRC \
250aafa4 82 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 83 | AARCH64_FEATURE_LSE \
84 | AARCH64_FEATURE_PAN \
85 | AARCH64_FEATURE_LOR \
86 | AARCH64_FEATURE_RDMA)
1924ff75 87#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 88 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 89 | AARCH64_FEATURE_RAS)
90#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 91 AARCH64_FEATURE_V8_3 \
f482d304
RS		 92 | AARCH64_FEATURE_RCPC \
93 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 94#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 95 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 96 | AARCH64_FEATURE_DOTPROD \
97 | AARCH64_FEATURE_F16_FML)
70d56181 98#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 99 AARCH64_FEATURE_V8_5 \
100 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 101 | AARCH64_FEATURE_FRINTTS \
2ac435d4
SD		 102 | AARCH64_FEATURE_SB \
103 | AARCH64_FEATURE_PREDRES)
70d56181 104
88f0ea34 105
a06ea964
NC		 106#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
107#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
108
109/* CPU-specific features. */
21b81e67 110typedef unsigned long long aarch64_feature_set;
a06ea964 111
93d8990c
SN		 112#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
113 ((~(CPU) & (FEAT)) == 0)
114
115#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 116 (((CPU) & (FEAT)) != 0)
117
93d8990c
SN		 118#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
119 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
120
a06ea964
NC		 121#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
122 do \
123 { \
124 (TARG) = (F1) | (F2); \
125 } \
126 while (0)
127
128#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
129 do \
130 { \
131 (TARG) = (F1) &~ (F2); \
132 } \
133 while (0)
134
135#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
136
a06ea964
NC		 137enum aarch64_operand_class
138{
139 AARCH64_OPND_CLASS_NIL,
140 AARCH64_OPND_CLASS_INT_REG,
141 AARCH64_OPND_CLASS_MODIFIED_REG,
142 AARCH64_OPND_CLASS_FP_REG,
143 AARCH64_OPND_CLASS_SIMD_REG,
144 AARCH64_OPND_CLASS_SIMD_ELEMENT,
145 AARCH64_OPND_CLASS_SISD_REG,
146 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 147 AARCH64_OPND_CLASS_SVE_REG,
148 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 149 AARCH64_OPND_CLASS_ADDRESS,
150 AARCH64_OPND_CLASS_IMMEDIATE,
151 AARCH64_OPND_CLASS_SYSTEM,
68a64283 152 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 153};
154
155/* Operand code that helps both parsing and coding.
156 Keep AARCH64_OPERANDS synced. */
157
158enum aarch64_opnd
159{
160 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
161
162 AARCH64_OPND_Rd, /* Integer register as destination. */
163 AARCH64_OPND_Rn, /* Integer register as source. */
164 AARCH64_OPND_Rm, /* Integer register as source. */
165 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
166 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
167 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
168 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
169 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
170
171 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
172 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 173 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 174 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 175 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
176 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
177
178 AARCH64_OPND_Fd, /* Floating-point Fd. */
179 AARCH64_OPND_Fn, /* Floating-point Fn. */
180 AARCH64_OPND_Fm, /* Floating-point Fm. */
181 AARCH64_OPND_Fa, /* Floating-point Fa. */
182 AARCH64_OPND_Ft, /* Floating-point Ft. */
183 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
184
185 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
186 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
187 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
188
f42f1a1d 189 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 190 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
191 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
192 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
193 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
194 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
195 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
196 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
197 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 198 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
199 qualifier is S_H. */
a06ea964
NC		 200 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
201 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
202 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
203 structure to all lanes. */
204 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
205
a6a51754
RL		 206 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
207 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 208
209 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 210 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 211 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
212 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
213 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
214 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
215 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
216 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
217 (no encoding). */
218 AARCH64_OPND_IMM0, /* Immediate for #0. */
219 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
220 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
221 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
222 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
223 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
224 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 225 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 226 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
227 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
228 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
229 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
230 AARCH64_OPND_BIT_NUM, /* Immediate. */
231 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
232 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 233 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 234 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
235 each condition flag. */
236
237 AARCH64_OPND_LIMM, /* Logical Immediate. */
238 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
239 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
240 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
241 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 242 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
243 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
244 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 245
246 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 247 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 248
249 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
250 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
251 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
252 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
253 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
254
255 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
256 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
257 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
258 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
259 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
260 negative or unaligned and there is
261 no writeback allowed. This operand code
262 is only used to support the programmer-
263 friendly feature of using LDR/STR as the
264 the mnemonic name for LDUR/STUR instructions
265 wherever there is no ambiguity. */
3f06e550 266 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 267 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
268 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 269 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 270 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
271
272 AARCH64_OPND_SYSREG, /* System register operand. */
273 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
274 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
275 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
276 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
277 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 278 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 279 AARCH64_OPND_BARRIER, /* Barrier operand. */
280 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
281 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 282 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 283
582e12bf 284 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 285 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
286 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
287 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
288 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
289 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
290 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 291 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
292 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
293 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
294 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 295 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 296 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
297 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
298 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
299 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
300 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
301 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
302 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
303 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
304 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
305 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
306 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
307 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
308 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
309 Bit 14 controls S/U choice. */
310 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
311 Bit 22 controls S/U choice. */
312 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
313 Bit 14 controls S/U choice. */
314 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
315 Bit 22 controls S/U choice. */
316 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
317 Bit 14 controls S/U choice. */
318 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
319 Bit 22 controls S/U choice. */
320 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
321 Bit 14 controls S/U choice. */
322 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
323 Bit 22 controls S/U choice. */
324 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
325 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
326 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
327 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
328 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
329 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
330 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 331 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
332 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 333 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
334 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
335 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
336 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 337 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
338 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 339 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
340 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
341 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 342 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 343 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 344 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 345 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
346 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
347 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
348 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
349 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
350 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
351 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
352 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 353 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
354 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 355 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
356 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
357 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
358 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
359 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
360 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
361 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
362 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
363 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
364 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
365 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
366 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 367 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
368 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
369 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
370 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 371 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
372 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
373 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
374 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
375 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 376 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
377 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
378 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 379 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
380 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
381 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
382 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
383 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 384 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 385};
386
387/* Qualifier constrains an operand. It either specifies a variant of an
388 operand type or limits values available to an operand type.
389
390 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
391
392enum aarch64_opnd_qualifier
393{
394 /* Indicating no further qualification on an operand. */
395 AARCH64_OPND_QLF_NIL,
396
397 /* Qualifying an operand which is a general purpose (integer) register;
398 indicating the operand data size or a specific register. */
399 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
400 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
401 AARCH64_OPND_QLF_WSP, /* WSP. */
402 AARCH64_OPND_QLF_SP, /* SP. */
403
404 /* Qualifying an operand which is a floating-point register, a SIMD
405 vector element or a SIMD vector element list; indicating operand data
406 size or the size of each SIMD vector element in the case of a SIMD
407 vector element list.
408 These qualifiers are also used to qualify an address operand to
409 indicate the size of data element a load/store instruction is
410 accessing.
411 They are also used for the immediate shift operand in e.g. SSHR. Such
412 a use is only for the ease of operand encoding/decoding and qualifier
413 sequence matching; such a use should not be applied widely; use the value
414 constraint qualifiers for immediate operands wherever possible. */
415 AARCH64_OPND_QLF_S_B,
416 AARCH64_OPND_QLF_S_H,
417 AARCH64_OPND_QLF_S_S,
418 AARCH64_OPND_QLF_S_D,
419 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 420 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
421 are selected by the instruction. Other than that it has no difference
422 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
423 reasons and is an exception from normal AArch64 disassembly scheme. */
424 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 425
426 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
427 register list; indicating register shape.
428 They are also used for the immediate shift operand in e.g. SSHR. Such
429 a use is only for the ease of operand encoding/decoding and qualifier
430 sequence matching; such a use should not be applied widely; use the value
431 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 432 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 433 AARCH64_OPND_QLF_V_8B,
434 AARCH64_OPND_QLF_V_16B,
3067d3b9 435 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 436 AARCH64_OPND_QLF_V_4H,
437 AARCH64_OPND_QLF_V_8H,
438 AARCH64_OPND_QLF_V_2S,
439 AARCH64_OPND_QLF_V_4S,
440 AARCH64_OPND_QLF_V_1D,
441 AARCH64_OPND_QLF_V_2D,
442 AARCH64_OPND_QLF_V_1Q,
443
d50c751e
RS		 444 AARCH64_OPND_QLF_P_Z,
445 AARCH64_OPND_QLF_P_M,
446
a06ea964 447 /* Constraint on value. */
a6a51754 448 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 449 AARCH64_OPND_QLF_imm_0_7,
450 AARCH64_OPND_QLF_imm_0_15,
451 AARCH64_OPND_QLF_imm_0_31,
452 AARCH64_OPND_QLF_imm_0_63,
453 AARCH64_OPND_QLF_imm_1_32,
454 AARCH64_OPND_QLF_imm_1_64,
455
456 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
457 or shift-ones. */
458 AARCH64_OPND_QLF_LSL,
459 AARCH64_OPND_QLF_MSL,
460
461 /* Special qualifier helping retrieve qualifier information during the
462 decoding time (currently not in use). */
463 AARCH64_OPND_QLF_RETRIEVE,
464};
465\f
466/* Instruction class. */
467
468enum aarch64_insn_class
469{
470 addsub_carry,
471 addsub_ext,
472 addsub_imm,
473 addsub_shift,
474 asimdall,
475 asimddiff,
476 asimdelem,
477 asimdext,
478 asimdimm,
479 asimdins,
480 asimdmisc,
481 asimdperm,
482 asimdsame,
483 asimdshf,
484 asimdtbl,
485 asisddiff,
486 asisdelem,
487 asisdlse,
488 asisdlsep,
489 asisdlso,
490 asisdlsop,
491 asisdmisc,
492 asisdone,
493 asisdpair,
494 asisdsame,
495 asisdshf,
496 bitfield,
497 branch_imm,
498 branch_reg,
499 compbranch,
500 condbranch,
501 condcmp_imm,
502 condcmp_reg,
503 condsel,
504 cryptoaes,
505 cryptosha2,
506 cryptosha3,
507 dp_1src,
508 dp_2src,
509 dp_3src,
510 exception,
511 extract,
512 float2fix,
513 float2int,
514 floatccmp,
515 floatcmp,
516 floatdp1,
517 floatdp2,
518 floatdp3,
519 floatimm,
520 floatsel,
521 ldst_immpost,
522 ldst_immpre,
523 ldst_imm9, /* immpost or immpre */
3f06e550 524 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 525 ldst_pos,
526 ldst_regoff,
527 ldst_unpriv,
528 ldst_unscaled,
529 ldstexcl,
530 ldstnapair_offs,
531 ldstpair_off,
532 ldstpair_indexed,
533 loadlit,
534 log_imm,
535 log_shift,
ee804238 536 lse_atomic,
a06ea964
NC		 537 movewide,
538 pcreladdr,
539 ic_system,
116b6019
RS		 540 sve_cpy,
541 sve_index,
542 sve_limm,
543 sve_misc,
544 sve_movprfx,
545 sve_pred_zm,
546 sve_shift_pred,
547 sve_shift_unpred,
548 sve_size_bhs,
549 sve_size_bhsd,
550 sve_size_hsd,
551 sve_size_sd,
a06ea964 552 testbranch,
f42f1a1d
TC		 553 cryptosm3,
554 cryptosm4,
65a55fbb 555 dotproduct,
a06ea964
NC		 556};
557
558/* Opcode enumerators. */
559
560enum aarch64_op
561{
562 OP_NIL,
563 OP_STRB_POS,
564 OP_LDRB_POS,
565 OP_LDRSB_POS,
566 OP_STRH_POS,
567 OP_LDRH_POS,
568 OP_LDRSH_POS,
569 OP_STR_POS,
570 OP_LDR_POS,
571 OP_STRF_POS,
572 OP_LDRF_POS,
573 OP_LDRSW_POS,
574 OP_PRFM_POS,
575
576 OP_STURB,
577 OP_LDURB,
578 OP_LDURSB,
579 OP_STURH,
580 OP_LDURH,
581 OP_LDURSH,
582 OP_STUR,
583 OP_LDUR,
584 OP_STURV,
585 OP_LDURV,
586 OP_LDURSW,
587 OP_PRFUM,
588
589 OP_LDR_LIT,
590 OP_LDRV_LIT,
591 OP_LDRSW_LIT,
592 OP_PRFM_LIT,
593
594 OP_ADD,
595 OP_B,
596 OP_BL,
597
598 OP_MOVN,
599 OP_MOVZ,
600 OP_MOVK,
601
602 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
603 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
604 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
605
606 OP_MOV_V, /* MOV alias for moving vector register. */
607
608 OP_ASR_IMM,
609 OP_LSR_IMM,
610 OP_LSL_IMM,
611
612 OP_BIC,
613
614 OP_UBFX,
615 OP_BFXIL,
616 OP_SBFX,
617 OP_SBFIZ,
618 OP_BFI,
d685192a 619 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 620 OP_UBFIZ,
621 OP_UXTB,
622 OP_UXTH,
623 OP_UXTW,
624
a06ea964
NC		 625 OP_CINC,
626 OP_CINV,
627 OP_CNEG,
628 OP_CSET,
629 OP_CSETM,
630
631 OP_FCVT,
632 OP_FCVTN,
633 OP_FCVTN2,
634 OP_FCVTL,
635 OP_FCVTL2,
636 OP_FCVTXN_S, /* Scalar version. */
637
638 OP_ROR_IMM,
639
e30181a5
YZ		 640 OP_SXTL,
641 OP_SXTL2,
642 OP_UXTL,
643 OP_UXTL2,
644
c0890d26
RS		 645 OP_MOV_P_P,
646 OP_MOV_Z_P_Z,
647 OP_MOV_Z_V,
648 OP_MOV_Z_Z,
649 OP_MOV_Z_Zi,
650 OP_MOVM_P_P_P,
651 OP_MOVS_P_P,
652 OP_MOVZS_P_P_P,
653 OP_MOVZ_P_P_P,
654 OP_NOTS_P_P_P_Z,
655 OP_NOT_P_P_P_Z,
656
c2c4ff8d
SN		 657 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
658
a06ea964
NC		 659 OP_TOTAL_NUM, /* Pseudo. */
660};
661
1d482394
TC		 662/* Error types. */
663enum err_type
664{
665 ERR_OK,
666 ERR_UND,
667 ERR_UNP,
668 ERR_NYI,
a68f4cd2 669 ERR_VFI,
1d482394
TC		 670 ERR_NR_ENTRIES
671};
672
a06ea964
NC		 673/* Maximum number of operands an instruction can have. */
674#define AARCH64_MAX_OPND_NUM 6
675/* Maximum number of qualifier sequences an instruction can have. */
676#define AARCH64_MAX_QLF_SEQ_NUM 10
677/* Operand qualifier typedef; optimized for the size. */
678typedef unsigned char aarch64_opnd_qualifier_t;
679/* Operand qualifier sequence typedef. */
680typedef aarch64_opnd_qualifier_t \
681 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
682
683/* FIXME: improve the efficiency. */
684static inline bfd_boolean
685empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
686{
687 int i;
688 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
689 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
690 return FALSE;
691 return TRUE;
692}
693
7e84b55d
TC		 694/* Forward declare error reporting type. */
695typedef struct aarch64_operand_error aarch64_operand_error;
696/* Forward declare instruction sequence type. */
697typedef struct aarch64_instr_sequence aarch64_instr_sequence;
698/* Forward declare instruction definition. */
699typedef struct aarch64_inst aarch64_inst;
700
a06ea964
NC		 701/* This structure holds information for a particular opcode. */
702
703struct aarch64_opcode
704{
705 /* The name of the mnemonic. */
706 const char *name;
707
708 /* The opcode itself. Those bits which will be filled in with
709 operands are zeroes. */
710 aarch64_insn opcode;
711
712 /* The opcode mask. This is used by the disassembler. This is a
713 mask containing ones indicating those bits which must match the
714 opcode field, and zeroes indicating those bits which need not
715 match (and are presumably filled in by operands). */
716 aarch64_insn mask;
717
718 /* Instruction class. */
719 enum aarch64_insn_class iclass;
720
721 /* Enumerator identifier. */
722 enum aarch64_op op;
723
724 /* Which architecture variant provides this instruction. */
725 const aarch64_feature_set *avariant;
726
727 /* An array of operand codes. Each code is an index into the
728 operand table. They appear in the order which the operands must
729 appear in assembly code, and are terminated by a zero. */
730 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
731
732 /* A list of operand qualifier code sequence. Each operand qualifier
733 code qualifies the corresponding operand code. Each operand
734 qualifier sequence specifies a valid opcode variant and related
735 constraint on operands. */
736 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
737
738 /* Flags providing information about this instruction */
eae424ae
TC		 739 uint64_t flags;
740
741 /* Extra constraints on the instruction that the verifier checks. */
742 uint32_t constraints;
4bd13cde 743
0c608d6b
RS		 744 /* If nonzero, this operand and operand 0 are both registers and
745 are required to have the same register number. */
746 unsigned char tied_operand;
747
4bd13cde 748 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 749 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
750 bfd_vma, bfd_boolean, aarch64_operand_error *,
751 struct aarch64_instr_sequence *);
a06ea964
NC		 752};
753
754typedef struct aarch64_opcode aarch64_opcode;
755
756/* Table describing all the AArch64 opcodes. */
757extern aarch64_opcode aarch64_opcode_table[];
758
759/* Opcode flags. */
760#define F_ALIAS (1 << 0)
761#define F_HAS_ALIAS (1 << 1)
762/* Disassembly preference priority 1-3 (the larger the higher). If nothing
763 is specified, it is the priority 0 by default, i.e. the lowest priority. */
764#define F_P1 (1 << 2)
765#define F_P2 (2 << 2)
766#define F_P3 (3 << 2)
767/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
768#define F_COND (1 << 4)
769/* Instruction has the field of 'sf'. */
770#define F_SF (1 << 5)
771/* Instruction has the field of 'size:Q'. */
772#define F_SIZEQ (1 << 6)
773/* Floating-point instruction has the field of 'type'. */
774#define F_FPTYPE (1 << 7)
775/* AdvSIMD scalar instruction has the field of 'size'. */
776#define F_SSIZE (1 << 8)
777/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
778#define F_T (1 << 9)
779/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
780#define F_GPRSIZE_IN_Q (1 << 10)
781/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
782#define F_LDS_SIZE (1 << 11)
783/* Optional operand; assume maximum of 1 operand can be optional. */
784#define F_OPD0_OPT (1 << 12)
785#define F_OPD1_OPT (2 << 12)
786#define F_OPD2_OPT (3 << 12)
787#define F_OPD3_OPT (4 << 12)
788#define F_OPD4_OPT (5 << 12)
789/* Default value for the optional operand when omitted from the assembly. */
790#define F_DEFAULT(X) (((X) & 0x1f) << 15)
791/* Instruction that is an alias of another instruction needs to be
792 encoded/decoded by converting it to/from the real form, followed by
793 the encoding/decoding according to the rules of the real opcode.
794 This compares to the direct coding using the alias's information.
795 N.B. this flag requires F_ALIAS to be used together. */
796#define F_CONV (1 << 20)
797/* Use together with F_ALIAS to indicate an alias opcode is a programmer
798 friendly pseudo instruction available only in the assembly code (thus will
799 not show up in the disassembly). */
800#define F_PSEUDO (1 << 21)
801/* Instruction has miscellaneous encoding/decoding rules. */
802#define F_MISC (1 << 22)
803/* Instruction has the field of 'N'; used in conjunction with F_SF. */
804#define F_N (1 << 23)
805/* Opcode dependent field. */
806#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 807/* Instruction has the field of 'sz'. */
808#define F_LSE_SZ (1 << 27)
4989adac
RS		 809/* Require an exact qualifier match, even for NIL qualifiers. */
810#define F_STRICT (1ULL << 28)
f9830ec1
TC		 811/* This system instruction is used to read system registers. */
812#define F_SYS_READ (1ULL << 29)
813/* This system instruction is used to write system registers. */
814#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 815/* This instruction has an extra constraint on it that imposes a requirement on
816 subsequent instructions. */
817#define F_SCAN (1ULL << 31)
818/* Next bit is 32. */
819
820/* Instruction constraints. */
821/* This instruction has a predication constraint on the instruction at PC+4. */
822#define C_SCAN_MOVPRFX (1U << 0)
823/* This instruction's operation width is determined by the operand with the
824 largest element size. */
825#define C_MAX_ELEM (1U << 1)
826/* Next bit is 2. */
a06ea964
NC		 827
828static inline bfd_boolean
829alias_opcode_p (const aarch64_opcode *opcode)
830{
831 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
832}
833
834static inline bfd_boolean
835opcode_has_alias (const aarch64_opcode *opcode)
836{
837 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
838}
839
840/* Priority for disassembling preference. */
841static inline int
842opcode_priority (const aarch64_opcode *opcode)
843{
844 return (opcode->flags >> 2) & 0x3;
845}
846
847static inline bfd_boolean
848pseudo_opcode_p (const aarch64_opcode *opcode)
849{
850 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
851}
852
853static inline bfd_boolean
854optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
855{
856 return (((opcode->flags >> 12) & 0x7) == idx + 1)
857 ? TRUE : FALSE;
858}
859
860static inline aarch64_insn
861get_optional_operand_default_value (const aarch64_opcode *opcode)
862{
863 return (opcode->flags >> 15) & 0x1f;
864}
865
866static inline unsigned int
867get_opcode_dependent_value (const aarch64_opcode *opcode)
868{
869 return (opcode->flags >> 24) & 0x7;
870}
871
872static inline bfd_boolean
873opcode_has_special_coder (const aarch64_opcode *opcode)
874{
ee804238 875 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 876 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
877 : FALSE;
878}
879\f
880struct aarch64_name_value_pair
881{
882 const char * name;
883 aarch64_insn value;
884};
885
886extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 887extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
888extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 889extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 890
49eec193
YZ		 891typedef struct
892{
893 const char * name;
894 aarch64_insn value;
895 uint32_t flags;
896} aarch64_sys_reg;
897
898extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 899extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 900extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 901extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
902 const aarch64_sys_reg *);
903extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
904 const aarch64_sys_reg *);
49eec193 905
a06ea964
NC		 906typedef struct
907{
875880c6 908 const char *name;
a06ea964 909 uint32_t value;
ea2deeec 910 uint32_t flags ;
a06ea964
NC		 911} aarch64_sys_ins_reg;
912
ea2deeec 913extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 914extern bfd_boolean
915aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
916 const aarch64_sys_ins_reg *);
ea2deeec 917
a06ea964
NC		 918extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
919extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
920extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
921extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 922extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 923
924/* Shift/extending operator kinds.
925 N.B. order is important; keep aarch64_operand_modifiers synced. */
926enum aarch64_modifier_kind
927{
928 AARCH64_MOD_NONE,
929 AARCH64_MOD_MSL,
930 AARCH64_MOD_ROR,
931 AARCH64_MOD_ASR,
932 AARCH64_MOD_LSR,
933 AARCH64_MOD_LSL,
934 AARCH64_MOD_UXTB,
935 AARCH64_MOD_UXTH,
936 AARCH64_MOD_UXTW,
937 AARCH64_MOD_UXTX,
938 AARCH64_MOD_SXTB,
939 AARCH64_MOD_SXTH,
940 AARCH64_MOD_SXTW,
941 AARCH64_MOD_SXTX,
2442d846 942 AARCH64_MOD_MUL,
98907a70 943 AARCH64_MOD_MUL_VL,
a06ea964
NC		 944};
945
946bfd_boolean
947aarch64_extend_operator_p (enum aarch64_modifier_kind);
948
949enum aarch64_modifier_kind
950aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
951/* Condition. */
952
953typedef struct
954{
955 /* A list of names with the first one as the disassembly preference;
956 terminated by NULL if fewer than 3. */
bb7eff52 957 const char *names[4];
a06ea964
NC		 958 aarch64_insn value;
959} aarch64_cond;
960
961extern const aarch64_cond aarch64_conds[16];
962
963const aarch64_cond* get_cond_from_value (aarch64_insn value);
964const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
965\f
966/* Structure representing an operand. */
967
968struct aarch64_opnd_info
969{
970 enum aarch64_opnd type;
971 aarch64_opnd_qualifier_t qualifier;
972 int idx;
973
974 union
975 {
976 struct
977 {
978 unsigned regno;
979 } reg;
980 struct
981 {
dab26bf4
RS		 982 unsigned int regno;
983 int64_t index;
a06ea964
NC		 984 } reglane;
985 /* e.g. LVn. */
986 struct
987 {
988 unsigned first_regno : 5;
989 unsigned num_regs : 3;
990 /* 1 if it is a list of reg element. */
991 unsigned has_index : 1;
992 /* Lane index; valid only when has_index is 1. */
dab26bf4 993 int64_t index;
a06ea964
NC		 994 } reglist;
995 /* e.g. immediate or pc relative address offset. */
996 struct
997 {
998 int64_t value;
999 unsigned is_fp : 1;
1000 } imm;
1001 /* e.g. address in STR (register offset). */
1002 struct
1003 {
1004 unsigned base_regno;
1005 struct
1006 {
1007 union
1008 {
1009 int imm;
1010 unsigned regno;
1011 };
1012 unsigned is_reg;
1013 } offset;
1014 unsigned pcrel : 1; /* PC-relative. */
1015 unsigned writeback : 1;
1016 unsigned preind : 1; /* Pre-indexed. */
1017 unsigned postind : 1; /* Post-indexed. */
1018 } addr;
561a72d4
TC		 1019
1020 struct
1021 {
1022 /* The encoding of the system register. */
1023 aarch64_insn value;
1024
1025 /* The system register flags. */
1026 uint32_t flags;
1027 } sysreg;
1028
a06ea964 1029 const aarch64_cond *cond;
a06ea964
NC		 1030 /* The encoding of the PSTATE field. */
1031 aarch64_insn pstatefield;
1032 const aarch64_sys_ins_reg *sysins_op;
1033 const struct aarch64_name_value_pair *barrier;
9ed608f9 1034 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1035 const struct aarch64_name_value_pair *prfop;
1036 };
1037
1038 /* Operand shifter; in use when the operand is a register offset address,
1039 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1040 struct
1041 {
1042 enum aarch64_modifier_kind kind;
a06ea964
NC		 1043 unsigned operator_present: 1; /* Only valid during encoding. */
1044 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1045 unsigned amount_present: 1;
2442d846 1046 int64_t amount;
a06ea964
NC		 1047 } shifter;
1048
1049 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1050 to be done on it. In some (but not all) of these
1051 cases, we need to tell libopcodes to skip the
1052 constraint checking and the encoding for this
1053 operand, so that the libopcodes can pick up the
1054 right opcode before the operand is fixed-up. This
1055 flag should only be used during the
1056 assembling/encoding. */
1057 unsigned present:1; /* Whether this operand is present in the assembly
1058 line; not used during the disassembly. */
1059};
1060
1061typedef struct aarch64_opnd_info aarch64_opnd_info;
1062
1063/* Structure representing an instruction.
1064
1065 It is used during both the assembling and disassembling. The assembler
1066 fills an aarch64_inst after a successful parsing and then passes it to the
1067 encoding routine to do the encoding. During the disassembling, the
1068 disassembler calls the decoding routine to decode a binary instruction; on a
1069 successful return, such a structure will be filled with information of the
1070 instruction; then the disassembler uses the information to print out the
1071 instruction. */
1072
1073struct aarch64_inst
1074{
1075 /* The value of the binary instruction. */
1076 aarch64_insn value;
1077
1078 /* Corresponding opcode entry. */
1079 const aarch64_opcode *opcode;
1080
1081 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1082 const aarch64_cond *cond;
1083
1084 /* Operands information. */
1085 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1086};
1087
a06ea964
NC		 1088\f
1089/* Diagnosis related declaration and interface. */
1090
1091/* Operand error kind enumerators.
1092
1093 AARCH64_OPDE_RECOVERABLE
1094 Less severe error found during the parsing, very possibly because that
1095 GAS has picked up a wrong instruction template for the parsing.
1096
1097 AARCH64_OPDE_SYNTAX_ERROR
1098 General syntax error; it can be either a user error, or simply because
1099 that GAS is trying a wrong instruction template.
1100
1101 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1102 Definitely a user syntax error.
1103
1104 AARCH64_OPDE_INVALID_VARIANT
1105 No syntax error, but the operands are not a valid combination, e.g.
1106 FMOV D0,S0
1107
0c608d6b
RS		 1108 AARCH64_OPDE_UNTIED_OPERAND
1109 The asm failed to use the same register for a destination operand
1110 and a tied source operand.
1111
a06ea964
NC		 1112 AARCH64_OPDE_OUT_OF_RANGE
1113 Error about some immediate value out of a valid range.
1114
1115 AARCH64_OPDE_UNALIGNED
1116 Error about some immediate value not properly aligned (i.e. not being a
1117 multiple times of a certain value).
1118
1119 AARCH64_OPDE_REG_LIST
1120 Error about the register list operand having unexpected number of
1121 registers.
1122
1123 AARCH64_OPDE_OTHER_ERROR
1124 Error of the highest severity and used for any severe issue that does not
1125 fall into any of the above categories.
1126
1127 The enumerators are only interesting to GAS. They are declared here (in
1128 libopcodes) because that some errors are detected (and then notified to GAS)
1129 by libopcodes (rather than by GAS solely).
1130
1131 The first three errors are only deteced by GAS while the
1132 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1133 only libopcodes has the information about the valid variants of each
1134 instruction.
1135
1136 The enumerators have an increasing severity. This is helpful when there are
1137 multiple instruction templates available for a given mnemonic name (e.g.
1138 FMOV); this mechanism will help choose the most suitable template from which
1139 the generated diagnostics can most closely describe the issues, if any. */
1140
1141enum aarch64_operand_error_kind
1142{
1143 AARCH64_OPDE_NIL,
1144 AARCH64_OPDE_RECOVERABLE,
1145 AARCH64_OPDE_SYNTAX_ERROR,
1146 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1147 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1148 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1149 AARCH64_OPDE_OUT_OF_RANGE,
1150 AARCH64_OPDE_UNALIGNED,
1151 AARCH64_OPDE_REG_LIST,
1152 AARCH64_OPDE_OTHER_ERROR
1153};
1154
1155/* N.B. GAS assumes that this structure work well with shallow copy. */
1156struct aarch64_operand_error
1157{
1158 enum aarch64_operand_error_kind kind;
1159 int index;
1160 const char *error;
1161 int data[3]; /* Some data for extra information. */
7d02540a 1162 bfd_boolean non_fatal;
a06ea964
NC		 1163};
1164
7e84b55d
TC		 1165/* AArch64 sequence structure used to track instructions with F_SCAN
1166 dependencies for both assembler and disassembler. */
1167struct aarch64_instr_sequence
1168{
1169 /* The instruction that caused this sequence to be opened. */
1170 aarch64_inst *instr;
1171 /* The number of instructions the above instruction allows to be kept in the
1172 sequence before an automatic close is done. */
1173 int num_insns;
1174 /* The instructions currently added to the sequence. */
1175 aarch64_inst **current_insns;
1176 /* The number of instructions already in the sequence. */
1177 int next_insn;
1178};
a06ea964
NC		 1179
1180/* Encoding entrypoint. */
1181
1182extern int
1183aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1184 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1185 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1186
1187extern const aarch64_opcode *
1188aarch64_replace_opcode (struct aarch64_inst *,
1189 const aarch64_opcode *);
1190
1191/* Given the opcode enumerator OP, return the pointer to the corresponding
1192 opcode entry. */
1193
1194extern const aarch64_opcode *
1195aarch64_get_opcode (enum aarch64_op);
1196
1197/* Generate the string representation of an operand. */
1198extern void
1199aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1200 const aarch64_opnd_info *, int, int *, bfd_vma *,
1201 char **);
a06ea964
NC		 1202
1203/* Miscellaneous interface. */
1204
1205extern int
1206aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1207
1208extern aarch64_opnd_qualifier_t
1209aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1210 const aarch64_opnd_qualifier_t, int);
1211
a68f4cd2
TC		 1212extern bfd_boolean
1213aarch64_is_destructive_by_operands (const aarch64_opcode *);
1214
a06ea964
NC		 1215extern int
1216aarch64_num_of_operands (const aarch64_opcode *);
1217
1218extern int
1219aarch64_stack_pointer_p (const aarch64_opnd_info *);
1220
e141d84e
YQ		 1221extern int
1222aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1223
1d482394 1224extern enum err_type
561a72d4 1225aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1226 aarch64_operand_error *);
1227
1228extern void
1229init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1230
a06ea964
NC		 1231/* Given an operand qualifier, return the expected data element size
1232 of a qualified operand. */
1233extern unsigned char
1234aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1235
1236extern enum aarch64_operand_class
1237aarch64_get_operand_class (enum aarch64_opnd);
1238
1239extern const char *
1240aarch64_get_operand_name (enum aarch64_opnd);
1241
1242extern const char *
1243aarch64_get_operand_desc (enum aarch64_opnd);
1244
e950b345
RS		 1245extern bfd_boolean
1246aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1247
a06ea964
NC		 1248#ifdef DEBUG_AARCH64
1249extern int debug_dump;
1250
1251extern void
1252aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1253
1254#define DEBUG_TRACE(M, ...) \
1255 { \
1256 if (debug_dump) \
1257 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1258 }
1259
1260#define DEBUG_TRACE_IF(C, M, ...) \
1261 { \
1262 if (debug_dump && (C)) \
1263 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1264 }
1265#else /* !DEBUG_AARCH64 */
1266#define DEBUG_TRACE(M, ...) ;
1267#define DEBUG_TRACE_IF(C, M, ...) ;
1268#endif /* DEBUG_AARCH64 */
1269
245d2e3f
RS		 1270extern const char *const aarch64_sve_pattern_array[32];
1271extern const char *const aarch64_sve_prfop_array[16];
1272
d3e12b29
YQ		 1273#ifdef __cplusplus
1274}
1275#endif
1276
a06ea964 1277#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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