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Enable the Dot Product extension by default for Armv8.4-a.
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
2571583a 3 Copyright (C) 2009-2017 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
a06ea964
NC		 64
65/* Architectures are the sum of the base and extensions. */
66#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
67 AARCH64_FEATURE_FP \
68 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 69#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
70 AARCH64_FEATURE_CRC \
250aafa4 71 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 72 | AARCH64_FEATURE_LSE \
73 | AARCH64_FEATURE_PAN \
74 | AARCH64_FEATURE_LOR \
75 | AARCH64_FEATURE_RDMA)
1924ff75 76#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 77 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 78 | AARCH64_FEATURE_RAS)
79#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 80 AARCH64_FEATURE_V8_3 \
f482d304
RS		 81 | AARCH64_FEATURE_RCPC \
82 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 83#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a
TC		 84 AARCH64_FEATURE_V8_4 \
85 | AARCH64_FEATURE_DOTPROD)
88f0ea34 86
a06ea964
NC		 87#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
88#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
89
90/* CPU-specific features. */
21b81e67 91typedef unsigned long long aarch64_feature_set;
a06ea964 92
93d8990c
SN		 93#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
94 ((~(CPU) & (FEAT)) == 0)
95
96#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 97 (((CPU) & (FEAT)) != 0)
98
93d8990c
SN		 99#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
100 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
101
a06ea964
NC		 102#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
103 do \
104 { \
105 (TARG) = (F1) | (F2); \
106 } \
107 while (0)
108
109#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
110 do \
111 { \
112 (TARG) = (F1) &~ (F2); \
113 } \
114 while (0)
115
116#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
117
a06ea964
NC		 118enum aarch64_operand_class
119{
120 AARCH64_OPND_CLASS_NIL,
121 AARCH64_OPND_CLASS_INT_REG,
122 AARCH64_OPND_CLASS_MODIFIED_REG,
123 AARCH64_OPND_CLASS_FP_REG,
124 AARCH64_OPND_CLASS_SIMD_REG,
125 AARCH64_OPND_CLASS_SIMD_ELEMENT,
126 AARCH64_OPND_CLASS_SISD_REG,
127 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 128 AARCH64_OPND_CLASS_SVE_REG,
129 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 130 AARCH64_OPND_CLASS_ADDRESS,
131 AARCH64_OPND_CLASS_IMMEDIATE,
132 AARCH64_OPND_CLASS_SYSTEM,
68a64283 133 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 134};
135
136/* Operand code that helps both parsing and coding.
137 Keep AARCH64_OPERANDS synced. */
138
139enum aarch64_opnd
140{
141 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
142
143 AARCH64_OPND_Rd, /* Integer register as destination. */
144 AARCH64_OPND_Rn, /* Integer register as source. */
145 AARCH64_OPND_Rm, /* Integer register as source. */
146 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
147 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
148 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
149 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
150 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
151
152 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
153 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 154 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 155 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 156 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
157 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
158
159 AARCH64_OPND_Fd, /* Floating-point Fd. */
160 AARCH64_OPND_Fn, /* Floating-point Fn. */
161 AARCH64_OPND_Fm, /* Floating-point Fm. */
162 AARCH64_OPND_Fa, /* Floating-point Fa. */
163 AARCH64_OPND_Ft, /* Floating-point Ft. */
164 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
165
166 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
167 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
168 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
169
f42f1a1d 170 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 171 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
172 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
173 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
174 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
175 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
176 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
177 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
178 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
179 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
180 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
181 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
182 structure to all lanes. */
183 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
184
a6a51754
RL		 185 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
186 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 187
188 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 189 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 190 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
191 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
192 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
193 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
194 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
195 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
196 (no encoding). */
197 AARCH64_OPND_IMM0, /* Immediate for #0. */
198 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
199 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
200 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
201 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
202 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
203 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 204 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 205 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
206 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
207 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
208 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
209 AARCH64_OPND_BIT_NUM, /* Immediate. */
210 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
211 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 212 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 213 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
214 each condition flag. */
215
216 AARCH64_OPND_LIMM, /* Logical Immediate. */
217 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
218 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
219 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
220 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 221 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
222 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
223 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 224
225 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 226 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 227
228 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
229 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
230 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
231 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
232 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
233
234 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
235 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
236 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
237 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
238 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
239 negative or unaligned and there is
240 no writeback allowed. This operand code
241 is only used to support the programmer-
242 friendly feature of using LDR/STR as the
243 the mnemonic name for LDUR/STUR instructions
244 wherever there is no ambiguity. */
3f06e550 245 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 246 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
247 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 248 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 249 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
250
251 AARCH64_OPND_SYSREG, /* System register operand. */
252 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
253 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
254 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
255 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
256 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
257 AARCH64_OPND_BARRIER, /* Barrier operand. */
258 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
259 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 260 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 261
582e12bf 262 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 263 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
264 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
265 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
266 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
267 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
268 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 269 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
270 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
271 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
272 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
273 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
274 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
275 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
276 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
277 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
278 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
279 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
280 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
281 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
282 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
283 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
284 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
285 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
286 Bit 14 controls S/U choice. */
287 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
288 Bit 22 controls S/U choice. */
289 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
290 Bit 14 controls S/U choice. */
291 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
292 Bit 22 controls S/U choice. */
293 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
294 Bit 14 controls S/U choice. */
295 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
296 Bit 22 controls S/U choice. */
297 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
298 Bit 14 controls S/U choice. */
299 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
300 Bit 22 controls S/U choice. */
301 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
302 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
303 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
304 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
305 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
306 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
307 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 308 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
309 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 310 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
311 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
312 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
313 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 314 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
315 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 316 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
317 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
318 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 319 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 320 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 321 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 322 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
323 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
324 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
325 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
326 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
327 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
328 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
329 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 330 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
331 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 332 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
333 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
334 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
335 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
336 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
337 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
338 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
339 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
340 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
341 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
342 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
343 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 344 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
345 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
346 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
347 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 348 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
349 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
350 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
351 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
352 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 353 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
354 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
355 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 356 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
357 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
358 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
359 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
360 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 361 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 362};
363
364/* Qualifier constrains an operand. It either specifies a variant of an
365 operand type or limits values available to an operand type.
366
367 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
368
369enum aarch64_opnd_qualifier
370{
371 /* Indicating no further qualification on an operand. */
372 AARCH64_OPND_QLF_NIL,
373
374 /* Qualifying an operand which is a general purpose (integer) register;
375 indicating the operand data size or a specific register. */
376 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
377 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
378 AARCH64_OPND_QLF_WSP, /* WSP. */
379 AARCH64_OPND_QLF_SP, /* SP. */
380
381 /* Qualifying an operand which is a floating-point register, a SIMD
382 vector element or a SIMD vector element list; indicating operand data
383 size or the size of each SIMD vector element in the case of a SIMD
384 vector element list.
385 These qualifiers are also used to qualify an address operand to
386 indicate the size of data element a load/store instruction is
387 accessing.
388 They are also used for the immediate shift operand in e.g. SSHR. Such
389 a use is only for the ease of operand encoding/decoding and qualifier
390 sequence matching; such a use should not be applied widely; use the value
391 constraint qualifiers for immediate operands wherever possible. */
392 AARCH64_OPND_QLF_S_B,
393 AARCH64_OPND_QLF_S_H,
394 AARCH64_OPND_QLF_S_S,
395 AARCH64_OPND_QLF_S_D,
396 AARCH64_OPND_QLF_S_Q,
397
398 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
399 register list; indicating register shape.
400 They are also used for the immediate shift operand in e.g. SSHR. Such
401 a use is only for the ease of operand encoding/decoding and qualifier
402 sequence matching; such a use should not be applied widely; use the value
403 constraint qualifiers for immediate operands wherever possible. */
404 AARCH64_OPND_QLF_V_8B,
405 AARCH64_OPND_QLF_V_16B,
3067d3b9 406 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 407 AARCH64_OPND_QLF_V_4H,
408 AARCH64_OPND_QLF_V_8H,
409 AARCH64_OPND_QLF_V_2S,
410 AARCH64_OPND_QLF_V_4S,
411 AARCH64_OPND_QLF_V_1D,
412 AARCH64_OPND_QLF_V_2D,
413 AARCH64_OPND_QLF_V_1Q,
414
d50c751e
RS		 415 AARCH64_OPND_QLF_P_Z,
416 AARCH64_OPND_QLF_P_M,
417
a06ea964 418 /* Constraint on value. */
a6a51754 419 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 420 AARCH64_OPND_QLF_imm_0_7,
421 AARCH64_OPND_QLF_imm_0_15,
422 AARCH64_OPND_QLF_imm_0_31,
423 AARCH64_OPND_QLF_imm_0_63,
424 AARCH64_OPND_QLF_imm_1_32,
425 AARCH64_OPND_QLF_imm_1_64,
426
427 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
428 or shift-ones. */
429 AARCH64_OPND_QLF_LSL,
430 AARCH64_OPND_QLF_MSL,
431
432 /* Special qualifier helping retrieve qualifier information during the
433 decoding time (currently not in use). */
434 AARCH64_OPND_QLF_RETRIEVE,
435};
436\f
437/* Instruction class. */
438
439enum aarch64_insn_class
440{
441 addsub_carry,
442 addsub_ext,
443 addsub_imm,
444 addsub_shift,
445 asimdall,
446 asimddiff,
447 asimdelem,
448 asimdext,
449 asimdimm,
450 asimdins,
451 asimdmisc,
452 asimdperm,
453 asimdsame,
454 asimdshf,
455 asimdtbl,
456 asisddiff,
457 asisdelem,
458 asisdlse,
459 asisdlsep,
460 asisdlso,
461 asisdlsop,
462 asisdmisc,
463 asisdone,
464 asisdpair,
465 asisdsame,
466 asisdshf,
467 bitfield,
468 branch_imm,
469 branch_reg,
470 compbranch,
471 condbranch,
472 condcmp_imm,
473 condcmp_reg,
474 condsel,
475 cryptoaes,
476 cryptosha2,
477 cryptosha3,
478 dp_1src,
479 dp_2src,
480 dp_3src,
481 exception,
482 extract,
483 float2fix,
484 float2int,
485 floatccmp,
486 floatcmp,
487 floatdp1,
488 floatdp2,
489 floatdp3,
490 floatimm,
491 floatsel,
492 ldst_immpost,
493 ldst_immpre,
494 ldst_imm9, /* immpost or immpre */
3f06e550 495 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 496 ldst_pos,
497 ldst_regoff,
498 ldst_unpriv,
499 ldst_unscaled,
500 ldstexcl,
501 ldstnapair_offs,
502 ldstpair_off,
503 ldstpair_indexed,
504 loadlit,
505 log_imm,
506 log_shift,
ee804238 507 lse_atomic,
a06ea964
NC		 508 movewide,
509 pcreladdr,
510 ic_system,
116b6019
RS		 511 sve_cpy,
512 sve_index,
513 sve_limm,
514 sve_misc,
515 sve_movprfx,
516 sve_pred_zm,
517 sve_shift_pred,
518 sve_shift_unpred,
519 sve_size_bhs,
520 sve_size_bhsd,
521 sve_size_hsd,
522 sve_size_sd,
a06ea964 523 testbranch,
f42f1a1d
TC		 524 cryptosm3,
525 cryptosm4,
65a55fbb 526 dotproduct,
a06ea964
NC		 527};
528
529/* Opcode enumerators. */
530
531enum aarch64_op
532{
533 OP_NIL,
534 OP_STRB_POS,
535 OP_LDRB_POS,
536 OP_LDRSB_POS,
537 OP_STRH_POS,
538 OP_LDRH_POS,
539 OP_LDRSH_POS,
540 OP_STR_POS,
541 OP_LDR_POS,
542 OP_STRF_POS,
543 OP_LDRF_POS,
544 OP_LDRSW_POS,
545 OP_PRFM_POS,
546
547 OP_STURB,
548 OP_LDURB,
549 OP_LDURSB,
550 OP_STURH,
551 OP_LDURH,
552 OP_LDURSH,
553 OP_STUR,
554 OP_LDUR,
555 OP_STURV,
556 OP_LDURV,
557 OP_LDURSW,
558 OP_PRFUM,
559
560 OP_LDR_LIT,
561 OP_LDRV_LIT,
562 OP_LDRSW_LIT,
563 OP_PRFM_LIT,
564
565 OP_ADD,
566 OP_B,
567 OP_BL,
568
569 OP_MOVN,
570 OP_MOVZ,
571 OP_MOVK,
572
573 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
574 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
575 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
576
577 OP_MOV_V, /* MOV alias for moving vector register. */
578
579 OP_ASR_IMM,
580 OP_LSR_IMM,
581 OP_LSL_IMM,
582
583 OP_BIC,
584
585 OP_UBFX,
586 OP_BFXIL,
587 OP_SBFX,
588 OP_SBFIZ,
589 OP_BFI,
d685192a 590 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 591 OP_UBFIZ,
592 OP_UXTB,
593 OP_UXTH,
594 OP_UXTW,
595
a06ea964
NC		 596 OP_CINC,
597 OP_CINV,
598 OP_CNEG,
599 OP_CSET,
600 OP_CSETM,
601
602 OP_FCVT,
603 OP_FCVTN,
604 OP_FCVTN2,
605 OP_FCVTL,
606 OP_FCVTL2,
607 OP_FCVTXN_S, /* Scalar version. */
608
609 OP_ROR_IMM,
610
e30181a5
YZ		 611 OP_SXTL,
612 OP_SXTL2,
613 OP_UXTL,
614 OP_UXTL2,
615
c0890d26
RS		 616 OP_MOV_P_P,
617 OP_MOV_Z_P_Z,
618 OP_MOV_Z_V,
619 OP_MOV_Z_Z,
620 OP_MOV_Z_Zi,
621 OP_MOVM_P_P_P,
622 OP_MOVS_P_P,
623 OP_MOVZS_P_P_P,
624 OP_MOVZ_P_P_P,
625 OP_NOTS_P_P_P_Z,
626 OP_NOT_P_P_P_Z,
627
c2c4ff8d
SN		 628 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
629
a06ea964
NC		 630 OP_TOTAL_NUM, /* Pseudo. */
631};
632
633/* Maximum number of operands an instruction can have. */
634#define AARCH64_MAX_OPND_NUM 6
635/* Maximum number of qualifier sequences an instruction can have. */
636#define AARCH64_MAX_QLF_SEQ_NUM 10
637/* Operand qualifier typedef; optimized for the size. */
638typedef unsigned char aarch64_opnd_qualifier_t;
639/* Operand qualifier sequence typedef. */
640typedef aarch64_opnd_qualifier_t \
641 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
642
643/* FIXME: improve the efficiency. */
644static inline bfd_boolean
645empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
646{
647 int i;
648 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
649 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
650 return FALSE;
651 return TRUE;
652}
653
654/* This structure holds information for a particular opcode. */
655
656struct aarch64_opcode
657{
658 /* The name of the mnemonic. */
659 const char *name;
660
661 /* The opcode itself. Those bits which will be filled in with
662 operands are zeroes. */
663 aarch64_insn opcode;
664
665 /* The opcode mask. This is used by the disassembler. This is a
666 mask containing ones indicating those bits which must match the
667 opcode field, and zeroes indicating those bits which need not
668 match (and are presumably filled in by operands). */
669 aarch64_insn mask;
670
671 /* Instruction class. */
672 enum aarch64_insn_class iclass;
673
674 /* Enumerator identifier. */
675 enum aarch64_op op;
676
677 /* Which architecture variant provides this instruction. */
678 const aarch64_feature_set *avariant;
679
680 /* An array of operand codes. Each code is an index into the
681 operand table. They appear in the order which the operands must
682 appear in assembly code, and are terminated by a zero. */
683 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
684
685 /* A list of operand qualifier code sequence. Each operand qualifier
686 code qualifies the corresponding operand code. Each operand
687 qualifier sequence specifies a valid opcode variant and related
688 constraint on operands. */
689 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
690
691 /* Flags providing information about this instruction */
692 uint32_t flags;
4bd13cde 693
0c608d6b
RS		 694 /* If nonzero, this operand and operand 0 are both registers and
695 are required to have the same register number. */
696 unsigned char tied_operand;
697
4bd13cde
NC		 698 /* If non-NULL, a function to verify that a given instruction is valid. */
699 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 700};
701
702typedef struct aarch64_opcode aarch64_opcode;
703
704/* Table describing all the AArch64 opcodes. */
705extern aarch64_opcode aarch64_opcode_table[];
706
707/* Opcode flags. */
708#define F_ALIAS (1 << 0)
709#define F_HAS_ALIAS (1 << 1)
710/* Disassembly preference priority 1-3 (the larger the higher). If nothing
711 is specified, it is the priority 0 by default, i.e. the lowest priority. */
712#define F_P1 (1 << 2)
713#define F_P2 (2 << 2)
714#define F_P3 (3 << 2)
715/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
716#define F_COND (1 << 4)
717/* Instruction has the field of 'sf'. */
718#define F_SF (1 << 5)
719/* Instruction has the field of 'size:Q'. */
720#define F_SIZEQ (1 << 6)
721/* Floating-point instruction has the field of 'type'. */
722#define F_FPTYPE (1 << 7)
723/* AdvSIMD scalar instruction has the field of 'size'. */
724#define F_SSIZE (1 << 8)
725/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
726#define F_T (1 << 9)
727/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
728#define F_GPRSIZE_IN_Q (1 << 10)
729/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
730#define F_LDS_SIZE (1 << 11)
731/* Optional operand; assume maximum of 1 operand can be optional. */
732#define F_OPD0_OPT (1 << 12)
733#define F_OPD1_OPT (2 << 12)
734#define F_OPD2_OPT (3 << 12)
735#define F_OPD3_OPT (4 << 12)
736#define F_OPD4_OPT (5 << 12)
737/* Default value for the optional operand when omitted from the assembly. */
738#define F_DEFAULT(X) (((X) & 0x1f) << 15)
739/* Instruction that is an alias of another instruction needs to be
740 encoded/decoded by converting it to/from the real form, followed by
741 the encoding/decoding according to the rules of the real opcode.
742 This compares to the direct coding using the alias's information.
743 N.B. this flag requires F_ALIAS to be used together. */
744#define F_CONV (1 << 20)
745/* Use together with F_ALIAS to indicate an alias opcode is a programmer
746 friendly pseudo instruction available only in the assembly code (thus will
747 not show up in the disassembly). */
748#define F_PSEUDO (1 << 21)
749/* Instruction has miscellaneous encoding/decoding rules. */
750#define F_MISC (1 << 22)
751/* Instruction has the field of 'N'; used in conjunction with F_SF. */
752#define F_N (1 << 23)
753/* Opcode dependent field. */
754#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 755/* Instruction has the field of 'sz'. */
756#define F_LSE_SZ (1 << 27)
4989adac
RS		 757/* Require an exact qualifier match, even for NIL qualifiers. */
758#define F_STRICT (1ULL << 28)
759/* Next bit is 29. */
a06ea964
NC		 760
761static inline bfd_boolean
762alias_opcode_p (const aarch64_opcode *opcode)
763{
764 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
765}
766
767static inline bfd_boolean
768opcode_has_alias (const aarch64_opcode *opcode)
769{
770 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
771}
772
773/* Priority for disassembling preference. */
774static inline int
775opcode_priority (const aarch64_opcode *opcode)
776{
777 return (opcode->flags >> 2) & 0x3;
778}
779
780static inline bfd_boolean
781pseudo_opcode_p (const aarch64_opcode *opcode)
782{
783 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
784}
785
786static inline bfd_boolean
787optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
788{
789 return (((opcode->flags >> 12) & 0x7) == idx + 1)
790 ? TRUE : FALSE;
791}
792
793static inline aarch64_insn
794get_optional_operand_default_value (const aarch64_opcode *opcode)
795{
796 return (opcode->flags >> 15) & 0x1f;
797}
798
799static inline unsigned int
800get_opcode_dependent_value (const aarch64_opcode *opcode)
801{
802 return (opcode->flags >> 24) & 0x7;
803}
804
805static inline bfd_boolean
806opcode_has_special_coder (const aarch64_opcode *opcode)
807{
ee804238 808 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 809 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
810 : FALSE;
811}
812\f
813struct aarch64_name_value_pair
814{
815 const char * name;
816 aarch64_insn value;
817};
818
819extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 820extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
821extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 822extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 823
49eec193
YZ		 824typedef struct
825{
826 const char * name;
827 aarch64_insn value;
828 uint32_t flags;
829} aarch64_sys_reg;
830
831extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 832extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 833extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 834extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
835 const aarch64_sys_reg *);
836extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
837 const aarch64_sys_reg *);
49eec193 838
a06ea964
NC		 839typedef struct
840{
875880c6 841 const char *name;
a06ea964 842 uint32_t value;
ea2deeec 843 uint32_t flags ;
a06ea964
NC		 844} aarch64_sys_ins_reg;
845
ea2deeec 846extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 847extern bfd_boolean
848aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
849 const aarch64_sys_ins_reg *);
ea2deeec 850
a06ea964
NC		 851extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
852extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
853extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
854extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
855
856/* Shift/extending operator kinds.
857 N.B. order is important; keep aarch64_operand_modifiers synced. */
858enum aarch64_modifier_kind
859{
860 AARCH64_MOD_NONE,
861 AARCH64_MOD_MSL,
862 AARCH64_MOD_ROR,
863 AARCH64_MOD_ASR,
864 AARCH64_MOD_LSR,
865 AARCH64_MOD_LSL,
866 AARCH64_MOD_UXTB,
867 AARCH64_MOD_UXTH,
868 AARCH64_MOD_UXTW,
869 AARCH64_MOD_UXTX,
870 AARCH64_MOD_SXTB,
871 AARCH64_MOD_SXTH,
872 AARCH64_MOD_SXTW,
873 AARCH64_MOD_SXTX,
2442d846 874 AARCH64_MOD_MUL,
98907a70 875 AARCH64_MOD_MUL_VL,
a06ea964
NC		 876};
877
878bfd_boolean
879aarch64_extend_operator_p (enum aarch64_modifier_kind);
880
881enum aarch64_modifier_kind
882aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
883/* Condition. */
884
885typedef struct
886{
887 /* A list of names with the first one as the disassembly preference;
888 terminated by NULL if fewer than 3. */
bb7eff52 889 const char *names[4];
a06ea964
NC		 890 aarch64_insn value;
891} aarch64_cond;
892
893extern const aarch64_cond aarch64_conds[16];
894
895const aarch64_cond* get_cond_from_value (aarch64_insn value);
896const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
897\f
898/* Structure representing an operand. */
899
900struct aarch64_opnd_info
901{
902 enum aarch64_opnd type;
903 aarch64_opnd_qualifier_t qualifier;
904 int idx;
905
906 union
907 {
908 struct
909 {
910 unsigned regno;
911 } reg;
912 struct
913 {
dab26bf4
RS		 914 unsigned int regno;
915 int64_t index;
a06ea964
NC		 916 } reglane;
917 /* e.g. LVn. */
918 struct
919 {
920 unsigned first_regno : 5;
921 unsigned num_regs : 3;
922 /* 1 if it is a list of reg element. */
923 unsigned has_index : 1;
924 /* Lane index; valid only when has_index is 1. */
dab26bf4 925 int64_t index;
a06ea964
NC		 926 } reglist;
927 /* e.g. immediate or pc relative address offset. */
928 struct
929 {
930 int64_t value;
931 unsigned is_fp : 1;
932 } imm;
933 /* e.g. address in STR (register offset). */
934 struct
935 {
936 unsigned base_regno;
937 struct
938 {
939 union
940 {
941 int imm;
942 unsigned regno;
943 };
944 unsigned is_reg;
945 } offset;
946 unsigned pcrel : 1; /* PC-relative. */
947 unsigned writeback : 1;
948 unsigned preind : 1; /* Pre-indexed. */
949 unsigned postind : 1; /* Post-indexed. */
950 } addr;
951 const aarch64_cond *cond;
952 /* The encoding of the system register. */
953 aarch64_insn sysreg;
954 /* The encoding of the PSTATE field. */
955 aarch64_insn pstatefield;
956 const aarch64_sys_ins_reg *sysins_op;
957 const struct aarch64_name_value_pair *barrier;
9ed608f9 958 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 959 const struct aarch64_name_value_pair *prfop;
960 };
961
962 /* Operand shifter; in use when the operand is a register offset address,
963 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
964 struct
965 {
966 enum aarch64_modifier_kind kind;
a06ea964
NC		 967 unsigned operator_present: 1; /* Only valid during encoding. */
968 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
969 unsigned amount_present: 1;
2442d846 970 int64_t amount;
a06ea964
NC		 971 } shifter;
972
973 unsigned skip:1; /* Operand is not completed if there is a fixup needed
974 to be done on it. In some (but not all) of these
975 cases, we need to tell libopcodes to skip the
976 constraint checking and the encoding for this
977 operand, so that the libopcodes can pick up the
978 right opcode before the operand is fixed-up. This
979 flag should only be used during the
980 assembling/encoding. */
981 unsigned present:1; /* Whether this operand is present in the assembly
982 line; not used during the disassembly. */
983};
984
985typedef struct aarch64_opnd_info aarch64_opnd_info;
986
987/* Structure representing an instruction.
988
989 It is used during both the assembling and disassembling. The assembler
990 fills an aarch64_inst after a successful parsing and then passes it to the
991 encoding routine to do the encoding. During the disassembling, the
992 disassembler calls the decoding routine to decode a binary instruction; on a
993 successful return, such a structure will be filled with information of the
994 instruction; then the disassembler uses the information to print out the
995 instruction. */
996
997struct aarch64_inst
998{
999 /* The value of the binary instruction. */
1000 aarch64_insn value;
1001
1002 /* Corresponding opcode entry. */
1003 const aarch64_opcode *opcode;
1004
1005 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1006 const aarch64_cond *cond;
1007
1008 /* Operands information. */
1009 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1010};
1011
1012typedef struct aarch64_inst aarch64_inst;
1013\f
1014/* Diagnosis related declaration and interface. */
1015
1016/* Operand error kind enumerators.
1017
1018 AARCH64_OPDE_RECOVERABLE
1019 Less severe error found during the parsing, very possibly because that
1020 GAS has picked up a wrong instruction template for the parsing.
1021
1022 AARCH64_OPDE_SYNTAX_ERROR
1023 General syntax error; it can be either a user error, or simply because
1024 that GAS is trying a wrong instruction template.
1025
1026 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1027 Definitely a user syntax error.
1028
1029 AARCH64_OPDE_INVALID_VARIANT
1030 No syntax error, but the operands are not a valid combination, e.g.
1031 FMOV D0,S0
1032
0c608d6b
RS		 1033 AARCH64_OPDE_UNTIED_OPERAND
1034 The asm failed to use the same register for a destination operand
1035 and a tied source operand.
1036
a06ea964
NC		 1037 AARCH64_OPDE_OUT_OF_RANGE
1038 Error about some immediate value out of a valid range.
1039
1040 AARCH64_OPDE_UNALIGNED
1041 Error about some immediate value not properly aligned (i.e. not being a
1042 multiple times of a certain value).
1043
1044 AARCH64_OPDE_REG_LIST
1045 Error about the register list operand having unexpected number of
1046 registers.
1047
1048 AARCH64_OPDE_OTHER_ERROR
1049 Error of the highest severity and used for any severe issue that does not
1050 fall into any of the above categories.
1051
1052 The enumerators are only interesting to GAS. They are declared here (in
1053 libopcodes) because that some errors are detected (and then notified to GAS)
1054 by libopcodes (rather than by GAS solely).
1055
1056 The first three errors are only deteced by GAS while the
1057 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1058 only libopcodes has the information about the valid variants of each
1059 instruction.
1060
1061 The enumerators have an increasing severity. This is helpful when there are
1062 multiple instruction templates available for a given mnemonic name (e.g.
1063 FMOV); this mechanism will help choose the most suitable template from which
1064 the generated diagnostics can most closely describe the issues, if any. */
1065
1066enum aarch64_operand_error_kind
1067{
1068 AARCH64_OPDE_NIL,
1069 AARCH64_OPDE_RECOVERABLE,
1070 AARCH64_OPDE_SYNTAX_ERROR,
1071 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1072 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1073 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1074 AARCH64_OPDE_OUT_OF_RANGE,
1075 AARCH64_OPDE_UNALIGNED,
1076 AARCH64_OPDE_REG_LIST,
1077 AARCH64_OPDE_OTHER_ERROR
1078};
1079
1080/* N.B. GAS assumes that this structure work well with shallow copy. */
1081struct aarch64_operand_error
1082{
1083 enum aarch64_operand_error_kind kind;
1084 int index;
1085 const char *error;
1086 int data[3]; /* Some data for extra information. */
1087};
1088
1089typedef struct aarch64_operand_error aarch64_operand_error;
1090
1091/* Encoding entrypoint. */
1092
1093extern int
1094aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1095 aarch64_insn *, aarch64_opnd_qualifier_t *,
1096 aarch64_operand_error *);
1097
1098extern const aarch64_opcode *
1099aarch64_replace_opcode (struct aarch64_inst *,
1100 const aarch64_opcode *);
1101
1102/* Given the opcode enumerator OP, return the pointer to the corresponding
1103 opcode entry. */
1104
1105extern const aarch64_opcode *
1106aarch64_get_opcode (enum aarch64_op);
1107
1108/* Generate the string representation of an operand. */
1109extern void
1110aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1111 const aarch64_opnd_info *, int, int *, bfd_vma *);
1112
1113/* Miscellaneous interface. */
1114
1115extern int
1116aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1117
1118extern aarch64_opnd_qualifier_t
1119aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1120 const aarch64_opnd_qualifier_t, int);
1121
1122extern int
1123aarch64_num_of_operands (const aarch64_opcode *);
1124
1125extern int
1126aarch64_stack_pointer_p (const aarch64_opnd_info *);
1127
e141d84e
YQ		 1128extern int
1129aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1130
36f4aab1 1131extern int
43cdf5ae 1132aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1133
a06ea964
NC		 1134/* Given an operand qualifier, return the expected data element size
1135 of a qualified operand. */
1136extern unsigned char
1137aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1138
1139extern enum aarch64_operand_class
1140aarch64_get_operand_class (enum aarch64_opnd);
1141
1142extern const char *
1143aarch64_get_operand_name (enum aarch64_opnd);
1144
1145extern const char *
1146aarch64_get_operand_desc (enum aarch64_opnd);
1147
e950b345
RS		 1148extern bfd_boolean
1149aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1150
a06ea964
NC		 1151#ifdef DEBUG_AARCH64
1152extern int debug_dump;
1153
1154extern void
1155aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1156
1157#define DEBUG_TRACE(M, ...) \
1158 { \
1159 if (debug_dump) \
1160 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1161 }
1162
1163#define DEBUG_TRACE_IF(C, M, ...) \
1164 { \
1165 if (debug_dump && (C)) \
1166 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1167 }
1168#else /* !DEBUG_AARCH64 */
1169#define DEBUG_TRACE(M, ...) ;
1170#define DEBUG_TRACE_IF(C, M, ...) ;
1171#endif /* DEBUG_AARCH64 */
1172
245d2e3f
RS		 1173extern const char *const aarch64_sve_pattern_array[32];
1174extern const char *const aarch64_sve_prfop_array[16];
1175
d3e12b29
YQ		 1176#ifdef __cplusplus
1177}
1178#endif
1179
a06ea964 1180#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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