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[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
85
13c60ad7 86
a06ea964
NC		 87/* Architectures are the sum of the base and extensions. */
88#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
89 AARCH64_FEATURE_FP \
90 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 91#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
92 AARCH64_FEATURE_CRC \
250aafa4 93 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 94 | AARCH64_FEATURE_LSE \
95 | AARCH64_FEATURE_PAN \
96 | AARCH64_FEATURE_LOR \
97 | AARCH64_FEATURE_RDMA)
1924ff75 98#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 99 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 100 | AARCH64_FEATURE_RAS)
101#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 102 AARCH64_FEATURE_V8_3 \
f482d304
RS		 103 | AARCH64_FEATURE_RCPC \
104 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 105#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 106 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 107 | AARCH64_FEATURE_DOTPROD \
108 | AARCH64_FEATURE_F16_FML)
70d56181 109#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 110 AARCH64_FEATURE_V8_5 \
111 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 112 | AARCH64_FEATURE_FRINTTS \
2ac435d4 113 | AARCH64_FEATURE_SB \
3fd229a4 114 | AARCH64_FEATURE_PREDRES \
ff605452 115 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 116 | AARCH64_FEATURE_BTI \
117 | AARCH64_FEATURE_SCXTNUM \
118 | AARCH64_FEATURE_ID_PFR2)
70d56181 119
88f0ea34 120
a06ea964
NC		 121#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
122#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
123
124/* CPU-specific features. */
21b81e67 125typedef unsigned long long aarch64_feature_set;
a06ea964 126
93d8990c
SN		 127#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
128 ((~(CPU) & (FEAT)) == 0)
129
130#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 131 (((CPU) & (FEAT)) != 0)
132
93d8990c
SN		 133#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
134 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
135
a06ea964
NC		 136#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
137 do \
138 { \
139 (TARG) = (F1) | (F2); \
140 } \
141 while (0)
142
143#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
144 do \
145 { \
146 (TARG) = (F1) &~ (F2); \
147 } \
148 while (0)
149
150#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
151
a06ea964
NC		 152enum aarch64_operand_class
153{
154 AARCH64_OPND_CLASS_NIL,
155 AARCH64_OPND_CLASS_INT_REG,
156 AARCH64_OPND_CLASS_MODIFIED_REG,
157 AARCH64_OPND_CLASS_FP_REG,
158 AARCH64_OPND_CLASS_SIMD_REG,
159 AARCH64_OPND_CLASS_SIMD_ELEMENT,
160 AARCH64_OPND_CLASS_SISD_REG,
161 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 162 AARCH64_OPND_CLASS_SVE_REG,
163 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 164 AARCH64_OPND_CLASS_ADDRESS,
165 AARCH64_OPND_CLASS_IMMEDIATE,
166 AARCH64_OPND_CLASS_SYSTEM,
68a64283 167 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 168};
169
170/* Operand code that helps both parsing and coding.
171 Keep AARCH64_OPERANDS synced. */
172
173enum aarch64_opnd
174{
175 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
176
177 AARCH64_OPND_Rd, /* Integer register as destination. */
178 AARCH64_OPND_Rn, /* Integer register as source. */
179 AARCH64_OPND_Rm, /* Integer register as source. */
180 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
181 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
182 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
183 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
184 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
185
186 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
187 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 188 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 189 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 190 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
191 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
192
193 AARCH64_OPND_Fd, /* Floating-point Fd. */
194 AARCH64_OPND_Fn, /* Floating-point Fn. */
195 AARCH64_OPND_Fm, /* Floating-point Fm. */
196 AARCH64_OPND_Fa, /* Floating-point Fa. */
197 AARCH64_OPND_Ft, /* Floating-point Ft. */
198 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
199
200 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
201 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
202 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
203
f42f1a1d 204 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 205 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
206 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
207 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
208 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
209 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
210 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
211 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
212 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 213 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
214 qualifier is S_H. */
a06ea964
NC		 215 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
216 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
217 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
218 structure to all lanes. */
219 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
220
a6a51754
RL		 221 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
222 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 223
224 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 225 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 226 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
227 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
228 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
229 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
230 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
231 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
232 (no encoding). */
233 AARCH64_OPND_IMM0, /* Immediate for #0. */
234 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
235 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
236 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
237 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
238 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
239 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 240 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 241 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
242 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
243 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
244 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
245 AARCH64_OPND_BIT_NUM, /* Immediate. */
246 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
247 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 248 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 249 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
250 each condition flag. */
251
252 AARCH64_OPND_LIMM, /* Logical Immediate. */
253 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
254 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
255 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
256 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 257 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
258 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
259 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 260
261 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 262 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 263
264 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
265 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
266 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
267 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
268 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
269
270 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
271 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
272 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
273 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
274 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
275 negative or unaligned and there is
276 no writeback allowed. This operand code
277 is only used to support the programmer-
278 friendly feature of using LDR/STR as the
279 the mnemonic name for LDUR/STUR instructions
280 wherever there is no ambiguity. */
3f06e550 281 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 282 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
283 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 284 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 285 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
286
287 AARCH64_OPND_SYSREG, /* System register operand. */
288 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
289 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
290 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
291 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
292 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 293 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 294 AARCH64_OPND_BARRIER, /* Barrier operand. */
295 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
296 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 297 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 298 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 299
582e12bf 300 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 301 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
302 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
303 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
304 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
305 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
306 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 307 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
308 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
309 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
310 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 311 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 312 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
313 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
314 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
315 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
316 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
317 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
318 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
319 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
320 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
321 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
322 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
323 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
324 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
325 Bit 14 controls S/U choice. */
326 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
327 Bit 22 controls S/U choice. */
328 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
329 Bit 14 controls S/U choice. */
330 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
331 Bit 22 controls S/U choice. */
332 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
333 Bit 14 controls S/U choice. */
334 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
335 Bit 22 controls S/U choice. */
336 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
337 Bit 14 controls S/U choice. */
338 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
339 Bit 22 controls S/U choice. */
340 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
341 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
342 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
343 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
344 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
345 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
346 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 347 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
348 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 349 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
350 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
351 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
352 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 353 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
354 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 355 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
356 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
357 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 358 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 359 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 360 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 361 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
362 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
363 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
364 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
365 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
366 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
367 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
368 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 369 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
370 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 371 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
372 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
373 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
374 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
375 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
376 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
377 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
378 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
379 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
380 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
381 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
382 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 383 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
384 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
385 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
386 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 387 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
388 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
389 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
390 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
391 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 392 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
393 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
394 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 395 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
396 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
397 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
398 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
399 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 400 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 401};
402
403/* Qualifier constrains an operand. It either specifies a variant of an
404 operand type or limits values available to an operand type.
405
406 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
407
408enum aarch64_opnd_qualifier
409{
410 /* Indicating no further qualification on an operand. */
411 AARCH64_OPND_QLF_NIL,
412
413 /* Qualifying an operand which is a general purpose (integer) register;
414 indicating the operand data size or a specific register. */
415 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
416 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
417 AARCH64_OPND_QLF_WSP, /* WSP. */
418 AARCH64_OPND_QLF_SP, /* SP. */
419
420 /* Qualifying an operand which is a floating-point register, a SIMD
421 vector element or a SIMD vector element list; indicating operand data
422 size or the size of each SIMD vector element in the case of a SIMD
423 vector element list.
424 These qualifiers are also used to qualify an address operand to
425 indicate the size of data element a load/store instruction is
426 accessing.
427 They are also used for the immediate shift operand in e.g. SSHR. Such
428 a use is only for the ease of operand encoding/decoding and qualifier
429 sequence matching; such a use should not be applied widely; use the value
430 constraint qualifiers for immediate operands wherever possible. */
431 AARCH64_OPND_QLF_S_B,
432 AARCH64_OPND_QLF_S_H,
433 AARCH64_OPND_QLF_S_S,
434 AARCH64_OPND_QLF_S_D,
435 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 436 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
437 are selected by the instruction. Other than that it has no difference
438 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
439 reasons and is an exception from normal AArch64 disassembly scheme. */
440 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 441
442 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
443 register list; indicating register shape.
444 They are also used for the immediate shift operand in e.g. SSHR. Such
445 a use is only for the ease of operand encoding/decoding and qualifier
446 sequence matching; such a use should not be applied widely; use the value
447 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 448 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 449 AARCH64_OPND_QLF_V_8B,
450 AARCH64_OPND_QLF_V_16B,
3067d3b9 451 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 452 AARCH64_OPND_QLF_V_4H,
453 AARCH64_OPND_QLF_V_8H,
454 AARCH64_OPND_QLF_V_2S,
455 AARCH64_OPND_QLF_V_4S,
456 AARCH64_OPND_QLF_V_1D,
457 AARCH64_OPND_QLF_V_2D,
458 AARCH64_OPND_QLF_V_1Q,
459
d50c751e
RS		 460 AARCH64_OPND_QLF_P_Z,
461 AARCH64_OPND_QLF_P_M,
462
a06ea964 463 /* Constraint on value. */
a6a51754 464 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 465 AARCH64_OPND_QLF_imm_0_7,
466 AARCH64_OPND_QLF_imm_0_15,
467 AARCH64_OPND_QLF_imm_0_31,
468 AARCH64_OPND_QLF_imm_0_63,
469 AARCH64_OPND_QLF_imm_1_32,
470 AARCH64_OPND_QLF_imm_1_64,
471
472 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
473 or shift-ones. */
474 AARCH64_OPND_QLF_LSL,
475 AARCH64_OPND_QLF_MSL,
476
477 /* Special qualifier helping retrieve qualifier information during the
478 decoding time (currently not in use). */
479 AARCH64_OPND_QLF_RETRIEVE,
480};
481\f
482/* Instruction class. */
483
484enum aarch64_insn_class
485{
486 addsub_carry,
487 addsub_ext,
488 addsub_imm,
489 addsub_shift,
490 asimdall,
491 asimddiff,
492 asimdelem,
493 asimdext,
494 asimdimm,
495 asimdins,
496 asimdmisc,
497 asimdperm,
498 asimdsame,
499 asimdshf,
500 asimdtbl,
501 asisddiff,
502 asisdelem,
503 asisdlse,
504 asisdlsep,
505 asisdlso,
506 asisdlsop,
507 asisdmisc,
508 asisdone,
509 asisdpair,
510 asisdsame,
511 asisdshf,
512 bitfield,
513 branch_imm,
514 branch_reg,
515 compbranch,
516 condbranch,
517 condcmp_imm,
518 condcmp_reg,
519 condsel,
520 cryptoaes,
521 cryptosha2,
522 cryptosha3,
523 dp_1src,
524 dp_2src,
525 dp_3src,
526 exception,
527 extract,
528 float2fix,
529 float2int,
530 floatccmp,
531 floatcmp,
532 floatdp1,
533 floatdp2,
534 floatdp3,
535 floatimm,
536 floatsel,
537 ldst_immpost,
538 ldst_immpre,
539 ldst_imm9, /* immpost or immpre */
3f06e550 540 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 541 ldst_pos,
542 ldst_regoff,
543 ldst_unpriv,
544 ldst_unscaled,
545 ldstexcl,
546 ldstnapair_offs,
547 ldstpair_off,
548 ldstpair_indexed,
549 loadlit,
550 log_imm,
551 log_shift,
ee804238 552 lse_atomic,
a06ea964
NC		 553 movewide,
554 pcreladdr,
555 ic_system,
116b6019
RS		 556 sve_cpy,
557 sve_index,
558 sve_limm,
559 sve_misc,
560 sve_movprfx,
561 sve_pred_zm,
562 sve_shift_pred,
563 sve_shift_unpred,
564 sve_size_bhs,
565 sve_size_bhsd,
566 sve_size_hsd,
567 sve_size_sd,
a06ea964 568 testbranch,
f42f1a1d
TC		 569 cryptosm3,
570 cryptosm4,
65a55fbb 571 dotproduct,
a06ea964
NC		 572};
573
574/* Opcode enumerators. */
575
576enum aarch64_op
577{
578 OP_NIL,
579 OP_STRB_POS,
580 OP_LDRB_POS,
581 OP_LDRSB_POS,
582 OP_STRH_POS,
583 OP_LDRH_POS,
584 OP_LDRSH_POS,
585 OP_STR_POS,
586 OP_LDR_POS,
587 OP_STRF_POS,
588 OP_LDRF_POS,
589 OP_LDRSW_POS,
590 OP_PRFM_POS,
591
592 OP_STURB,
593 OP_LDURB,
594 OP_LDURSB,
595 OP_STURH,
596 OP_LDURH,
597 OP_LDURSH,
598 OP_STUR,
599 OP_LDUR,
600 OP_STURV,
601 OP_LDURV,
602 OP_LDURSW,
603 OP_PRFUM,
604
605 OP_LDR_LIT,
606 OP_LDRV_LIT,
607 OP_LDRSW_LIT,
608 OP_PRFM_LIT,
609
610 OP_ADD,
611 OP_B,
612 OP_BL,
613
614 OP_MOVN,
615 OP_MOVZ,
616 OP_MOVK,
617
618 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
619 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
620 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
621
622 OP_MOV_V, /* MOV alias for moving vector register. */
623
624 OP_ASR_IMM,
625 OP_LSR_IMM,
626 OP_LSL_IMM,
627
628 OP_BIC,
629
630 OP_UBFX,
631 OP_BFXIL,
632 OP_SBFX,
633 OP_SBFIZ,
634 OP_BFI,
d685192a 635 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 636 OP_UBFIZ,
637 OP_UXTB,
638 OP_UXTH,
639 OP_UXTW,
640
a06ea964
NC		 641 OP_CINC,
642 OP_CINV,
643 OP_CNEG,
644 OP_CSET,
645 OP_CSETM,
646
647 OP_FCVT,
648 OP_FCVTN,
649 OP_FCVTN2,
650 OP_FCVTL,
651 OP_FCVTL2,
652 OP_FCVTXN_S, /* Scalar version. */
653
654 OP_ROR_IMM,
655
e30181a5
YZ		 656 OP_SXTL,
657 OP_SXTL2,
658 OP_UXTL,
659 OP_UXTL2,
660
c0890d26
RS		 661 OP_MOV_P_P,
662 OP_MOV_Z_P_Z,
663 OP_MOV_Z_V,
664 OP_MOV_Z_Z,
665 OP_MOV_Z_Zi,
666 OP_MOVM_P_P_P,
667 OP_MOVS_P_P,
668 OP_MOVZS_P_P_P,
669 OP_MOVZ_P_P_P,
670 OP_NOTS_P_P_P_Z,
671 OP_NOT_P_P_P_Z,
672
c2c4ff8d
SN		 673 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
674
a06ea964
NC		 675 OP_TOTAL_NUM, /* Pseudo. */
676};
677
1d482394
TC		 678/* Error types. */
679enum err_type
680{
681 ERR_OK,
682 ERR_UND,
683 ERR_UNP,
684 ERR_NYI,
a68f4cd2 685 ERR_VFI,
1d482394
TC		 686 ERR_NR_ENTRIES
687};
688
a06ea964
NC		 689/* Maximum number of operands an instruction can have. */
690#define AARCH64_MAX_OPND_NUM 6
691/* Maximum number of qualifier sequences an instruction can have. */
692#define AARCH64_MAX_QLF_SEQ_NUM 10
693/* Operand qualifier typedef; optimized for the size. */
694typedef unsigned char aarch64_opnd_qualifier_t;
695/* Operand qualifier sequence typedef. */
696typedef aarch64_opnd_qualifier_t \
697 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
698
699/* FIXME: improve the efficiency. */
700static inline bfd_boolean
701empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
702{
703 int i;
704 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
705 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
706 return FALSE;
707 return TRUE;
708}
709
7e84b55d
TC		 710/* Forward declare error reporting type. */
711typedef struct aarch64_operand_error aarch64_operand_error;
712/* Forward declare instruction sequence type. */
713typedef struct aarch64_instr_sequence aarch64_instr_sequence;
714/* Forward declare instruction definition. */
715typedef struct aarch64_inst aarch64_inst;
716
a06ea964
NC		 717/* This structure holds information for a particular opcode. */
718
719struct aarch64_opcode
720{
721 /* The name of the mnemonic. */
722 const char *name;
723
724 /* The opcode itself. Those bits which will be filled in with
725 operands are zeroes. */
726 aarch64_insn opcode;
727
728 /* The opcode mask. This is used by the disassembler. This is a
729 mask containing ones indicating those bits which must match the
730 opcode field, and zeroes indicating those bits which need not
731 match (and are presumably filled in by operands). */
732 aarch64_insn mask;
733
734 /* Instruction class. */
735 enum aarch64_insn_class iclass;
736
737 /* Enumerator identifier. */
738 enum aarch64_op op;
739
740 /* Which architecture variant provides this instruction. */
741 const aarch64_feature_set *avariant;
742
743 /* An array of operand codes. Each code is an index into the
744 operand table. They appear in the order which the operands must
745 appear in assembly code, and are terminated by a zero. */
746 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
747
748 /* A list of operand qualifier code sequence. Each operand qualifier
749 code qualifies the corresponding operand code. Each operand
750 qualifier sequence specifies a valid opcode variant and related
751 constraint on operands. */
752 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
753
754 /* Flags providing information about this instruction */
eae424ae
TC		 755 uint64_t flags;
756
757 /* Extra constraints on the instruction that the verifier checks. */
758 uint32_t constraints;
4bd13cde 759
0c608d6b
RS		 760 /* If nonzero, this operand and operand 0 are both registers and
761 are required to have the same register number. */
762 unsigned char tied_operand;
763
4bd13cde 764 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 765 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
766 bfd_vma, bfd_boolean, aarch64_operand_error *,
767 struct aarch64_instr_sequence *);
a06ea964
NC		 768};
769
770typedef struct aarch64_opcode aarch64_opcode;
771
772/* Table describing all the AArch64 opcodes. */
773extern aarch64_opcode aarch64_opcode_table[];
774
775/* Opcode flags. */
776#define F_ALIAS (1 << 0)
777#define F_HAS_ALIAS (1 << 1)
778/* Disassembly preference priority 1-3 (the larger the higher). If nothing
779 is specified, it is the priority 0 by default, i.e. the lowest priority. */
780#define F_P1 (1 << 2)
781#define F_P2 (2 << 2)
782#define F_P3 (3 << 2)
783/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
784#define F_COND (1 << 4)
785/* Instruction has the field of 'sf'. */
786#define F_SF (1 << 5)
787/* Instruction has the field of 'size:Q'. */
788#define F_SIZEQ (1 << 6)
789/* Floating-point instruction has the field of 'type'. */
790#define F_FPTYPE (1 << 7)
791/* AdvSIMD scalar instruction has the field of 'size'. */
792#define F_SSIZE (1 << 8)
793/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
794#define F_T (1 << 9)
795/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
796#define F_GPRSIZE_IN_Q (1 << 10)
797/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
798#define F_LDS_SIZE (1 << 11)
799/* Optional operand; assume maximum of 1 operand can be optional. */
800#define F_OPD0_OPT (1 << 12)
801#define F_OPD1_OPT (2 << 12)
802#define F_OPD2_OPT (3 << 12)
803#define F_OPD3_OPT (4 << 12)
804#define F_OPD4_OPT (5 << 12)
805/* Default value for the optional operand when omitted from the assembly. */
806#define F_DEFAULT(X) (((X) & 0x1f) << 15)
807/* Instruction that is an alias of another instruction needs to be
808 encoded/decoded by converting it to/from the real form, followed by
809 the encoding/decoding according to the rules of the real opcode.
810 This compares to the direct coding using the alias's information.
811 N.B. this flag requires F_ALIAS to be used together. */
812#define F_CONV (1 << 20)
813/* Use together with F_ALIAS to indicate an alias opcode is a programmer
814 friendly pseudo instruction available only in the assembly code (thus will
815 not show up in the disassembly). */
816#define F_PSEUDO (1 << 21)
817/* Instruction has miscellaneous encoding/decoding rules. */
818#define F_MISC (1 << 22)
819/* Instruction has the field of 'N'; used in conjunction with F_SF. */
820#define F_N (1 << 23)
821/* Opcode dependent field. */
822#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 823/* Instruction has the field of 'sz'. */
824#define F_LSE_SZ (1 << 27)
4989adac
RS		 825/* Require an exact qualifier match, even for NIL qualifiers. */
826#define F_STRICT (1ULL << 28)
f9830ec1
TC		 827/* This system instruction is used to read system registers. */
828#define F_SYS_READ (1ULL << 29)
829/* This system instruction is used to write system registers. */
830#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 831/* This instruction has an extra constraint on it that imposes a requirement on
832 subsequent instructions. */
833#define F_SCAN (1ULL << 31)
834/* Next bit is 32. */
835
836/* Instruction constraints. */
837/* This instruction has a predication constraint on the instruction at PC+4. */
838#define C_SCAN_MOVPRFX (1U << 0)
839/* This instruction's operation width is determined by the operand with the
840 largest element size. */
841#define C_MAX_ELEM (1U << 1)
842/* Next bit is 2. */
a06ea964
NC		 843
844static inline bfd_boolean
845alias_opcode_p (const aarch64_opcode *opcode)
846{
847 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
848}
849
850static inline bfd_boolean
851opcode_has_alias (const aarch64_opcode *opcode)
852{
853 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
854}
855
856/* Priority for disassembling preference. */
857static inline int
858opcode_priority (const aarch64_opcode *opcode)
859{
860 return (opcode->flags >> 2) & 0x3;
861}
862
863static inline bfd_boolean
864pseudo_opcode_p (const aarch64_opcode *opcode)
865{
866 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
867}
868
869static inline bfd_boolean
870optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
871{
872 return (((opcode->flags >> 12) & 0x7) == idx + 1)
873 ? TRUE : FALSE;
874}
875
876static inline aarch64_insn
877get_optional_operand_default_value (const aarch64_opcode *opcode)
878{
879 return (opcode->flags >> 15) & 0x1f;
880}
881
882static inline unsigned int
883get_opcode_dependent_value (const aarch64_opcode *opcode)
884{
885 return (opcode->flags >> 24) & 0x7;
886}
887
888static inline bfd_boolean
889opcode_has_special_coder (const aarch64_opcode *opcode)
890{
ee804238 891 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 892 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
893 : FALSE;
894}
895\f
896struct aarch64_name_value_pair
897{
898 const char * name;
899 aarch64_insn value;
900};
901
902extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 903extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
904extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 905extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 906
49eec193
YZ		 907typedef struct
908{
909 const char * name;
910 aarch64_insn value;
911 uint32_t flags;
912} aarch64_sys_reg;
913
914extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 915extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 916extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 917extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
918 const aarch64_sys_reg *);
919extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
920 const aarch64_sys_reg *);
49eec193 921
a06ea964
NC		 922typedef struct
923{
875880c6 924 const char *name;
a06ea964 925 uint32_t value;
ea2deeec 926 uint32_t flags ;
a06ea964
NC		 927} aarch64_sys_ins_reg;
928
ea2deeec 929extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 930extern bfd_boolean
931aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
932 const aarch64_sys_ins_reg *);
ea2deeec 933
a06ea964
NC		 934extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
935extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
936extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
937extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 938extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 939
940/* Shift/extending operator kinds.
941 N.B. order is important; keep aarch64_operand_modifiers synced. */
942enum aarch64_modifier_kind
943{
944 AARCH64_MOD_NONE,
945 AARCH64_MOD_MSL,
946 AARCH64_MOD_ROR,
947 AARCH64_MOD_ASR,
948 AARCH64_MOD_LSR,
949 AARCH64_MOD_LSL,
950 AARCH64_MOD_UXTB,
951 AARCH64_MOD_UXTH,
952 AARCH64_MOD_UXTW,
953 AARCH64_MOD_UXTX,
954 AARCH64_MOD_SXTB,
955 AARCH64_MOD_SXTH,
956 AARCH64_MOD_SXTW,
957 AARCH64_MOD_SXTX,
2442d846 958 AARCH64_MOD_MUL,
98907a70 959 AARCH64_MOD_MUL_VL,
a06ea964
NC		 960};
961
962bfd_boolean
963aarch64_extend_operator_p (enum aarch64_modifier_kind);
964
965enum aarch64_modifier_kind
966aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
967/* Condition. */
968
969typedef struct
970{
971 /* A list of names with the first one as the disassembly preference;
972 terminated by NULL if fewer than 3. */
bb7eff52 973 const char *names[4];
a06ea964
NC		 974 aarch64_insn value;
975} aarch64_cond;
976
977extern const aarch64_cond aarch64_conds[16];
978
979const aarch64_cond* get_cond_from_value (aarch64_insn value);
980const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
981\f
982/* Structure representing an operand. */
983
984struct aarch64_opnd_info
985{
986 enum aarch64_opnd type;
987 aarch64_opnd_qualifier_t qualifier;
988 int idx;
989
990 union
991 {
992 struct
993 {
994 unsigned regno;
995 } reg;
996 struct
997 {
dab26bf4
RS		 998 unsigned int regno;
999 int64_t index;
a06ea964
NC		 1000 } reglane;
1001 /* e.g. LVn. */
1002 struct
1003 {
1004 unsigned first_regno : 5;
1005 unsigned num_regs : 3;
1006 /* 1 if it is a list of reg element. */
1007 unsigned has_index : 1;
1008 /* Lane index; valid only when has_index is 1. */
dab26bf4 1009 int64_t index;
a06ea964
NC		 1010 } reglist;
1011 /* e.g. immediate or pc relative address offset. */
1012 struct
1013 {
1014 int64_t value;
1015 unsigned is_fp : 1;
1016 } imm;
1017 /* e.g. address in STR (register offset). */
1018 struct
1019 {
1020 unsigned base_regno;
1021 struct
1022 {
1023 union
1024 {
1025 int imm;
1026 unsigned regno;
1027 };
1028 unsigned is_reg;
1029 } offset;
1030 unsigned pcrel : 1; /* PC-relative. */
1031 unsigned writeback : 1;
1032 unsigned preind : 1; /* Pre-indexed. */
1033 unsigned postind : 1; /* Post-indexed. */
1034 } addr;
561a72d4
TC		 1035
1036 struct
1037 {
1038 /* The encoding of the system register. */
1039 aarch64_insn value;
1040
1041 /* The system register flags. */
1042 uint32_t flags;
1043 } sysreg;
1044
a06ea964 1045 const aarch64_cond *cond;
a06ea964
NC		 1046 /* The encoding of the PSTATE field. */
1047 aarch64_insn pstatefield;
1048 const aarch64_sys_ins_reg *sysins_op;
1049 const struct aarch64_name_value_pair *barrier;
9ed608f9 1050 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1051 const struct aarch64_name_value_pair *prfop;
1052 };
1053
1054 /* Operand shifter; in use when the operand is a register offset address,
1055 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1056 struct
1057 {
1058 enum aarch64_modifier_kind kind;
a06ea964
NC		 1059 unsigned operator_present: 1; /* Only valid during encoding. */
1060 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1061 unsigned amount_present: 1;
2442d846 1062 int64_t amount;
a06ea964
NC		 1063 } shifter;
1064
1065 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1066 to be done on it. In some (but not all) of these
1067 cases, we need to tell libopcodes to skip the
1068 constraint checking and the encoding for this
1069 operand, so that the libopcodes can pick up the
1070 right opcode before the operand is fixed-up. This
1071 flag should only be used during the
1072 assembling/encoding. */
1073 unsigned present:1; /* Whether this operand is present in the assembly
1074 line; not used during the disassembly. */
1075};
1076
1077typedef struct aarch64_opnd_info aarch64_opnd_info;
1078
1079/* Structure representing an instruction.
1080
1081 It is used during both the assembling and disassembling. The assembler
1082 fills an aarch64_inst after a successful parsing and then passes it to the
1083 encoding routine to do the encoding. During the disassembling, the
1084 disassembler calls the decoding routine to decode a binary instruction; on a
1085 successful return, such a structure will be filled with information of the
1086 instruction; then the disassembler uses the information to print out the
1087 instruction. */
1088
1089struct aarch64_inst
1090{
1091 /* The value of the binary instruction. */
1092 aarch64_insn value;
1093
1094 /* Corresponding opcode entry. */
1095 const aarch64_opcode *opcode;
1096
1097 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1098 const aarch64_cond *cond;
1099
1100 /* Operands information. */
1101 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1102};
1103
ff605452
SD		 1104/* Defining the HINT #imm values for the aarch64_hint_options. */
1105#define HINT_OPD_CSYNC 0x11
1106#define HINT_OPD_C 0x22
1107#define HINT_OPD_J 0x24
1108#define HINT_OPD_JC 0x26
1109#define HINT_OPD_NULL 0x00
1110
a06ea964
NC		 1111\f
1112/* Diagnosis related declaration and interface. */
1113
1114/* Operand error kind enumerators.
1115
1116 AARCH64_OPDE_RECOVERABLE
1117 Less severe error found during the parsing, very possibly because that
1118 GAS has picked up a wrong instruction template for the parsing.
1119
1120 AARCH64_OPDE_SYNTAX_ERROR
1121 General syntax error; it can be either a user error, or simply because
1122 that GAS is trying a wrong instruction template.
1123
1124 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1125 Definitely a user syntax error.
1126
1127 AARCH64_OPDE_INVALID_VARIANT
1128 No syntax error, but the operands are not a valid combination, e.g.
1129 FMOV D0,S0
1130
0c608d6b
RS		 1131 AARCH64_OPDE_UNTIED_OPERAND
1132 The asm failed to use the same register for a destination operand
1133 and a tied source operand.
1134
a06ea964
NC		 1135 AARCH64_OPDE_OUT_OF_RANGE
1136 Error about some immediate value out of a valid range.
1137
1138 AARCH64_OPDE_UNALIGNED
1139 Error about some immediate value not properly aligned (i.e. not being a
1140 multiple times of a certain value).
1141
1142 AARCH64_OPDE_REG_LIST
1143 Error about the register list operand having unexpected number of
1144 registers.
1145
1146 AARCH64_OPDE_OTHER_ERROR
1147 Error of the highest severity and used for any severe issue that does not
1148 fall into any of the above categories.
1149
1150 The enumerators are only interesting to GAS. They are declared here (in
1151 libopcodes) because that some errors are detected (and then notified to GAS)
1152 by libopcodes (rather than by GAS solely).
1153
1154 The first three errors are only deteced by GAS while the
1155 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1156 only libopcodes has the information about the valid variants of each
1157 instruction.
1158
1159 The enumerators have an increasing severity. This is helpful when there are
1160 multiple instruction templates available for a given mnemonic name (e.g.
1161 FMOV); this mechanism will help choose the most suitable template from which
1162 the generated diagnostics can most closely describe the issues, if any. */
1163
1164enum aarch64_operand_error_kind
1165{
1166 AARCH64_OPDE_NIL,
1167 AARCH64_OPDE_RECOVERABLE,
1168 AARCH64_OPDE_SYNTAX_ERROR,
1169 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1170 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1171 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1172 AARCH64_OPDE_OUT_OF_RANGE,
1173 AARCH64_OPDE_UNALIGNED,
1174 AARCH64_OPDE_REG_LIST,
1175 AARCH64_OPDE_OTHER_ERROR
1176};
1177
1178/* N.B. GAS assumes that this structure work well with shallow copy. */
1179struct aarch64_operand_error
1180{
1181 enum aarch64_operand_error_kind kind;
1182 int index;
1183 const char *error;
1184 int data[3]; /* Some data for extra information. */
7d02540a 1185 bfd_boolean non_fatal;
a06ea964
NC		 1186};
1187
7e84b55d
TC		 1188/* AArch64 sequence structure used to track instructions with F_SCAN
1189 dependencies for both assembler and disassembler. */
1190struct aarch64_instr_sequence
1191{
1192 /* The instruction that caused this sequence to be opened. */
1193 aarch64_inst *instr;
1194 /* The number of instructions the above instruction allows to be kept in the
1195 sequence before an automatic close is done. */
1196 int num_insns;
1197 /* The instructions currently added to the sequence. */
1198 aarch64_inst **current_insns;
1199 /* The number of instructions already in the sequence. */
1200 int next_insn;
1201};
a06ea964
NC		 1202
1203/* Encoding entrypoint. */
1204
1205extern int
1206aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1207 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1208 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1209
1210extern const aarch64_opcode *
1211aarch64_replace_opcode (struct aarch64_inst *,
1212 const aarch64_opcode *);
1213
1214/* Given the opcode enumerator OP, return the pointer to the corresponding
1215 opcode entry. */
1216
1217extern const aarch64_opcode *
1218aarch64_get_opcode (enum aarch64_op);
1219
1220/* Generate the string representation of an operand. */
1221extern void
1222aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1223 const aarch64_opnd_info *, int, int *, bfd_vma *,
1224 char **);
a06ea964
NC		 1225
1226/* Miscellaneous interface. */
1227
1228extern int
1229aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1230
1231extern aarch64_opnd_qualifier_t
1232aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1233 const aarch64_opnd_qualifier_t, int);
1234
a68f4cd2
TC		 1235extern bfd_boolean
1236aarch64_is_destructive_by_operands (const aarch64_opcode *);
1237
a06ea964
NC		 1238extern int
1239aarch64_num_of_operands (const aarch64_opcode *);
1240
1241extern int
1242aarch64_stack_pointer_p (const aarch64_opnd_info *);
1243
e141d84e
YQ		 1244extern int
1245aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1246
1d482394 1247extern enum err_type
561a72d4 1248aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1249 aarch64_operand_error *);
1250
1251extern void
1252init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1253
a06ea964
NC		 1254/* Given an operand qualifier, return the expected data element size
1255 of a qualified operand. */
1256extern unsigned char
1257aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1258
1259extern enum aarch64_operand_class
1260aarch64_get_operand_class (enum aarch64_opnd);
1261
1262extern const char *
1263aarch64_get_operand_name (enum aarch64_opnd);
1264
1265extern const char *
1266aarch64_get_operand_desc (enum aarch64_opnd);
1267
e950b345
RS		 1268extern bfd_boolean
1269aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1270
a06ea964
NC		 1271#ifdef DEBUG_AARCH64
1272extern int debug_dump;
1273
1274extern void
1275aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1276
1277#define DEBUG_TRACE(M, ...) \
1278 { \
1279 if (debug_dump) \
1280 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1281 }
1282
1283#define DEBUG_TRACE_IF(C, M, ...) \
1284 { \
1285 if (debug_dump && (C)) \
1286 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1287 }
1288#else /* !DEBUG_AARCH64 */
1289#define DEBUG_TRACE(M, ...) ;
1290#define DEBUG_TRACE_IF(C, M, ...) ;
1291#endif /* DEBUG_AARCH64 */
1292
245d2e3f
RS		 1293extern const char *const aarch64_sve_pattern_array[32];
1294extern const char *const aarch64_sve_prfop_array[16];
1295
d3e12b29
YQ		 1296#ifdef __cplusplus
1297}
1298#endif
1299
a06ea964 1300#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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