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[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
6f2750fe 3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
40#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 41#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 42#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 43#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
44#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
45#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 46#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 47#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 48#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 49#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 50#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 51#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 52#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 53#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 54#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 55#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
a06ea964
NC		 56
57/* Architectures are the sum of the base and extensions. */
58#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
59 AARCH64_FEATURE_FP \
60 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 61#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
62 AARCH64_FEATURE_CRC \
250aafa4 63 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
1924ff75 68#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 69 AARCH64_FEATURE_V8_2 \
87018195 70 | AARCH64_FEATURE_F16 \
1924ff75
SN		 71 | AARCH64_FEATURE_RAS)
72#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
73 AARCH64_FEATURE_V8_3)
88f0ea34 74
a06ea964
NC		 75#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
76#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
77
78/* CPU-specific features. */
79typedef unsigned long aarch64_feature_set;
80
93d8990c
SN		 81#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
82 ((~(CPU) & (FEAT)) == 0)
83
84#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 85 (((CPU) & (FEAT)) != 0)
86
93d8990c
SN		 87#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
88 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
89
a06ea964
NC		 90#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
91 do \
92 { \
93 (TARG) = (F1) | (F2); \
94 } \
95 while (0)
96
97#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
98 do \
99 { \
100 (TARG) = (F1) &~ (F2); \
101 } \
102 while (0)
103
104#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
105
a06ea964
NC		 106enum aarch64_operand_class
107{
108 AARCH64_OPND_CLASS_NIL,
109 AARCH64_OPND_CLASS_INT_REG,
110 AARCH64_OPND_CLASS_MODIFIED_REG,
111 AARCH64_OPND_CLASS_FP_REG,
112 AARCH64_OPND_CLASS_SIMD_REG,
113 AARCH64_OPND_CLASS_SIMD_ELEMENT,
114 AARCH64_OPND_CLASS_SISD_REG,
115 AARCH64_OPND_CLASS_SIMD_REGLIST,
116 AARCH64_OPND_CLASS_CP_REG,
f11ad6bc
RS		 117 AARCH64_OPND_CLASS_SVE_REG,
118 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 119 AARCH64_OPND_CLASS_ADDRESS,
120 AARCH64_OPND_CLASS_IMMEDIATE,
121 AARCH64_OPND_CLASS_SYSTEM,
68a64283 122 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 123};
124
125/* Operand code that helps both parsing and coding.
126 Keep AARCH64_OPERANDS synced. */
127
128enum aarch64_opnd
129{
130 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
131
132 AARCH64_OPND_Rd, /* Integer register as destination. */
133 AARCH64_OPND_Rn, /* Integer register as source. */
134 AARCH64_OPND_Rm, /* Integer register as source. */
135 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
136 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
137 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
138 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
139 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
140
141 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
142 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 143 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 144 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 145 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
146 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
147
148 AARCH64_OPND_Fd, /* Floating-point Fd. */
149 AARCH64_OPND_Fn, /* Floating-point Fn. */
150 AARCH64_OPND_Fm, /* Floating-point Fm. */
151 AARCH64_OPND_Fa, /* Floating-point Fa. */
152 AARCH64_OPND_Ft, /* Floating-point Ft. */
153 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
154
155 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
156 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
157 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
158
159 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
160 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
161 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
162 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
163 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
164 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
165 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
166 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
167 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
168 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
169 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
170 structure to all lanes. */
171 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
172
173 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
174 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
175
176 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
177 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
178 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
179 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
180 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
181 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
182 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
183 (no encoding). */
184 AARCH64_OPND_IMM0, /* Immediate for #0. */
185 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
186 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
187 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
188 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
189 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
190 AARCH64_OPND_IMM, /* Immediate. */
191 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
192 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
193 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
194 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
195 AARCH64_OPND_BIT_NUM, /* Immediate. */
196 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
197 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 198 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 199 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
200 each condition flag. */
201
202 AARCH64_OPND_LIMM, /* Logical Immediate. */
203 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
204 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
205 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
206 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 207 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
208 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
209 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 210
211 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 212 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 213
214 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
215 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
216 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
217 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
218 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
219
220 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
221 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
222 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
223 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
224 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
225 negative or unaligned and there is
226 no writeback allowed. This operand code
227 is only used to support the programmer-
228 friendly feature of using LDR/STR as the
229 the mnemonic name for LDUR/STUR instructions
230 wherever there is no ambiguity. */
3f06e550 231 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 232 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
233 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
234 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
235
236 AARCH64_OPND_SYSREG, /* System register operand. */
237 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
238 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
239 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
240 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
241 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
242 AARCH64_OPND_BARRIER, /* Barrier operand. */
243 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
244 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 245 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 246
98907a70
RS		 247 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
248 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
249 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
250 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
251 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
252 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 253 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
254 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
255 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
256 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
257 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
258 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
259 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
260 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
261 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
262 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
263 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
264 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
265 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
266 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
267 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
268 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
269 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
270 Bit 14 controls S/U choice. */
271 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
272 Bit 22 controls S/U choice. */
273 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
274 Bit 14 controls S/U choice. */
275 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
276 Bit 22 controls S/U choice. */
277 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
278 Bit 14 controls S/U choice. */
279 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
280 Bit 22 controls S/U choice. */
281 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
282 Bit 14 controls S/U choice. */
283 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
284 Bit 22 controls S/U choice. */
285 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
286 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
287 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
288 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
289 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
290 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
291 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 292 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
293 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 294 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
295 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
296 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
297 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
e950b345
RS		 298 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
299 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
300 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 301 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 302 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 303 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 304 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
305 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
306 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
307 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
308 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
309 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
310 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
311 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 312 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
313 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 314 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
315 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
316 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
317 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
318 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
319 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
320 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
321 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
322 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
323 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
324 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
325 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 326 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
327 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
328 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
329 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 330 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
331 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
332 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
333 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
334 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
335 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
336 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
337 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
338 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
339 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
a06ea964
NC		 340};
341
342/* Qualifier constrains an operand. It either specifies a variant of an
343 operand type or limits values available to an operand type.
344
345 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
346
347enum aarch64_opnd_qualifier
348{
349 /* Indicating no further qualification on an operand. */
350 AARCH64_OPND_QLF_NIL,
351
352 /* Qualifying an operand which is a general purpose (integer) register;
353 indicating the operand data size or a specific register. */
354 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
355 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
356 AARCH64_OPND_QLF_WSP, /* WSP. */
357 AARCH64_OPND_QLF_SP, /* SP. */
358
359 /* Qualifying an operand which is a floating-point register, a SIMD
360 vector element or a SIMD vector element list; indicating operand data
361 size or the size of each SIMD vector element in the case of a SIMD
362 vector element list.
363 These qualifiers are also used to qualify an address operand to
364 indicate the size of data element a load/store instruction is
365 accessing.
366 They are also used for the immediate shift operand in e.g. SSHR. Such
367 a use is only for the ease of operand encoding/decoding and qualifier
368 sequence matching; such a use should not be applied widely; use the value
369 constraint qualifiers for immediate operands wherever possible. */
370 AARCH64_OPND_QLF_S_B,
371 AARCH64_OPND_QLF_S_H,
372 AARCH64_OPND_QLF_S_S,
373 AARCH64_OPND_QLF_S_D,
374 AARCH64_OPND_QLF_S_Q,
375
376 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
377 register list; indicating register shape.
378 They are also used for the immediate shift operand in e.g. SSHR. Such
379 a use is only for the ease of operand encoding/decoding and qualifier
380 sequence matching; such a use should not be applied widely; use the value
381 constraint qualifiers for immediate operands wherever possible. */
382 AARCH64_OPND_QLF_V_8B,
383 AARCH64_OPND_QLF_V_16B,
3067d3b9 384 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 385 AARCH64_OPND_QLF_V_4H,
386 AARCH64_OPND_QLF_V_8H,
387 AARCH64_OPND_QLF_V_2S,
388 AARCH64_OPND_QLF_V_4S,
389 AARCH64_OPND_QLF_V_1D,
390 AARCH64_OPND_QLF_V_2D,
391 AARCH64_OPND_QLF_V_1Q,
392
d50c751e
RS		 393 AARCH64_OPND_QLF_P_Z,
394 AARCH64_OPND_QLF_P_M,
395
a06ea964
NC		 396 /* Constraint on value. */
397 AARCH64_OPND_QLF_imm_0_7,
398 AARCH64_OPND_QLF_imm_0_15,
399 AARCH64_OPND_QLF_imm_0_31,
400 AARCH64_OPND_QLF_imm_0_63,
401 AARCH64_OPND_QLF_imm_1_32,
402 AARCH64_OPND_QLF_imm_1_64,
403
404 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
405 or shift-ones. */
406 AARCH64_OPND_QLF_LSL,
407 AARCH64_OPND_QLF_MSL,
408
409 /* Special qualifier helping retrieve qualifier information during the
410 decoding time (currently not in use). */
411 AARCH64_OPND_QLF_RETRIEVE,
412};
413\f
414/* Instruction class. */
415
416enum aarch64_insn_class
417{
418 addsub_carry,
419 addsub_ext,
420 addsub_imm,
421 addsub_shift,
422 asimdall,
423 asimddiff,
424 asimdelem,
425 asimdext,
426 asimdimm,
427 asimdins,
428 asimdmisc,
429 asimdperm,
430 asimdsame,
431 asimdshf,
432 asimdtbl,
433 asisddiff,
434 asisdelem,
435 asisdlse,
436 asisdlsep,
437 asisdlso,
438 asisdlsop,
439 asisdmisc,
440 asisdone,
441 asisdpair,
442 asisdsame,
443 asisdshf,
444 bitfield,
445 branch_imm,
446 branch_reg,
447 compbranch,
448 condbranch,
449 condcmp_imm,
450 condcmp_reg,
451 condsel,
452 cryptoaes,
453 cryptosha2,
454 cryptosha3,
455 dp_1src,
456 dp_2src,
457 dp_3src,
458 exception,
459 extract,
460 float2fix,
461 float2int,
462 floatccmp,
463 floatcmp,
464 floatdp1,
465 floatdp2,
466 floatdp3,
467 floatimm,
468 floatsel,
469 ldst_immpost,
470 ldst_immpre,
471 ldst_imm9, /* immpost or immpre */
3f06e550 472 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 473 ldst_pos,
474 ldst_regoff,
475 ldst_unpriv,
476 ldst_unscaled,
477 ldstexcl,
478 ldstnapair_offs,
479 ldstpair_off,
480 ldstpair_indexed,
481 loadlit,
482 log_imm,
483 log_shift,
ee804238 484 lse_atomic,
a06ea964
NC		 485 movewide,
486 pcreladdr,
487 ic_system,
116b6019
RS		 488 sve_cpy,
489 sve_index,
490 sve_limm,
491 sve_misc,
492 sve_movprfx,
493 sve_pred_zm,
494 sve_shift_pred,
495 sve_shift_unpred,
496 sve_size_bhs,
497 sve_size_bhsd,
498 sve_size_hsd,
499 sve_size_sd,
a06ea964
NC		 500 testbranch,
501};
502
503/* Opcode enumerators. */
504
505enum aarch64_op
506{
507 OP_NIL,
508 OP_STRB_POS,
509 OP_LDRB_POS,
510 OP_LDRSB_POS,
511 OP_STRH_POS,
512 OP_LDRH_POS,
513 OP_LDRSH_POS,
514 OP_STR_POS,
515 OP_LDR_POS,
516 OP_STRF_POS,
517 OP_LDRF_POS,
518 OP_LDRSW_POS,
519 OP_PRFM_POS,
520
521 OP_STURB,
522 OP_LDURB,
523 OP_LDURSB,
524 OP_STURH,
525 OP_LDURH,
526 OP_LDURSH,
527 OP_STUR,
528 OP_LDUR,
529 OP_STURV,
530 OP_LDURV,
531 OP_LDURSW,
532 OP_PRFUM,
533
534 OP_LDR_LIT,
535 OP_LDRV_LIT,
536 OP_LDRSW_LIT,
537 OP_PRFM_LIT,
538
539 OP_ADD,
540 OP_B,
541 OP_BL,
542
543 OP_MOVN,
544 OP_MOVZ,
545 OP_MOVK,
546
547 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
548 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
549 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
550
551 OP_MOV_V, /* MOV alias for moving vector register. */
552
553 OP_ASR_IMM,
554 OP_LSR_IMM,
555 OP_LSL_IMM,
556
557 OP_BIC,
558
559 OP_UBFX,
560 OP_BFXIL,
561 OP_SBFX,
562 OP_SBFIZ,
563 OP_BFI,
d685192a 564 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 565 OP_UBFIZ,
566 OP_UXTB,
567 OP_UXTH,
568 OP_UXTW,
569
a06ea964
NC		 570 OP_CINC,
571 OP_CINV,
572 OP_CNEG,
573 OP_CSET,
574 OP_CSETM,
575
576 OP_FCVT,
577 OP_FCVTN,
578 OP_FCVTN2,
579 OP_FCVTL,
580 OP_FCVTL2,
581 OP_FCVTXN_S, /* Scalar version. */
582
583 OP_ROR_IMM,
584
e30181a5
YZ		 585 OP_SXTL,
586 OP_SXTL2,
587 OP_UXTL,
588 OP_UXTL2,
589
c0890d26
RS		 590 OP_MOV_P_P,
591 OP_MOV_Z_P_Z,
592 OP_MOV_Z_V,
593 OP_MOV_Z_Z,
594 OP_MOV_Z_Zi,
595 OP_MOVM_P_P_P,
596 OP_MOVS_P_P,
597 OP_MOVZS_P_P_P,
598 OP_MOVZ_P_P_P,
599 OP_NOTS_P_P_P_Z,
600 OP_NOT_P_P_P_Z,
601
c2c4ff8d
SN		 602 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
603
a06ea964
NC		 604 OP_TOTAL_NUM, /* Pseudo. */
605};
606
607/* Maximum number of operands an instruction can have. */
608#define AARCH64_MAX_OPND_NUM 6
609/* Maximum number of qualifier sequences an instruction can have. */
610#define AARCH64_MAX_QLF_SEQ_NUM 10
611/* Operand qualifier typedef; optimized for the size. */
612typedef unsigned char aarch64_opnd_qualifier_t;
613/* Operand qualifier sequence typedef. */
614typedef aarch64_opnd_qualifier_t \
615 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
616
617/* FIXME: improve the efficiency. */
618static inline bfd_boolean
619empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
620{
621 int i;
622 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
623 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
624 return FALSE;
625 return TRUE;
626}
627
628/* This structure holds information for a particular opcode. */
629
630struct aarch64_opcode
631{
632 /* The name of the mnemonic. */
633 const char *name;
634
635 /* The opcode itself. Those bits which will be filled in with
636 operands are zeroes. */
637 aarch64_insn opcode;
638
639 /* The opcode mask. This is used by the disassembler. This is a
640 mask containing ones indicating those bits which must match the
641 opcode field, and zeroes indicating those bits which need not
642 match (and are presumably filled in by operands). */
643 aarch64_insn mask;
644
645 /* Instruction class. */
646 enum aarch64_insn_class iclass;
647
648 /* Enumerator identifier. */
649 enum aarch64_op op;
650
651 /* Which architecture variant provides this instruction. */
652 const aarch64_feature_set *avariant;
653
654 /* An array of operand codes. Each code is an index into the
655 operand table. They appear in the order which the operands must
656 appear in assembly code, and are terminated by a zero. */
657 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
658
659 /* A list of operand qualifier code sequence. Each operand qualifier
660 code qualifies the corresponding operand code. Each operand
661 qualifier sequence specifies a valid opcode variant and related
662 constraint on operands. */
663 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
664
665 /* Flags providing information about this instruction */
666 uint32_t flags;
4bd13cde 667
0c608d6b
RS		 668 /* If nonzero, this operand and operand 0 are both registers and
669 are required to have the same register number. */
670 unsigned char tied_operand;
671
4bd13cde
NC		 672 /* If non-NULL, a function to verify that a given instruction is valid. */
673 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
a06ea964
NC		 674};
675
676typedef struct aarch64_opcode aarch64_opcode;
677
678/* Table describing all the AArch64 opcodes. */
679extern aarch64_opcode aarch64_opcode_table[];
680
681/* Opcode flags. */
682#define F_ALIAS (1 << 0)
683#define F_HAS_ALIAS (1 << 1)
684/* Disassembly preference priority 1-3 (the larger the higher). If nothing
685 is specified, it is the priority 0 by default, i.e. the lowest priority. */
686#define F_P1 (1 << 2)
687#define F_P2 (2 << 2)
688#define F_P3 (3 << 2)
689/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
690#define F_COND (1 << 4)
691/* Instruction has the field of 'sf'. */
692#define F_SF (1 << 5)
693/* Instruction has the field of 'size:Q'. */
694#define F_SIZEQ (1 << 6)
695/* Floating-point instruction has the field of 'type'. */
696#define F_FPTYPE (1 << 7)
697/* AdvSIMD scalar instruction has the field of 'size'. */
698#define F_SSIZE (1 << 8)
699/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
700#define F_T (1 << 9)
701/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
702#define F_GPRSIZE_IN_Q (1 << 10)
703/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
704#define F_LDS_SIZE (1 << 11)
705/* Optional operand; assume maximum of 1 operand can be optional. */
706#define F_OPD0_OPT (1 << 12)
707#define F_OPD1_OPT (2 << 12)
708#define F_OPD2_OPT (3 << 12)
709#define F_OPD3_OPT (4 << 12)
710#define F_OPD4_OPT (5 << 12)
711/* Default value for the optional operand when omitted from the assembly. */
712#define F_DEFAULT(X) (((X) & 0x1f) << 15)
713/* Instruction that is an alias of another instruction needs to be
714 encoded/decoded by converting it to/from the real form, followed by
715 the encoding/decoding according to the rules of the real opcode.
716 This compares to the direct coding using the alias's information.
717 N.B. this flag requires F_ALIAS to be used together. */
718#define F_CONV (1 << 20)
719/* Use together with F_ALIAS to indicate an alias opcode is a programmer
720 friendly pseudo instruction available only in the assembly code (thus will
721 not show up in the disassembly). */
722#define F_PSEUDO (1 << 21)
723/* Instruction has miscellaneous encoding/decoding rules. */
724#define F_MISC (1 << 22)
725/* Instruction has the field of 'N'; used in conjunction with F_SF. */
726#define F_N (1 << 23)
727/* Opcode dependent field. */
728#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 729/* Instruction has the field of 'sz'. */
730#define F_LSE_SZ (1 << 27)
4989adac
RS		 731/* Require an exact qualifier match, even for NIL qualifiers. */
732#define F_STRICT (1ULL << 28)
733/* Next bit is 29. */
a06ea964
NC		 734
735static inline bfd_boolean
736alias_opcode_p (const aarch64_opcode *opcode)
737{
738 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
739}
740
741static inline bfd_boolean
742opcode_has_alias (const aarch64_opcode *opcode)
743{
744 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
745}
746
747/* Priority for disassembling preference. */
748static inline int
749opcode_priority (const aarch64_opcode *opcode)
750{
751 return (opcode->flags >> 2) & 0x3;
752}
753
754static inline bfd_boolean
755pseudo_opcode_p (const aarch64_opcode *opcode)
756{
757 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
758}
759
760static inline bfd_boolean
761optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
762{
763 return (((opcode->flags >> 12) & 0x7) == idx + 1)
764 ? TRUE : FALSE;
765}
766
767static inline aarch64_insn
768get_optional_operand_default_value (const aarch64_opcode *opcode)
769{
770 return (opcode->flags >> 15) & 0x1f;
771}
772
773static inline unsigned int
774get_opcode_dependent_value (const aarch64_opcode *opcode)
775{
776 return (opcode->flags >> 24) & 0x7;
777}
778
779static inline bfd_boolean
780opcode_has_special_coder (const aarch64_opcode *opcode)
781{
ee804238 782 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 783 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
784 : FALSE;
785}
786\f
787struct aarch64_name_value_pair
788{
789 const char * name;
790 aarch64_insn value;
791};
792
793extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 794extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
795extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 796extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 797
49eec193
YZ		 798typedef struct
799{
800 const char * name;
801 aarch64_insn value;
802 uint32_t flags;
803} aarch64_sys_reg;
804
805extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 806extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 807extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 808extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
809 const aarch64_sys_reg *);
810extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
811 const aarch64_sys_reg *);
49eec193 812
a06ea964
NC		 813typedef struct
814{
875880c6 815 const char *name;
a06ea964 816 uint32_t value;
ea2deeec 817 uint32_t flags ;
a06ea964
NC		 818} aarch64_sys_ins_reg;
819
ea2deeec 820extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 821extern bfd_boolean
822aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
823 const aarch64_sys_ins_reg *);
ea2deeec 824
a06ea964
NC		 825extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
826extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
827extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
828extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
829
830/* Shift/extending operator kinds.
831 N.B. order is important; keep aarch64_operand_modifiers synced. */
832enum aarch64_modifier_kind
833{
834 AARCH64_MOD_NONE,
835 AARCH64_MOD_MSL,
836 AARCH64_MOD_ROR,
837 AARCH64_MOD_ASR,
838 AARCH64_MOD_LSR,
839 AARCH64_MOD_LSL,
840 AARCH64_MOD_UXTB,
841 AARCH64_MOD_UXTH,
842 AARCH64_MOD_UXTW,
843 AARCH64_MOD_UXTX,
844 AARCH64_MOD_SXTB,
845 AARCH64_MOD_SXTH,
846 AARCH64_MOD_SXTW,
847 AARCH64_MOD_SXTX,
2442d846 848 AARCH64_MOD_MUL,
98907a70 849 AARCH64_MOD_MUL_VL,
a06ea964
NC		 850};
851
852bfd_boolean
853aarch64_extend_operator_p (enum aarch64_modifier_kind);
854
855enum aarch64_modifier_kind
856aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
857/* Condition. */
858
859typedef struct
860{
861 /* A list of names with the first one as the disassembly preference;
862 terminated by NULL if fewer than 3. */
bb7eff52 863 const char *names[4];
a06ea964
NC		 864 aarch64_insn value;
865} aarch64_cond;
866
867extern const aarch64_cond aarch64_conds[16];
868
869const aarch64_cond* get_cond_from_value (aarch64_insn value);
870const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
871\f
872/* Structure representing an operand. */
873
874struct aarch64_opnd_info
875{
876 enum aarch64_opnd type;
877 aarch64_opnd_qualifier_t qualifier;
878 int idx;
879
880 union
881 {
882 struct
883 {
884 unsigned regno;
885 } reg;
886 struct
887 {
dab26bf4
RS		 888 unsigned int regno;
889 int64_t index;
a06ea964
NC		 890 } reglane;
891 /* e.g. LVn. */
892 struct
893 {
894 unsigned first_regno : 5;
895 unsigned num_regs : 3;
896 /* 1 if it is a list of reg element. */
897 unsigned has_index : 1;
898 /* Lane index; valid only when has_index is 1. */
dab26bf4 899 int64_t index;
a06ea964
NC		 900 } reglist;
901 /* e.g. immediate or pc relative address offset. */
902 struct
903 {
904 int64_t value;
905 unsigned is_fp : 1;
906 } imm;
907 /* e.g. address in STR (register offset). */
908 struct
909 {
910 unsigned base_regno;
911 struct
912 {
913 union
914 {
915 int imm;
916 unsigned regno;
917 };
918 unsigned is_reg;
919 } offset;
920 unsigned pcrel : 1; /* PC-relative. */
921 unsigned writeback : 1;
922 unsigned preind : 1; /* Pre-indexed. */
923 unsigned postind : 1; /* Post-indexed. */
924 } addr;
925 const aarch64_cond *cond;
926 /* The encoding of the system register. */
927 aarch64_insn sysreg;
928 /* The encoding of the PSTATE field. */
929 aarch64_insn pstatefield;
930 const aarch64_sys_ins_reg *sysins_op;
931 const struct aarch64_name_value_pair *barrier;
9ed608f9 932 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 933 const struct aarch64_name_value_pair *prfop;
934 };
935
936 /* Operand shifter; in use when the operand is a register offset address,
937 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
938 struct
939 {
940 enum aarch64_modifier_kind kind;
a06ea964
NC		 941 unsigned operator_present: 1; /* Only valid during encoding. */
942 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
943 unsigned amount_present: 1;
2442d846 944 int64_t amount;
a06ea964
NC		 945 } shifter;
946
947 unsigned skip:1; /* Operand is not completed if there is a fixup needed
948 to be done on it. In some (but not all) of these
949 cases, we need to tell libopcodes to skip the
950 constraint checking and the encoding for this
951 operand, so that the libopcodes can pick up the
952 right opcode before the operand is fixed-up. This
953 flag should only be used during the
954 assembling/encoding. */
955 unsigned present:1; /* Whether this operand is present in the assembly
956 line; not used during the disassembly. */
957};
958
959typedef struct aarch64_opnd_info aarch64_opnd_info;
960
961/* Structure representing an instruction.
962
963 It is used during both the assembling and disassembling. The assembler
964 fills an aarch64_inst after a successful parsing and then passes it to the
965 encoding routine to do the encoding. During the disassembling, the
966 disassembler calls the decoding routine to decode a binary instruction; on a
967 successful return, such a structure will be filled with information of the
968 instruction; then the disassembler uses the information to print out the
969 instruction. */
970
971struct aarch64_inst
972{
973 /* The value of the binary instruction. */
974 aarch64_insn value;
975
976 /* Corresponding opcode entry. */
977 const aarch64_opcode *opcode;
978
979 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
980 const aarch64_cond *cond;
981
982 /* Operands information. */
983 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
984};
985
986typedef struct aarch64_inst aarch64_inst;
987\f
988/* Diagnosis related declaration and interface. */
989
990/* Operand error kind enumerators.
991
992 AARCH64_OPDE_RECOVERABLE
993 Less severe error found during the parsing, very possibly because that
994 GAS has picked up a wrong instruction template for the parsing.
995
996 AARCH64_OPDE_SYNTAX_ERROR
997 General syntax error; it can be either a user error, or simply because
998 that GAS is trying a wrong instruction template.
999
1000 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1001 Definitely a user syntax error.
1002
1003 AARCH64_OPDE_INVALID_VARIANT
1004 No syntax error, but the operands are not a valid combination, e.g.
1005 FMOV D0,S0
1006
0c608d6b
RS		 1007 AARCH64_OPDE_UNTIED_OPERAND
1008 The asm failed to use the same register for a destination operand
1009 and a tied source operand.
1010
a06ea964
NC		 1011 AARCH64_OPDE_OUT_OF_RANGE
1012 Error about some immediate value out of a valid range.
1013
1014 AARCH64_OPDE_UNALIGNED
1015 Error about some immediate value not properly aligned (i.e. not being a
1016 multiple times of a certain value).
1017
1018 AARCH64_OPDE_REG_LIST
1019 Error about the register list operand having unexpected number of
1020 registers.
1021
1022 AARCH64_OPDE_OTHER_ERROR
1023 Error of the highest severity and used for any severe issue that does not
1024 fall into any of the above categories.
1025
1026 The enumerators are only interesting to GAS. They are declared here (in
1027 libopcodes) because that some errors are detected (and then notified to GAS)
1028 by libopcodes (rather than by GAS solely).
1029
1030 The first three errors are only deteced by GAS while the
1031 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1032 only libopcodes has the information about the valid variants of each
1033 instruction.
1034
1035 The enumerators have an increasing severity. This is helpful when there are
1036 multiple instruction templates available for a given mnemonic name (e.g.
1037 FMOV); this mechanism will help choose the most suitable template from which
1038 the generated diagnostics can most closely describe the issues, if any. */
1039
1040enum aarch64_operand_error_kind
1041{
1042 AARCH64_OPDE_NIL,
1043 AARCH64_OPDE_RECOVERABLE,
1044 AARCH64_OPDE_SYNTAX_ERROR,
1045 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1046 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1047 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1048 AARCH64_OPDE_OUT_OF_RANGE,
1049 AARCH64_OPDE_UNALIGNED,
1050 AARCH64_OPDE_REG_LIST,
1051 AARCH64_OPDE_OTHER_ERROR
1052};
1053
1054/* N.B. GAS assumes that this structure work well with shallow copy. */
1055struct aarch64_operand_error
1056{
1057 enum aarch64_operand_error_kind kind;
1058 int index;
1059 const char *error;
1060 int data[3]; /* Some data for extra information. */
1061};
1062
1063typedef struct aarch64_operand_error aarch64_operand_error;
1064
1065/* Encoding entrypoint. */
1066
1067extern int
1068aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1069 aarch64_insn *, aarch64_opnd_qualifier_t *,
1070 aarch64_operand_error *);
1071
1072extern const aarch64_opcode *
1073aarch64_replace_opcode (struct aarch64_inst *,
1074 const aarch64_opcode *);
1075
1076/* Given the opcode enumerator OP, return the pointer to the corresponding
1077 opcode entry. */
1078
1079extern const aarch64_opcode *
1080aarch64_get_opcode (enum aarch64_op);
1081
1082/* Generate the string representation of an operand. */
1083extern void
1084aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1085 const aarch64_opnd_info *, int, int *, bfd_vma *);
1086
1087/* Miscellaneous interface. */
1088
1089extern int
1090aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1091
1092extern aarch64_opnd_qualifier_t
1093aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1094 const aarch64_opnd_qualifier_t, int);
1095
1096extern int
1097aarch64_num_of_operands (const aarch64_opcode *);
1098
1099extern int
1100aarch64_stack_pointer_p (const aarch64_opnd_info *);
1101
e141d84e
YQ		 1102extern int
1103aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1104
36f4aab1 1105extern int
43cdf5ae 1106aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
36f4aab1 1107
a06ea964
NC		 1108/* Given an operand qualifier, return the expected data element size
1109 of a qualified operand. */
1110extern unsigned char
1111aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1112
1113extern enum aarch64_operand_class
1114aarch64_get_operand_class (enum aarch64_opnd);
1115
1116extern const char *
1117aarch64_get_operand_name (enum aarch64_opnd);
1118
1119extern const char *
1120aarch64_get_operand_desc (enum aarch64_opnd);
1121
e950b345
RS		 1122extern bfd_boolean
1123aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1124
a06ea964
NC		 1125#ifdef DEBUG_AARCH64
1126extern int debug_dump;
1127
1128extern void
1129aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1130
1131#define DEBUG_TRACE(M, ...) \
1132 { \
1133 if (debug_dump) \
1134 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1135 }
1136
1137#define DEBUG_TRACE_IF(C, M, ...) \
1138 { \
1139 if (debug_dump && (C)) \
1140 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1141 }
1142#else /* !DEBUG_AARCH64 */
1143#define DEBUG_TRACE(M, ...) ;
1144#define DEBUG_TRACE_IF(C, M, ...) ;
1145#endif /* DEBUG_AARCH64 */
1146
245d2e3f
RS		 1147extern const char *const aarch64_sve_pattern_array[32];
1148extern const char *const aarch64_sve_prfop_array[16];
1149
d3e12b29
YQ		 1150#ifdef __cplusplus
1151}
1152#endif
1153
a06ea964 1154#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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